System on chip based on photoelectric mixing and photoelectric fusion chip

Abstract

The invention relates to the field of photoelectric hybrid computing, in particular to a photoelectric hybrid-based system on chip, which comprises at least one photoelectric fusion chip, the photoelectric fusion chip comprises a plurality of photoelectric fusion chips connected through an inter-chip interconnection module, and each photoelectric fusion chip comprises a photon integrated circuit (PIC) and an electronic integrated circuit (EIC); the electronic integrated circuit EIC comprises an ADC array, a control unit, a DAC array, a DSP array and a transmission unit which are in on-chip interconnection through on-chip interconnection units. Wherein the ADC array is respectively coupled to the photon integrated circuit PIC and the DSP array and is used for acquiring an analog signal from the photon integrated circuit PIC, converting the analog signal into a digital signal and sending the digital signal to the DSP array; the DSP array is in data communication with the control unit and the transmission unit through the on-chip interconnection unit and is used for obtaining matrix data to be operated from the on-chip interconnection unit, sending the matrix data to be operated to the photon integrated circuit PIC through the DAC array, obtaining data from the ADC array and transmitting the data to the on-chip interconnection unit.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic hybrid computing, and particularly to an on-chip system and an optoelectronic fusion chip based on optoelectronic hybrid. Background Art

[0002] After decades of development, optical computing technology has become increasingly mature since its inception. Optoelectronic fusion computing with integrated optical chips has become a common method for accelerating AI hardware. Using a photonic chip to replace an electronic chip for vector multiplication and addition operations in neural network algorithms can significantly improve energy efficiency and speed. However, current photonic chip computing belongs to analog quantity operations, and the control of analog quantities, the acquisition of operation results, and the operation of its upper-layer SoC system still need to be based on existing semiconductor electronic chips. Therefore, how to perform SoC integration has become an essential consideration in system architecture design.

[0003] Generally, in order to verify the functions of each bare chip and to facilitate the separate replacement and separate maintenance of each bare chip, the architecture of the current SoC system based on optoelectronic hybrid computing usually adopts a discrete design. That is, in addition to setting a PIC die for optical computing, ADC die / DAC die / PIC die, etc. are also separately and independently set, and then a 2D package is used to implement an optoelectronic fusion Chip. A large number of serdes modules need to be added for the large amount of data interaction between this Chip and the upper-layer ASIC. See Figure 2 However, this discrete design framework is not suitable for the commercial mass production of optoelectronic hybrid computing systems. Because a large number of computing tasks need to be executed in optical computing, which naturally involves a large amount of data transmission and data interaction. Therefore, a large number of serdes modules will cause losses in three aspects: power consumption, signal integrity, and scale scalability, greatly weakening the computing power and power consumption benefits brought by the photonic chip to the overall system, and becoming an important bottleneck for whether optoelectronic fusion computing can bring an actual computing power revolution.

[0004] In the traditional field of electronic computing, in order to reduce system power consumption and area, a Chinese patent application with publication number CN114722001A discloses a software-defined analog-digital hybrid SoC chip architecture, which proposes a monolithic integrated design of ADC / DAC analog circuits and digital array control processing logic. It adopts a heterogeneous fusion architecture of "ADC / DAC core" + "software-defined operation module" + "eFPGA core", integrating the usually independently existing analog ADC chip (ADC die), analog DAC chip (DAC die), digital signal processing chip (DSP die), and digital control FPGA chip into one chip.

[0005] However, the above chip architecture is only for the analog-digital hybrid SoC, that is, the traditional electronic computing field, and is not applicable to the optoelectronic hybrid SoC system that performs a large number of computing tasks. Summary of the Invention

[0006] The object of the present invention is to provide an optoelectronic hybrid on-chip system and an optoelectronic fusion chip, which partly solve or alleviate the above deficiencies in the prior art, have low power consumption, and have high scalability.

[0007] To solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions: The present invention provides an optoelectronic hybrid on-chip system, which includes: a plurality of optoelectronic fusion chips connected through an inter-chip interconnect module, and the optoelectronic fusion chip includes: a photonic integrated circuit PIC and an electronic integrated circuit EIC; the electronic integrated circuit EIC includes: an ADC array, a control unit, a DAC array, a DSP array, and a transmission unit that are interconnected through an intra-chip interconnect unit; wherein, The ADC array is respectively coupled to the photonic integrated circuit PIC and the DSP array, and is used to obtain an analog signal from the photonic integrated circuit PIC and convert it into a digital signal and send it to the DSP array for digital signal preprocessing; The DSP array communicates with the control unit and the transmission unit respectively through the intra-chip interconnect unit, and is used to obtain matrix data to be calculated from the intra-chip interconnect unit, send it to the photonic integrated circuit PIC through the DAC array, and obtain data from the ADC array, and after performing digital signal preprocessing on the obtained data, transfer it to the intra-chip interconnect unit.

[0008] Preferably, the electronic integrated circuit EIC further includes: a storage unit coupled to the intra-chip interconnect unit.

[0009] Preferably, the photonic integrated circuit PIC and the electronic integrated circuit EIC are packaged into an optoelectronic fusion chip through 3D packaging technology.

[0010] Preferably, the inter-chip interconnect module adopts the UCIe protocol to realize the interconnection of multiple optoelectronic fusion chips; and / or, the intra-chip interconnect unit adopts an intra-chip bus protocol.

[0011] Preferably, the transmission unit includes a SerDes sub-unit coupled to the inter-chip interconnect module.

[0012] Preferably, the ADC array includes at least a first ADC array and a second ADC array, wherein, The control unit pre-matches a first ADC array for the photonic integrated circuit PIC based on the attribute information of the photonic integrated circuit PIC, sets the first ADC array to the working state, and at the same time, sets the second ADC array to the sleep state; wherein, the attribute information includes the sampling accuracy requirement for the ADC and / or the sampling frequency requirement for the ADC. When the first ADC array in the working state fails, the control unit sets the second ADC from the sleep state to the working state.

[0013] Preferably, the ADC array includes a first ADC array and at least two second ADC arrays. The greater the difference between the key indicators of at least two of the second ADC arrays and the key indicators of the first ADC array, the lower its priority. The key indicators are sampling accuracy or sampling frequency; wherein, The control unit pre-matches a first ADC array for the photonic integrated circuit PIC based on the attribute information of the photonic integrated circuit PIC, sets the first ADC array to the working state, and at the same time, sets all the second ADC arrays to the sleep state; wherein, the attribute information includes the sampling accuracy requirement for the ADC and / or the sampling frequency requirement for the ADC. When the first ADC array in the working state fails, the control unit sets the second ADC array with the highest priority among at least two of the second ADCs from the sleep state to the working state.

[0014] Of course, further, if the second ADC array with the highest priority fails or is damaged, the second ADC array with the second highest priority is set from the sleep state to the working state, and so on, until all the second ADC arrays fail, then an alarm is given to prompt replacement of the optoelectronic integration chip.

[0015] Preferably, the DSP array is configured to automatically match a corresponding digital signal preprocessing scheme according to the attribute information of the first ADC array when the first ADC array is set to the working state; or, when the second ADC array is set to the working state, automatically match a corresponding digital signal preprocessing scheme according to the attribute information of the second ADC array; wherein, the attribute information includes: processing speed and processing bit width. That is, each time a new ADC array is started, the DSP array automatically matches a corresponding digital signal processing scheme according to the attribute information of the newly started ADC array.

[0016] Preferably, in the electronic integrated circuit EIC, the DAC array includes a WDAC array and an XDAC array. The WDAC array is located in the central region of the substrate, the XDAC array is located in a first partition near the first side of the central region, the ADC array is located in a second partition near the second side of the central region, and the control unit, DSP array, and transmission unit are all located in a third partition near the third side of the central region. The first side and the third side are oppositely arranged, and the second side is adjacent to the first side or the third side. Wherein, within the third partition, the on-chip interconnection unit is located at the center, and the control unit and the DSP array are arranged in parallel and are located between the on-chip interconnection unit and the WDAC array.

[0017] Preferably, the SerDes sub-unit is located at the edge of the third partition.

[0018] Preferably, the DAC array includes: an XDAC sub-array and a WDAC sub-array respectively coupled to the photonic integrated circuit PIC and the DSP array. Among them, the XDAC sub-array is used to convert the data matrix to be operated into an analog signal and send it to the photonic integrated circuit PIC; the WDAC sub-array is used to convert the weight matrix to be operated into an analog signal and send it to the photonic integrated circuit PIC.

[0019] In a second aspect of the present invention, there is provided an optoelectronic fusion chip, which includes: a photonic integrated circuit PIC and an electronic integrated circuit EIC encapsulated together by 3D packaging technology; the electronic integrated circuit EIC includes: an ADC array, a control unit, a DAC array, a DSP array, and a transmission unit interconnected on-chip through an on-chip interconnection unit; wherein, the ADC array is respectively coupled to the photonic integrated circuit PIC and the DSP array, and is used to obtain an analog signal from the photonic integrated circuit PIC and convert it into a digital signal and send it to the DSP array for data signal preprocessing; The DSP array communicates with the control unit and the transmission unit respectively through the on-chip interconnection unit, and is used to obtain the matrix data to be operated from the on-chip interconnection unit, send it to the photonic integrated circuit PIC through the DAC array, and obtain data from the ADC array, and after performing digital signal preprocessing on the obtained data, transfer it to the on-chip interconnection unit.

[0020] Preferably, the ADC array includes a first ADC array and a second ADC array, wherein, The control unit pre - matches a first ADC array for the photonic integrated circuit (PIC) based on the attribute information of the PIC, sets the first ADC array to the working state, and simultaneously sets the second ADC array to the sleep state; wherein the attribute information includes the sampling accuracy requirement for the ADC and / or the sampling frequency requirement for the ADC. When a failure occurs in the first ADC array in the working state, the control unit sets the second ADC array from the sleep state to the working state.

[0021] Preferably, the DSP array is configured to automatically match a corresponding first digital signal pre - processing scheme according to the attribute information of the first ADC array when the first ADC array is set to the working state; or to automatically match a corresponding second digital signal pre - processing scheme according to the attribute information of the second ADC array when the second ADC array is set to the working state; wherein the attribute information includes: processing speed, processing bit width.

[0022] Preferably, the ADC array includes a first ADC array and at least two second ADC arrays. The greater the difference in the key indicators between at least two of the second ADC arrays and the key indicators of the first ADC array, the lower their priority. The key indicators include sampling accuracy or sampling frequency; wherein The control unit pre - matches a first ADC array for the photonic integrated circuit (PIC) based on the attribute information of the PIC, sets the first ADC array to the working state, and simultaneously sets all the second ADC arrays to the sleep state; wherein the attribute information includes the sampling accuracy requirement for the ADC and / or the sampling frequency requirement for the ADC. When a failure occurs in the first ADC array in the working state, the control unit sets the second ADC array with the highest priority among at least two second ADCs from the sleep state to the working state. Of course, further, if the second ADC array with the highest priority fails or is damaged, the second ADC array with the second - highest priority is set from the sleep state to the working state, and so on, until all second ADC arrays fail, then an alarm is given to prompt replacement of the optoelectronic fusion chip.

[0023] Preferably, the electronic integrated circuit (EIC) further includes: a transmission unit, and the transmission unit includes: a SerDes sub - unit for data communication with an upper - layer system or other optoelectronic fusion chips.

[0024] Preferably, the on - chip interconnection unit adopts an on - chip bus protocol.

[0025] Beneficial effects: In the field of optoelectronic hybrid computing, compared with the traditional SoC in the field of electronic computing, since a large number of vector operation tasks need to be assigned to the PIC, and the 3D stacking technology is used for packaging between the EIC and the PIC, it is necessary to consider the interaction of a large amount of data to be calculated and its calculation results with the upper-layer system. In view of this, the system-on-chip of the present invention integrates the ADC / DAC into the upper-layer SoC, directly mounts the DSP on the on-chip interconnection unit to obtain the EIC Die, that is, the ADC / DAC under this architecture does not need to interact with the upper-layer module through any high-speed interface module; then the EIC Die and the PIC Die are packaged into an optoelectronic fusion Chip through the 3D stacking technology, and a communication expansion module, for example, UCIe, can support the extended interconnection of multiple Chips.

[0026] Due to the use of the on-chip interconnection method, compared with the discrete design Soc system, the number of serdes modules is reduced. On the one hand, the problem of high power consumption caused by introducing a large number of serdes modules is avoided, and the signal integrity is ensured; on the other hand, the use of a communication expansion module greatly improves the scalability of the chip scale.

[0027] However, precisely because all multiple electronic devices are integrated into one EIC, once a certain component is damaged, the entire EIC needs to be replaced, which will undoubtedly greatly increase the cost. On the other hand, since different PICs perform different computing tasks, their requirements for the EIC are also different. For example, some PICs require a higher sampling accuracy of the ADC in the EIC, while some PICs require a higher sampling frequency of the ADC in the EIC. During the integrated design process of the PIC and the EIC, once it is found that the current EIC does not match the PIC, the EIC needs to be redesigned or reworked and replaced. Redesigning will greatly increase the R & D cost, and reworking and replacing may damage the EIC and / or PIC. Therefore, considering the above two aspects, at least two ADC arrays (for example, an ADC array with high sampling accuracy and an ADC array with high sampling frequency) are integrated in the EIC in this application to cover the different requirements of different PICs, so that after the integrated packaging of the PIC and the EIC is realized by using the 3D stacking technology, the first ADC array that meets its requirements (i.e., the best match among many ADC arrays) can be automatically matched according to the attribute information of the PIC; if the ADC of this type is damaged or mismatched due to the increase of the usage time, the iteration of the PIC technology, or other reasons (for example, with the aging of time and frequency usage, its performance gradually decreases, making a more suitable situation appear in other ADCs), the second ADC array is started to serve the PIC, so that the entire EIC does not need to be directly replaced, thereby reducing the product cost on the premise of ensuring the normal operation of the entire system. On the other hand, precisely because a large number of serdes modules are not introduced, space and possibility are provided for integrating multiple ADC arrays, and at the same time, it provides the possibility for the miniaturization of the entire system. Brief Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts do not necessarily draw according to the actual scale. Obviously, the following described drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0029] Figure 1 Schematic diagram of the framework of an optoelectronic hybrid on-chip system according to the present invention; Figure 2 Schematic diagram of the framework of the existing on-chip system for reflection; Figure 3 Schematic diagram of the distribution of each device in an embodiment of the EIC chip in the optoelectronic fusion chip in an optoelectronic hybrid on-chip system according to the present invention; Figure 4 To reflect the distribution schematic diagram of each device in another embodiment of the EIC chip in the optoelectronic integration chip in the optoelectronic hybrid on-chip system of the present invention.

[0030] Summary of reference numeral identification: 100, PIC die (i.e., photonic integrated circuit PIC); 200, EIC die (i.e., electronic integrated circuit EIC); 201, on-chip interconnection sub-module, 2011, on-chip interconnection unit, 2012, DSP array, 202, ADC array, 203, CPU (or control unit), 204, DAC array, 205, storage unit, 206, transmission unit; 300, inter-chip interconnection module; 10, optoelectronic integration chip. Detailed implementation manners

[0031] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0032] In this article, suffixes such as "module", "component" or "unit" used to represent elements are only for the convenience of explaining the present invention, and have no specific meaning in themselves. Therefore, "module", "component" or "unit" can be used interchangeably.

[0033] In this article, terms such as "upper", "lower", "inner", "outer", "front", "rear", "one end", "the other end", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0034] In this article, unless otherwise clearly specified and defined, terms such as "installed", "provided with", "connected", etc. shall be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0035] As used herein, "coupled" is used in an operational sense and is not limited to direct or indirect coupling. "Coupled to" is generally used in the sense of direct coupling, while "coupled with" is generally used in the sense of direct or indirect coupling. "Coupled" in an electronic system can refer to a configuration that allows the flow of information, signals, data, or physical quantities (such as electricity) between two elements that are coupled to or coupled with each other. In some cases, the flow can be unidirectional, and in other cases, the flow can be bidirectional or multi-directional. Coupling can be electrical, capacitive, inductive, electromagnetic, optical, or through any other process permitted physically.

[0036] As used herein, "and / or" includes any and all combinations of one or more of the listed related items.

[0037] As used herein, "a plurality of" means two or more, i.e., it includes two, three, four, five, etc.

[0038] Glossary of terms: die: Refers to a bare die / bare chip, which is a very small unit in a silicon wafer, including a single fully designed chip and parts of the scribe line regions horizontally and vertically adjacent to the chip. A die is cut from a wafer. For example, an electrical bare chip (EIC Die) and a photonic bare chip (PIC Die).

[0039] chip (or (chiplet)): Refers to a chip, which is a general term for semiconductor component products and is obtained by packaging multiple dies. That is, an integrated circuit with simple or specialized functions used in combination with other ICs or chiplets in a multi-chip module. For example, an electronic integrated circuit (EIC, also simply referred to as an electrical chip) and a photonic integrated circuit (PIC, also simply referred to as an optical chip).

[0040] SerDes: An abbreviation for SERializer / DESerializer. It is mainly used to convert a continuous data stream (such as USB, Ethernet, etc.) into a serial data stream and restore the serial data stream to a continuous data stream. It is usually used for data transmission between chips (i.e., inter-chip). SerDes can also be used for communication within an SoC to save time and space.

[0041] SOC (System On Chip): A system-on-chip, or also known as a system on a chip. It is an integrated circuit that contains all the necessary components of a computer or other electronic system on a single chip (chip). These components usually include a processor, memory, and input / output interfaces.

[0042] Interconnect: An on-chip interconnect unit for enabling data transfer between internal functional components of a system-on-chip (i.e., within an SoC). Preferably, it can be implemented using protocols such as the AMBA bus protocol, the NOC on-chip network protocol, etc.

[0043] On-chip interconnect: It refers to the interconnection between various functional components within the same die through the Interconnect, without the need to set up additional transmission devices (such as SerDes) for connection to achieve data communication or data transfer. For example, it is electrically connected through one or more conductive elements (such as vias, pads, traces, microstrips, striplines, etc.) provided within the substrate. UCIe (Universal Chiplet Interconnect Express): A universal chiplet interface standard, which is a universal standard for enabling interconnection and interoperability between on-chip Chiplets that supports custom multi-protocols such as PCIe.

[0044] Inter-chip interconnect: It refers to the interconnection between chips. Preferably, SerDes is used to implement inter-chip interconnect.

[0045] Generally, for functional verification, in the SoC framework of the prior art, the electronic part mostly adopts a split design: ADC die / DAC die / PIC die. However, this split design brings losses in three aspects: power consumption, signal integrity, and scalability. In view of this, the present invention integrates ADC / DAC into the upper layer by adding a DSP array and an on-chip interconnect unit to obtain an EIC die, and then packages the EIC die and the PIC die to obtain an optoelectronic fusion chip. That is, each optoelectronic fusion chip (chip) is functionally divided into: an electrical die (EIC Die) for control and data transfer, and a photonic die (PIC Die) for computing. Then, an on-chip interconnect sub-module and a DSP array are set in the electrical die to achieve data communication connection between internal electronic units, that is, an integrated electrical chip structure is adopted, and then the electrical chip and the optical chip are packaged using 3D packaging technology; the SoC Chip based on the architecture of the present invention is composed of two Dies (electrical chip and optical chip), and supports the interconnection and expansion of multiple optoelectronic fusion chips (chips) to adapt to the operation requirements of larger-scale neural networks.

[0046] Embodiment 1: Refer to Figure 1 , the present invention provides an optoelectronic fusion chip 10. Specifically, it includes: a PIC die 100 and an EIC die 200 packaged together. Preferably, the PIC die 100 and the EIC die 200 are packaged into an optoelectronic fusion chip 10 through 3D packaging technology.

[0047] In this embodiment, the EIC die 200 includes: an ADC array 202, a control unit 203, a DAC array 204, a DSP array 2012, and a transmission unit 206 that are interconnected within the die through an on-chip interconnection module 201. Among them, the ADC array 202 is respectively coupled to the PIC die 100 and the DSP array 2012 in the on-chip interconnection module 201, and is used to obtain an analog signal from the PIC die 100 and convert it into a digital signal and send it to the DSP array 2012 for digital signal preprocessing (including filtering, denoising, etc.). Among them, the DSP array 2012 is coupled to the DAC array 204, and respectively communicates with the control unit 203 and the transmission unit 206 through the interconnection unit 2011 in the on-chip interconnection module 201, and is used to obtain the matrix data to be calculated from the interconnection unit 2011, and send it to the PIC die 100 through the DAC array 204, and obtain data from the ADC array 202, and after performing digital signal preprocessing on the obtained data, then pass it to the interconnection unit 2011.

[0048] In this embodiment, by setting the on-chip interconnection unit 2011, the DAC array, the ADC array, the DSP array, the control unit, etc. are interconnected within the die, so as to be integrated into an electrical die chip that realizes control and data transmission. Among them, the ADC array and the DAC array are also connected to the PIC at the same time. Therefore, the design of the electrical die chip with an integrated structure avoids problems such as high power consumption caused by introducing a large number of serdes modules in the discrete design structure.

[0049] In some embodiments, the EIC die 200 further includes: a storage unit 205 coupled to the interconnection unit 2011.

[0050] In some embodiments, the optoelectronic fusion chip 10 communicates with the upper-layer system or multiple optoelectronic fusion chips 10 through the transmission unit 206. Specifically, the transmission unit 206 includes: a SerDes sub-unit for communicating with the upper-layer system or other optoelectronic fusion chips 10.

[0051] In this embodiment, UCIe is used as the inter-die interconnection module, and the SerDes sub-unit is used to realize data communication between the electrical die chip and the upper-layer system or other optoelectronic fusion chips, which greatly improves the scalability of the chip scale.

[0052] In some embodiments, the DAC array 204 specifically includes: an XDAC sub-array and a WDAC sub-array respectively coupled to the PIC die 100 and the DSP array 2012. Among them, the XDAC sub-array is used to convert the data matrix to be calculated into an analog signal and send it to the optical matrix multiplication module 100; the WDAC sub-array is used to convert the weight matrix to be calculated into an analog signal and send it to the PIC die 100.

[0053] In some embodiments, the system-on-chip further includes an interconnect unit 2011 connected to the transmission unit 206, and multiple optoelectronic integration chips 10 perform data communication through the interconnect unit 2011.

[0054] See Figure 3 , in some embodiments, the above ADC array includes a first ADC array and a second ADC array. Specifically, the control unit pre-matches the first ADC array for the PIC based on the attribute information of the PIC, and sets the first ADC array to the working state. At the same time, the second ADC array is set to the sleep state; wherein, the attribute information includes the sampling accuracy requirement and / or sampling frequency requirement for the ADC; when the first ADC array in the working state fails or no longer matches, the control unit sets the second ADC array from the sleep state to the working state.

[0055] Generally, the system will perform an initialization configuration before use. During the initialization process, the control unit (such as Figure 3 and Figure 4 the CPU shown in) will pre-obtain the sampling requirements of the current PIC for the ADC array, such as specific attribute information including sampling accuracy or sampling frequency, etc., and then automatically match the corresponding ADC array according to the attribute information.

[0056] For example, the target sampling accuracy required by the current PIC for the ADC is R0. Therefore, if the sampling accuracies of both ADC arrays (such as ADCI and ADCII) are less than or greater than the target sampling accuracy R0, the control unit will automatically select the ADC array closest to the target sampling accuracy R0 from the two ADC arrays as the first ADC array and set it to the working state, while setting the other ADC array to the sleep state (when both are greater than the target sampling accuracy, it is not that the larger the sampling accuracy, the better, because the larger the sampling accuracy means longer conversion time and greater power consumption. Therefore, select the ADC array closest to the target sampling accuracy as the first ADC array); if the sampling accuracies of the two ADC arrays are one greater than the target sampling accuracy R0 and the other less than the target sampling accuracy R0, the control unit will select the ADC array greater than the target sampling accuracy R0 as the first ADC array and set it to the working state, while setting the other ADC array to the sleep state; of course, if the sampling accuracies of both ADC arrays are equal to the target sampling accuracy R0 or are not much different from the target sampling accuracy R0, randomly select one as the first ADC array.

[0057] For another example, the current PIC requires the target sampling frequency of the ADC to be f0. Therefore, if the sampling frequencies of both ADC arrays are less than or greater than the target sampling frequency f0, the control unit will automatically select the ADC array closest to the target sampling frequency f0 from the two ADC arrays as the first ADC array, set it to the working state, and set the other ADC array to the sleep state; if the sampling frequencies of the two ADC arrays are such that one is greater than the target sampling frequency f0 and the other is less than the target sampling frequency f0, the control unit will select the ADC array greater than the target sampling frequency f0 as the first ADC array, set it to the working state, and set the other ADC array to the sleep state; of course, if the sampling frequencies of both ADC arrays are equal to the target sampling frequency f0 (or not much different from the target sampling frequency f0), then one is randomly selected as the first ADC array.

[0058] See Figure 3 , in some embodiments, the WDAC array in the EIC is located in the central region of the substrate, the XDAC array is located in the first partition on the first side close to the central region, the ADC array is located in the second partition on the second side close to the central region, and the control unit, the DSP array, and the transmission unit are all located in the third partition on the third side close to the central region. The first side and the third side are oppositely arranged, and the second side is adjacent to one side or the third side; wherein, within the third partition, the on-chip interconnection unit is in the center, and the control unit and the DSP array are arranged in parallel and are located between the on-chip interconnection unit and the WDAC array.

[0059] In some other embodiments, due to the reduction in the introduction of Serders, there is a certain amount of space available for integrating other components. Therefore, different ADC arrays can also be set according to different sampling accuracy requirements and / or different sampling frequency requirements. For example, see Figure 4 , the ADC array includes ADCI, ADCII, and ADCIII, and the sampling accuracies of the three ADC arrays are different, being R1, R2, and R3 respectively, and the sampling frequencies are also different, being f1, f2, and f3 respectively, so that it can be adapted to more models of PICs.

[0060] In some other embodiments, the key metrics of at least two ADC arrays are the same. For example, the sampling accuracies of ADCI and ADCII are the same: R1 = R2, but different from the sampling accuracy R3 of ADCIII; however, their sampling frequencies may be the same or different. When ADCI, originally serving as the first ADC array, fails or is damaged, the control unit preferentially activates ADCII, which serves as the second ADC array and has the highest priority, to replace ADCI, while ADCIII, which serves as the second ADC array and has a lower priority, remains in the sleep state. And when ADCII also fails or is damaged, the control unit then activates ADCIII. That is, by setting second ADC arrays with different priority levels, while ensuring the normal operation of the system, the computing power of the system is also maximally guaranteed. If some of the sampling accuracies are greater than R0 and some are less than R0, then the priority of the second ADC array with a sampling accuracy greater than R0 is higher than that of the second ADC array with a sampling accuracy less than R0; if the sampling accuracies are all greater than R0 or all less than R0, then among the multiple second ADC arrays, the one with a smaller difference (e.g., the absolute value of the difference) between the sampling accuracy and the target sampling accuracy has a higher priority.

[0061] Similarly, if the sampling frequencies of ADCI and ADCII are the same: f1 = f2, but different from the sampling frequency of ADCIII; however, their sampling accuracies may be the same or different. When ADCI, originally serving as the first ADC array, fails or is damaged, the control unit preferentially activates ADCII to replace ADCI, while ADCIII remains in the sleep state.

[0062] Correspondingly, due to the setting of different ADC arrays, the DSP array needs to match corresponding digital signal preprocessing schemes for different ADC arrays. Specifically, the DSP can pre-store the digital signal preprocessing schemes configured for each ADC array. Therefore, it only needs to automatically match the corresponding digital signal preprocessing scheme according to the attribute information of the currently activated ADC: model, sampling frequency, resolution, etc. For example, when the first ADC array is activated, the DSP automatically matches the corresponding first digital signal preprocessing scheme (such as the first processing speed corresponding to the sampling frequency of the first ADC array and the first processing bit width corresponding to the resolution of the first ADC array) according to the attribute information (such as sampling frequency or resolution) of the first ADC array; or when the second ADC array is activated, it automatically matches the corresponding second digital signal preprocessing scheme (such as the second processing speed corresponding to the sampling frequency of the second ADC array and the second processing bit width corresponding to the resolution of the second ADC array) according to the attribute information of the second ADC array.

[0063] Furthermore, since three ADC arrays are provided, and when the sampling accuracies and sampling frequencies of the three ADC arrays are different, and the sampling requirements of the PIC for the ADC do not satisfy only one of the sampling accuracy and the sampling frequency, but need to meet both of these indicators, it is necessary to match the best ADC array from them as the first ADC array according to the attribute information of the PIC during the initialization process, so as to maximize the role of setting multiple ADC arrays.

[0064] Specifically, if the current PIC not only needs to match the sampling accuracy with the ADC array, but also needs to match the sampling frequency. Calculate the respective matching degrees P of each ADC array: ADCI, ADCII, and ADCIII according to the attribute information of the current PIC (for example, the sampling accuracy is at least R0; the sampling frequency is at least f0). Correspondingly, filter out the ADC arrays that meet the conditions: 1) the sampling accuracy is greater than R0; 2) the sampling frequency is greater than f0, and then calculate the matching degree between the i-th ADC array among the filtered ADC arrays and the current PIC. , where is the sampling accuracy of the i-th ADC array, is the sampling frequency of the i-th ADC array. Sort the matching degrees of all ADC arrays, and use the ADC array with the smallest matching degree as the best matching ADC (i.e., the first ADC array) of the current PIC, set its status to the working state, and set the status of the remaining ADC arrays (i.e., the second ADC arrays, including the ADC arrays with a sampling accuracy less than R0 or a sampling frequency less than f0) to the sleep state. When the best matching ADC fails, select the one with the smallest matching degree from the remaining ADC arrays to match the current PIC, and so on.

[0065] Of course, if all the filtered ADC arrays are damaged, start the ADC arrays with a sampling accuracy less than R0 or a sampling frequency less than f0.

[0066] Generally, ideally, there are ADC arrays that satisfy both of the above two filtering conditions. However, in practical applications, there are also cases where all ADC arrays only satisfy one of the above two filtering conditions. At this time, the above matching degree is: , and similarly, sort the respective ADC arrays based on the matching degree (i.e., priority sorting), but select the smallest one from them as the best matching ADC array to match the current PIC, that is, set the status of the best matching ADC array to the working state.

[0067] Of course, if there are at least two ADC arrays with the same matching degree, at least one alternative ADC array that does not meet the above conditions 1) or 2) is selected therefrom, and one ADC array closest to the target sampling accuracy R0 or the target sampling frequency f0 is selected therefrom. For example, if there are ADC I and ADC II with the same matching degree, and the sampling accuracies of both arrays are less than the target sampling accuracy R0, therefore, one ADC array closest to R0 is selected therefrom as the first ADC array. Another example is that if there are ADC I and ADC II with the same matching degree, but the sampling accuracy of ADC I is less than the target sampling accuracy R0 and its sampling frequency is greater than or equal to the target sampling frequency f0; while the sampling accuracy of ADC II is greater than or equal to the target sampling accuracy R0 and its sampling frequency is less than the target sampling frequency f0, therefore, the difference between the sampling accuracy of ADC I and the target sampling accuracy R0 and the difference between the sampling frequency of ADC II and the target sampling frequency f0 are calculated respectively, and one ADC with the smallest difference is selected therefrom as the first ADC array.

[0068] In some embodiments, since the SerDes subunit needs to interact with the outside of the chip, such as for inter-chip interaction, therefore, the SerDes subunit is located at the edge of the third partition.

[0069] In this embodiment, since the on-chip system uses the 3D stacking technology to stack the EIC and the PIC, therefore, on the one hand, the data flow between the EIC and the PIC is considered, and on the other hand, the data flow inside the EIC is also considered. Therefore, the above spatial layout is adopted, so as to reduce the congestion of the interconnection lines between components to a certain extent. For example, the on-chip interconnection unit needs to interact frequently with storage units such as the control unit, DSP, SRAM (i.e., the first storage unit), and DMA (i.e., the second storage unit), and at the same time, it also needs to interact with the SerDes subunit that interacts with the outside of the chip. Therefore, the on-chip interconnection unit is arranged at the center of the third partition, and the control unit and DSP are arranged between it and the DAC, while on the other side, that is, at the edge of the third partition (or the edge of the substrate), the SerDes subunit is arranged.

[0070] Embodiment 2: Refer to Figure 1 , which is a schematic framework diagram of an on-chip system based on optoelectronic hybrid according to the present invention. Specifically, the on-chip system includes: at least one optoelectronic fusion chip 10. Specifically, the optoelectronic fusion chip 10 includes: a PIC die 100 and an EIC die 200 packaged together.

[0071] In this embodiment, the EIC die 200 includes: an ADC array 202, a control unit 203, a DAC array 204, a DSP array 2012, and a transmission unit 206 that are interconnected on-chip through an on-chip interconnection module 201; among them, the ADC array 202 is respectively coupled to the PIC die 100 and the DSP array 2012 in the on-chip interconnection module 201, and is used to obtain an analog signal from the PIC die 100 and convert it into a digital signal and send it to the DSP array 2012 for digital signal preprocessing; among them, the DSP array 2012 is coupled to the DAC array 204 and performs data communication with the control unit 203 and the transmission unit 206 respectively through the interconnection unit 2011 in the on-chip interconnection module 201, and is used to obtain the matrix data to be calculated from the interconnection unit 2011 and send it to the PIC die 100 through the DAC array 204, and obtain data from the ADC array 202, and after performing digital signal preprocessing, transfer it to the interconnection unit 2011.

[0072] Among them, the PIC die 100 and the EIC die 200 are packaged into an optoelectronic integration chip 10 through 3D packaging technology.

[0073] In some embodiments, the EIC die 200 further includes: a storage unit 205 coupled to the interconnection unit 2011.

[0074] In some embodiments, the optoelectronic integration chip 10 performs data communication with an upper-layer system or multiple optoelectronic integration chips 10 through the transmission unit 206.

[0075] In some embodiments, the above-mentioned transmission unit 206 includes: a SerDes subunit for performing data communication with an upper-layer system or other optoelectronic integration chips 10.

[0076] In some embodiments, the DAC array 204 specifically includes: an XDAC sub-array and a WDAC sub-array respectively coupled to the PIC die 100 and the DSP array 2012, where the XDAC sub-array is used to convert the data matrix to be calculated into an analog signal and send it to the optical matrix multiplication module 100; the WDAC sub-array is used to convert the weight matrix to be calculated into an analog signal and send it to the PIC die 100.

[0077] In some embodiments, the above ADC array specifically includes: a first ADC array and a second ADC array. Among them, the control unit pre-matches the first ADC array for the photonic integrated circuit PIC based on the attribute information of the photonic integrated circuit PIC, and sets the first ADC array to the working state. At the same time, the second ADC array is set to the sleep state. Among them, the attribute information includes the sampling accuracy requirement for the ADC and / or the sampling frequency requirement for the ADC. When the first ADC array in the working state fails, the control unit sets the second ADC from the sleep state to the working state.

[0078] Further, the DSP array is configured to automatically match the corresponding digital signal preprocessing scheme (including processing speed and processing bit width) according to the attribute information of the first ADC array (including sampling frequency and resolution) when the first ADC array is set to the working state; or, when the second ADC array is set to the working state, automatically match the corresponding digital signal preprocessing scheme according to the attribute information of the second ADC array (including sampling frequency and resolution), including: processing speed and processing bit width.

[0079] Of course, in some other embodiments, multiple second ADC arrays can be set in the ADC array, and the multiple second ADC arrays are prioritized according to the attribute information of the first ADC array. For example, the first ADC array is matched according to the sampling accuracy of the current PIC. Therefore, the priority of the second ADC array with the same sampling accuracy as the first ADC array is set to the highest, and the lower the priority of the other second ADC arrays with a greater difference in sampling accuracy from the first ADC array. When the first ADC array fails or is damaged, the second ADC array with the highest priority is started. Similarly, if the first ADC array is matched according to the sampling frequency of the current PIC. Therefore, the priority of the second ADC array with the same sampling frequency as the first ADC array is set to the highest, and the lower the priority of the other second ADC arrays with a greater difference in sampling frequency from the first ADC array. When the first ADC array fails or is damaged, the second ADC array with the highest priority is started. Of course, the method in the first embodiment above can also be used to calculate the matching degree of each ADC array with the PIC, and then determine the first ADC array based on the size of the matching degree. The principle can refer to the above embodiment and will not be elaborated here.

[0080] In some embodiments, the on-chip system further includes: an interconnection unit 2011 connected to the transmission unit 206, and multiple optoelectronic fusion chips 10 perform data communication through the interconnection unit 2011.

[0081] It should be noted that in this text, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including such element.

[0082] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the spirit and scope protected by the claims of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. An optoelectronic hybrid-based on-chip system, characterized in that Including: A plurality of optoelectronic integrated chips connected by an inter-chip interconnection module, and the optoelectronic integrated chip includes: a photonic integrated circuit PIC and an electronic integrated circuit EIC stacked by 3D stacking technology; the electronic integrated circuit EIC includes: an ADC array, a control unit, a DAC array, a DSP array, and a transmission unit interconnected through an intra-chip interconnection unit; wherein, The ADC array is respectively coupled to the photonic integrated circuit PIC and the DSP array, and is configured to obtain an analog signal from the photonic integrated circuit PIC and convert it into a digital signal and send it to the DSP array for digital signal preprocessing; The DSP array performs data communication with the control unit and the transmission unit respectively through the intra-chip interconnection unit, and is configured to obtain matrix data to be calculated from the intra-chip interconnection unit, send it to the photonic integrated circuit PIC through the DAC array, and obtain data from the ADC array, and after performing digital signal preprocessing on the obtained data, transfer it to the intra-chip interconnection unit.

2. The on-chip system based on optoelectronic hybrid according to claim 1, wherein The ADC array includes a first ADC array and a second ADC array, wherein, The control unit pre-matches the first ADC array for the photonic integrated circuit PIC based on the attribute information of the photonic integrated circuit PIC, sets the first ADC array to the working state, and at the same time, sets the second ADC array to the sleep state; wherein, the attribute information includes the sampling accuracy requirement for the ADC and / or the sampling frequency requirement for the ADC; When the first ADC array in the working state fails, the control unit sets the second ADC from the sleep state to the working state.

3. The on-chip system based on optoelectronic hybrid according to claim 2, characterized in that, The DSP array is configured to automatically match a corresponding digital signal preprocessing scheme according to the attribute information of the first ADC array when the first ADC array is set to the working state; Or, When the second ADC array is set to the working state, automatically match a corresponding digital signal preprocessing scheme according to the attribute information of the second ADC array; wherein, the attribute information includes: sampling frequency and resolution; the digital signal preprocessing scheme includes: processing speed and processing bit width.

4. The on-chip system based on optoelectronic hybrid according to claim 1, characterized in that, The ADC array includes a first ADC array and at least two second ADC arrays. The greater the difference between the key indicators of at least two second ADC arrays and the key indicators of the first ADC array, the lower its priority. The key indicators are sampling accuracy or sampling frequency; wherein, The control unit pre-matches the first ADC array for the photonic integrated circuit PIC based on the attribute information of the photonic integrated circuit PIC, sets the first ADC array to the working state, and at the same time, sets all the second ADC arrays to the sleep state; wherein, the attribute information includes the sampling accuracy requirement for the ADC and / or the sampling frequency requirement for the ADC; When the first ADC array in the working state fails, the control unit sets the second ADC array with the highest priority among at least two second ADCs from the sleep state to the working state.

5. A photoelectric hybrid-based on-chip system according to claim 1, characterized in that, The electronic integrated circuit EIC further includes: a storage unit coupled to the on-chip interconnection unit.

6. The on-chip system based on optoelectronic hybrid according to claim 1, characterized in that, The inter-chip interconnection module adopts the UCIe protocol; and / or, the on-chip interconnection unit adopts an on-chip bus protocol; and / or, the transmission unit includes a SerDes sub-unit coupled to the inter-chip interconnection module.

7. An optoelectronic hybrid-based on-chip system according to claim 2 or 4, characterized in that In the electronic integrated circuit EIC, the DAC array includes a WDAC array and an XDAC array. The WDAC array is located in the central region of the substrate. The XDAC array is located in a first partition near the first side of the central region. The ADC array is located in a second partition near the second side of the central region. The control unit, the DSP array, and the transmission unit are all located in a third partition near the third side of the central region. The first side and the third side are oppositely arranged. The second side is adjacent to the first side or the third side. Among them, within the third partition, the on-chip interconnection unit is in the center. The control unit and the DSP array are arranged side by side and are located between the on-chip interconnection unit and the WDAC array. The SerDes sub-unit is located at the edge of the third partition.

8. An optoelectronic integrated chip, characterized in that, Including: A photonic integrated circuit PIC and an electronic integrated circuit EIC encapsulated together by 3D packaging technology; the electronic integrated circuit EIC includes: an ADC array, a control unit, a DAC array, a DSP array, and a transmission unit that are interconnected on-chip through an on-chip interconnection unit; among them, The ADC array is respectively coupled to the photonic integrated circuit PIC and the DSP array, and is used to obtain an analog signal from the photonic integrated circuit PIC and convert it into a digital signal and send it to the DSP array for preprocessing of data signals. The DSP array conducts data communication with the control unit and the transmission unit respectively through the on-chip interconnection unit, and is used to obtain matrix data to be calculated from the on-chip interconnection unit and send it to the photonic integrated circuit PIC through the DAC array, and obtain data from the ADC array, and after preprocessing the obtained data digitally, then transfer it to the on-chip interconnection unit.

9. The optoelectronic integration chip according to claim 8, wherein, The ADC array includes a first ADC array and a second ADC array, among which, The control unit pre-matches the first ADC array for the photonic integrated circuit PIC based on the attribute information of the photonic integrated circuit PIC, and sets the first ADC array to the working state, and at the same time, sets the second ADC array to the sleep state; among them, the attribute information includes the sampling accuracy requirement for the ADC and / or the sampling frequency requirement for the ADC. When the first ADC array in the working state fails, the control unit sets the second ADC array from the sleep state to the working state; correspondingly, The DSP array is configured to automatically match a corresponding first digital signal preprocessing scheme according to the attribute information of the first ADC array when the first ADC array is set to the working state; or, when the second ADC array is set to the working state, automatically match a corresponding second digital signal preprocessing scheme according to the attribute information of the second ADC array; wherein, the attribute information includes: processing speed, processing bit width.

10. A photoelectric fusion chip according to claim 9, characterized in that, The electronic integrated circuit EIC further includes: a transmission unit, the transmission unit includes: a SerDes sub-unit for data communication with an upper-layer system or other said optoelectronic fusion chips; and / or, the on-chip interconnection unit adopts an on-chip bus protocol.

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