Circuit layout determination method and device, equipment and medium

Abstract

The invention provides a circuit layout determination method and device, equipment and a medium, and relates to the technical field of computers. The method comprises the following steps: acquiring wiring constraint data of a plurality of signal line groups; and determining an initial spacing between the processor and the memory module based on the wiring constraint data of the target signal line group and the associated signal line group in the plurality of signal line groups. The target signal line group is a signal line group of which the spatial degree of freedom meets a predetermined condition in the plurality of signal line groups, and the associated signal line group is at least one signal line group which affects the spatial degree of freedom of the target signal line group in the first direction in the plurality of signal line groups. Determining a compensation distance between the processor and the memory module based on the compensation length required by the target signal line group; the compensation length represents the total length, needing to be compensated, of a plurality of target signal lines in the target signal line group under the condition that the target signal lines meet the intra-group equal-length constraint condition. Based on the initial spacing and the compensation spacing, a layout spacing of a processor and a memory module of the circuit is determined.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and more particularly, to a method, apparatus, device, and medium for determining a circuit layout. Background Art

[0002] Multiple types of devices and signal lines are usually arranged on the main board of a server. To save development time, the routing of the devices and signal lines on the main board is designed in parallel. Therefore, a rough position for signal line routing needs to be reserved between different modules. For example, a certain reserved space is set between a processor and a memory module for laying signal lines connecting the processor and the memory module.

[0003] However, if the reserved space is too large, the signal lines will be too long, increasing the risk of loss and affecting the space of other devices; if the reserved space is too small, it may cause the signal lines to fail to meet the requirements of spacing and equal length, and the signal lines cannot be connected to the processor and the memory module. In the related art, the reserved space between the processor and the memory module is usually determined based on experience, and the rationality and accuracy of the reserved space still need to be improved. Summary of the Invention

[0004] In view of this, this application provides a method, apparatus, device, and medium for determining a circuit layout.

[0005] One aspect of this application provides a method for determining a circuit layout, including: obtaining wiring constraint data of multiple signal line groups; where the multiple signal line groups are used to be laid between a processor and a memory module to connect the processor and the memory module; determining an initial spacing between the processor and the memory module based on the wiring constraint data of a target signal line group and an associated signal line group in the multiple signal line groups; the target signal line group is a signal line group in the multiple signal line groups whose spatial degree of freedom meets a predetermined condition, and the associated signal line group is at least one signal line group in the multiple signal line groups that affects the spatial degree of freedom of the target signal line group in a first direction; determining a compensation spacing between the processor and the memory module based on the compensation length required by the target signal line group; the compensation length represents the total length that multiple target signal lines in the target signal line group need to be compensated under the condition of meeting the equal length constraint within the group; determining the layout spacing between the processor and the memory module of the circuit based on the initial spacing and the compensation spacing.

[0006] Another aspect of the present application provides an apparatus for determining a circuit layout, characterized by comprising: an acquisition module for acquiring routing constraint data of a plurality of signal line groups; wherein the plurality of signal line groups are used for being routed between a processor and a memory module to connect the processor and the memory module; a first determination module for determining an initial spacing between the processor and the memory module based on the routing constraint data of a target signal line group and an associated signal line group in the plurality of signal line groups; the target signal line group is a signal line group in the plurality of signal line groups whose spatial degree of freedom meets a predetermined condition, and the associated signal line group is at least one signal line group in the plurality of signal line groups that affects the spatial degree of freedom of the target signal line group in a first direction; a second determination module for determining a compensation spacing between the processor and the memory module based on the compensation length required by the target signal line group; the compensation length represents the length that needs to be compensated for a plurality of target signal lines in the target signal line group when the equal-length constraint condition within the group is satisfied; a third determination module for determining the layout spacing between the processor and the memory module of the circuit based on the initial spacing and the compensation spacing.

[0007] Another aspect of the present application provides an electronic device, comprising: one or more processors; a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the above method.

[0008] Another aspect of the present application further provides a computer-readable storage medium, on which a computer program or instruction is stored, and when the computer program or instruction is executed by a processor, the steps of the above method are implemented.

[0009] Another aspect of the present application further provides a computer program product, comprising a computer program or instruction, and when the computer program or instruction is executed by a processor, the steps of the above method are implemented.

[0010] According to the technical solution of the present application, by determining a target signal line group and an associated signal group whose spatial degrees of freedom meet preset conditions from a plurality of signal line groups, and based on the routing constraint data of the target signal line group and the associated signal line group, the minimum initial spacing that can accommodate the target signal line group and the associated signal line group between the processor and the memory module can be determined. By the compensation length required by the target signal line group, the compensation spacing is determined, and the actual required layout spacing of the target signal line group under the equal-length constraint condition can be further determined. Thus, the rationality and accuracy of the reserved space are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Through the following description of the embodiments of the present application with reference to the drawings, the above content and other objects, features and advantages of the present application will become clearer.

[0012] Figure 1Shows an application scenario diagram of a method for determining a circuit layout according to an embodiment of the present application.

[0013] Figure 2 Shows a flowchart of a method for determining a circuit layout according to an embodiment of the present application.

[0014] Figure 3A Shows a schematic diagram of the composition structure of a signal line group according to an embodiment of the present application.

[0015] Figure 3B Shows a schematic diagram of a scenario for determining an initial spacing according to an embodiment of the present application.

[0016] Figure 3C Shows a scenario diagram where the spacing between a processor and a memory module is less than the initial spacing according to an embodiment of the present application.

[0017] Figure 3D Shows a scenario diagram where the spacing between a processor and a memory module is greater than the initial spacing according to an embodiment of the present application.

[0018] Figure 4 Shows a distribution diagram of the pin positions of a processor and a memory module according to an embodiment of the present application.

[0019] Figure 5 Shows a schematic diagram of the principle for determining the length difference between target signal lines according to an embodiment of the present application.

[0020] Figure 6 Shows a module diagram of a device for determining a circuit layout according to an embodiment of the present application.

[0021] Figure 7 Shows a block diagram of an electronic device suitable for implementing the method described above according to an embodiment of the present application. Detailed implementation

[0022] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present application. In the following detailed description, for the sake of explanation, many specific details are set forth in order to provide a comprehensive understanding of the embodiments of the present application. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present application.

[0023] The terms used herein are merely for the purpose of describing specific embodiments and are not intended to limit the present application. The terms "including", "comprising", etc. used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0024] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0025] In cases where expressions similar to "at least one of A, B, and C, etc." are used, generally, it should be interpreted according to the meaning that those of ordinary skill in the art usually understand this expression (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0026] Figure 1 The application scenario diagram schematically shows the determination method of the circuit layout according to an embodiment of the present application.

[0027] As Figure 1 shown, the application scenario of the determination method of the circuit layout may include a processor 110 and a memory module 120. The processor 110 and the memory module 120 are connected by a plurality of signal line groups 130. The signal line group 130 includes a plurality of signal lines 131. The signal lines 131 are arranged between the processor 110 and the memory module 120 and are respectively connected to the corresponding pins of the processor 110 and the memory module 120.

[0028] Schematically, the processor 110 may be, for example, a central processing unit (CPU), or other types of general-purpose processors. The memory module 120 may be, for example, a Dual Inline Memory Module (DIMM). The signal line 130 may be, for example, a DDR (Double Data Rate) signal line.

[0029] Figure 2 The flowchart shows the determination method of the circuit layout according to an embodiment of the present application.

[0030] As Figure 2 shown, the method includes operations S210 to S240.

[0031] In operation S210, obtain the wiring constraint data of a plurality of signal line groups; wherein, the plurality of signal line groups are used to be arranged between the processor and the memory module to connect the processor and the memory module.

[0032] In operation S220, based on the routing constraint data of the target signal line group and the associated signal line group among multiple signal line groups, determine the initial spacing between the processor and the memory module; the target signal line group is the signal line group among multiple signal line groups whose spatial degree of freedom meets a predetermined condition, and the associated signal line group is at least one signal line group among multiple signal line groups that affects the spatial degree of freedom of the target signal line group in the first direction.

[0033] In operation S230, based on the compensation length required by the target signal line group, determine the compensation spacing between the processor and the memory module; the compensation length represents the total length that multiple target signal lines in the target signal line group need to be compensated under the condition of meeting the equal-length constraint within the group.

[0034] In operation S240, based on the initial spacing and the compensation spacing, determine the layout spacing between the processor and the memory module of the circuit.

[0035] The routing constraint data refers to the data that enables the layout of signal lines to meet the layout constraint conditions, and the layout constraint conditions include, for example, signal line width conditions, signal line spacing conditions, and equal-length constraint conditions, etc., so that the layout of signal lines meets requirements such as electrical performance, signal integrity, and electromagnetic compatibility.

[0036] Multiple signal line groups are routed between the processor and the memory module. Taking the CPU and DIMM as an example, there are 8 data signal line groups, one ECC (Error Correcting Code) signal line group, one Clk (Clock) signal line group, and two A_C (Address / Command) signal line groups between the CPU and the DIMM. Among them, the Clk signal line group is routed in the middle, the 1st to 4th data signal line groups, one A_C signal line group, and the ECC signal line group are routed on the left side of the Clk signal line group, and the 5th to 8th data line groups and one A_C signal line group are routed on the right side of the Clk signal line group.

[0037] The spatial degree of freedom represents the degree to which the signal line group can flexibly adjust its position, orientation, and layout. It can reflect the available routing space resources and the range of routing adjustments that the signal line group can make under the condition of meeting the routing constraint conditions. The spatial degree of freedom of the signal line group is affected by the adjacent signal line groups on both sides and the spacing between the processor and the memory module.

[0038] The predetermined condition can be the condition of meeting the minimum spatial degree of freedom among multiple signal line groups. The target signal line group can be the signal line group with the minimum spatial degree of freedom among multiple signal line groups. The first direction can be, for example, the horizontal direction parallel to the processor and the memory module. The associated signal line group can be, for example, the signal line group that affects the spatial degree of freedom of the target signal line group in the horizontal direction.

[0039] Before determining the initial pitch, the routing patterns of each signal line group can be determined first. According to the routing patterns of each signal line group, the target signal line group and the associated signal line group can be determined.

[0040] For example, the routing pattern of the outermost signal line group can be determined first. According to the routing pattern, it can be determined whether the outermost signal line group occupies the space between the processor and the memory module. If it occupies, the outermost signal line group is the associated signal line group; if it does not occupy, the outermost signal line group is not the associated signal line group. Similarly, the second outermost signal line group can be further determined whether it is the associated signal line group in the same way.

[0041] Continuing with the CPU and DIMM as an example, since there are 6 signal line groups and 5 signal line groups on the left and right sides of the Clk signal line group respectively; if the space on the left meets the layout constraint conditions of the signal line group, the space on the right will also necessarily meet. Since the first group of data signal line groups is located on the outermost side, the space freedom degree is the largest. The second and third groups of data signal line groups have space to extend in the direction where the first signal line group is located, and the space freedom degree is the second. The A_C signal line group and the Clk signal line group are located in the middle, and the connection of their signal lines is basically perpendicular to the CPU and DIMM, and basically meets the equal-length constraint conditions. The ECC signal line group can compress the space of the fourth data signal line group to the left, so the fourth data signal line group is the target signal line group. If the space of the target signal line group meets the routing constraint conditions, the spaces of the remaining signal line groups will also meet the routing constraint conditions.

[0042] If the space freedom degree of the fourth data signal line group is not affected by the first data signal line group located on the outermost side by means of wire winding, while the second and third data signal line groups will affect the freedom degree of the fourth data signal line group to the left in the horizontal direction, then the second and third groups of data signal line groups are the associated signal line groups. Then, according to the routing constraint data of the second, third, and fourth data signal line groups, the initial pitch between the processor and the memory module is determined.

[0043] The initial pitch represents the minimum pitch that can accommodate the target signal line group and the associated signal line group between the processor and the memory module without considering the equal-length constraint conditions.

[0044] Due to the different sizes between the processor and the memory module, the pitches between the processor pins and the memory module pins connecting different target signal lines are different. To meet the equal-length constraint conditions, some signal lines need to be compensated. According to the compensation lengths required by multiple target signal lines to meet the equal-length constraint conditions, the compensation pitch is determined, and then the actual required pitch of the target signal line can be determined.

[0045] According to an embodiment of the present application, by determining a target signal line group and an associated signal group whose degrees of freedom in space meet preset conditions from multiple signal line groups, and based on the wiring constraint data of the target signal line group and the associated signal line group, the minimum initial spacing that can accommodate the target signal line group and the associated signal line group between the processor and the memory module can be determined. By the compensation length required by the target signal lines, the compensation spacing can be determined, and further the actual required layout spacing of the target signal line group under the condition of meeting the equal-length constraint can be determined. Thus, the rationality and accuracy of the reserved space are improved.

[0046] According to an embodiment of the present application, the wiring constraint data includes the signal line width, the intra-group spacing of the signal line group, and the inter-group spacing of the signal line group. Determining the initial spacing between the processor and the memory module based on the wiring constraint data of the target signal line group and multiple associated signal line groups in multiple signal line groups may include: determining the respective widths of the target signal line group and the associated signal line groups based on the signal line width and the intra-group spacing of the signal line group; determining the initial spacing based on the width of the target signal line group, the width of the associated signal line group, and the inter-group spacing of the signal line group.

[0047] The signal line width refers to the physical width of the signal line, and the signal line width can directly affect the impedance and transmission characteristics of the signal. The intra-group spacing of the signal line group refers to the minimum spacing between adjacent signal lines within the same signal line group. The intra-group spacing is used to avoid crosstalk between signal lines. The inter-group spacing of the signal lines refers to the minimum spacing between different signal line groups. The inter-group spacing is used to reduce interference between different signal groups.

[0048] A signal line group includes multiple signal lines. According to the sum of the widths of the multiple signal lines in the signal line group and the spacing between adjacent signal lines, the width of a signal line group can be obtained.

[0049] Figure 3A The schematic diagram of the composition structure of the signal line group according to an embodiment of the present application is shown.

[0050] As Figure 3A shown, in this embodiment, each signal line group includes 8 DQ (Data Input / Output) signal lines and 2 pairs of DQS (Data Strobe) signal lines. The DQS signal appears in the form of a differential signal. There are two pairs of DQS signal lines in the middle, and 4 DQ signal lines above and below, jointly forming a group of data signal lines. The line width of the DQ signal line is a, the line width of the DQS signal line is b, the width between the DQS signal lines is c, and the spacing between the DQ signal lines and the spacing between the DQ signal lines and the DQS signal lines are both d. Then the width S1 of a signal line group = 8a + 9d + 2x(2b + c).

[0051] The initial spacing between the processor and the memory module should be such that it just meets the requirement that both the target signal line group and the associated signal line group can be connected to the corresponding pins of the memory module. At this time, the spacing between the processor and the memory module is the smallest, which can not only meet the routing requirements of the target signal lines and the associated signal lines, but also avoid wasting extra space.

[0052] The following further describes Figures 3B - 3D the method for determining the initial spacing.

[0053] Figure 3B Fig. shows a schematic diagram of a scenario for determining the initial spacing according to an embodiment of the present application.

[0054] As Figure 3B shown, when the rightmost first target signal line 301 in the target signal line group is exactly connected to the corresponding pin 302 of the memory module, the determined initial spacing just meets the requirement that both the target signal line group and the associated signal line group led out from the processor can be connected to the corresponding pins of the memory module. At this time, according to the width of the target signal line group, the width of the associated signal line group, and the inter-group spacing of the signal line groups, the initial spacing can be obtained.

[0055] Figure 3C Fig. shows a scenario diagram of the spacing between the processor and the memory module being less than the initial spacing according to an embodiment of the present application.

[0056] As Figure 3C shown, if the spacing between the processor and the memory module is less than the initial spacing, it causes insufficient space on the left side, so that the path of the rightmost first target signal line 301 is blocked by adjacent signal lines and cannot be connected to the corresponding pin 302 of the memory module.

[0057] Figure 3D Fig. shows a scenario diagram of the spacing between the processor and the memory module being greater than the initial spacing according to an embodiment of the present application.

[0058] As Figure 3D shown, if the spacing between the processor and the memory module is greater than the initial spacing, although the rightmost first target signal line 301 can be connected to the corresponding pin 302 of the memory module, it also results in a surplus of space on the left side, causing waste of space.

[0059] According to the embodiment of the present application, after determining the target signal line group and the associated signal line group, the initial spacing can be quickly and accurately determined through the signal line width, the intra-group spacing of the signal line groups, and the inter-group spacing of the signal lines, improving the efficiency of determining the initial spacing.

[0060] According to an embodiment of the present application, the compensation length is determined as follows: Based on the positions of the pins where the processor and the memory module are respectively connected to the target signal line group, the first compensation length of the target signal line group is determined. The first compensation length is the sum of the first lengths that each of the multiple target signal lines needs to be compensated under the condition of satisfying the equal-length constraint within the group. Based on the routing lengths of the multiple target signal lines between the processor and the memory module when the target signal lines of the target signal line group are routed in a straight line and / or with turns, the second compensation length of the target signal line group is determined. Based on the first compensation length and the second compensation length, the compensation length is determined.

[0061] Since the pins on the processor and the memory module are distributed in different areas, the connection path lengths to the memory module are different. By comparing the pin positions where the target signal lines are connected on the processor and the memory module, the length differences of the target signal lines caused by the pin position differences can be determined. According to the length differences, the first compensation length that each target signal line needs to be compensated can be determined.

[0062] The target signal lines can connect the processor and the memory module in a straight line. However, in some cases, due to factors such as space limitations and signal integrity requirements, the target signal lines need to be routed with turns. Different routing methods will result in different actual routing lengths of the target signal lines between the processor and the memory module. Based on the actual routing lengths of each target signal line, the second compensation length that the multiple target signal lines need to be compensated is determined.

[0063] Exemplarily, the first compensation length and the second compensation length can be added together to obtain the compensation length that the multiple target signal lines need to be compensated.

[0064] According to an embodiment of the present application, by comprehensively considering the initial length mismatch caused by the pin position differences between the processor and the memory module, and the additional length differences caused by the actual routing paths when the target signal lines are routed in a straight line and with turns, the comprehensive compensation length is finally determined, which can accurately quantify and compensate the signal line length deviation caused by the dual factors of hardware layout and routing path.

[0065] According to an embodiment of the present application, determining the first compensation length of the target signal line group based on the positions of the pins where the processor and the memory module are connected to the target signal line group may include: Based on the spacing between multiple pins of the processor along the second direction, determining the first pin compensation length of the target signal line group, where the first direction is perpendicular to the second direction. Based on the spacing between multiple pins of the memory module along the second direction, determining the second pin compensation length of the target signal line group; Based on the first pin compensation length and the second pin compensation length, determining the first compensation length.

[0066] Exemplarily, the pin positions of multiple processors connected to the target signal line group can be obtained, and the pin position of the processor closest to the memory module is used as the first reference position. The distances between the remaining processor pins and the first reference position in the second direction (i.e., the direction perpendicular to the processor) are determined respectively, and the compensation length of each target signal line to the processor pins is obtained. According to the compensation length of each target signal line to the processor pins, the first pin compensation length of the target signal line group is obtained.

[0067] Similarly, the memory pin positions of multiple memory modules connected to the target signal line can be obtained, and the memory pin position closest to the processor is used as the second reference position. The distances between the remaining memory pin positions and the second reference position in the second direction are determined respectively, and the compensation length of each target signal line to the memory pins is obtained. According to the compensation length of each target signal line to the memory pins, the second pin compensation length of the target signal line group is obtained.

[0068] Figure 4 Shows the pin position distribution diagram of the processor and the memory module according to the embodiment of the present application.

[0069] As Figure 4 shown, in this embodiment, multiple pins in the processor 110 are arranged in 4 rows in a queue form. The pins of the processor 110 can be divided into four echelons, represented by C1, C2, C3, and C4. Each echelon represents the pins belonging to the same row position. Similarly, the pins of the memory module 120 are divided into two echelons, represented by D1 and D2. Each echelon also represents the pins belonging to the same row position.

[0070] The pin position coordinates of the processor 110 and the memory module 120 connected to the multiple target signal lines can be obtained by querying the signal data of the multiple target signal lines in the target signal line group. The ordinates of the pins of the processor 110 are arranged in ascending order, and they are successively divided into C1, C2, C3, and C4 echelons. The ordinates of the pins of the memory module 120 are arranged in ascending order, and they are successively divided into D1 and D2 echelons. Taking the ordinate of the C1 echelon as the standard, and calculating the differences between the ordinates of C1 and C2, C3, and C4 respectively, the obtained length differences are the first pin compensation lengths. Similarly, taking the ordinate of the D1 echelon as the standard, calculating the difference between the ordinates of D1 and D2, the obtained length difference is the second pin compensation length. Then, according to the first length difference and the second length difference, the first compensation length is determined.

[0071] According to an embodiment of the present application, by comprehensively quantifying the pin pitch differences between the integrated processor and the memory module in the vertical direction, the initial length differences of the target signal lines caused by uneven pin position distributions are quantified, and based on this, the first compensation length is calculated, which can accurately identify and compensate for the signal line length deviations caused by pin positions in the hardware layout, thereby effectively reducing the deviation risks caused by differences in pin distribution positions.

[0072] According to an embodiment of the present application, based on the routing lengths of multiple target signal lines in a target signal line group between a processor and a memory module when the target signal lines are routed in a straight line and / or with turns, determining the second compensation length of the target signal line group may include: determining the routing manner of the target signal line group between the processor and the memory module, where the routing manner includes the number of turns and the turning angles of the target signal lines; based on the routing manner, determining the length differences between the first target signal line and the i-th target signal line when the target signal lines are routed in a straight line and / or with turns, where i = 2,..., I and I is the number of target signal lines; and determining the second compensation length based on the length differences between the first target signal line and the i-th target signal line.

[0073] The number of turns represents the number of times the direction changes in the path of the target signal line from the processor to the memory module. The turning angle refers to the angle change when the signal line makes a turn, for example, 45 degrees, 90 degrees, etc.

[0074] For example, the target signal line group may start from the processor, first route with a 45-degree turn, then route horizontally, and then route with a 45-degree turn before connecting to the memory module. Therefore, the target signal line group makes 2 turns, and the turning angle is 45 degrees. By clarifying the specific routing path of the target signal line group, it can provide a basis for subsequent length difference calculations.

[0075] Exemplarily, the first target signal line may be the signal line with the longest path. By calculating the length differences between the first target signal line and the second to the I-th target signal lines respectively, the lengths that the second to the I-th target signal lines need to be compensated are obtained.

[0076] According to an embodiment of the present application, by analyzing the routing manner of the target signal lines, calculating the length differences between different signal lines, and determining the second compensation length based on the length differences, the equal-length matching of the target signal lines is achieved.

[0077] According to an embodiment of the present application, based on the routing manner, determining the length difference between the first target signal line and the i-th target signal line in the case of straight and / or turning routing of the target signal line group includes: based on the routing manner, determining a target line segment from the routing path of the target signal line group, where the target line segment represents a line segment that affects the routing difference between multiple target signal lines to meet a preset difference condition; determining the length difference based on the turning angle of the target line segment, the width of the target signal line, the intra-group spacing of the target signal line group, and the spacing of multiple pins of the memory module connected to the target signal line group in the first direction.

[0078] The target line segment refers to a broken line segment in the routing path of the target signal line from the processor to the memory module that significantly affects the routing difference between multiple target signal lines.

[0079] The preset difference condition refers to the tolerance range of the signal line length difference. If the length difference of the broken line segment is higher than the tolerance range, then the broken line segment is the target line segment; if the length difference of the broken line segment is lower than the tolerance range, then the length difference of the broken line segment can be ignored.

[0080] Figure 5 The schematic diagram of determining the length difference between target signal lines according to an embodiment of the present application is shown.

[0081] As Figure 5 shown, in this embodiment, the target signal line group has 12 target signal lines, which are the first target signal line, the second target signal line,..., the twelfth target signal line in sequence from left to right. The target signal line group first turns and routes at 45 degrees, then routes in the horizontal direction, and then turns and routes at 45 degrees again before connecting to the memory module. Among them, the horizontal routing is a broken line segment that significantly affects the routing difference between multiple target signal lines, that is, the target line segment.

[0082] For example, the distance between point A and point B can be determined as X1 according to the spacing of the pins where the first target signal line and the twelfth target signal line are connected to the memory module in the horizontal direction. According to the width of the target signal line and the intra-group width of the target signal line, the vertical distance between different target signals can be determined. For example, the distance between point C and point D is the width S1 of the target signal line group. Since the turning angle is 45 degrees, the distance between point B and point C can be determined as S1. Therefore, the distance between point A and point C can be determined as X1 - S1. Since the target line segment is parallel to the AC segment, the length of the first target signal line on the target line segment can be approximately equal to the length of the AC segment. Therefore, the length of the first target signal line on the target line segment is X1 - S1.

[0083] Based on a similar method, the horizontal spacing X2 between the pins connecting the second target signal line and the twelfth target signal line to the memory module is obtained, and then the length of the second target signal line on the target line segment can be determined as X2 - (S1-a-d), and so on. The lengths of the third to twelfth target signal lines on the target line segment are calculated respectively. After determining the length of each target signal line on the target line segment, the length differences between the target signal lines can be determined.

[0084] According to the embodiments of the present application, by identifying the target line segment, the key factors causing the length differences of the signal lines can be accurately located. By means of parameters such as the turning angle, the signal line width, the intra-group spacing, and the pin spacing, the length differences of the target line segment can be simply and quickly determined.

[0085] According to the embodiments of the present application, determining the compensation spacing between the processor and the memory module based on the compensation lengths required for multiple target signal lines in the target signal line group may include: determining the compensation area that needs to be compensated for the target signal line group in the case of curved routing based on the compensation lengths; and determining the compensation spacing based on the compensation area.

[0086] Determining the compensation area that needs to be compensated for multiple target signal lines in the case of curved routing based on the compensation lengths may include: determining the number of bending times of the target signal line based on the compensation lengths and a preset curved path length, where the curved path length is the increased length of the raised part formed by the target signal line through wire winding; and determining the total area required for the target signal to be routed in a curved manner based on the number of bending times and the area of the raised part. The area of the raised part can be determined according to the bending amplitude and the bending spacing.

[0087] Determining the compensation spacing based on the compensation area may include: determining the compensation spacing based on the total wire-wound area and the spacing between the first pin of the processor and the first pin of the memory module in the first direction. The first pin and the second pin are connected to the same target signal line.

[0088] According to the embodiments of the present application, by calculating the compensation area required in the case of curved routing based on the compensation lengths of the target signal line group and further determining the compensation spacing, equal-length compensation of the target signal lines is achieved.

[0089] Figure 6 A block diagram of a determining device for a circuit layout according to an embodiment of the present application is shown.

[0090] As Figure 6 shown, the determining device 600 includes an acquisition module 610, a first determination module 620, a second determination module 630, and a third determination module 640.

[0091] An acquisition module 610 is configured to acquire routing constraint data of a plurality of signal line groups; wherein, the plurality of signal line groups are used to be routed between a processor and a memory module to connect the processor and the memory module.

[0092] A first determination module 620 is configured to determine an initial spacing between the processor and the memory module based on the routing constraint data of a target signal line group and an associated signal line group among the plurality of signal line groups; the target signal line group is a signal line group among the plurality of signal line groups whose spatial degrees of freedom satisfy a predetermined condition, and the associated signal line group is at least one signal line group among the plurality of signal line groups that affects the spatial degrees of freedom of the target signal line group in a first direction.

[0093] A second determination module 630 is configured to determine a compensation spacing between the processor and the memory module based on the compensation length required by the target signal line group; the compensation length represents the total length that multiple target signal lines in the target signal line group need to be compensated under the condition of satisfying the equal-length constraint within the group.

[0094] A third determination module 640 is configured to determine a layout spacing between the processor and the memory module of the circuit based on the initial spacing and the compensation spacing.

[0095] According to an embodiment of the present application, the routing constraint data includes a signal line width, an intra-group spacing of the signal line group, and an inter-group spacing of the signal line group.

[0096] According to an embodiment of the present application, the first determination module 610 includes a first determination sub-module and a second determination sub-module.

[0097] The first determination sub-module is configured to determine the respective widths of the target signal line group and the associated signal line group based on the signal line width and the intra-group spacing of the signal line group.

[0098] The second determination sub-module is configured to determine the initial spacing based on the width of the target signal line group, the width of the associated signal line group, and the inter-group spacing of the signal line group.

[0099] According to an embodiment of the present application, the compensation length is determined by a third determination sub-module, a fourth determination sub-module, and a fifth determination sub-module in the second determination module 630.

[0100] The third determination sub-module is configured to determine a first compensation length of the target signal line group based on the positions of the pins where the processor and the memory module are respectively connected to the target signal line group, and the first compensation length is the sum of the first lengths that multiple target signal lines need to be compensated respectively under the condition of satisfying the equal-length constraint within the group.

[0101] The fourth determination sub-module is configured to determine a second compensation length of the target signal line group based on the routing lengths of multiple target signal lines between the processor and the memory module when the target signal line group of the target signal line group is routed in a straight line and / or with turns.

[0102] The fifth determination sub-module is configured to determine a compensation length based on the first compensation length and the second compensation length.

[0103] According to an embodiment of the present application, the third determination sub-module includes a first determination unit, a second determination unit, and a third determination unit.

[0104] The first determination unit is configured to determine a first pin compensation length of the target signal line group based on the pitch between multiple pins of the processor along the second direction, where the first direction is perpendicular to the second direction.

[0105] The second determination unit is configured to determine a second pin compensation length of the target signal line group based on the pitch between multiple pins of the memory module along the second direction.

[0106] The third determination unit is configured to determine the first compensation length based on the first pin compensation length and the second pin compensation length.

[0107] According to an embodiment of the present application, the fourth determination sub-module includes a fourth determination unit, a fifth determination unit, and a sixth determination unit.

[0108] The fourth determination unit is configured to determine the routing mode of the target signal line group between the processor and the memory module, where the routing mode includes the number of turns and the turning angles of the target signal lines.

[0109] The fifth determination unit is configured to determine the length difference between the first target signal line and the i-th target signal line of the target signal line group in the case of straight-line and / or turning routing based on the routing mode, where i = 2,..., I, and I is the number of target signal lines.

[0110] The sixth determination unit is configured to determine the second compensation length based on the length difference between the first target signal line and the i-th target signal line.

[0111] According to an embodiment of the present application, the fifth determination unit includes a first determination subunit and a second determination subunit.

[0112] The first determination subunit is configured to determine a target line segment from the routing path of the target signal line based on the routing mode, and the target line segment represents a line segment that affects the routing difference between multiple target signal lines to meet a preset difference condition.

[0113] A second determination subunit, configured to determine a length difference based on a turning angle of a target line segment, a width of a target signal line, an intra-group spacing of a target signal line group, and a spacing of a plurality of pins of a memory module connected to the target signal line group in a first direction.

[0114] According to an embodiment of the present application, the second determination module 630 includes a compensation area determination sub-module and a compensation spacing determination sub-module.

[0115] The compensation area determination sub-module is configured to determine a compensation area that needs to be compensated for a plurality of target signal line groups in the case of a curved trace based on a compensation length.

[0116] The compensation spacing determination sub-module is configured to determine a compensation spacing based on the compensation area.

[0117] According to an embodiment of the present application, any of the acquisition module 610, the first determination module 620, the second determination module 630, and the third determination module 640 can be combined and implemented in one module, or any one of them can be split into multiple modules. Alternatively, at least part of the functions of one or more of these modules can be combined with at least part of the functions of other modules and implemented in one module. According to an embodiment of the present application, at least one of the acquisition module 610, the first determination module 620, the second determination module 630, and the third determination module 640 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on substrate, a system on package, an application specific integrated circuit (ASIC), or can be implemented by any other reasonable means such as integrating or packaging a circuit, etc., in hardware or firmware, or implemented in any one of the three implementation manners of software, hardware, and firmware, or in an appropriate combination of any several of them. Alternatively, at least one of the acquisition module 610, the first determination module 620, the second determination module 630, and the third determination module 640 can be at least partially implemented as a computer program module, and when the computer program module is run, the corresponding functions can be executed.

[0118] Figure 7 A block diagram of an electronic device suitable for implementing the method described above according to an embodiment of the present application is shown. Figure 7 The shown electronic device is only an example and should not bring any limitation to the functions and the usage scope of the embodiments of the present application.

[0119] The electronic device is intended to represent various forms of digital computers, such as, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as, personal digital processors, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are only examples and are not intended to limit the implementation of the present application described herein and / or claimed.

[0120] As Figure 7 shown, the electronic device 700 includes a computing unit 701 that can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 702 or a computer program loaded from a storage unit 708 into a random access memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the electronic device 700 can also be stored. The computing unit 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0121] Multiple components in the electronic device 700 are connected to the I / O interface 705, including: an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, an optical disk, etc.; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 709 allows the electronic device 700 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0122] The computing unit 701 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 executes the various methods and processes described above, such as the testing method. For example, in some embodiments, the testing method can be implemented as a computer software program that is tangibly embodied in a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the testing method described above can be executed. Alternatively, in other embodiments, the computing unit 701 can be configured to execute the testing method in any other suitable manner (e.g., by means of firmware).

[0123] Various embodiments of the systems and techniques described above in this document can be implemented in digital electronic circuitry, integrated circuit systems, field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), application-specific standard products (ASSP), systems-on-a-chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special or general-purpose programmable processor, that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0124] The program code for implementing the methods of the present application can be written in any combination of one or more programming languages. These program codes can be provided to the processor or controller of a general-purpose computer, a special-purpose computer, or other programmable testing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0125] In the context of this application, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0126] To provide for interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide for interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic, speech, or tactile input).

[0127] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of a communication network include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0128] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

[0129] Those skilled in the art can understand that the features described in the various embodiments of the present application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present application. In particular, without departing from the spirit and teachings of the present application, the features described in the various embodiments of the present application can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present application.

[0130] The above describes the embodiments of the present application. However, these embodiments are only for illustrative purposes and not for limiting the scope of the present application. Although the embodiments are described separately above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present application.

Claims

1. A method for determining a circuit layout, characterized in that, Including: Obtaining wiring constraint data for multiple signal line groups; wherein, the multiple signal line groups are used to be laid between a processor and a memory module to connect the processor and the memory module; Based on the wiring constraint data of a target signal line group and an associated signal line group among the multiple signal line groups, determining an initial spacing between the processor and the memory module; the target signal line group is a signal line group among the multiple signal line groups whose spatial degree of freedom meets a predetermined condition, and the associated signal line group is at least one signal line group among the multiple signal line groups that affects the spatial degree of freedom of the target signal line group in a first direction; Based on the compensation length required by the target signal line group, determining a compensation spacing between the processor and the memory module; the compensation length represents the total length that multiple target signal lines in the target signal line group need to be compensated under the condition of meeting the equal-length constraint within the group; Based on the initial spacing and the compensation spacing, determining a layout spacing between the processor and the memory module of the circuit.

2. The method according to claim 1, wherein The wiring constraint data includes a signal line width, an intra-group spacing of the signal line group, and an inter-group spacing of the signal line group; Based on the wiring constraint data of a target signal line group and an associated signal line group among the multiple signal line groups, determining an initial spacing between the processor and the memory module includes: Based on the signal line width and the intra-group spacing of the signal line group, determining the respective widths of the target signal line group and the associated signal line group; Based on the width of the target signal line group, the width of the associated signal line group, and the inter-group spacing of the signal line group, determining the initial spacing.

3. The method according to claim 1, characterized in that The compensation length is determined by the following method: Based on the positions of the pins of the processor and the memory module respectively connected to the target signal line group, determining a first compensation length of the target signal line group, where the first compensation length is the sum of the first lengths that multiple target signal lines need to be compensated respectively under the condition of meeting the equal-length constraint within the group; Based on the routing lengths of multiple target signal lines between the processor and the memory module respectively when the target signal line group is routed in a straight line and / or with turns, determining a second compensation length of the target signal line group; Based on the first compensation length and the second compensation length, determining the compensation length.

4. The method according to claim 3, wherein Based on the positions of the pins of the processor and the memory module respectively connected to the target signal line group, determining the first compensation length of the target signal line group includes: Based on the spacing between multiple pins of the processor along a second direction, determining a first pin compensation length of the target signal line group, where the first direction is perpendicular to the second direction; Based on the spacing between multiple pins of the memory module along the second direction, determining a second pin compensation length of the target signal line group; Based on the first pin compensation length and the second pin compensation length, determining the first compensation length.

5. The method according to claim 3, characterized in that, Determining a second compensation length of the target signal line group based on the routing lengths of multiple target signal lines between the processor and the memory module when the target signal line group is routed in a straight line and / or with turns, includes: Determining the routing manner of the target signal line group between the processor and the memory module, where the routing manner includes the number of turns and the turning angles of the target signal lines; Based on the routing manner, determining the length differences between the first target signal line and the i-th target signal line of the target signal line group when routed in a straight line and / or with turns, where i = 2,..., I, and I is the number of the target signal lines; Based on the length differences between the first target signal line and the i-th target signal line, determining the second compensation length.

6. The method according to claim 5, characterized in that, Based on the routing manner, determining the length differences between the first target signal line and the i-th target signal line of the target signal line group when routed in a straight line and / or with turns, includes: Based on the routing manner, determining target line segments from the routing path of the target signal line group, where the target line segments represent the line segments that affect the routing differences between multiple target signal lines to meet a preset difference condition; Based on the turning angles of the target line segments, the line widths of the target signal lines, the intra-group spacing of the target signal line group, and the spacing of multiple pins of the memory module connected to the target signal line group in a first direction, determining the length differences.

7. The method according to any one of claims 1 to 6, characterized in that Determining a compensation spacing between the processor and the memory module based on the compensation lengths required by multiple target signal lines in the target signal line group, includes: Based on the compensation lengths, determining the compensation area that needs to be compensated when the target signal line group is routed in a bent manner; Based on the compensation area, determining the compensation spacing.

8. A device for determining a circuit layout, characterized in that, Includes: An acquisition module, acquiring the routing constraint data of multiple signal line groups; where multiple signal line groups are used to be routed between the processor and the memory module to connect the processor and the memory module; A first determination module, determining an initial spacing between the processor and the memory module based on the routing constraint data of the target signal line group and the associated signal line group in multiple signal line groups; the target signal line group is a signal line group among multiple signal line groups whose spatial freedom degree meets a predetermined condition, and the associated signal line group is at least one signal line group among multiple signal line groups that affects the spatial freedom degree of the target signal line group in a first direction; A second determination module, determining a compensation spacing between the processor and the memory module based on the compensation length required by the target signal line group; the compensation length represents the total length that multiple target signal lines in the target signal line group need to be compensated under the condition of meeting the equal-length constraint within the group; A third determination module, determining the layout spacing between the processor and the memory module of the circuit based on the initial spacing and the compensation spacing.

9. An electronic device, includes: One or more processors; A memory, configured to store one or more programs, Wherein, when the one or more programs are executed by the one or more processors, the one or more processors are caused to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having executable instructions stored thereon, which when executed by a processor cause the processor to implement the method according to any one of claims 1 to 7.

11. A computer program product, comprising a computer program or instructions, characterized in that, The computer program or instructions, when executed by a processor, implement the steps of the method according to any one of claims 1 to 7.

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