Method, device, equipment and medium for determining circuit layout

Abstract

The present application provides a method, device, equipment and medium for determining a circuit layout, and relates to the field of computer technology. The method comprises: obtaining wiring constraint data of a plurality of signal line groups. Based on the wiring constraint data of a target signal line group and an associated signal line group in the plurality of signal line groups, determining the initial spacing between the processor and the memory module. The target signal line group is a signal line group whose spatial freedom satisfies a predetermined condition among the plurality of signal line groups, and the associated signal line group is at least one signal line group among the plurality of signal line groups that affects the spatial freedom of the target signal line group in the first direction. Based on the compensation length required by the target signal line group, the compensation spacing between the processor and the memory module is determined; the compensation length represents the total length of the target signal line that needs to be compensated for the plurality of target signal lines in the target signal line group under the condition that the target signal line satisfies the equal length constraint within the group. Based on the initial spacing and the compensation spacing, the layout spacing of the processor and the memory module of the circuit is determined.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to a method, apparatus, device, and medium for determining a circuit layout. Background Art

[0002] A server motherboard typically houses a variety of components and signal lines. To save development time, the routing of components and signal lines across the motherboard is often designed in parallel. Therefore, it's necessary to reserve approximate locations for signal line routing between different modules. For example, a certain amount of space is reserved between the processor and memory modules to route the signal lines connecting the processor and memory modules.

[0003] However, if the reserved space is too large, signal lines will be too long, increasing the risk of loss and affecting the space available for other components. If the reserved space is too small, signal lines may not meet spacing and equal length requirements, making it impossible to connect to the processor and memory modules. In related technologies, the reserved space between processors and memory modules is usually determined based on experience, and the rationality and accuracy of the reserved space needs to be improved. Summary of the Invention

[0004] In view of this, the present application provides a method, apparatus, device, and medium for determining a circuit layout.

[0005] One aspect of the present application provides a method for determining a circuit layout, comprising: obtaining routing constraint data of a plurality of signal line groups; wherein the plurality of signal line groups are used to be arranged between a processor and a memory module to connect the processor and the memory module; determining an initial spacing between the processor and the memory module based on routing constraint data of a target signal line group and an associated signal line group in the plurality of signal line groups; the target signal line group is a signal line group in the plurality of signal line groups whose spatial freedom satisfies a predetermined condition, and the associated signal line group is at least one signal line group in the plurality of signal line groups that affects the spatial freedom of the target signal line group in a first direction; determining a compensation spacing between the processor and the memory module based on a required compensation length of the target signal line group; the compensation length represents the total length of the target signal lines that needs to be compensated for when the target signal lines meet the equal length constraint condition within the group; determining the layout spacing of the processor and the memory module of the circuit based on the initial spacing and the compensation spacing.

[0006] Another aspect of the present application provides a circuit layout determination device, characterized in that it includes: an acquisition module, which acquires wiring constraint data of multiple signal line groups; wherein the multiple signal line groups are used to be arranged between the processor and the memory module to connect the processor and the memory module; a first determination module, which determines the initial spacing between the processor and the memory module based on the wiring constraint data of the target signal line group and the associated signal line group in the multiple signal line groups; the target signal line group is a signal line group in the multiple signal line groups whose spatial freedom meets a predetermined condition, and the associated signal line group is at least one signal line group in the multiple signal line groups that affects the spatial freedom of the target signal line group in the first direction; a second determination module, which determines the compensation spacing between the processor and the memory module based on the compensation length required by the target signal line group; the compensation length represents the length that multiple target signal lines in the target signal line group need to be compensated when the target signal line meets the equal length constraint condition within the group; a third determination module, which determines the layout spacing between the processor and the memory module of the circuit based on the initial spacing and the compensation spacing.

[0007] Another aspect of the present application provides an electronic device, comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the above method.

[0008] Another aspect of the present application further provides a computer-readable storage medium having a computer program or instructions stored thereon, which implements the steps of the above method when the computer program or instructions are executed by a processor.

[0009] Another aspect of the present application further provides a computer program product, including a computer program or instructions, which implement the steps of the above method when the computer program or instructions are executed by a processor.

[0010] According to the technical solution of this application, by identifying a target signal line group and associated signal groups whose spatial freedom meets preset conditions from multiple signal line groups, and based on the routing constraint data of the target signal line group and the associated signal line group, the minimum initial spacing between the processor and the memory module that can accommodate the target signal line group and the associated signal line group can be determined. By determining the compensation spacing by the required compensation length of the target signal line group, the actual layout spacing required for the target signal line group under the equal length constraint can be further determined, thereby improving the rationality and accuracy of the reserved space. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings.

[0012] Figure 1An application scenario diagram of a method for determining a circuit layout according to an embodiment of the present application is shown.

[0013] Figure 2 A flow chart of a method for determining a circuit layout according to an embodiment of the present application is shown.

[0014] Figure 3A A schematic diagram of the structure of a signal line group according to an embodiment of the present application is shown.

[0015] Figure 3B A schematic diagram of a scenario for determining an initial distance according to an embodiment of the present application is shown.

[0016] Figure 3C A diagram showing a scenario in which the distance between the processor and the memory module according to an embodiment of the present application is smaller than the initial distance.

[0017] Figure 3D A diagram showing a scenario in which the distance between the processor and the memory module according to an embodiment of the present application is greater than the initial distance.

[0018] Figure 4 The figure shows the pin position distribution diagram of the processor and memory module according to the embodiment of the present application.

[0019] Figure 5 A schematic diagram illustrating a principle for determining the length difference between target signal lines according to an embodiment of the present application is shown.

[0020] Figure 6 A module diagram of a circuit layout determination device according to an embodiment of the present application is shown.

[0021] Figure 7 A block diagram of an electronic device suitable for implementing the method described above according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0023] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The terms "comprise," "include," etc. used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0024] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0025] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0026] Figure 1 The following schematically illustrates an application scenario of a method for determining a circuit layout according to an embodiment of the present application.

[0027] like Figure 1 As shown, the application scenario of the circuit layout determination method may include a processor 110 and a memory module 120. The processor 110 and the memory module 120 are connected via a plurality of signal line groups 130. The signal line group 130 includes a plurality of signal lines 131. The signal lines 131 are provided between the processor 110 and the memory module 120 and are respectively connected to corresponding pins of the processor 110 and the memory module 120.

[0028] Illustratively, the processor 110 may be, for example, a central processing unit (CPU) or another type of general-purpose processor. The memory module 120 may be, for example, a dual inline memory module (DIMM). The signal line 130 may be, for example, a DDR (Double Data Rate) signal line.

[0029] Figure 2 A flow chart of a method for determining a circuit layout according to an embodiment of the present application is shown.

[0030] like Figure 2 As shown, the method includes operations S210 to S240.

[0031] In operation S210 , routing constraint data of a plurality of signal line groups is acquired; wherein the plurality of signal line groups are used to be routed between a processor and a memory module to connect the processor and the memory module.

[0032] In operation S220, an initial spacing between the processor and the memory module is determined based on routing constraint data of a target signal line group and associated signal line groups among the multiple signal line groups; the target signal line group is a signal line group among the multiple signal line groups whose spatial freedom meets a predetermined condition, and the associated signal line group is at least one signal line group among the multiple signal line groups that affects the spatial freedom of the target signal line group in the first direction.

[0033] In operation S230, a compensation spacing between the processor and the memory module is determined based on the compensation length required by the target signal line group; the compensation length represents the total length of multiple target signal lines in the target signal line group that needs to be compensated while satisfying the equal length constraint within the group.

[0034] In operation S240 , a layout spacing between the processor and the memory module of the circuit is determined based on the initial spacing and the compensation spacing.

[0035] Routing constraint data refers to data that ensures that the layout of signal lines meets the layout constraint conditions. The layout constraint conditions include, for example, signal line width conditions, signal line spacing conditions, and equal length constraints, so that the layout of signal lines meets the requirements of electrical performance, signal integrity, electromagnetic compatibility, etc.

[0036] Multiple signal lines are routed between the processor and memory modules. For example, between the CPU and DIMMs, there are eight data signal lines, one ECC (Error Correcting Code) signal line, one Clk (Clock) signal line, and two A_C (Address / Command) signal lines. The Clk signal line group is located in the center, with the first through fourth data signal lines, one A_C signal line, and the ECC signal line group located to the left of the Clk signal line group. The fifth through eighth data signal lines and one A_C signal line group are located to the right of the Clk signal line group.

[0037] Spatial freedom indicates the degree to which a signal line group can flexibly adjust its position, routing, and layout. It reflects the available routing space and the range of routing adjustments that can be made while satisfying routing constraints. The spatial freedom of a signal line group is affected by the spacing between adjacent signal line groups, as well as between the processor and memory modules.

[0038] The predetermined condition may be a condition that satisfies the minimum spatial freedom among the multiple signal line groups. The target signal line group may be the signal line group with the minimum spatial freedom among the multiple signal line groups. The first direction may be, for example, a horizontal direction parallel to the processor and the memory module. The associated signal line group may be, for example, a signal line group that affects the spatial freedom of the target signal line group in the horizontal direction.

[0039] Before determining the initial spacing, the routing pattern of each signal line group may be determined first, and the target signal line group and the associated signal line group may be determined based on the routing pattern of each signal line group.

[0040] For example, the routing pattern of the outermost signal line group can be determined first. Based on the routing pattern, it can be determined whether the outermost signal line group occupies the space between the processor and the memory module. If so, the outermost signal line group is an associated signal line group. If not, the outermost signal line group is not an associated signal line group. Similarly, the same method can be used to further determine whether the second outermost signal line group is an associated signal line group.

[0041] Continuing with the CPU and DIMM example, since the Clk signal line group has six signal line groups on its left and five signal line groups on its right, respectively, if the space on the left meets the signal line group routing constraints, then the space on the right must also meet them. Since the first data signal line group is located on the outermost side, it has the greatest spatial freedom. The second and third data signal line groups have space to extend toward the first signal line group and have the next greatest spatial freedom. The A_C signal line group and the Clk signal line group are located in the center, and their signal line connections are essentially perpendicular to the CPU and DIMM, essentially meeting the equal length constraint. The ECC signal line group can compress the space of the fourth data signal line group to the left, so the fourth data signal line group is the target signal line group. If the space of the target signal line group meets the routing constraints, then the space of the remaining signal line groups also meets the routing constraints.

[0042] If the outermost data signal line group, the first, does not affect the spatial freedom of the fourth data signal line group through routing, while the second and third data signal line groups affect the fourth data signal line group's horizontal freedom to the left, then the second and third data signal line groups are considered associated signal line groups. The initial spacing between the processor and memory module is then determined based on the routing constraint data for the second, third, and fourth data signal line groups.

[0043] The initial spacing represents the minimum spacing between the processor and the memory module that can accommodate the target signal line group and the associated signal line group without considering the equal length constraint.

[0044] Due to the different sizes of the processor and memory modules, the spacing between the processor pins and memory module pins connecting different target signal lines varies. To meet the equal length constraint, some signal lines need to be compensated. Based on the compensation lengths required for multiple target signal lines to meet the equal length constraint, the compensation spacing is determined, which in turn determines the actual required spacing between the target signal lines.

[0045] According to an embodiment of the present application, by determining a target signal line group and associated signal groups whose spatial freedom meets preset conditions from multiple signal line groups, and based on the routing constraint data of the target signal line group and the associated signal line group, the minimum initial spacing between the processor and the memory module that can accommodate the target signal line group and the associated signal line group can be determined. By determining the compensation spacing by the required compensation length of the target signal line, the actual layout spacing required for the target signal line group under the condition of satisfying the equal length constraint can be further determined, thereby improving the rationality and accuracy of the reserved space.

[0046] According to an embodiment of the present application, the routing constraint data includes signal line width, intra-group spacing of signal line groups, and inter-group spacing of signal line groups. Determining the initial spacing between the processor and the memory module based on the routing constraint data of a target signal line group and a plurality of associated signal line groups in the plurality of signal line groups may include: determining the width of each of the target signal line group and the associated signal line groups based on the signal line width and the intra-group spacing of the signal line groups; and determining the initial spacing based on the width of the target signal line group, the width of the associated signal line groups, and the inter-group spacing of the signal line groups.

[0047] Signal line width refers to the physical width of a signal line, which directly affects the signal's impedance and transmission characteristics. Intra-group spacing refers to the minimum spacing between adjacent signal lines within the same signal line group. Intra-group spacing is used to prevent crosstalk between signal lines. Inter-group spacing refers to the minimum spacing between different signal line groups. Inter-group spacing is used to reduce interference between different signal groups.

[0048] A signal line group includes multiple signal lines. The width of a signal line group can be obtained according to the sum of the widths of the multiple signal lines in the signal line group and the spacing between adjacent signal lines.

[0049] Figure 3A A schematic diagram of the structure of a signal line group according to an embodiment of the present application is shown.

[0050] like Figure 3A As shown, in this embodiment, each signal line group includes eight DQ (Data Input / Output) signal lines and two pairs of DQS (Data Strobe) signal lines. The DQS signal is presented as a differential signal, with two pairs of DQS signal lines in the middle, four DQ signal lines above and below, forming a data signal line group. The width of the DQ signal line is a, the width of the DQS signal line is b, the width between DQS signal lines is c, and the spacing between DQ signal lines and the spacing between DQ signal lines are both d. Therefore, the width of a signal line group, S1, = 8a + 9d + 2x(2b + c).

[0051] The initial spacing between the processor and the memory module should be just enough to ensure that both the target signal line group and the associated signal line group can be connected to the corresponding pins of the memory module. At this time, the spacing between the processor and the memory module is minimal, which can not only meet the routing requirements of the target signal lines and the associated signal lines, but also avoid wasting excess space.

[0052] The following combination Figure 3B to Figure 3D The method of determining the initial spacing is further explained.

[0053] Figure 3B A schematic diagram of a scenario for determining an initial distance according to an embodiment of the present application is shown.

[0054] like Figure 3B As shown, when the first target signal line 301 on the far right of the target signal line group is connected to the corresponding pin 302 of the memory module, the initial spacing is determined to ensure that both the target signal line group and the associated signal line group extending from the processor can be connected to the corresponding pins of the memory module. In this case, the initial spacing can be determined based on the width of the target signal line group, the width of the associated signal line group, and the spacing between the signal line groups.

[0055] Figure 3C A diagram showing a scenario in which the distance between the processor and the memory module according to an embodiment of the present application is smaller than the initial distance.

[0056] like Figure 3C As shown, if the spacing between the processor and the memory module is smaller than the initial spacing, resulting in insufficient space on the left, the path of the first target signal line 301 on the right is blocked by the adjacent signal line and cannot be connected to the corresponding pin 302 of the memory module.

[0057] Figure 3D A diagram showing a scenario in which the distance between the processor and the memory module according to an embodiment of the present application is greater than the initial distance.

[0058] like Figure 3D As shown, if the distance between the processor and the memory module is greater than the initial distance, although the first target signal line 301 on the right can be connected to the corresponding pin 302 of the memory module, it also leaves a margin on the left side, resulting in space waste.

[0059] According to an embodiment of the present application, after determining the target signal line group and the associated signal line group, the initial spacing can be quickly and accurately determined through the signal line width, the intra-group spacing of the signal line group, and the inter-group spacing of the signal lines, thereby improving the efficiency of determining the initial spacing.

[0060] According to an embodiment of the present application, the compensation length is determined as follows: based on the positions of the pins of the processor and memory module connected to the target signal line group, a first compensation length of the target signal line group is determined, where the first compensation length is the sum of the first lengths that need to be compensated for each of the multiple target signal lines, while satisfying the equal length constraint within the group. A second compensation length of the target signal line group is determined based on the routing lengths of the multiple target signal lines between the processor and the memory module, when the target signal lines of the target signal line group are routed in straight lines and / or with turns. The compensation length is determined based on the first compensation length and the second compensation length.

[0061] Because the pins on the processor and memory module are distributed in different areas, the lengths of the connection paths to the memory module differ. By comparing the pin locations of the target signal lines on the processor and memory module, the length differences of the target signal lines caused by these differences can be determined. Based on these length differences, a first compensation length to be compensated for each target signal line can be determined.

[0062] The target signal line can connect the processor and memory module in a straight line. However, in some cases, due to factors such as space constraints and signal integrity requirements, the target signal line needs to be routed in a zigzag pattern. Different routing methods can result in different actual routing lengths of the target signal line between the processor and memory module. Based on the actual routing length of each target signal line, a second compensation length is determined for each target signal line.

[0063] Exemplarily, the first compensation length and the second compensation length may be added together to obtain the compensation lengths that need to be compensated for the plurality of target signal lines.

[0064] According to the embodiments of the present application, by comprehensively considering the initial length mismatch caused by the difference in the pin positions of the processor and the memory module, as well as the additional length difference of the target signal line due to the actual routing path in the straight line and turning routing conditions, the comprehensive compensation length is finally determined, which can accurately quantify and compensate for the signal line length deviation caused by the dual factors of hardware layout and routing path.

[0065] According to an embodiment of the present application, determining a first compensation length of a target signal line group based on positions of pins of a processor and a memory module connected to the target signal line group may include: determining a first pin compensation length of the target signal line group based on a spacing between multiple pins of the processor along a second direction, wherein the first direction is perpendicular to the second direction; determining a second pin compensation length of the target signal line group based on a spacing between multiple pins of the memory module along the second direction; and determining the first compensation length based on the first pin compensation length and the second pin compensation length.

[0066] For example, the pin positions of multiple processors connected to the target signal line group can be obtained. The pin position of the processor closest to the memory module is used as a first reference position. The spacing between the remaining processor pins and the first reference position in a second direction (i.e., a direction perpendicular to the processor) is determined to obtain the compensation length of each target signal line relative to the processor pin. Based on the compensation length of each target signal line relative to the processor pin, the first pin compensation length of the target signal line group is obtained.

[0067] Similarly, the memory pin positions of multiple memory modules connected to the target signal line can be obtained. The memory pin position closest to the processor is used as the second reference position. The distances between the remaining memory pin positions and the second reference position in the second direction are determined to obtain the compensation length of each target signal line for the memory pin. Based on the compensation length of each target signal line for the memory pin, the second pin compensation length of the target signal line group is obtained.

[0068] Figure 4 The figure shows the pin position distribution diagram of the processor and memory module according to the embodiment of the present application.

[0069] like Figure 4 As shown, in this embodiment, the plurality of pins in the processor 110 are arranged in four rows in a queue format. The pins of the processor 110 can be divided into four echelons, denoted by C1, C2, C3, and C4, with each echelon representing pins belonging to the same row. Similarly, the pins of the memory module 120 are divided into two echelons, denoted by D1 and D2, with each echelon also representing pins belonging to the same row.

[0070] By querying the signal data of multiple target signal lines in the target signal line group, the pin position coordinates of the processor 110 and the memory module 120 connected to the multiple target signal lines can be obtained. Arrange the vertical coordinates of the pins of the processor 110 from small to large and divide them into C1, C2, C3, and C4 echelons in turn. Arrange the vertical coordinates of the pins of the memory module 120 from small to large and divide them into D1 and D2 echelons in turn. Take the vertical coordinate of the C1 echelon as the standard, and calculate the difference between the vertical coordinates of C1 and C2, C3, and C4 respectively. The length difference obtained is the first pin compensation length. Similarly, take the vertical coordinate of the D1 echelon as the standard, calculate the difference between the vertical coordinates of D1 and D2, and the length difference obtained is the second pin compensation length. Then determine the first compensation length based on the first length difference and the second length difference.

[0071] According to the embodiments of the present application, by comprehensively considering the pin spacing differences between the processor and the memory module in the vertical direction, the initial length difference of the target signal line due to the uneven distribution of the pin positions is quantified, and the first compensation length is calculated based on this. This can accurately identify and compensate for the signal line length deviation caused by the pin position in the hardware layout, thereby effectively reducing the deviation risk caused by the difference in the pin distribution position.

[0072] According to an embodiment of the present application, based on the routing lengths of multiple target signal lines of the target signal line group between the processor and the memory module when the target signal lines are routed in a straight line and / or with turns, determining the second compensation length of the target signal line group may include: determining a routing method of the target signal line group between the processor and the memory module, wherein the routing method includes the number of turns and the turning angle of the turn made by the target signal line; based on the routing method, determining the length difference between the first target signal line and the i-th target signal line when the target signal lines are routed in a straight line and / or with turns, wherein i=2,…,I,I is the number of target signal lines; determining the second compensation length based on the length difference between the first target signal line and the i-th target signal line.

[0073] The number of turns indicates the number of times the target signal line changes direction along its path from the processor to the memory module. The turning angle refers to the angle change of the signal line during the turn, for example, 45 degrees or 90 degrees.

[0074] For example, a target signal line group might start from the processor, first make a 45-degree turn, then run horizontally, and then make another 45-degree turn before connecting to the memory module. Therefore, this target signal line group makes two turns, each at a 45-degree angle. By clarifying the specific routing path of the target signal line group, we can provide a basis for subsequent length difference calculations.

[0075] Exemplarily, the first target signal line may be the signal line with the longest path. By respectively calculating the length difference between the first target signal line and the second to first target signal lines, the lengths of the second to first target signal lines that need to be compensated are obtained.

[0076] According to an embodiment of the present application, by analyzing the routing pattern of the target signal line, calculating the length difference between different signal lines, and determining the second compensation length based on the length difference, equal length matching of the target signal line is achieved.

[0077] According to an embodiment of the present application, based on the routing method, the length difference between the first target signal line and the i-th target signal line of the target signal line group in the case of straight and / or turning routing is determined, including: based on the routing method, determining the target line segment from the routing path of the target signal line group, the target line segment being characterized as a line segment that affects the routing difference between multiple target signal lines and satisfies a preset difference condition; determining the length difference based on the turning angle of the target line segment, the width of the target signal line, the intra-group spacing of the target signal line group, and the spacing of multiple pins of the memory module connected to the target signal line group in the first direction.

[0078] The target line segment refers to a broken line segment that significantly affects the routing difference between multiple target signal lines in the routing path of the target signal line from the processor to the memory module.

[0079] The preset difference condition refers to the tolerance range for signal line length differences. If the length difference of a broken line segment exceeds the tolerance range, the broken line segment is considered the target segment. If the length difference of a broken line segment is below the tolerance range, the length difference of the broken line segment is ignored.

[0080] Figure 5 A schematic diagram illustrating a principle for determining the length difference between target signal lines according to an embodiment of the present application is shown.

[0081] like Figure 5 As shown, in this embodiment, the target signal line group includes 12 target signal lines, identified from left to right as the first target signal line, the second target signal line, ..., the 12th target signal line. The target signal line group first makes a 45-degree turn, then runs horizontally, and then makes another 45-degree turn before connecting to the memory module. The horizontal routing is the broken line segment that significantly affects the routing differences between the multiple target signal lines, i.e., the target line segment.

[0082] For example, the distance between point A and point B can be determined as X1 based on the horizontal spacing between the pins connecting the first and 12th target signal lines to the memory module. The vertical distance between different target signals can be determined based on the width of the target signal line and the width within the target signal line group. For example, the distance between point C and point D is the width S1 of the target signal line group. Since the turning angle is 45 degrees, the distance between point B and point C can be determined as S1, therefore, the distance between point A and point C can be determined to be X1- Since the target line segment is parallel to the AC segment, the length of the first target signal line in the target line segment can be approximately equal to the length of the AC segment. Therefore, the length of the first target signal line in the target line segment is X1- S1.

[0083] Based on a similar method, the horizontal distance between the pins connecting the second target signal line and the 12th target signal line to the memory module is X2, and the length of the second target signal line in the target line segment can be determined to be X2- (S1-ad), and so on, calculate the lengths of the 3rd to 12th target signal lines in the target line segment. After determining the length of each target signal line in the target line segment, the length difference between the target signal lines can be determined.

[0084] According to the embodiments of the present application, by identifying the target line segment, the key factors that cause signal line length differences can be accurately located. By using parameters such as turning angle, signal line width, intra-group spacing, and pin spacing, the length difference of the target line segment can be easily and quickly determined.

[0085] According to an embodiment of the present application, determining the compensation spacing between the processor and the memory module based on the compensation lengths required for multiple target signal lines in the target signal line group may include: determining the compensation area that needs to be compensated for the target signal line group in the case of curved routing based on the compensation length; and determining the compensation spacing based on the compensation area.

[0086] Determining the compensation areas required for curved routing of multiple target signal lines based on the compensation lengths may include: determining the number of bends required for the target signal lines based on the compensation lengths and a predetermined bending path length, where the bending path length is the length of a raised portion formed by winding the target signal lines; and determining the total area required for curved routing of the target signal lines based on the number of bends and the area of ​​the raised portion. The area of ​​the raised portion may be determined based on the bend amplitude and bend spacing.

[0087] Determining the compensation spacing based on the compensation area may include determining the compensation spacing based on a total area of ​​the wiring and a spacing in a first direction between a first pin of the processor and a first pin of the memory module. The first pin and the second pin are connected to the same target signal line.

[0088] According to an embodiment of the present application, by calculating the compensation area required for curved routing based on the compensation length of the target signal line group, and further determining the compensation spacing, equal length compensation of the target signal lines is achieved.

[0089] Figure 6 A module diagram of a circuit layout determination device according to an embodiment of the present application is shown.

[0090] like Figure 6 As shown, the determination device 600 includes an acquisition module 610 , a first determination module 620 , a second determination module 630 and a third determination module 640 .

[0091] The acquisition module 610 is configured to acquire routing constraint data of a plurality of signal line groups, wherein the plurality of signal line groups are configured to be arranged between a processor and a memory module to connect the processor and the memory module.

[0092] The first determination module 620 determines the initial spacing between the processor and the memory module based on the routing constraint data of the target signal line group and the associated signal line group in the multiple signal line groups; the target signal line group is a signal line group in the multiple signal line groups whose spatial freedom meets the predetermined conditions, and the associated signal line group is at least one signal line group in the multiple signal line groups that affects the spatial freedom of the target signal line group in the first direction.

[0093] The second determination module 630 determines the compensation spacing between the processor and the memory module based on the compensation length required by the target signal line group; the compensation length represents the total length of multiple target signal lines in the target signal line group that need to be compensated while satisfying the equal length constraint within the group.

[0094] The third determining module 640 determines a layout spacing between the processor and the memory module of the circuit based on the initial spacing and the compensation spacing.

[0095] According to an embodiment of the present application, the wiring constraint data includes signal line width, intra-group spacing of signal line groups, and inter-group spacing of signal line groups.

[0096] According to an embodiment of the present application, the first determining module 610 includes a first determining submodule and a second determining submodule.

[0097] The first determining submodule is configured to determine the widths of the target signal line group and the associated signal line group based on the signal line widths and the intra-group spacings of the signal line groups.

[0098] The second determining submodule is configured to determine an initial spacing based on the width of the target signal line group, the width of the associated signal line group, and the spacing between the signal line groups.

[0099] According to an embodiment of the present application, the compensation length is determined by the third determining submodule, the fourth determining submodule, and the fifth determining submodule in the second determining module 630 .

[0100] The third determination submodule is used to determine the first compensation length of the target signal line group based on the positions of the pins of the processor and the memory module connected to the target signal line group respectively. The first compensation length is the sum of the first lengths that need to be compensated for each of the multiple target signal lines under the condition of satisfying the equal length constraint within the group.

[0101] The fourth determination submodule is used to determine the second compensation length of the target signal line group based on the routing lengths of multiple target signal lines between the processor and the memory module when the target signal line group is routed in a straight line and / or a turning line.

[0102] The fifth determining submodule is configured to determine the compensation length based on the first compensation length and the second compensation length.

[0103] According to an embodiment of the present application, the third determining submodule includes a first determining unit, a second determining unit, and a third determining unit.

[0104] The first determining unit is configured to determine a first pin compensation length of the target signal line group based on a spacing between a plurality of pins of the processor along a second direction, wherein the first direction is perpendicular to the second direction.

[0105] The second determining unit is configured to determine a second pin compensation length of the target signal line group based on a spacing between a plurality of pins of the memory module along a second direction.

[0106] The third determining unit is configured to determine the first compensation length based on the first pin compensation length and the second pin compensation length.

[0107] According to an embodiment of the present application, the fourth determining submodule includes a fourth determining unit, a fifth determining unit, and a sixth determining unit.

[0108] The fourth determining unit is configured to determine a routing pattern of the target signal line group between the processor and the memory module, wherein the routing pattern includes the number of turns and the turning angles of the target signal line.

[0109] The fifth determination unit is used to determine the length difference between the first target signal line and the i-th target signal line in the target signal line group when the target signal line group is routed in a straight line and / or a turning line based on the routing method, where i=2,…,I, I is the number of target signal lines.

[0110] The sixth determining unit is configured to determine a second compensation length based on a length difference between the first target signal line and the i-th target signal line.

[0111] According to an embodiment of the present application, the fifth determining unit includes a first determining subunit and a second determining subunit.

[0112] The first determining subunit is configured to determine a target line segment from a routing path of a target signal line based on a routing mode, where the target line segment is characterized as a line segment that affects routing differences between multiple target signal lines and satisfies a preset difference condition.

[0113] The second determining subunit is configured to determine the length difference based on the turning angle of the target line segment, the width of the target signal line, the intra-group spacing of the target signal line group, and the spacing in the first direction of multiple pins of the memory module connected to the target signal line group.

[0114] According to an embodiment of the present application, the second determination module 630 includes a compensation area determination submodule and a compensation distance determination submodule.

[0115] The compensation area determination submodule is used to determine the compensation area that needs to be compensated for multiple target signal line groups in the case of curved routing based on the compensation length.

[0116] The compensation distance determination submodule is used to determine the compensation distance based on the compensation area.

[0117] According to embodiments of the present application, any multiple modules among the acquisition module 610, the first determination module 620, the second determination module 630, and the third determination module 640 may be combined into a single module, or any one of these modules may be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of other modules and implemented in a single module. According to embodiments of the present application, at least one of the acquisition module 610, the first determination module 620, the second determination module 630, and the third determination module 640 may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or may be implemented in hardware or firmware through any other reasonable means of circuit integration or packaging, or may be implemented in any one of the three implementation methods of software, hardware, and firmware, or any appropriate combination of any of these. Alternatively, at least one of the acquisition module 610 , the first determination module 620 , the second determination module 630 , and the third determination module 640 may be at least partially implemented as a computer program module, which may perform corresponding functions when executed.

[0118] Figure 7 A block diagram of an electronic device suitable for implementing the method described above according to an embodiment of the present application is shown. Figure 7 The electronic device shown is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0119] Electronic device is intended to refer to various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic device may also refer to various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are intended to be examples only and are not intended to limit the implementation of the present application described and / or claimed herein.

[0120] like Figure 7 As shown, electronic device 700 includes a computing unit 701, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 702 or a computer program loaded from a storage unit 708 into a random access memory (RAM) 703. Various programs and data required for the operation of electronic device 700 may also be stored in RAM 703. Computing unit 701, ROM 702, and RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to bus 704.

[0121] Multiple components in the electronic device 700 are connected to the I / O interface 705, including an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, an optical disk, etc.; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 709 allows the electronic device 700 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0122] The computing unit 701 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as the testing method. For example, in some embodiments, the testing method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program may be loaded and / or installed onto the electronic device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the testing method described above may be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to perform the testing method via any other suitable means (e.g., via firmware).

[0123] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-a-chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0124] The program code for implementing the method of the present application can be written in any combination of one or more programming languages. Such program code can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable test device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0125] In the context of this application, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or apparatus. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0126] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0127] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0128] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0129] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

[0130] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A method for determining a circuit layout, characterized in that: include: Acquire routing constraint data of a plurality of signal line groups; wherein the plurality of signal line groups are used to be arranged between a processor and a memory module to connect the processor and the memory module; Based on routing constraint data of a target signal line group and associated signal line groups among the plurality of signal line groups, an initial spacing between the processor and the memory module is determined; the target signal line group is a signal line group among the plurality of signal line groups whose spatial freedom satisfies a predetermined condition, and the associated signal line group is at least one signal line group among the plurality of signal line groups that affects the spatial freedom of the target signal line group in a first direction; the spatial freedom represents the degree to which the position, direction, and layout of the signal line group can be adjusted, and the spatial freedom is affected by the spacing between adjacent signal line groups on both sides and between the processor and the memory module; the predetermined condition is a condition that satisfies the minimum spatial freedom among the plurality of signal line groups; determining a compensation spacing between the processor and the memory module based on a compensation length required by the target signal line group; the compensation length represents a total length of a plurality of target signal lines in the target signal line group that needs to be compensated while satisfying an equal length constraint within the group; A layout spacing between the processor and the memory module of the circuit is determined based on the initial spacing and the compensated spacing.

2. The method according to claim 1, characterized in that The routing constraint data includes signal line width, intra-group spacing of signal line groups, and inter-group spacing of signal line groups; Determining an initial spacing between the processor and the memory module based on routing constraint data of a target signal line group and associated signal line groups in the plurality of signal line groups includes: determining the widths of the target signal line group and the associated signal line group based on the signal line width and the intra-group spacing of the signal line group; The initial spacing is determined based on the width of the target signal line group, the width of the associated signal line group, and the spacing between the signal line groups.

3. The method according to claim 1, characterized in that The compensation length is determined as follows: determining, based on positions of pins of the processor and the memory module respectively connected to the target signal line group, a first compensation length of the target signal line group, the first compensation length being the sum of first lengths of each of the plurality of target signal lines that need to be compensated under a condition that an equal length constraint within the group is satisfied; determining a second compensation length of the target signal line group based on the routing lengths of the plurality of target signal lines between the processor and the memory module when the target signal line group is routed in a straight line and / or a turning line; The compensation length is determined based on the first compensation length and the second compensation length.

4. The method according to claim 3, characterized in that Determining a first compensation length of the target signal line group based on positions of pins of the processor and the memory module respectively connected to the target signal line group includes: determining a first pin compensation length of the target signal line group based on a spacing between a plurality of pins of the processor along a second direction, wherein the first direction is perpendicular to the second direction; determining a second pin compensation length of the target signal line group based on a spacing between a plurality of pins of the memory module along the second direction; The first compensation length is determined based on the first pin compensation length and the second pin compensation length.

5. The method according to claim 3, characterized in that Determining a second compensation length of the target signal line group based on the routing lengths of the plurality of target signal lines between the processor and the memory module when the target signal line group is routed in a straight line and / or a turning line includes: Determining a routing pattern of the target signal line group between the processor and the memory module, wherein the routing pattern includes the number of turns and the turning angles of the target signal lines; Based on the routing mode, determining a length difference between a first target signal line and an i-th target signal line in the target signal line group when the target signal line group is routed in a straight line and / or a turning line, where i=2, ..., 1, and I is the number of the target signal lines; The second compensation length is determined based on a length difference between the first target signal line and the i-th target signal line.

6. The method according to claim 5, characterized in that Determining, based on the routing mode, a length difference between a first target signal line and an i-th target signal line in the target signal line group when the target signal line group is routed in a straight line and / or a turning line, comprising: Based on the routing mode, determining a target line segment from the routing path of the target signal line group, wherein the target line segment is characterized as a line segment that affects the routing difference between the plurality of target signal lines to meet a preset difference condition; The length difference is determined based on the turning angle of the target line segment, the signal line width of the target signal line, the intra-group spacing of the target signal line group, and the spacing in the first direction of multiple pins of the memory module connected to the target signal line group.

7. The method according to any one of claims 1 to 6, characterized in that: Determining a compensation distance between the processor and the memory module based on compensation lengths required by a plurality of target signal lines in a target signal line group includes: Based on the compensation length, determining a compensation area of ​​the target signal line group that needs to be compensated in a curved routing situation; The compensation distance is determined based on the compensation area.

8. A circuit layout determination device, characterized in that: include: An acquisition module is configured to acquire routing constraint data of a plurality of signal line groups, wherein the plurality of signal line groups are used to be arranged between a processor and a memory module to connect the processor and the memory module; a first determining module, configured to determine an initial spacing between the processor and the memory module based on routing constraint data of a target signal line group and associated signal line groups among the plurality of signal line groups; the target signal line group being a signal line group among the plurality of signal line groups whose spatial freedom satisfies a predetermined condition, and the associated signal line group being at least one signal line group among the plurality of signal line groups that affects the spatial freedom of the target signal line group in a first direction; the spatial freedom representing the degree to which a signal line group can adjust its position, direction, and layout, and the spatial freedom being affected by the spacing between adjacent signal line groups on both sides and between the processor and the memory module, and the predetermined condition representing the condition with the smallest spatial freedom among the plurality of signal line groups; A second determining module determines a compensation spacing between the processor and the memory module based on a compensation length required by the target signal line group; the compensation length represents a total length of a plurality of target signal lines in the target signal line group that needs to be compensated while satisfying an equal length constraint within the group; A third determining module determines a layout spacing between the processor and the memory module of the circuit based on the initial spacing and the compensation spacing.

9. An electronic device comprising: one or more processors; a memory for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors are enabled to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, causes the processor to implement the method according to any one of claims 1 to 7.

11. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instructions are executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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