A method and system for evaluating a multi-level UPQC topology

Abstract

The present application relates to the technical field of level data evaluation, and more particularly to a multi-level UPQC topology evaluation method and system. The method comprises the following steps: obtaining a multi-level UPQC design drawing; extracting design parameters from the multi-level UPQC design drawing to obtain UPQC design parameters; deconstructing the electrical coordination mode according to the UPQC design parameters; performing electrical energy connection topology mapping based on the electrical coordination mode to obtain connection topology data; and constructing a UPQC topology structure model based on the connection topology data and power distribution path data. Through data processing technology and simulation technology, the present application can accurately identify the power flow path and detect the steady-state performance of the UPQC topology structure, thereby accurately evaluating the performance indicators of the multi-level UPQC topology structure, improving the accuracy of the evaluation, and shortening the evaluation time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of level data evaluation, and in particular to a multi-level UPQC topology evaluation method and system. BACKGROUND

[0002] A unified power quality conditioner (UPQC) is a power device that integrates multiple power quality regulation functions, and can simultaneously solve voltage quality problems (such as voltage drop, voltage rise, voltage transient) and current quality problems (such as current harmonics, reactive power compensation) in the power grid. The UPQC is usually composed of a series module (DVR part) and a parallel module (APF part). The existing multi-level UPQC topology evaluation technology mainly focuses on the analysis of a single characteristic or a single structure, lacks comprehensive evaluation of the multi-level UPQC topology structure, lacks accurate identification and analysis of the power flow path, and the existing evaluation method often focuses on the steady-state performance, while ignoring the dynamic performance evaluation, and lacks detection of the topology component loss and effective quantification of the power redundancy regulation sensitivity. SUMMARY

[0003] Therefore, it is necessary to provide a multi-level UPQC topology evaluation method and system to solve at least one of the above technical problems.

[0004] To achieve the above-mentioned purpose, a multi-level UPQC topology evaluation method, the method comprising the following steps:

[0005] Step S1: Obtain a multi-level UPQC design drawing; extract the design parameters of the multi-level UPQC design drawing to obtain UPQC design parameters;

[0006] Step S2: Disassemble the electrical coordination mode according to the UPQC design parameters; perform electrical energy connection topology mapping based on the electrical coordination mode to obtain connection topology structure data; identify the power flow path based on the connection topology structure data to obtain power distribution path data; and construct a UPQC topology structure model based on the connection topology data and the power distribution path data;

[0007] Step S3: Obtain multi-level operation data; input the multi-level operation data into the UPQC topology structure model and monitor the multi-level working performance parameters; perform UPQC structure steady-state identification on the multi-level working performance parameters to generate structure steady-state data; and perform topology component loss detection on the structure steady-state data to generate topology component loss data;

[0008] Step S4: evaluating the power redundancy regulation sensitivity according to the topology component loss data; and performing topology module performance evaluation on the UPQC topology structure model based on the power redundancy regulation sensitivity, to obtain a multi-level UPQC topology structure evaluation report.

[0009] The application can fully reflect the electrical characteristics and topology structure of the UPQC system by obtaining multi-level UPQC design drawings and extracting design parameters. Based on the design parameter deconstruction of the electrical coordination mode, the connection topology structure data is further obtained through the electrical energy connection topology mapping, and the power flow path is identified, and finally an accurate UPQC topology structure model is constructed. This process ensures comprehensive understanding and modeling of the multi-level UPQC system from design to operation. After obtaining the multi-level operation data, the data is input into the UPQC topology structure model, which can monitor the multi-level working performance parameters in real time. Through structural steady-state identification of these parameters, structural steady-state data is generated, which provides a quantitative basis for stability under different operating conditions. At the same time, the structural steady-state data is subjected to topology component loss detection, which can accurately evaluate the loss of each component in actual operation, providing key information for system optimization and maintenance; based on the topology component loss data, the power redundancy regulation sensitivity is evaluated, which can accurately reflect the power regulation capability of the system under different operating conditions. This sensitivity evaluation not only considers the impact of loss data on power redundancy, but also combines the performance characteristics of the topology structure module, making the performance evaluation of the UPQC topology structure more comprehensive and in-depth. In this way, the regulation efficiency of the system under different operating conditions is effectively identified; based on the power redundancy regulation sensitivity, the module performance of the UPQC topology structure model is evaluated, which can generate a detailed multi-level UPQC topology structure evaluation report, covering the performance of the system under different operating conditions, including power distribution, loss, and power regulation capability, etc. Key indicators provide comprehensive technical support for the optimization design, operation management and fault diagnosis of the UPQC system, and improve the overall performance and reliability of the system. Therefore, through data processing technology and simulation technology, the application accurately identifies the power flow path and detects the steady-state performance of the UPQC topology structure, thereby accurately evaluating the performance indicators of the multi-level UPQC topology structure, improving the accuracy of the evaluation and shortening the evaluation time.

[0010] Preferably, step S1 comprises the following steps:

[0011] Step S11: obtaining multi-level UPQC design drawings;

[0012] Step S12: marking the hardware modules of the multi-level UPQC design drawings, wherein the hardware modules include series converter modules, parallel converter modules, and DC bus energy storage element modules;

[0013] Step S13: Extract the number of switch connection nodes of the series converter module with a frequency range of 10 kHz-50 kHz, extract the rated voltage range of 110 V-400 V, and record the rated current capacity as the series converter design parameters;

[0014] Step S14: Extract the number of grid interface of the parallel converter module, the current output, and the voltage control parameters, and record them as the parallel converter design parameters;

[0015] Step S15: Extract the voltage storage capacity of the DC bus energy storage element module, extract the charge and discharge current with a charge and discharge rate of 0.5C-2C, and record them as the DC bus energy storage design parameters;

[0016] Step S16: Combine the series converter design parameters, the parallel converter design parameters, and the DC bus energy storage design parameters into UPQC design parameters.

[0017] The multi-level UPQC design drawing provides an accurate structural basis for the subsequent evaluation process. The hardware layout and electrical connection relationship of the multi-level UPQC system are recorded in detail in the design drawing, ensuring the accuracy and pertinence of the subsequent parameter extraction and analysis process. Through the design drawing, the topology structure and mutual relationship of each hardware module can be clearly determined. The hardware modules in the multi-level UPQC design drawing are marked to clearly distinguish the series converter module, the parallel converter module, and the DC bus energy storage element module. This process provides a clear range and object for subsequent parameter extraction, avoiding omission or confusion in the parameter extraction process. Through marking, the independence and pertinence of parameter extraction and subsequent evaluation process of each module can be ensured. The number of switch connection nodes, the rated voltage range (110V-400V), and the rated current capacity of the series converter module are extracted and recorded as series converter design parameters, which can accurately obtain the key electrical characteristics of the series converter module in the multi-level UPQC topology structure. The number of switch connection nodes reflects the topology complexity and current distribution capability of the series converter module. The number of grid interfaces, current output, and voltage control parameters of the parallel converter module are extracted and recorded as parallel converter design parameters, which can clearly determine the electrical function and control capability of the parallel converter module in the multi-level UPQC topology structure. The number of grid interfaces reflects the connection capability of the parallel converter module with the grid, and the current output and voltage control parameters determine the electrical energy regulation accuracy and stability in the system. The voltage energy storage capacity and charge-discharge current (charge-discharge rate of 0.5C-2C) of the DC bus energy storage element module are extracted and recorded as DC bus energy storage design parameters, which can accurately obtain the energy storage and release capability of the energy storage element module in the multi-level UPQC topology structure. The voltage energy storage capacity reflects the capacity size of the energy storage element, and the charge-discharge current determines the energy conversion efficiency and dynamic response capability in the system. The series converter design parameters, parallel converter design parameters, and DC bus energy storage design parameters are combined into UPQC design parameters to avoid evaluation errors caused by scattered parameters.

[0018] Preferably, the step S2 includes:

[0019] According to the number of switch connection nodes, the rated current capacity is mapped to the node current capacity to obtain a node current mapping value. Based on the node current mapping value, the rated voltage range is subjected to voltage level adaptation degree detection, the voltage level adaptation degree is parameterized for the adaptation relationship of the series converter module, and series converter electrical adaptation data is generated.

[0020] According to the number of grid interfaces, interface current flux is determined based on the interface current flux and voltage control parameters, the voltage control degree of the parallel converter module is detected, the voltage control degree is mapped by a constraint relationship, and parallel converter constraint data is generated;

[0021] Based on the voltage energy storage capacity and the charge and discharge current, the rated energy storage capacity is detected, the energy storage limit is determined according to the rated energy storage capacity, and the energy storage element limit of the DC bus energy storage element module is determined, and the DC bus energy storage limit data is obtained.

[0022] Based on the series converter electrical adaptation data, the parallel converter constraint data and the DC bus energy storage limit data, the electrical collaborative matching is carried out, and the electrical collaborative mode is obtained.

[0023] According to the number of switch connection nodes, node current capacity mapping of rated current capacity is carried out, and based on the mapping value, voltage level adaptation degree detection of rated voltage range is carried out, and then the voltage level adaptation degree is parameterized to the series converter module, which can ensure that the series converter module accurately matches the voltage level and current capacity demand of the power grid in the multi-level UPQC topology, thereby improving the power quality regulation ability and operation stability of the system; According to the number of grid interfaces, interface current flux is determined based on the interface current flux and voltage control parameters, the voltage control degree of the parallel converter module is detected, the voltage control degree is mapped by a constraint relationship, which can effectively constrain the voltage control degree of the parallel converter module, and ensure its stable operation in the multi-level UPQC topology, avoid the performance degradation caused by voltage fluctuation; Based on the voltage energy storage capacity and the charge and discharge current, the rated energy storage capacity is detected, and the energy storage limit is determined according to the rated energy storage capacity, and then the energy storage element limit of the DC bus energy storage element module is determined, which can ensure that the DC bus energy storage element module matches the energy storage capacity and the charge and discharge current in the multi-level UPQC topology, avoid overcharging or overdischarging of the energy storage element, prolong the service life of the energy storage element, and improve the energy utilization efficiency of the system; Based on the series converter electrical adaptation data, the parallel converter constraint data and the DC bus energy storage limit data, the electrical collaborative matching is carried out, which can realize efficient collaborative work between modules in the multi-level UPQC topology, optimize the overall performance of the system, improve the power quality regulation efficiency, and reduce the system operation cost.

[0024] Preferably, the electrical energy connection topology mapping based on the electrical collaborative mode in step S2 comprises:

[0025] The electrical collaborative mode is divided into types, including series converter electrical adaptation type, parallel converter constraint type and DC bus energy storage limit type.

[0026] detecting a series energy total amount of the series converter electrical adaptation type; performing series energy parameterization on the series energy total amount to obtain series energy parameters; determining a series topology structure based on the series energy parameters to obtain series topology structure data;

[0027] detecting a parallel energy distribution amount of the parallel converter constraint type; marking parallel paths based on the parallel energy distribution amount to determine a parallel topology structure based on the parallel paths to obtain parallel topology structure data;

[0028] detecting an energy buffer amount of the DC bus energy storage limit type; determining a DC bus buffer structure based on the energy buffer amount to obtain DC bus buffer structure data;

[0029] merging the series topology structure data, the parallel topology structure data and the DC bus buffer structure to generate connection topology structure data.

[0030] The electrical coordination mode is divided into the series converter electrical adaptation type, the parallel converter constraint type and the DC bus energy storage limit type, precise classification of functions of each key module in the multi-level UPQC topology structure is realized, and the function positioning of each module in the system is ensured to be accurate and correct.

[0031] The series energy total amount of the series converter electrical adaptation type is detected, and series energy parameterization processing is performed thereon, the series topology structure is determined based on the series energy parameters, the topology structure of the series converter can be accurately optimized according to the actual energy transmission capacity of the series converter, efficient energy transmission and voltage adaptation in a high frequency (10 kHz-50 kHz) and a wide voltage range (110 V-400 V) are ensured; the parallel energy distribution amount of the parallel converter constraint type is detected, and parallel path marking is performed based on the distribution amount, and then the parallel topology structure is determined; by accurately distributing the parallel energy, the power transmission path of the parallel converter module can be optimized, and efficient energy distribution and voltage control in the multi-level UPQC topology structure are ensured; the energy buffer amount of the DC bus energy storage limit type is detected, and the DC bus buffer structure is determined based on the buffer amount to generate DC bus buffer structure data, the buffer capacity of the DC bus can be accurately optimized according to the charge and discharge rate (0.5C-2C) and the voltage energy storage capacity of the energy storage element, efficient energy buffering and voltage stabilization under dynamic working conditions are ensured; the series topology structure data, the parallel topology structure data and the DC bus buffer structure data are merged, the coordinated optimization of each module in the multi-level UPQC topology structure is realized, and the system as a whole has efficient energy transmission, distribution and buffering capacity.

[0032] Preferably, the step S2 comprises:

[0033] The connection topology data is marked and segmented by structural section, and the structural section position is generated;

[0034] The structural section position is detected by series voltage division, and series voltage division is obtained;

[0035] The structural section position is detected by parallel flow, and parallel flow is obtained;

[0036] The level power difference value is calculated based on series voltage division and parallel flow, the difference point of the structural section position is marked according to the level power difference value, and the power amount of the difference point is recorded, and the structural section power difference amount is obtained;

[0037] The structural section power difference amount is sorted in ascending order, and the power ascending data is obtained;

[0038] The power flow direction is determined according to the power ascending data, and the power ascending amount is recorded to obtain the power distribution path data.

[0039] The connection topology data is marked and segmented by structural section, and the connection topology data is marked and segmented by structural section, which realizes the fine division of the multi-level UPQC topology structure, can clearly determine the specific position and function boundary of each structural section in the system, and provides a clear analysis object for subsequent voltage division, flow detection and power difference calculation; the structural section position is detected by series voltage division, which can accurately obtain the voltage distribution of each structural section in the series path, and ensure that the voltage distribution of the series converter module under different levels meets the design requirements; the structural section position is detected by parallel flow, which can accurately measure the current distribution of each structural section in the parallel path, and provides a quantitative basis for the power distribution of the parallel converter module, and ensures that the parallel topology structure can efficiently realize power distribution; by calculating the level power difference value of series voltage division and parallel flow, the power difference between each structural section can be quantified, and the calculation process is based on the logarithmic relationship of power level, which can effectively reflect the dynamic change of power between different structural sections; the structural section position is marked by difference point and the power amount is recorded, which can clearly determine the specific position and size of the power difference, and provide accurate positioning information for subsequent power distribution optimization, and ensure that the system can realize dynamic adjustment under power imbalance; the structural section power difference amount is sorted in ascending order, which can clearly present the priority of the power difference of each structural section, and provide an ordered data basis for the optimization of power distribution path, and ensure that the system can be reasonably distributed according to the priority of power demand; based on the power ascending data, the power flow direction is determined and the power ascending amount is recorded, which realizes the visualization and optimization of power flow in the multi-level UPQC topology structure, and ensures that the system can realize efficient and stable power distribution under dynamic operation conditions.

[0040] Preferably, the inputting the multi-level operation data into the UPQC topology model and monitoring the multi-level operation performance parameters in step S3 comprises:

[0041] determining the input voltage range quantity for the multi-level operation data, and measuring the level switching frequency according to the input voltage range quantity;

[0042] identifying the single-level operation characteristics based on the input voltage range quantity and the level switching frequency, and performing multi-level operation coupling mode analysis on the single-level operation characteristics to obtain multi-level operation mode data;

[0043] inputting the multi-level operation mode data into the UPQC topology model, and starting UPQC simulation;

[0044] continuously monitoring the output voltage harmonics of the UPQC topology model, and recording the output voltage harmonic content;

[0045] continuously monitoring the total current harmonic distortion of the UPQC topology model, and recording the total current harmonic distortion rate;

[0046] continuously monitoring the level change response characteristics of the UPQC topology model, and recording the level response time;

[0047] integrating the output voltage harmonic content, the total current harmonic distortion rate and the level response time to obtain the multi-level operation performance parameters.

[0048] The application determines the input voltage range quantity and the level switching frequency, and can provide accurate input condition description for the operation of the multi-level UPQC system. The determination of the input voltage range quantity provides basic data for the operation of the system under different voltage levels, and the determination of the level switching frequency provides a key parameter for subsequent level operation mode analysis; by identifying the single-level operation characteristics and performing multi-level operation coupling mode analysis, the single-level operation characteristics and the multi-level operation mode can be organically combined, and the dynamic characteristics of the multi-level UPQC system under different operation modes can be effectively reflected. The multi-level operation mode data is input into the UPQC topology structure model and the simulation is started, and the performance evaluation of the system under actual operation conditions can be realized. The simulation process can simulate the voltage, current and level switching characteristics of the system under different operation modes; the output voltage harmonic content is continuously monitored and recorded, and the voltage quality of the system can be accurately evaluated. The harmonic content is calculated by Fourier transform and the like, and the total harmonic distortion rate (THDu) of the harmonic voltage can be expressed in percentage form; the total harmonic distortion of the current is continuously monitored and recorded, and the current quality of the system can be accurately evaluated. The total harmonic distortion rate (THDi) of the current is obtained by calculating the ratio of the effective value of the harmonic current to the effective value of the fundamental current, and can effectively reflect the interference degree of the current harmonic in the system; the level change response characteristics are continuously monitored and the level response time is recorded, and the dynamic performance of the system in the level switching process can be evaluated. The level response time reflects the response speed of the system to the input voltage change, and is an important indicator for measuring the stability and rapidity of the system; the above monitoring data is integrated to generate multi-level working performance parameters, and the comprehensive performance of the UPQC topology structure in actual operation can be comprehensively evaluated, and the multi-level UPQC system can achieve the best performance in power quality improvement and dynamic response capability.

[0049] Preferably, the UPQC structure steady-state identification of the multi-level working performance parameters in step S3 comprises:

[0050] The output voltage harmonic content is detected for harmonic frequency, and the harmonic frequency detection rounds are set to 5-8 rounds to obtain the output voltage harmonic frequency;

[0051] The output voltage harmonic content is marked for voltage harmonic time according to the output voltage harmonic frequency; the harmonic cycle characteristic identification is performed based on the voltage harmonic time and the output voltage harmonic frequency to generate the output voltage harmonic cycle data;

[0052] The level harmonic distortion amplitude value is obtained by determining the current total harmonic distortion amplitude based on the output voltage harmonic cycle data;

[0053] The level impedance fluctuation degree is generated by evaluating the level harmonic distortion amplitude value based on the level response time;

[0054] The UPQC structure steady state data is obtained by mapping the level impedance fluctuation degree.

[0055] The harmonic component in the output voltage and the frequency characteristics thereof can be comprehensively identified by setting the harmonic number detection round to 5-8 rounds, so that the harmonic characteristics in the multi-level UPQC topology structure can be accurately evaluated; the time domain distribution characteristics of the harmonic component can be determined by time marking the output voltage harmonic content, so that the dynamic characteristics of the harmonic can be accurately analyzed; the periodic variation law of the harmonic can be quantified by identifying the harmonic period characteristics, so that the overall evaluation of the system harmonic influence can be ensured; the distortion amplitude of the total harmonic distortion of the current can be determined by using the output voltage harmonic period data, so that the influence degree of the harmonic on the current waveform can be quantified, and the accurate evaluation of the system dynamic performance can be ensured; the impedance fluctuation of the level harmonic distortion amplitude value can be evaluated by combining the level response time, so that the impedance variation characteristics of the system under dynamic operation conditions can be accurately reflected, and the precise analysis of the system stability can be ensured; the structure stable state mapping can be performed based on the level impedance fluctuation degree, so that the data reflecting the stability of the UPQC topology structure can be generated, and the stable operation of the system under complex working conditions can be ensured.

[0056] Preferably, the topology component loss detection of the structure steady state data in step S3 comprises:

[0057] The level steady state working frequency, the level steady state adjustment accuracy and the level steady state modulation mode of the structure steady state data are extracted;

[0058] The level adjustment conduction loss detection is performed according to the level steady state working frequency and the level steady state adjustment accuracy, so as to obtain adjustment conduction loss data;

[0059] The modulation quantity loss detection is performed based on the level steady state adjustment accuracy and the level steady state modulation mode, so as to obtain modulation quantity loss data;

[0060] The operation loss detection is performed based on the level steady state working frequency and the level steady state modulation mode, so as to obtain modulation operation loss data;

[0061] The topology component loss data is obtained by combining the adjustment conduction loss data, the modulation quantity loss data and the modulation operation loss data.

[0062] The application extracts the level steady-state working frequency, level steady-state regulation accuracy and level steady-state modulation mode in the structure steady-state data, can provide accurate operation parameters for subsequent loss detection; the level regulation on-conduction loss detection is carried out based on the level steady-state working frequency and the level steady-state regulation accuracy, can quantify the on-conduction loss of the power device under steady-state operation, and ensure accurate evaluation of system efficiency; the modulation quantity loss detection is carried out through the level steady-state regulation accuracy and the level steady-state modulation mode, can quantify the energy loss in the modulation process; the operation loss detection is carried out in combination with the level steady-state working frequency and the level steady-state modulation mode, can comprehensively evaluate the loss of the system under steady-state operation; the regulation on-conduction loss data, the modulation quantity loss data and the modulation operation loss data are combined, can comprehensively reflect the loss characteristics of the multi-level UPQC topology structure under steady-state operation, and provide complete data support for system performance evaluation and optimization.

[0063] Preferably, step S4 comprises the following steps:

[0064] Step S41: determining the electric energy influence quantity of the topology component loss data to obtain electric energy output influence quantity data;

[0065] Step S42: recording the redundant electric energy according to the electric energy output influence quantity data, and detecting the redundant electric energy interval value when the redundant electric energy is 0% to 30%, marking as a low-level redundant regulation interval; when the redundant electric energy is 30% to 70%, marking as a medium-level redundant regulation interval; when the redundant electric energy is 70% to 100%, marking as a high-level redundant regulation interval;

[0066] Step S43: integrating the low-level redundant regulation interval, the medium-level redundant regulation interval and the high-level redundant regulation interval to obtain level redundant regulation interval data;

[0067] Step S44: evaluating the topology component loss data according to the level redundant regulation interval data to generate electric energy redundant regulation sensitivity;

[0068] Step S45: evaluating the operating condition loss change of the UPQC topology structure model based on the electric energy redundant regulation sensitivity to obtain operating condition loss evaluation data;

[0069] Step S46: evaluating the module performance regulation efficiency of the UPQC topology structure model according to the operating condition loss evaluation data to obtain module performance regulation evaluation data;

[0070] Step S47: integrating the operating condition loss evaluation data and the module performance regulation evaluation data to obtain a multi-level UPQC topology structure evaluation report.

[0071] The application can quantify the actual influence of the loss on the system electric energy output by measuring the electric energy influence quantity of the topological component loss data, provide basic data for subsequent redundant electric energy quantity recording and adjustment interval detection, and ensure accurate evaluation of system energy utilization efficiency; record the redundant electric energy quantity based on the electric energy output influence quantity data, and divide low, medium and high redundant adjustment intervals according to the size of the redundant electric energy quantity, which can clearly show the running state of the system under different redundant levels and provide classification basis for subsequent adjustment sensitivity evaluation; integrate the data of different redundant adjustment intervals to ensure systematic analysis of the redundant adjustment capacity of the system; evaluate the adjustment sensitivity of the topological component loss data based on the level redundant adjustment interval data, which can quantify the adjustment capacity of the system under different redundant intervals, and the generated electric energy redundant adjustment sensitivity provides a key parameter for subsequent operating condition loss change evaluation; use the electric energy redundant adjustment sensitivity to evaluate the operating condition loss change of the UPQC topological structure model, which can comprehensively analyze the loss change characteristics of the system under different operating conditions, and the generated operating condition loss evaluation data provides data support for subsequent module performance adjustment efficiency evaluation; evaluate the module performance adjustment efficiency of the UPQC topological structure model based on the operating condition loss evaluation data, which can quantify the performance adjustment efficiency of each module under different conditions, and the generated module performance adjustment evaluation data; the operating condition loss evaluation data and the module performance adjustment evaluation data can systematically reflect the performance of the UPQC topological structure under different operating conditions, and provide comprehensive evaluation basis for the optimization design and operation of the system.

[0072] The application also provides a level UPQC topological structure evaluation system for the above-mentioned level UPQC topological structure evaluation method, which comprises:

[0073] The UPQC design parameter acquisition module is used for acquiring the multi-level UPQC design drawing; the design parameters of the multi-level UPQC design drawing are extracted to obtain the UPQC design parameters;

[0074] The UPQC topological structure model construction module is used for deconstructing the electrical coordination mode according to the UPQC design parameters; the electric energy connection topological mapping is carried out based on the electrical coordination mode to obtain connection topological structure data; the power flow path of the electric level is identified based on the connection topological structure data to obtain power distribution path data; and the UPQC topological structure model is constructed based on the connection topological data and the power distribution path data;

[0075] The topology component loss detection module is configured to acquire multi-level operation data; input the multi-level operation data into the UPQC topology structure model and monitor multi-level operation performance parameters; perform UPQC structure steady state identification on the multi-level operation performance parameters to generate structure steady state data; and perform topology component loss detection on the structure steady state data to generate topology component loss data.

[0076] The topology structure module performance evaluation module is configured to evaluate power redundancy regulation sensitivity according to the topology component loss data; perform topology structure module performance evaluation on the UPQC topology structure model based on the power redundancy regulation sensitivity to obtain a multi-level UPQC topology structure evaluation report.

[0077] The present application realizes full-process automatic processing from multi-level UPQC design parameter acquisition to topology structure performance evaluation, can accurately extract design parameters, construct an accurate topology structure model, and perform real-time monitoring and analysis on multi-level operation data. The system can quantitatively evaluate the loss characteristics of the topology component, identify the power redundancy regulation sensitivity, and generate a detailed topology structure evaluation report, thereby improving the efficiency and accuracy of UPQC topology structure evaluation. BRIEF DESCRIPTION OF DRAWINGS

[0078] Figure 1 It is a step flowchart of a multi-level UPQC topology structure evaluation method;

[0079] Figure 2 It is Figure 1 It is a detailed implementation step flowchart of step S1 in the method;

[0080] Figure 3 It is Figure 1 It is a detailed implementation step flowchart of step S4 in the method;

[0081] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0082] The technical method of the present application will be described clearly and completely in combination with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0083] Further, the accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application. In the drawings:

[0084] It is to be understood that, although terms such as "first", "second", and the like can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the example embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0085] To achieve the above object, there is provided Figures 1 to 3 A multi-level UPQC topology evaluation method, the method comprising the following steps:

[0086] Step S1: Obtain a multi-level UPQC design drawing; extract the design parameters of the multi-level UPQC design drawing to obtain UPQC design parameters;

[0087] Step S2: Deconstruct the electrical synergy mode according to the UPQC design parameters; perform electrical energy connection topology mapping based on the electrical synergy mode to obtain connection topology structure data; identify the power flow path based on the connection topology structure data to obtain power distribution path data; construct a UPQC topology structure model based on the connection topology data and the power distribution path data;

[0088] Step S3: Obtain multi-level operation data; input the multi-level operation data into the UPQC topology structure model and monitor the multi-level working performance parameters; perform UPQC structure steady-state identification on the multi-level working performance parameters to generate structure steady-state data; perform topology component loss detection on the structure steady-state data to generate topology component loss data;

[0089] Step S4: Evaluate the electrical energy redundancy regulation sensitivity according to the topology component loss data; perform topology structure module performance evaluation on the UPQC topology structure model based on the electrical energy redundancy regulation sensitivity to obtain a multi-level UPQC topology evaluation report.

[0090] The application can fully reflect the electrical characteristics and topological structure of the UPQC system by obtaining multi-level UPQC design drawings and extracting design parameters. Based on the design parameter deconstruction of the electrical coordination mode, the connection topological structure data is further obtained through the electrical energy connection topological mapping, and the power flow path is identified, and finally the accurate UPQC topological structure model is constructed. This process ensures the comprehensive understanding and modeling of the multi-level UPQC system from design to operation. After obtaining the multi-level operation data, it is input into the UPQC topological structure model, which can monitor the multi-level working performance parameters in real time. Through the structural steady-state identification of these parameters, the structural steady-state data is generated, which provides a quantitative basis for the stability of the system under different operating conditions. At the same time, the structural steady-state data is used for topological component loss detection, which can accurately evaluate the loss of each component in actual operation, providing key information for system optimization and maintenance; based on the topological component loss data, the electrical energy redundancy regulation sensitivity is evaluated, which can accurately reflect the electrical energy regulation ability of the system under different operating conditions. This sensitivity evaluation not only considers the influence of loss data on electrical energy redundancy, but also combines the performance characteristics of the topological structure module, making the performance evaluation of the UPQC topological structure more comprehensive and in-depth. Through this way, the regulation efficiency of the system under different operating conditions is effectively identified; based on the electrical energy redundancy regulation sensitivity, the performance of the UPQC topological structure model is evaluated, which can generate a detailed multi-level UPQC topological structure evaluation report, covering the performance of the system under different operating conditions, including power distribution, loss and electrical energy regulation ability and other key indicators, providing comprehensive technical support for the optimization design, operation management and fault diagnosis of the UPQC system, improving the overall performance and reliability of the system. Therefore, through data processing technology and simulation technology, the power flow path is accurately identified, and the steady-state performance of the UPQC topological structure is detected, so as to accurately evaluate the performance indicators of the multi-level UPQC topological structure, improve the accuracy of evaluation and shorten the evaluation time.

[0091] In the embodiment of the application, as shown in the reference Figure 1 The multi-level UPQC topological structure evaluation method includes the following steps:

[0092] Step S1: Obtain multi-level UPQC design drawings; extract design parameters from the multi-level UPQC design drawings to obtain UPQC design parameters;

[0093] In the embodiment of the application, the multi-level UPQC design drawing is obtained through electrical design software or drawing management system, and the drawing should include the detailed circuit connection mode of the multi-level UPQC, the layout of each component and the annotation information of key parameters; the specific operation is: reading the pre-designed multi-level UPQC topology drawing file from the storage device, and the file format is usually CAD format or other common electrical design drawing format; then, the design parameter extraction of the multi-level UPQC design drawing is carried out by using image recognition technology or circuit analysis software; the image recognition technology identifies and analyzes the circuit elements, connection lines and annotated parameters in the drawing through steps such as gray image processing, edge detection and shape description; specifically, the color drawing is converted into a gray image to simplify the image recognition process; the outline of the circuit element and the connection line are extracted through the edge detection algorithm; the geometric characteristics of the circuit element such as area and perimeter are calculated, and the annotated parameter information is extracted. The extracted key design parameters include the number of levels of the multi-level topology structure, the capacitance voltage value of each sub-module, the inductance value, the model and number of switching devices and the like. For example, for the modular multi-level converter (MMC) type UPQC, the capacitance voltage value (such as ±Vdc) of each sub-module and the bridge arm inductance value (L) and the like need to be extracted.

[0094] Step S2: decomposing the electrical coordination mode according to the UPQC design parameters; performing electrical energy connection topology mapping based on the electrical coordination mode to obtain connection topology structure data; performing level power flow path identification on the connection topology structure data to obtain power distribution path data; constructing a UPQC topology structure model based on the connection topology data and the power distribution path data;

[0095] In the embodiment of the present application, the electrical coordination mode of the multi-level UPQC is deconstructed according to the design parameters of the multi-level UPQC. By analyzing the capacitance voltage value (such as ±Vdc), inductance value (L), switch device model and quantity, etc. in the design parameters, and combining the basic principles of the electrical system, the series-parallel port coordination relationship of the UPQC is determined. For the non-isolated single-phase three-bridge-arm UPQC, the parallel port is composed of bridge arm a (VT1, VT2), bridge arm b (VT3, VT4) and port filter (La1, La2, Ca), which is used to compensate the power factor and harmonic current of the grid side; the series port is composed of bridge arm b (VT3, VT4), bridge arm c (VT5, VT6) and series filter (Cbc, Lc), which is used to compensate the load voltage; based on the electrical coordination mode, the electrical connection topology mapping is performed, and the deconstructed series-parallel port relationship is mapped to the electrical connection topology structure by using the electrical system modeling tool. By setting the connection relationship of each bridge arm, the filter parameter and the connection mode of the DC bus capacitor, the parallel port is equivalent to a current source and is connected in parallel to the grid; the series port is equivalent to a voltage source and is connected in series between the grid and the load; the level power flow path of the connection topology structure data is identified to obtain the power distribution path data. By analyzing the power flow direction in the topology structure, and combining the active power exchange relationship of the DC bus capacitor, the power distribution path between the bridge arms is identified. For example, the instantaneous power (ppc) flowing from the parallel port to the DC bus capacitor and the instantaneous power (psc) flowing from the DC bus capacitor to the series port are identified, and the power distribution coefficient of each path is calculated according to the power flow relationship. The model is constructed by using the electrical system modeling tool (such as MATLAB / Simulink or PSIM), and the specific steps are as follows: the inductance value (1mH), capacitance value (10μF) and switch characteristics (such as turn-on and turn-off time) of the IGBT of each bridge arm are input into the modeling tool; according to the connection topology data, the parallel port is equivalent to a current source and the series port is equivalent to a voltage source; the parallel port is connected to the grid side and the series port is connected between the grid and the load; according to the power distribution path data, the power exchange relationship between the DC bus capacitor and each port is set; external conditions are added: the grid side voltage and the load side voltage are added to the model to simulate the actual operating environment; the accuracy of the model is verified by simulation. In the simulation process, the stability of the DC bus voltage and the accuracy of the power distribution are monitored, and if it is found that the DC bus voltage fluctuates greatly, the fluctuation can be reduced by adjusting the power distribution coefficient or optimizing the control strategy.

[0096] Step S3: obtaining multi-level operation data; inputting the multi-level operation data into the UPQC topology structure model and monitoring the multi-level working performance parameters; performing UPQC structure steady state identification on the multi-level working performance parameters to generate structure steady state data; performing topology component loss detection on the structure steady state data to generate topology component loss data;

[0097] In the embodiment of the present application, multi-level operation data is obtained, key electrical parameters in the UPQC system are monitored in real time through high-precision sensors and a data acquisition system, including DC bus voltage (Vdc), bridge arm current (Ia, Ib, Ic), submodule capacitor voltage (Uc), and grid-side voltage (Ug) and load-side voltage (UL), the sampling frequency is set to 10 kHz to ensure the accuracy and real-time performance of the data, the multi-level operation data is input into the UPQC topology structure model, and the multi-level working performance parameters are monitored. The UPQC topology structure model constructed by the simulation software (such as MATLAB / Simulink) takes the collected operation data as the input signal; through model simulation, the steady-state performance parameters of the system are monitored in real time, including the fluctuation range of the DC bus voltage (ΔVdc), the balance degree of the submodule capacitor voltage (ΔUc), the total harmonic distortion rate of the grid-side voltage (THD_G) and the total harmonic distortion rate of the load-side voltage (THD_L); the multi-level working performance parameters are identified for the steady state of the UPQC structure, the frequency spectrum characteristics of the grid-side current (Ig) and the load-side current (IL) are analyzed through Fourier transform, and whether the system reaches the steady state operation is identified. When the ratio of the fundamental component to the total harmonic component of the grid-side current is greater than 0.95, and the fluctuation range of the DC bus voltage is less than ±1% of the rated voltage, it is determined that the system is in steady state operation; at this time, the key parameters in the steady state are recorded, including the average value of the DC bus voltage (Vdc_avg), the average value of the submodule capacitor voltage (Uc_avg) and the fundamental component of the grid-side current (Ig_fundamental), the topology component loss detection is performed on the steady state data, according to the steady state data, the characteristic parameters of the IGBT module and the capacitor are combined, and the losses of each component are calculated; for the IGBT module, an average power loss calculation model based on the switching period is adopted, and the on-state loss, turn-on loss and turn-off loss are calculated respectively. The specific calculation method is as follows: the on-state loss is related to the product of the IGBT terminal voltage and the collector current and the duty cycle of the switching period; the turn-on loss is related to the switching frequency, the turn-on energy, the gate resistance coefficient and the junction temperature coefficient; the turn-off loss is related to the switching frequency, the turn-off energy, the gate resistance coefficient and the junction temperature coefficient. For the submodule capacitor, the equivalent series resistance (ESR) and the loss of the capacitance value are calculated by monitoring the voltage and current waveforms of the capacitor. A multi-point sampling method is adopted to sample the submodule capacitor voltage within the power frequency period, and the voltage and current state equations are constructed by combining the IGBT switching signal, the modulation ratio, the alternating current and voltage, etc. information, and the capacitance value and the ESR value are obtained by solving.

[0098] Step S4: evaluating the power redundancy adjustment sensitivity according to the topology component loss data; performing topology structure module performance evaluation on the UPQC topology structure model based on the power redundancy adjustment sensitivity, and obtaining a multi-level UPQC topology structure evaluation report.

[0099] ​In the embodiment of the present application, the power redundancy regulation sensitivity is evaluated according to the topological component loss data. Specifically, for the IGBT module, the loss is mainly divided into on-state loss, turn-on loss and turn-off loss; taking the IGBT of model FF450R12ME4 as an example,

[0100] The on-state loss P_cond is calculated by measuring the on-state voltage drop (Vce_on) and working current (Ic) of the IGBT, and combining the duty cycle (D), i.e. P_cond = Vce_on x Ic x D. The turn-on loss P_on is related to the switching frequency (f_sw) and turn-on energy (E_on), and the calculation formula is P_on = f_sw x E_on. The turn-off loss P_off is related to the switching frequency (f_sw) and turn-off energy (E_off), and the calculation formula is P_off = f_sw x E_off. The capacitance loss is mainly caused by the equivalent series resistance (ESR), and for a capacitor with a rated capacitance value of 100 μF, the ESR value of the capacitor is measured using a capacitor tester, and it is assumed that the ESR is 5 Ω. According to the capacitance value (C) and working frequency (f), the capacitive reactance Xc = 1 / (2πfC) is calculated, for example, for a frequency of 50 Hz and a capacitance of 100 μF, Xc ≈ 318.3 Ω; the capacitance loss P_loss = I^2 x ESR, where I is the ripple current flowing through the capacitor, for example, when the ripple current is 5.28 A, the loss power is about 1.115 W. The loss data of the IGBT and the capacitor are combined with parameters such as the DC bus voltage fluctuation range (ΔVdc), the sub-module capacitance voltage equalization degree (ΔUc), etc., to analyze the influence of the loss on the power redundancy regulation. If the increase of the loss leads to the increase of ΔVdc, it indicates that the power redundancy regulation sensitivity is high. The performance of the UPQC topological structure model is evaluated by using the analytic hierarchy process (AHP), and according to the power redundancy regulation sensitivity, the loss, reliability, transient and steady state characteristics, system stability, cost and other factors, an evaluation index system is constructed: the relationship between the loss and the topology: taking the total loss of the IGBT and the capacitor as the index; reliability: taking the junction temperature change range of the IGBT and the ESR stability of the capacitor as the index; transient and steady state characteristics: taking the DC bus voltage fluctuation range (ΔVdc) and the sub-module capacitance voltage equalization degree (ΔUc) as the index; system stability: taking the power factor of the grid side and the load side as the index; cost: taking the cost of the IGBT and the capacitor as the index. The evaluation index system is used to evaluate the performance of the UPQC topological structure model, and the UPQC topological structure model with the best performance is selected as the optimal UPQC topological structure model. And the load side voltage total harmonic distortion (THD_L) is an index; Cost: the unit loss cost of IGBT module and capacitor is an index; Through the analytic hierarchy process, the weight coefficients of each index are determined by combining data analysis. For example, the weight of the loss index is 0.3, the weight of the reliability index is 0.25, the weight of the transient state characteristic index is 0.2, the weight of the system stability index is 0.15, and the weight of the cost index is 0.1. According to the weight coefficients and the actual values of each index, the comprehensive scores of different topological structures (such as cascaded H-bridge, modular multilevel converter MMC, etc.) are calculated; According to the performance ranking result, a multi-level UPQC topology evaluation report is generated.

[0101] As an example of the present application, reference is made to Figure 2 In this example, the step S1 includes:

[0102] Step S11: Obtain the multi-level UPQC design drawing;

[0103] Step S12: Mark the hardware module of the multi-level UPQC design drawing, wherein the hardware module includes a series converter module, a parallel converter module and a DC bus energy storage element module;

[0104] Step S13: Extract the number of switch connection nodes of the series converter module in the frequency range of 10kHz-50kHz, extract the rated voltage range of 110V-400V, and record the rated current capacity as the series converter design parameters;

[0105] Step S14: Extract the number of grid interfaces of the parallel converter module, the current output, and the voltage control parameters, and record them as the parallel converter design parameters;

[0106] Step S15: Extract the voltage energy storage capacity of the DC bus energy storage element module, extract the charge and discharge current in the charge and discharge rate of 0.5C-2C, and record them as the DC bus energy storage design parameters;

[0107] Step S16: Combine the series converter design parameters, the parallel converter design parameters and the DC bus energy storage design parameters into UPQC design parameters.

[0108] In the embodiment of the present application, professional electrical design software (such as AutoCAD or SolidWorks) is used to open and read the design drawing file of the multi-level UPQC. The design drawing should include detailed circuit connection, hardware module layout and key parameter annotation. In the design drawing, the hardware module is distinguished and annotated using the marking tool. The hardware module includes series converter module, parallel converter module and DC bus energy storage element module. The series converter module usually includes switching devices (such as IGBT) and inductors; the parallel converter module includes grid interface and filter; the DC bus energy storage element module includes capacitors or batteries; the number of switching connection nodes in the series converter module with a frequency range of 10 kHz to 50 kHz is extracted using image recognition technology or manual measurement tool. For example, by analyzing the layout of switching devices in the circuit diagram, the number of nodes is counted as 10; the rated voltage range of the series converter module is extracted, and by reading the drawing annotation or design description, it is confirmed that the range is 110V to 400V; the rated current capacity is extracted, and by analyzing the current path and the rated current of the switching device, it is determined that the value is 100A. These parameters are recorded as series converter design parameters; the number of grid interfaces of the parallel converter module is extracted, and by counting the number of interfaces marked in the drawing, it is determined that it is 3; the current output is extracted, and by analyzing the design current path of the parallel converter, it is determined that the value is 150A; the voltage control parameter is extracted, and by reading the control range marked in the drawing, it is confirmed that it is ±10% of the rated voltage. These parameters are recorded as parallel converter design parameters; the voltage energy storage capacity of the DC bus energy storage element module is extracted, and by reading the capacitor or battery parameters marked in the drawing, it is confirmed that the value is 1000V; the charge and discharge current amount with a charge and discharge rate of 0.5C to 2C is extracted, and by analyzing the charge and discharge characteristic curve of the energy storage element, it is determined that the value is 50A to 200A. These parameters are recorded as DC bus energy storage design parameters; the series converter design parameters, parallel converter design parameters and DC bus energy storage design parameters extracted above are integrated to form complete UPQC design parameters.

[0109] Preferably, the step S2 includes:

[0110] According to the number of switching connection nodes, the rated current capacity is mapped to the node current capacity to obtain a node current mapping value; based on the node current mapping value, the rated voltage range is detected for voltage level adaptation degree, and the voltage level adaptation degree is parameterized for the adaptation relationship of the series converter module to generate series converter electrical adaptation data;

[0111] According to the number of grid interfaces, interface current flux is determined based on the interface current flux and the voltage control parameter, the voltage control degree of the parallel converter module is detected, the voltage control degree is mapped by a constraint relationship, and the parallel converter constraint data is generated;

[0112] Based on the voltage energy storage capacity and the charge and discharge current, the rated energy storage capacity is detected; according to the rated energy storage capacity, the energy storage limit is determined, and the energy storage element limit of the DC bus energy storage element module is determined, and the DC bus energy storage limit data is obtained;

[0113] Based on the series converter electrical adaptation data, the parallel converter constraint data and the DC bus energy storage limit data, the electrical coordination matching is carried out, and the electrical coordination mode is obtained.

[0114] In the embodiment of the present application, the design parameters of the series converter module are read by using electrical design software (such as AutoCAD or SolidWorks), the number of switch connection nodes (such as 10) and the rated current capacity (such as 100 A) are extracted. Through the node current capacity mapping algorithm, each node is assigned a corresponding current capacity; if the number of nodes is 10 and the rated current capacity is 100 A, then the current capacity mapping value of each node is 10 A; according to the node current mapping value (10 A), combined with the rated voltage range of the series converter module (110 V-400 V), the voltage level adaptation detection tool is used for analysis. By calculating the adaptation relationship between the node current mapping value and the rated voltage range, the series converter electrical adaptation data is generated. For example, if the adaptation degree of the node current mapping value in the rated voltage range is high, it indicates that the module has good electrical adaptation at this voltage level; the number of power grid interfaces (such as 3) and the current output (such as 150 A) of the parallel converter module are extracted. Through the interface current flux calculation tool, the current flux of each interface is determined, if the number of power grid interfaces is 3 and the current output is 150 A, then the current flux of each interface is 50 A. Combined with the voltage control parameters (such as ±10% of the rated voltage), the voltage control degree detection of the parallel converter module is carried out, and the constraint data is generated. The voltage energy storage capacity (such as 1000 V) and the charge and discharge current (such as 50 A-200 A) of the DC bus energy storage element module are extracted. Through the energy storage capacity detection tool, the rated energy storage capacity is calculated; if the voltage energy storage capacity is 1000 V and the charge and discharge current range is 50 A-200 A, then the rated energy storage capacity is 100 kW, according to the rated energy storage capacity, the energy storage limit is determined, and the DC bus energy storage limit data is generated; the series converter electrical adaptation data, the parallel converter constraint data and the DC bus energy storage limit data are input into the electrical collaborative matching system. Through the collaborative matching algorithm, the electrical collaborative relationship between the modules is analyzed, if the electrical adaptation of the series converter is good, and the constraint data of the parallel converter matches the DC bus energy storage limit data, then it is determined that the UPQC topology structure has a good electrical collaborative mode.

[0115] Preferably, the step S2 of mapping the electrical connection topology based on the electrical collaborative mode comprises:

[0116] dividing the electrical collaborative mode into types, including series converter electrical adaptation type, parallel converter constraint type and DC bus energy storage limit type;

[0117] detecting the series electrical energy total amount of the series converter electrical adaptation type; performing electrical energy series parameterization on the series electrical energy total amount to obtain electrical energy series parameters; determining the series topology structure according to the electrical energy series parameters to obtain series topology structure data;

[0118] detecting a shunt converter constraint type of a shunt power distribution amount; performing shunt path marking according to the shunt power distribution amount, determining a shunt topology structure based on the shunt path, and obtaining shunt topology structure data;

[0119] detecting a DC bus energy storage limit type of an energy buffer amount; determining a DC bus buffer structure according to the energy buffer amount, and obtaining DC bus buffer structure data;

[0120] merging the series topology structure data, the shunt topology structure data, and the DC bus buffer structure to generate connection topology structure data.

[0121] In the embodiment of the present application, the electrical coordination mode is divided into series converter electrical adaptation type, parallel converter constraint type and DC bus energy storage limit type. Through the electrical coordination matching tool, the electrical adaptation data of the series converter, the constraint data of the parallel converter and the energy storage limit data of the DC bus are analyzed to determine the coordination type of each module; the electrical energy detection equipment is used to detect the total electrical energy of the series converter module. According to the rated current capacity (such as 100A) of the series converter and the node current mapping value (such as 10A / node), the total electrical energy of the series is calculated. For example, if the number of nodes is 10, the total electrical energy of the series is 100A*10 nodes=1000A; according to the total electrical energy of the series, the electrical energy is distributed to each node through the parameterization tool to obtain the electrical energy series parameter. For example, the total electrical energy of 1000A is distributed to 10 nodes, and the electrical energy series parameter of each node is 100A; according to the electrical energy series parameter, the rated voltage range (such as 110V-400V) of the series converter module is combined to determine the series topology structure through the topology structure analysis tool, if the electrical energy series parameter is 100A and the rated voltage range is 110V-400V, the corresponding series topology structure data is generated, and the voltage and current parameters of each node are recorded; the electrical energy distribution detection tool is used, combined with the current output of the parallel converter module (such as 150A) and the number of grid interfaces (such as 3), to calculate the parallel electrical energy distribution. For example, the electrical energy distribution of each interface is 150A / 3=50A; according to the parallel electrical energy distribution, each interface is marked through the parallel path marking tool, and the parallel topology structure is determined based on the interface current flux and voltage control parameter (such as ±10% rated voltage), if the electrical energy distribution of each interface is 50A and the voltage control range is ±10%, the corresponding parallel topology structure data is generated; the energy storage detection device is used to detect the electrical energy buffer of the DC bus energy storage element module. According to the voltage energy storage capacity (such as 1000V) and the charge and discharge current (such as 50A-200A), the electrical energy buffer is calculated. For example, the electrical energy buffer is 1000V*200A=200kW, and the DC bus buffer structure is determined through the buffer structure analysis tool according to the electrical energy buffer. For example, if the electrical energy buffer is 200kW, the corresponding DC bus buffer structure data is generated, and the charge and discharge limit of the energy storage element is recorded. The series topology structure data, the parallel topology structure data and the DC bus buffer structure data are integrated to generate complete connection topology structure data through the topology structure merging tool.

[0122] Preferably, the step S2 of identifying the electrical level power flow path of the connection topology structure data comprises:

[0123] The connection topology structure data is marked and segmented to generate a structure segment position.

[0124] The series voltage division quantity is detected for the structure section position to obtain a series voltage division quantity;

[0125] The parallel flow quantity is detected for the structure section position to obtain a parallel flow quantity;

[0126] The level power difference value is calculated based on the series voltage division quantity and the parallel flow quantity; the difference point of the structure section position is marked according to the level power difference value, and the power quantity of the difference point is recorded to obtain a structure section power difference quantity;

[0127] The structure section power difference quantity is sorted in ascending order to obtain power ascending order data;

[0128] The power flow direction is determined according to the power ascending order data, and the power ascending order quantity is recorded to obtain power distribution path data.

[0129] In the embodiment of the present application, the electrical topology analysis tool is used to process the connection topology structure data. First, according to the electrical connection relationship of the topology structure, the entire topology structure is marked by sections. For example, the series converter module is divided into multiple structural sections, and each structural section contains several switch connection nodes. Assuming that the entire series converter module contains 10 nodes, according to the electrical function, it is divided into 3 structural sections, which are marked as section 1 (nodes 1-3), section 2 (nodes 4-7) and section 3 (nodes 8-10) respectively; a high-precision voltage detection device is used to measure the voltage of each structural section. Assuming that the voltage of section 1 is 110V, the voltage of section 2 is 220V, and the voltage of section 3 is 330V, these voltage values are the series voltage division amounts of each structural section; a current detection device is used to measure the parallel current distribution of each structural section. For example, assuming that the total current of the parallel converter module is 150A, the parallel current distribution is detected to determine the current distribution amount of each structural section. Assuming that the parallel current distribution amount of section 1 is 50A, that of section 2 is 60A, and that of section 3 is 40A; according to the series voltage division amount and the parallel current distribution amount, the power difference value of each structural section is calculated. For example, the power of section 1 is 110V×50A=5.5kW, the power of section 2 is 220V×60A=13.2kW, and the power of section 3 is 330V×40A=13.2kW. The power difference value is calculated, for example, the power difference value between section 1 and section 2 is 13.2kW-5.5kW=7.7kW; for the calculated power difference value, the corresponding structural section position is marked, the power difference value 7.7kW between section 1 and section 2 is marked as difference point 1, and the power difference value 0kW between section 2 and section 3 (because the powers are the same) is marked as difference point 2. These marked difference points and their power amounts are recorded as structural section power difference amounts; all structural section power difference amounts are sorted in ascending order. For example, assuming that the obtained power difference amounts are: difference point 1 is 7.7kW, and difference point 2 is 0kW; after sorting, the power ascending data is: 0kW (difference point 2), 7.7kW (difference point 1); according to the power ascending data, the power flow direction is determined, from difference point 2 (0kW) to difference point 1 (7.7kW), the power flow direction is from section 2 to section 1. The power value of each difference point is recorded to clearly determine the flow direction and size of the power in the topology structure.

[0130] Preferably, the step S3 of inputting the multi-level operation data into the UPQC topology structure model and monitoring the multi-level working performance parameters comprises:

[0131] The input voltage range amount of the multi-level operation data is determined, and the level switching frequency is determined according to the input voltage range amount;

[0132] Identify single-level operation characteristics based on input voltage range and level switching frequency, and analyze single-level operation characteristics in multi-level operation coupling mode to obtain multi-level operation mode data;

[0133] Input multi-level operation mode data into UPQC topology structure model, and start UPQC simulation;

[0134] Continuously monitor output voltage harmonics of UPQC topology structure model, and record output voltage harmonic content;

[0135] Continuously monitor total current harmonic distortion of UPQC topology structure model, and record total current harmonic distortion rate;

[0136] Continuously monitor level change response characteristics of UPQC topology structure model, and record level response time;

[0137] Integrate output voltage harmonic content, total current harmonic distortion rate and level response time to obtain multi-level working performance parameters.

[0138] In the embodiment of the present application, a high-precision voltage sensor is used to collect the input voltage signal in the multi-level operation data, to determine the input voltage range, for example, the input voltage range is 110V-400V; the frequency of the input voltage signal is measured by frequency measurement technology (such as direct measurement method or equal-precision measurement method), to obtain the level switching frequency, assuming that the frequency of the input voltage signal is 50Hz, which can be accurately measured by the equal-precision measurement method; according to the input voltage range (110V-400V) and the level switching frequency (50Hz), the signal analysis tool is used to identify the single-level operation characteristics. For example, the voltage amplitude during single-level operation is 220V, and the corresponding level switching frequency is 50Hz. The single-level operation characteristics are coupled and analyzed with the multi-level operation mode by using the multi-level operation coupling mode analysis tool, to generate the multi-level operation mode data, to record the voltage, frequency and switching characteristics of each level. The multi-level operation mode data is imported into the UPQC topology structure model, and the simulation software (such as MATLAB / Simulink) is used to start the UPQC simulation. During the simulation process, the actual operation state of the UPQC system is simulated according to the input multi-level operation mode data; during the simulation process, the harmonic analysis tool (such as FFT analysis) is used to monitor the output voltage of the UPQC topology structure model in real time. The output voltage signal is collected by using a high-precision data acquisition card (such as NI-9215), and the FFT optimization algorithm (such as Hanning window + interpolation correction) is used to calculate the harmonic content of the output voltage. For example, the total harmonic distortion rate (THD) of the output voltage is 5%, which is recorded as the output voltage harmonic content; the harmonic analysis tool is also used to monitor the current signal of the UPQC topology structure model. The current signal is collected by using a current sensor (such as HIOKI CT6840), and the total harmonic distortion rate (THD) of the current is calculated. For example, the total harmonic distortion rate of the current is 3%, which is recorded; the level change of the UPQC topology structure model is monitored in real time by using a high-speed data acquisition card (such as NI-9215). The level response time is recorded by analyzing the time delay in the level switching process. For example, the level response time is 100μs; the recorded output voltage harmonic content (5%), current total harmonic distortion rate (3%) and level response time (100μs) are integrated to generate the multi-level working performance parameters.

[0139] Preferably, the UPQC structure steady-state identification of the multi-level working performance parameters in step S3 comprises:

[0140] The harmonic content of the output voltage is detected by the harmonic number detection, and the harmonic number detection rounds are set to 5-8 rounds to obtain the output voltage harmonic number;

[0141] The output voltage harmonic content is time-marked according to the output voltage harmonic order; harmonic cycle characteristic recognition is performed based on the voltage harmonic time and the output voltage harmonic order, and output voltage harmonic cycle data is generated;

[0142] The output voltage harmonic cycle data is used to determine the distortion amplitude of the total current harmonic distortion, and the level harmonic distortion amplitude value is obtained;

[0143] The level harmonic distortion amplitude value is evaluated based on the level response time to generate the level impedance fluctuation degree;

[0144] UPQC structure stable state mapping is performed according to the level impedance fluctuation degree, and structure stable state data is obtained.

[0145] In this embodiment of the invention, a harmonic analyzer or power quality analyzer is used to detect the harmonic order of the output voltage of the UPQC topology model. The harmonic order detection rounds are set to 5-8 rounds, and the voltage signal is decomposed into the fundamental frequency and various harmonic components using Fast Fourier Transform (FFT) technology. For example, the detected harmonic orders include the 3rd, 5th, 7th, and 9th harmonics, which are recorded as the output voltage harmonic orders. Based on the detected output voltage harmonic orders, time series analysis technology is used to time-stamp the harmonic signal. The time point of occurrence of each harmonic component is recorded using a high-precision data acquisition system; for example, the 3rd harmonic appears at 0.01 seconds, the 5th harmonic appears at 0.02 seconds, and so on. These time stamps are used for subsequent analysis of the harmonic periodic characteristics. The periodic characteristics of the voltage harmonic signal are analyzed using the variance curve period identification method. Combining the voltage harmonic time and harmonic order, the periodic characteristics of each harmonic component are calculated. For example, the period of the 3rd harmonic is 0.02 seconds, and the period of the 5th harmonic is 0.01 seconds. Generate output voltage harmonic cycle data and record the periodic characteristics of each harmonic component. Analyze the impact of the output voltage harmonic cycle data on the total harmonic distortion (THD) of the current. Calculate the level harmonic distortion amplitude by comparing the current distortion under different harmonic cycles. For example, when the 3rd harmonic cycle is 0.02 seconds, the current THD is 3.5%; when the 5th harmonic cycle is 0.01 seconds, the current THD is 4.2%. Record these distortion amplitude values ​​as level harmonic distortion amplitude values. Use level response time data (e.g., 100 μs) to evaluate impedance fluctuations of the level harmonic distortion amplitude values. Evaluate the impedance fluctuation level by analyzing the relationship between the time delay during level switching and the harmonic distortion amplitude. For example, if the level response time is 100 μs and the 3rd harmonic distortion amplitude is 3.5%, the corresponding impedance fluctuation level is 5%. Record these impedance fluctuation levels as evaluation results. Input the level impedance fluctuation data into the UPQC structural stability mapping system. By analyzing the relationship between impedance fluctuation and system stability, structural steady-state data is generated. For example, if the impedance fluctuation is 5%, the mapping result shows that the UPQC structure is in a stable state; if the impedance fluctuation exceeds 10%, the mapping result shows that the system may enter an unstable state. The final structural steady-state data is used for subsequent topology evaluation.

[0146] Preferably, the topology component loss detection of the structural steady-state data in step S3 includes:

[0147] Extract the electrostatic steady-state operating frequency, electrostatic steady-state adjustment accuracy, and electrostatic steady-state modulation method from the structural steady-state data;

[0148] Based on the steady-state operating frequency and steady-state adjustment accuracy, the level adjustment conduction loss is detected to obtain the adjustment conduction loss data.

[0149] The modulation quantity loss data is obtained by detecting the modulation quantity loss based on the level steady state regulation accuracy and the level steady state modulation mode;

[0150] The modulation operation loss data is obtained by detecting the modulation operation loss based on the level steady state operation frequency and the level steady state modulation mode;

[0151] The topology component loss data is obtained by combining the regulation conduction loss data, the modulation quantity loss data and the modulation operation loss data.

[0152] In the embodiment of the application, the key parameters in the structure steady state data are extracted through the simulation results of the UPQC topology structure model, for example, the level steady state operation frequency is 50 Hz, the level steady state regulation accuracy is ±1%, and the level steady state modulation mode is pulse width modulation (PWM); the conduction loss of the power device (such as IGBT) in the UPQC is detected by using the power analyzer. Under the conditions of the level steady state operation frequency (50 Hz) and the regulation accuracy (±1%), the voltage drop and the current of the power device in the conduction state are measured, and the regulation conduction loss data is calculated. For example, the voltage drop of a certain IGBT in the conduction state is 2 V, the current is 100 A, and the conduction loss is 200 W. Through the simulation analysis tool, the switching loss in the modulation process is analyzed in combination with the level steady state regulation accuracy (±1%) and the modulation mode (PWM). For example, under the PWM modulation, the switching loss is mainly determined by the switching frequency and the device characteristics. Assuming that the switching frequency is 10 kHz, the loss of each switching process is 10 mJ, and the modulation quantity loss data is calculated. The overall operation loss of the UPQC under the conditions of the level steady state operation frequency (50 Hz) and the modulation mode (PWM) is evaluated by using the simulation model. The total loss in the operation process is calculated by monitoring the DC bus voltage, the current and the working state of each power device. For example, the operation loss includes the conduction loss, the switching loss and the capacitor charging and discharging loss, and the total loss is 500 W. The above detected loss data is integrated to form complete topology component loss data. For example, the regulation conduction loss is 200 W, the modulation quantity loss is 100 W, the modulation operation loss is 500 W, and the combined topology component loss data is 800 W.

[0153] As an example of the present application, reference is made to Fig. 1, wherein the step S4 comprises, in the present example: Figure 3

[0154] The step S41: the power energy influence quantity determination is performed on the topology component loss data, and the power energy output influence quantity data is obtained.

[0155] ​Step S42: Redundant power quantity is recorded according to the electric energy output influence quantity data, and the redundant power quantity is detected in the redundant adjustment interval, when the redundant power quantity is 0%~30%, it is marked as the low level redundant adjustment interval; when the redundant power quantity is 30%~70%, it is marked as the medium level redundant adjustment interval; when the redundant power quantity is 70%~100%, it is marked as the high level redundant adjustment interval;

[0156] Step S43: The low level redundant adjustment interval, the medium level redundant adjustment interval and the high level redundant adjustment interval are integrated to obtain the level redundant adjustment interval data;

[0157] Step S44: The adjustment sensitivity of the topology component loss data is evaluated according to the level redundant adjustment interval data, and the electric energy redundant adjustment sensitivity is generated;

[0158] Step S45: The operating condition loss change of the UPQC topology structure model is evaluated based on the electric energy redundant adjustment sensitivity, and the operating condition loss evaluation data is obtained;

[0159] Step S46: The module performance adjustment efficiency of the UPQC topology structure model is evaluated according to the operating condition loss evaluation data, and the module performance adjustment evaluation data is obtained;

[0160] Step S47: The operating condition loss evaluation data and the module performance adjustment evaluation data are summarized in the evaluation report, and the multi-level UPQC topology structure evaluation report is obtained.

[0161] In the embodiment of the present application, a high-precision power analyzer is used to monitor the key components (such as IGBT, capacitor, etc.) in the UPQC topology structure in real time, and record the loss data thereof. Through dynamic electric energy measurement technology, combined with fast Fourier transform (FFT) or wavelet transform, the power value of each frequency component is calculated by frequency domain decomposition of the electric energy output signal. For example, for a certain IGBT module, the loss is 200W at the fundamental frequency of 50Hz; the loss is 50W at the switching frequency of 10kHz. By comparing and analyzing these loss data with the power value of the electric energy output signal, the electric energy output influence data is obtained. Based on the electric energy output influence data, the redundant electric energy is calculated. For example, if the total electric energy output of the system is 1000W, and the actual demand is 800W, then the redundant electric energy is 200W. According to the percentage of the redundant electric energy, it is divided into different intervals: when the redundant electric energy is 0% to 30%, it is marked as the low-level redundant regulation interval; when the redundant electric energy is 30% to 70%, it is marked as the medium-level redundant regulation interval; when the redundant electric energy is 70% to 100%, it is marked as the high-level redundant regulation interval. The redundant regulation interval data marked above is integrated to form complete level redundant regulation interval data. For example, the percentage of redundant electric energy and the corresponding regulation interval of the system under different operating conditions are recorded for subsequent analysis. Combined with the level redundant regulation interval data, the change trend of the topology component loss data is analyzed. For example, when the system is in the low-level redundant regulation interval, the loss data changes little, indicating that the regulation sensitivity is low; when it is in the high-level redundant regulation interval, the loss data changes significantly, indicating that the regulation sensitivity is high. Through quantitative analysis, the UPQC topology structure model is simulated by using a simulation tool (such as MATLAB / Simulink), combined with the electric energy redundant regulation sensitivity, to simulate the loss change under different operating conditions. For example, in the low redundant regulation interval, the simulation result shows that the loss is 300W; in the medium redundant regulation interval, the loss is 400W; in the high redundant regulation interval, the loss is 500W. These data are recorded as operating condition loss evaluation data. By analyzing the operating condition loss evaluation data, the module performance regulation efficiency is calculated. For example, if the loss is reduced from 300W to 250W under a certain operating condition, the regulation efficiency is 16.7%. By comparing the regulation efficiency under different operating conditions, the module performance regulation evaluation data is generated. All the above evaluation data is summarized to form a multi-level UPQC topology structure evaluation report. The operating condition loss evaluation data and the module performance regulation evaluation data are recorded in detail in the report, which provides a basis for subsequent topology structure optimization.

[0162] The present application also provides a multi-level UPQC topology structure evaluation system for the multi-level UPQC topology structure evaluation method.

[0163] The UPQC design parameter acquisition module is configured to acquire multi-level UPQC design drawings; and to extract design parameters from the multi-level UPQC design drawings to obtain UPQC design parameters.

[0164] The UPQC topology structure model construction module is configured to deconstruct an electrical synergy mode according to the UPQC design parameters; to perform electrical energy connection topology mapping based on the electrical synergy mode to obtain connection topology structure data; to identify power distribution path data by identifying power flow paths at different levels based on the connection topology data; and to construct a UPQC topology structure model based on the connection topology data and the power distribution path data.

[0165] The topology component loss detection module is configured to acquire multi-level operation data; to input the multi-level operation data into the UPQC topology structure model and monitor multi-level working performance parameters; to generate structure steady-state data by performing UPQC structure steady-state identification on the multi-level working performance parameters; and to generate topology component loss data by performing topology component loss detection on the structure steady-state data.

[0166] The topology structure module performance evaluation module is configured to evaluate electrical energy redundancy regulation sensitivity according to the topology component loss data; and to perform topology structure module performance evaluation on the UPQC topology structure model based on the electrical energy redundancy regulation sensitivity to obtain a multi-level UPQC topology structure evaluation report.

[0167] The present application realizes full-process automatic processing from multi-level UPQC design parameter acquisition to topology structure performance evaluation, can accurately extract design parameters, construct an accurate topology structure model, and perform real-time monitoring and analysis on multi-level operation data. The system can quantitatively evaluate the loss characteristics of the topology components, identify the electrical energy redundancy regulation sensitivity, and generate a detailed topology structure evaluation report, thereby improving the efficiency and accuracy of UPQC topology structure evaluation.

[0168] Therefore, from any viewpoint, the embodiments should be considered as exemplary and non-limiting, the scope of the present application being defined by the appended claims and not by the above description, therefore all the variations falling within the meaning and scope of the equivalent elements of the application file are intended to be included in the present application.

[0169] The above description is merely one specific implementation of the application, which enables a person skilled in the art to understand or implement the application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the present application will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for evaluating a multi-level UPQC topology, characterized in that, The method comprises the following steps: Step S1: Obtain multi-level UPQC design drawings; extract design parameters from the multi-level UPQC design drawings to obtain UPQC design parameters; Step S2: Deconstruct the electrical coordination mode according to the UPQC design parameters; perform electrical energy connection topology mapping based on the electrical coordination mode to obtain connection topology structure data; identify the power flow path of the connection topology structure data to obtain power distribution path data; Construct a UPQC topology structure model based on the connection topology data and the power distribution path data; Step S3: Obtain multi-level operation data; input the multi-level operation data into the UPQC topology structure model and monitor multi-level working performance parameters; perform UPQC structure steady-state identification on the multi-level working performance parameters to generate structure steady-state data; perform topology component loss detection on the structure steady-state data to generate topology component loss data; Step S4: Evaluate the electrical energy redundancy regulation sensitivity according to the topology component loss data; perform topology structure module performance evaluation on the UPQC topology structure model based on the electrical energy redundancy regulation sensitivity to obtain a multi-level UPQC topology structure evaluation report.

2. The method for evaluating the multi-level UPQC topology according to claim 1, characterized in that, Step S1 comprises the following steps: Step S11: Obtain multi-level UPQC design drawings; Step S12: Mark the hardware modules of the multi-level UPQC design drawings, wherein the hardware modules include series converter modules, parallel converter modules, and DC bus energy storage element modules; Step S13: Extract the number of switch connection nodes of the series converter modules with a frequency range of 10 kHz to 50 kHz, extract the rated voltage range of 110 V to 400 V, and extract the rated current capacity, and record them as series converter design parameters; Step S14: Extract the number of grid interfaces of the parallel converter modules, the current output, and the voltage control parameters, and record them as parallel converter design parameters; Step S15: Extract the voltage energy storage capacity of the DC bus energy storage element modules, extract the charge and discharge current with a charge and discharge rate of 0.5C to 2C, and record them as DC bus energy storage design parameters; Step S16: Combine the series converter design parameters, the parallel converter design parameters, and the DC bus energy storage design parameters into UPQC design parameters.

3. The method for evaluating the multi-level UPQC topology according to claim 2, characterized in that, The deconstruction of the electrical coordination mode according to the UPQC design parameters in step S2 comprises: Map the rated current capacity according to the number of switch connection nodes to obtain node current mapping values; perform voltage level adaptation degree detection on the rated voltage range based on the node current mapping values, parameterize the adaptation relationship of the series converter modules according to the voltage level adaptation degree, and generate series converter electrical adaptation data; Determine the interface current flux of the current output according to the number of grid interfaces, and perform voltage control degree detection on the parallel converter modules based on the interface current flux and the voltage control parameters; map the constraint relationship of the voltage control degree to generate parallel converter constraint data; Detect rated energy storage capacity based on voltage energy storage capacity and charge-discharge current; determine energy storage limit according to rated energy storage capacity, and determine energy storage element limit of DC bus energy storage element module according to energy storage limit, to obtain DC bus energy storage limit data; Perform electrical coordination matching based on series converter electrical adaptation data, parallel converter constraint data and DC bus energy storage limit data, to obtain electrical coordination mode.

4. The method for evaluating the multi-level UPQC topology according to claim 1, characterized in that, The electrical energy connection topology mapping based on the electrical coordination mode in step S2 comprises: Classify the electrical coordination mode into series converter electrical adaptation type, parallel converter constraint type and DC bus energy storage limit type; Detect series electrical energy total amount of series converter electrical adaptation type; parameterize electrical energy series connection according to series electrical energy total amount, to obtain electrical energy series connection parameters; determine series topology structure according to electrical energy series connection parameters, to obtain series topology structure data; Detect parallel electrical energy distribution amount of parallel converter constraint type; mark parallel path according to parallel electrical energy distribution amount, determine parallel topology structure based on parallel path, to obtain parallel topology structure data; Detect electrical energy buffer amount of DC bus energy storage limit type; determine DC bus buffer structure according to electrical energy buffer amount, to obtain DC bus buffer structure data; Merge series topology structure data, parallel topology structure data and DC bus buffer structure, to generate connection topology structure data.

5. The method for evaluating the multi-level UPQC topology according to claim 1, characterized in that, The electrical level power flow path identification of connection topology structure data in step S2 comprises: Mark and segment structure section position of connection topology structure data, to generate structure section position; Detect series voltage division amount of structure section position, to obtain series voltage division amount; Detect parallel flow amount of structure section position, to obtain parallel flow amount; Calculate electrical level power difference value based on series voltage division amount and parallel flow amount; mark difference point of structure section position according to electrical level power difference value, and record power amount of difference point, to obtain structure section power difference amount; Sort structure section power difference amount in ascending order, to obtain power ascending order data; Determine power flow direction according to power ascending order data, and record power ascending order amount, to obtain power distribution path data.

6. The method for evaluating the multi-level UPQC topology according to claim 1, wherein, The input of multi-level operation data into UPQC topology structure model and monitoring of multi-level working performance parameters in step S3 comprises: Determine input voltage range amount of multi-level operation data, and measure level switching frequency according to input voltage range amount; Identify single-level operation characteristics based on input voltage range amount and level switching frequency, and analyze multi-level operation coupling mode according to single-level operation characteristics, to obtain multi-level operation mode data; Input multi-level operation mode data into UPQC topology structure model, and start UPQC simulation; Continuously monitor output voltage harmonics of UPQC topology structure model, and record output voltage harmonic content; Continuously monitor current total harmonic distortion of UPQC topology structure model, and record current total harmonic distortion rate; Continuously monitor level change response characteristics of UPQC topology structure model, and record level response time; The output voltage harmonic content, the current total harmonic distortion rate and the level response time are integrated to obtain the multi-level working performance parameters.

7. The method of claim 6, wherein, The UPQC structure steady state recognition of the multi-level working performance parameters in step S3 comprises: The harmonic number detection is performed on the output voltage harmonic content, and the harmonic number detection rounds are set to 5-8 rounds to obtain the output voltage harmonic number; The voltage harmonic time is marked on the output voltage harmonic content according to the output voltage harmonic number, and the harmonic cycle characteristics are recognized based on the voltage harmonic time and the output voltage harmonic number to generate the output voltage harmonic cycle data; The distortion amplitude of the current total harmonic distortion rate is determined by the output voltage harmonic cycle data to obtain the level harmonic distortion amplitude value; The impedance fluctuation degree of the level harmonic distortion amplitude value is evaluated based on the level response time to generate the level impedance fluctuation degree; The UPQC structure stable state is mapped according to the level impedance fluctuation degree to obtain the structure stable state data.

8. The method for evaluating the multi-level UPQC topology according to claim 1, wherein, The topology component loss detection of the structure stable state data in step S3 comprises: The level steady state working frequency, the level steady state adjustment accuracy and the level steady state modulation mode of the structure stable state data are extracted; The level adjustment conduction loss data is obtained by performing the level adjustment conduction loss detection on the level steady state working frequency and the level steady state adjustment accuracy; The modulation quantity loss data is obtained by performing the modulation quantity loss detection based on the level steady state adjustment accuracy and the level steady state modulation mode; The modulation running loss data is obtained by performing the running loss detection based on the level steady state working frequency and the level steady state modulation mode; The topology component loss data is obtained by combining the adjustment conduction loss data, the modulation quantity loss data and the modulation running loss data.

9. The method for evaluating the multi-level UPQC topology according to claim 1, wherein, Step S4 comprises the following steps: Step S41: The power output influence quantity data is obtained by performing the power influence quantity detection on the topology component loss data; Step S42: The redundant power quantity is recorded according to the power output influence quantity data, and the redundant adjustment interval value detection is performed on the redundant power quantity, when the redundant power quantity is 0%-30%, the level low redundant adjustment interval is marked, when the redundant power quantity is 30%-70%, the level medium redundant adjustment interval is marked, and when the redundant power quantity is 70%-100%, the level high redundant adjustment interval is marked; Step S43: The level redundant adjustment interval data is obtained by integrating the level low redundant adjustment interval, the level medium redundant adjustment interval and the level high redundant adjustment interval; Step S44: The power redundant adjustment sensitivity is generated by performing the adjustment sensitivity evaluation on the topology component loss data according to the level redundant adjustment interval data; Step S45: The running condition loss change evaluation data is obtained by performing the running condition loss change evaluation on the UPQC topology structure model based on the power redundant adjustment sensitivity; Step S46: The module performance adjustment evaluation data is obtained by performing the module performance adjustment efficiency evaluation on the UPQC topology structure model according to the running condition loss evaluation data; Step S47: The multi-level UPQC topology structure evaluation report is obtained by performing the evaluation report summary on the running condition loss evaluation data and the module performance adjustment evaluation data.

10. A system for evaluating a UPQC topology, the system comprising: A level UPQC topology structure evaluation system is used to perform the level UPQC topology structure evaluation method as claimed in claim 1, and the level UPQC topology structure evaluation system comprises: a UPQC design parameter acquisition module, configured to acquire a multi-level UPQC design drawing; and perform design parameter extraction on the multi-level UPQC design drawing to obtain UPQC design parameters; a UPQC topology structure model construction module, configured to deconstruct an electrical coordination mode according to the UPQC design parameters; perform electrical energy connection topology mapping based on the electrical coordination mode to obtain connection topology structure data; perform level power flow path identification on the connection topology structure data to obtain power distribution path data; and construct a UPQC topology structure model based on the connection topology data and the power distribution path data; a topology component loss detection module, configured to acquire multi-level operation data; input the multi-level operation data to the UPQC topology structure model and monitor multi-level working performance parameters; perform UPQC structure steady-state identification on the multi-level working performance parameters to generate structure steady-state data; and perform topology component loss detection on the structure steady-state data to generate topology component loss data; a topology structure module performance evaluation module, configured to evaluate electrical energy redundancy regulation sensitivity according to the topology component loss data; and perform topology structure module performance evaluation on the UPQC topology structure model based on the electrical energy redundancy regulation sensitivity to obtain a multi-level UPQC topology structure evaluation report.

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