Mixed function bridgeless topology circuit adopting GaN device

Abstract

The invention discloses a mixed function bridgeless topology circuit adopting a GaN device, which adopts a solution of combining totem-pole-like bridgeless and LLC (Logical Link Control), can simultaneously realize three functions of bridgeless rectification, power factor correction (PFC) and isolated direct current-direct current (DC / DC) conversion, and harmonic waves can meet the requirements of the industrial field. The topology circuit only needs four high-speed GaN power HEMT devices, two low-speed Si power MOSFET devices, two low-speed Si power thyristors and one auxiliary small inductor capable of correcting input current waveforms, does not need a rectifier bridge, only needs one-stage control to stabilize output voltage, and greatly simplifies the difficulty of system design.

Description

Technical Field

[0001] The present invention relates to a hybrid functional bridge-less topology circuit using GaN devices, belonging to the technical field of topology circuits. Background Art

[0002] The traditional silicon-based solutions have reached the performance bottleneck. The new generation of wide bandgap semiconductor devices, such as gallium nitride (GaN) high electron mobility transistors (HEMTs), have significant advantages such as high operating frequency, high operating efficiency, high breakdown voltage, high temperature resistance, strong radiation resistance, and no reverse recovery. They can promote the development of traditional power electronic products towards smaller sizes and higher efficiency, and are an ideal choice to replace the silicon-based solutions to meet future requirements.

[0003] There are various forms of bridge-less power factor correction (PFC) topology circuits. In recent years, considering the technical solutions adopted in the industry, the totem pole PFC topology circuit (TP-PFC) is a bridge-less PFC topology circuit that is particularly beneficial for leveraging the advantages of GaN HEMT devices, with a peak operating efficiency of up to 99%. After adopting GaN HEMT devices, this circuit can effectively suppress the zero-crossing spike current. By using a soft-switching control method, its peak operating efficiency can be pushed above 99%. However, this circuit can only achieve the PFC function and cannot achieve the isolated DC-DC conversion (DC / DC) function. It often needs to be combined with an isolated DC / DC topology circuit to form a two-stage architecture, and two independent control systems are required to finally meet the design requirements of mains input and isolated DC output. The overall peak operating efficiency of the two-stage circuit is about 97%, as Figure 1 shown.

[0004] Single-stage topology circuits can simultaneously achieve PFC and isolated DC / DC functions through a single-stage circuit, replacing the traditional two-stage topology circuit of PFC plus isolated DC / DC. This can effectively reduce the number of components, improve work efficiency, reduce costs, and enhance reliability, making it an ideal topology architecture. Most existing single-stage topology circuits are for low power. Based on the traditional flyback topology architecture, they use the natural following of the current waveform with the voltage waveform in the critical mode (CrM) to achieve a better PFC function. However, they use a full-bridge rectifier, resulting in a relatively low system efficiency. The power rating is usually below 200W, and multiple coupled coils are used on the primary side of the transformer in this circuit, requiring a trade-off design between work efficiency and PF value. Patent CN115549476A (A Single-stage Series Resonant Conversion Device, Nanjing Borland Electronic Technology Co., Ltd.) proposed a single-stage series resonant conversion device. This device is based on the traditional series resonant (LLC) topology circuit and does not make any improvements to the topology circuit. It only introduces a new charge control method in control to solve the problem of unstable output voltage when the input voltage range is relatively wide. This circuit has a high power capacity but still uses a full-bridge rectifier and does not include the PFC function, and there is still room for improving the system efficiency. Patent CN114710050A (A Control Method for a Single-stage Power Conversion Device, Nanjing Borland Electronic Technology Co., Ltd.) also introduces a new pulse width modulation (PWM) control method based on the traditional cascaded half-bridge LLC (CHB-LLC) topology circuit to increase the input voltage range. This circuit has a high power capacity but also uses a full-bridge rectifier and does not include the PFC function, and there is still room for improving the system efficiency.

[0005] The purpose of this invention patent is to propose a new type of single-stage topology circuit and its soft-switching control method, giving full play to the advantages of GaN HEMT devices, achieving PFC and isolated DC / DC functions simultaneously through a single-stage circuit, integrating TP-PFC and resonant isolated DC / DC into one, realizing the full functions of single-stage, bridge-less, high-power, soft-switching, and isolated output, and achieving the goals of high efficiency and small size. Summary of the Invention

[0006] The purpose of the present invention is to provide a hybrid-function bridge-less topology circuit using GaN devices.

[0007] The purpose of the present invention is achieved through the following technical solutions:

[0008] A hybrid functional bridge - less topology circuit using GaN devices, comprising: an AC input terminal, a PFC inductor Lpa, four GaN HEMTs M1, M2, M3, M4, two Si MOSFETs K1 and K2, two thyristors Dpa1 and Dpa2, a resonant capacitor Cra, a resonant inductor Lr, an energy - storage capacitor CB, a transformer Ta, a secondary - side rectifier circuit, an output filter capacitor Co, and an output load resistor Ro;

[0009] The first end of the AC input terminal is connected to the first end of the PFC inductor Lpa. The second end of the PFC inductor Lpa is connected to the anode of the thyristor Dpa1. The cathode of the thyristor Dpa1 is connected to the same - name end of the primary winding Np1 of the transformer Ta and the anode of the thyristor Dpa2. The cathode of the thyristor Dpa2 is connected between the second end of the PFC inductor Lpa and the anode of the thyristor Dpa1. The second end of the AC input terminal is connected to the drain of the Si MOSFET K2. The source of the Si MOSFET K2 is connected to the sources of the GaN HEMT M2, the GaN HEMT M4, and the negative electrode of the energy - storage capacitor CB. The drain of the GaN HEMT M2 is connected to the source of the GaN HEMT M1. The drain of the GaN HEMT M1 is connected to the drain of the Si MOSFET K1, the source of the GaN HEMT M3, and the drain of the GaN HEMT M4. The source of the Si MOSFET K1 is connected to the drain of the Si MOSFET K2. The drain of the GaN HEMT M3 is connected in series with the resonant capacitor Cra and the resonant inductor Lr in sequence. The second end of the resonant inductor Lr is connected to the same - name end of the primary winding Np2 of the transformer Ta. The positive electrode of the energy - storage capacitor CB is connected between the drain of the GaN HEMT M3 and the resonant capacitor Cra. The primary winding Np2 of the transformer Ta is connected in series with the primary winding Np1. The different - name end of the primary winding Np1 is connected between the drain of the GaN HEMT M2 and the source of the GaN HEMT M1;

[0010] The output terminal of the secondary winding Nsa of the transformer Ta is connected to the input terminal of the secondary - side rectifier circuit. The output terminal of the secondary - side rectifier circuit is connected in parallel with the output filter capacitor Co and the output load resistor Ro to achieve DC output.

[0011] Preferably, the secondary - side rectifier circuit includes four transistors S1, S2, S3, S4 connected in a bridge.

[0012] Preferably, the same-name end of the secondary winding Nsa of the transformer Ta is connected to the source electrode of the transistor S1, the drain electrode of the transistor S1 is connected to the drain electrode of the transistor S3, the source electrode of the transistor S3 is connected to the drain electrode of the transistor S4, the source electrode of the transistor S4 is connected to the source electrode of the transistor S2, the drain electrode of the transistor S2 is connected to the source electrode of the transistor S1, the different-name end of the secondary winding Nsa of the transformer Ta is connected between the source electrode of the transistor S3 and the drain electrode of the transistor S4, the positive terminal of the output filter capacitor Co is connected between the drain electrode of the transistor S1 and the drain electrode of the transistor S3, the negative terminal of the output filter capacitor Co is connected between the source electrode of the transistor S2 and the source electrode of the transistor S4, one end of the output load resistor Ro is connected between the drain electrode of the transistor S1 and the drain electrode of the transistor S3, and the other end of the output load resistor Ro is connected between the source electrode of the transistor S2 and the source electrode of the transistor S4.

[0013] Preferably, the transistor is a GaN HEMT or a Si MOSFET.

[0014] Preferably, it further includes another energy storage capacitor CB1, which is connected in series with the energy storage capacitor CB. One end of the energy storage capacitor CB1 is connected between the drain electrode of the GaN HEMT M3 and the positive terminal of the energy storage capacitor CB, and the other end is connected to the resonant capacitor Cra.

[0015] Preferably, the transformer Ta further includes a resonant inductor Lm, and the resonant inductor Lm is connected in parallel with the series-connected primary winding.

[0016] Preferably, Lpa = Lr, NP1 = NP2, and LM = 3 to 8·Lr.

[0017] The present invention also discloses a control method for the above hybrid-function bridge-less topology circuit using GaN devices. Specifically,

[0018] (1) When it is determined that the AC input voltage is in the positive half-cycle, first turn off M3 and M4, or turn off M3 and turn on M4, and enter the PFC energy storage stage. At this time, the current flow direction is: the first AC input terminal → Lpa → Dpa1 → NP1 → M2 → K2 → the second AC input terminal;

[0019] At this time, the LLC is in the first half-cycle, and M2 conducts to form a loop. The current flow direction is: CB → Cra → Lr → LM → M2 → CB,

[0020] The corresponding current flow direction of the transformer secondary side in the first half-cycle is: the same-name end of Nsa → S1 → Co → S4 → the different-name end of Nsa;

[0021] When the current of the PFC inductor Lpa reaches the preset threshold, the controller closes M4 and opens M3, injecting the energy of the PFC inductor through M1 and M3 into the energy storage capacitor CB. At the same time, the LLC resonant cavity enters the second half-cycle resonant state. When entering the PFC boost stage, the PFC current flow direction at this time is: the first AC input terminal → Lpa → Dpa1 → NP1 → M1 → M3 → CB → K2 → the second AC input terminal;

[0022] At this time, the LLC is in the second half-cycle, and only M1 conducts to form a loop. The current flow direction is: the first AC input terminal → Lpa → Dpa1 → NP2 → Lr → Cra → CB → K2 → the second AC input terminal,

[0023] The corresponding current flow direction of the secondary side of the transformer in the second half-cycle is: the non-polar end of Nsa → S3 → Co → S2 → the polar end of Nsa;

[0024] (2) When it is determined that the AC input voltage is in the negative half-cycle, M3 is opened, and both K1 and M4 are closed, entering the PFC energy storage stage. At this time, the current flow direction is: the second AC input terminal → K1 → M1 → NP1 → Dpa2 → Lpa → the first AC input terminal;

[0025] At this time, the LLC is in the first half-cycle, and only M1 conducts to form a loop. The current flow direction is: CB → Cra → Lr → LM → → M1 → M4 → CB,

[0026] The corresponding current flow direction of the secondary side of the transformer in the first half-cycle is: the polar end of Nsa → S1 → Co → S4 → the non-polar end of Nsa;

[0027] When the reverse current of the PFC inductor reaches the threshold, the controller closes M3 and opens M4, injecting the energy through M2 and M3 into the energy storage capacitor CB. At the same time, when the LLC resonant cavity switches to the second half-cycle working state and enters the PFC boost stage, the PFC current flow direction at this time is: the second AC input terminal → K1 → M3 → CB → M2 → NP1 → Dpa2 → Lpa → the first AC input terminal;

[0028] At this time, the LLC is in the second half-cycle, and only M2 conducts to form a loop. The current flow direction is: the source of M2 → LM → Lr → Cra → CB → the drain of M2,

[0029] The corresponding current flow direction of the secondary side of the transformer in the second half-cycle is: the non-polar end of Nsa → S3 → Co → S2 → the polar end of Nsa.

[0030] The present invention uses a single-stage circuit to simultaneously achieve power factor correction and isolated DC-DC conversion functions and is a bridge-less design. Among them, the isolated DC-DC conversion operates in a series resonant soft-switching mode, while the power factor correction auxiliary inductor operates in a discontinuous mode. The isolated DC-DC conversion transformer and the power factor correction auxiliary inductor can also adopt an integrated magnetic component design. This technology breaks through a single-module power of more than 2 kW, is compatible with a wide input voltage (85 - 305 VAC) and complex load scenarios, and provides a power solution with high efficiency, compactness, and reliability for front-line fields such as electric vehicle superchargers, high-computing power data centers, and smart grids.

[0031] The beneficial effects of the present invention are as follows:

[0032] 1. Single-stage: It adopts a set of control systems to achieve both PFC function and DC / DC isolated output function. All magnetic components can be integrated in the same magnetic core. Compared with the traditional two-stage structure, the size can be reduced by at least 15%.

[0033] 2. Bridge-less: There is no rectifier bridge. Compared with the bridge rectification scheme, the efficiency can be increased by at least 1%.

[0034] 3. High power of several kilowatts, which is increased from the traditional flyback power level below 200 W to a power level of 2 kW and above.

[0035] 4. Full soft-switching, high efficiency, and low EMI: The peak efficiency can theoretically reach more than 97.5%. Compared with the Figure 1 traditional two-stage circuit, the efficiency can be increased by about 0.5%.

[0036] 5. High operating frequency: It can operate at a high-frequency state of 500 kHz - 4 MHz or even higher. Description of the Drawings

[0037] Figure 1 It is a circuit architecture diagram of a traditional totem-pole bridge-less PFC and isolated LLC two-stage circuit.

[0038] Figure 2 It is a circuit diagram of the hybrid function bridge-less topology of the present invention using GaN devices.

[0039] Figure 3 It is the topology circuit of Embodiment 1.

[0040] Figure 4 It is the topology circuit of Embodiment 2.

[0041] Figure 5 It is the positive half-cycle high-frequency energy storage working timing diagram of Embodiment 1.

[0042] Figure 6 It is the positive half-cycle high-frequency boost working timing diagram of Embodiment 1.

[0043] Figure 7 It is the negative half - cycle high - frequency energy storage working timing diagram of Embodiment 1.

[0044] Figure 8 It is the negative half - cycle high - frequency boost working timing diagram of Embodiment 1.

[0045] Figure 9 It is the positive half - cycle high - frequency energy storage and boost working timing waveform diagram of Embodiment 1.

[0046] Figure 10 It is the negative half - cycle high - frequency energy storage and boost working timing waveform diagram of Embodiment 1.

[0047] Figure 11 It is the control logic block diagram of the present invention. Specific implementation manners

[0048] Figure 2 It shows the circuit structure block diagram of the present invention.

[0049] Embodiment 1

[0050] As Figure 3 shown, the hybrid - function bridgeless topology circuit adopting GaN devices in this embodiment includes: an AC input terminal, a PFC inductor Lpa, four GaN HEMTs M1, M2, M3, M4, two Si MOSFETs K1 and K2, two thyristors Dpa1 and Dpa2, a resonant capacitor Cra, a resonant inductor Lr, an energy - storage capacitor CB, a transformer Ta, a secondary - side rectification circuit, an output filter capacitor Co, and an output load resistor Ro;

[0051] The first end of the AC input terminal is connected to the first end of the PFC inductor Lpa. The second end of the PFC inductor Lpa is connected to the anode of the thyristor Dpa1. The cathode of the thyristor Dpa1 is connected to the same-name end of the primary winding Np1 of the transformer Ta and the anode of the thyristor Dpa2. The cathode of the thyristor Dpa2 is connected between the second end of the PFC inductor Lpa and the anode of the thyristor Dpa1. The second end of the AC input terminal is connected to the drain of the Si MOSFET K2. The source of the Si MOSFET K2 is connected to the source of the GaN HEMT M2, the source of the GaN HEMT M4, and the negative electrode of the energy storage capacitor CB. The drain of the GaN HEMT M2 is connected to the source of the GaN HEMT M1. The drain of the GaN HEMT M1 is connected to the drain of the Si MOSFET K1, the source of the GaN HEMT M3, and the drain of the GaN HEMT M4. The source of the Si MOSFET K1 is connected to the drain of the Si MOSFET K2. The drain of the GaN HEMT M3 is connected in series with the resonant capacitor Cra and the resonant inductor Lr. Cra and Lr together form a high-frequency resonant cavity. The second end of the resonant inductor Lr is connected to the same-name end of the primary winding Np2 of the transformer Ta. The positive electrode of the energy storage capacitor CB is connected between the drain of the GaN HEMT M3 and the resonant capacitor Cra. The primary winding Np2 of the transformer Ta is connected in series with the primary winding Np1. The different-name end of the primary winding Np1 is connected between the drain of the GaN HEMT M2 and the source of the GaN HEMT M1. The transformer Ta further includes a resonant inductor Lm. The resonant inductor Lm is connected in parallel with the series-connected primary windings. Cra, Lr, and Lm together form a resonant cavity during the dead time. Let Lpa = Lr, NP1 = NP2, and LM = 3 - 8·Lr;

[0052] The output terminal of the secondary winding Nsa of the transformer Ta is connected to the input terminal of the secondary rectifier circuit. The output terminals of the secondary rectifier circuit are connected in parallel with an output filter capacitor Co and an output load resistor Ro to achieve DC output. Specifically, the secondary rectifier circuit includes four transistors S1, S2, S3, and S4 connected in a bridge configuration. The transistors can be GaN HEMTs or SiMOSFETs. The same-name terminal of the secondary winding Nsa of the transformer Ta is connected to the source electrode of the transistor S1. The drain electrode of the transistor S1 is connected to the drain electrode of the transistor S3. The source electrode of the transistor S3 is connected to the drain electrode of the transistor S4. The source electrode of the transistor S4 is connected to the source electrode of the transistor S2. The drain electrode of the transistor S2 is connected to the source electrode of the transistor S1. The different-name terminal of the secondary winding Nsa of the transformer Ta is connected between the source electrode of the transistor S3 and the drain electrode of the transistor S4. The positive terminal of the output filter capacitor Co is connected between the drain electrodes of the transistors S1 and S3. The negative terminal of the output filter capacitor Co is connected between the source electrodes of the transistors S2 and S4. One end of the output load resistor Ro is connected between the drain electrodes of the transistors S1 and S3, and the other end of the output load resistor Ro is connected between the source electrodes of the transistors S2 and S4.

[0053] As Figures 5 - 8 shown, the working path of this circuit is as follows:

[0054] Positive half-cycle working loop:

[0055] PFC energy storage stage: Input a → Lpa → Dpa1 → e → NP1 → c → M2 → g → K2 → b (at this time, both M3 and M4 are off or M3 is off and M4 is on);

[0056] PFC boost stage: Input a → Lpa → Dpa1 → e → NP1 → c → M1 → f → M3 → d → CB → g → K2 → b (at this time, M3 is on and M4 is off);

[0057] LLC first half-cycle (corresponding to the PFC energy storage stage, with M2 conducting to form a loop): CB → d → Cra → Lr → h → LM → c → M2 → g;

[0058] LLC second half-cycle (corresponding to the PFC boost stage, with M1 conducting to form a loop): a → Lpa → Dpa1 → e → NP2 → h → Lr → Cra → d → CB → g → K2 → b;

[0059] Secondary first half-cycle (corresponding to the PFC energy storage stage, with M2 conducting to form a loop): Nsa → i → S1 → m → Co → n → S4 → j;

[0060] Secondary second half-cycle (corresponding to the PFC boost stage, with M1 conducting to form a loop): Nsa → j → S3 → m → Co → n → S2 → i;

[0061] The high-frequency energy storage and boost working timing waveform diagram for the positive half-cycle is as Figure 9 shown.

[0062] Negative half-cycle working loop:

[0063] PFC energy storage stage: Input b → K1 → f → M1 → c → NP1 → e → Dpa2 → Lpa → a (at this time, M3 is disconnected and M4 is closed) (at this time, both K1 and M4 are closed, and point b is the reference 0 voltage for point g);

[0064] PFC boost stage: Input b → K1 → f → M3 → d → CB → g → M2 → c → NP1 → e → Dpa2 → Lpa → a (at this time, M3 is closed and M4 is disconnected);

[0065] The first half of the LLC cycle (corresponding to the PFC energy storage stage, with M1 conducting to form a loop): CB → d → Cra → Lr → h → LM → c → M1 → f → M4 → g (at this time, M3 is disconnected and M4 is closed) (at this time, both K1 and M4 are closed, and point b is the reference 0 voltage for point g);

[0066] The second half of the LLC cycle (corresponding to the PFC boost stage, with M2 conducting to form a loop): c → LM → h → Lr → Cra → d → CB → g → M2 → c;

[0067] The first half of the secondary side (corresponding to the PFC energy storage stage, with M1 conducting to form a loop): Nsa → i → S1 → m → Co → n → S4 → j;

[0068] The second half of the secondary side (corresponding to the PFC boost stage, with M2 conducting to form a loop): Nsa → j → S3 → m → Co → n → S2 → i;

[0069] The high-frequency energy storage and boost working timing waveform diagram for the negative half-cycle is as Figure 10 shown.

[0070] Its control logic is as Figure 11As shown, the principle is as follows: the controller first identifies the polarity change and performs zero-crossing detection by continuously sampling the AC input voltage Va. Specifically, if Va changes from negative to positive in two consecutive sampling cycles, it is determined that the positive half cycle has started; if it changes from positive to negative, it is the start of the negative half cycle. The controller updates the internal state machine accordingly and executes the PFC and LLC control strategies corresponding to the positive half cycle or the negative half cycle. On this basis, the system further distinguishes whether it is currently in the energy storage stage or the boost stage according to the control state of the two power devices M3 and M4. When M3 is disconnected and M4 is closed, or both M3 and M4 are disconnected, the system is in the PFC energy storage stage. At this time, the input current stores energy through the PFC inductor Lpa, and the energy enters the magnetic flux loop and is stored in the primary magnetic field of the transformer and the energy storage capacitor CB; when M3 is turned on and M4 is disconnected, the system is in the PFC boost stage, and the energy stored in the previous stage is released through the GaN device and drives the resonant cavity to operate, while driving the secondary rectifier output. Based on this judgment logic, the controller controls the combination of Dpa1, Dpa2, K1, K2 and M1, M2, M3, M4 and other devices to conduct, forming a forward or reverse PFC current path, and at the same time excites the resonant circuit to enter the first half cycle or the second half cycle of LLC working state. At the same time, the DSP also performs PID regulation according to the deviation between the output voltage Vo and the reference value, dynamically controls the conduction time or PWM frequency of M1 or M2, and realizes closed-loop voltage regulation of the output voltage. Under different load conditions, the system automatically selects the control strategy: when the load is between 10% and 50%, PWM and PFM mixed control is adopted; when the load is less than 10%, it enters the fixed frequency hopping mode, adopts a fixed 200kHz frequency and conducts intermittently in the no-load interval. The secondary side rectification part adopts synchronous rectification. The DSP generates the drive signals of S1 to S4 in real time according to the conduction state of M1 / M2, and transmits them to the secondary side drive circuit through optical coupling isolation, so that the rectifier tube is alternately turned on in the first and second half cycles of LLC to achieve rectification.

[0071] Example 2

[0072] like Figure 4 As shown, the circuit structure of this embodiment is basically the same as that of Embodiment 1, except that it further includes another energy storage capacitor CB1, which is connected in series with the energy storage capacitor CB2. One end of the energy storage capacitor CB1 is connected between the drain of the GaN HEMT M3 and the positive end of the energy storage capacitor CB2, and the other end is connected to the resonant capacitor Cra. CB1 and CB2 are energy storage capacitors, which can be electrolytic capacitors or ceramic capacitors. Usually, CB1 is a ceramic capacitor and CB2 is an electrolytic capacitor. The connection of CB1 and CB2 in series can solve the withstand voltage problem of CB2, which is more conducive to the withstand voltage selection of capacitors.

[0073] Its working path is:

[0074] Positive half cycle working loop:

[0075] PFC energy storage stage: Input a → Lpa → Dpa1 → e → NP1 → c → M2 → g → K2 → b (at this time, both M3 and M4 are off or M3 is off and M4 is on);

[0076] PFC boost stage: Input a → Lpa → Dpa1 → e → NP1 → c → M1 → f → M3 → d2 → CB2 → g → K2 → b (at this time, M3 is on and M4 is off);

[0077] First half of LLC (corresponding to PFC energy storage stage, with M2 conducting to form a loop): CB1 and CB2 in series → d1 → Cra → Lr → h → LM → c → M2 → g;

[0078] Second half of LLC (corresponding to PFC boost stage, with M1 conducting to form a loop): a → Lpa → Dpa1 → e → NP2 → h → Lr → Cra → d1 → CB1 and CB2 in series → g → K2 → b;

[0079] First half of secondary side (corresponding to PFC energy storage stage, with M2 conducting to form a loop): Nsa → i → S1 → m → Co → n → S4 → j;

[0080] Second half of secondary side (corresponding to PFC boost stage, with M1 conducting to form a loop): Nsa → j → S3 → m → Co → n → S2 → i;

[0081] Negative half - cycle working loop:

[0082] PFC energy storage stage: Input b → K1 → f → M1 → c → NP1 → e → Dpa2 → Lpa → a (at this time, M3 is off and M4 is on) (at this time, both K1 and M4 are on, and point b is the reference 0 voltage for point g);

[0083] PFC boost stage: Input b → K1 → f → M3 → d2 → CB2 → g → M2 → c → NP1 → e → Dpa2 → Lpa → a (at this time, M3 is on and M4 is off);

[0084] First half of LLC (corresponding to PFC energy storage stage, with M1 conducting to form a loop): CB1 and CB2 in series → d1 → Cra → Lr → h → LM → c → M1 → f → M4 → g (at this time, M3 is off and M4 is on) (at this time, both K1 and M4 are on, and point b is the reference 0 voltage for point g);

[0085] Second half of LLC (corresponding to PFC boost stage, with M2 conducting to form a loop): c → LM → h → Lr → Cra → d → CB1 and CB2 in series → g → M2 → c;

[0086] The first half of the secondary side (corresponding to the PFC energy storage stage, with M1 conducting in total to form a loop): Nsa → i → S1 → m → Co → n → S4 → j;

[0087] The second half of the secondary side (corresponding to the PFC boost stage, with M2 conducting in total to form a loop): Nsa → j → S3 → m → Co → n → S2 → i.

[0088] The above embodiments are preferred embodiments of the present invention. However, the embodiments of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A hybrid functional bridgeless topology circuit using GaN devices, characterized in that Including: AC input terminal, PFC inductor Lpa, four GaN HEMTs M1, M2, M3, M4, two Si MOSFETs K1 and K2, two thyristors Dpa1 and Dpa2, resonant capacitor Cra, resonant inductor Lr, energy storage capacitor CB, transformer Ta, secondary rectifier circuit, output filter capacitor Co and output load resistor Ro; The first end of the AC input terminal is connected to the first end of the PFC inductor Lpa, the second end of the PFC inductor Lpa is connected to the anode of the thyristor Dpa1, the cathode of the thyristor Dpa1 is connected to the same-name end of the primary winding Np1 of the transformer Ta and the anode of the thyristor Dpa2, the cathode of the thyristor Dpa2 is connected between the second end of the PFC inductor Lpa and the anode of the thyristor Dpa1, the second end of the AC input terminal is connected to the drain of the Si MOSFET K2, the source of the Si MOSFET K2 is connected to the sources of the GaN HEMT M2, the GaN HEMT M4 and the negative electrode of the energy storage capacitor CB, the drain of the GaN HEMT M2 is connected to the source of the GaN HEMT M1, the drain of the GaN HEMT M1 is connected to the drain of the Si MOSFET K1, the source of the GaN HEMT M3, the drain of the GaN HEMT M4, the source of the Si MOSFET K1 is connected to the drain of the Si MOSFET K2, the drain of the GaN HEMT M3 is connected in series with the resonant capacitor Cra and the resonant inductor Lr in sequence, the second end of the resonant inductor Lr is connected to the same-name end of the primary winding Np2 of the transformer Ta, the positive electrode of the energy storage capacitor CB is connected between the drain of the GaN HEMT M3 and the resonant capacitor Cra, the primary winding Np2 of the transformer Ta is connected in series with the primary winding Np1, and the different-name end of the primary winding Np1 is connected between the drain of the GaN HEMT M2 and the source of the GaN HEMT M1; The output terminal of the secondary winding Nsa of the transformer Ta is connected to the input terminal of the secondary rectifier circuit, and the output terminal of the secondary rectifier circuit is connected in parallel with the output filter capacitor Co and the output load resistor Ro to realize DC output.

2. The hybrid functional bridgeless topology circuit using GaN devices according to claim 1, characterized in that: The secondary rectifier circuit includes four bridge-connected transistors S1, S2, S3, S4.

3. The hybrid functional bridgeless topology circuit using GaN devices according to claim 2, characterized in that: The same-named end of the secondary winding Nsa of the transformer Ta is connected to the source electrode of the transistor S1. The drain electrode of the transistor S1 is connected to the drain electrode of the transistor S3. The source electrode of the transistor S3 is connected to the drain electrode of the transistor S4. The source electrode of the transistor S4 is connected to the source electrode of the transistor S2. The drain electrode of the transistor S2 is connected to the source electrode of the transistor S1. The different-named end of the secondary winding Nsa of the transformer Ta is connected between the source electrode of the transistor S3 and the drain electrode of the transistor S4. The positive terminal of the output filter capacitor Co is connected between the drain electrode of the transistor S1 and the drain electrode of the transistor S3. The negative terminal of the output filter capacitor Co is connected between the source electrode of the transistor S2 and the source electrode of the transistor S4. One end of the output load resistor Ro is connected between the drain electrode of the transistor S1 and the drain electrode of the transistor S3. The other end of the output load resistor Ro is connected between the source electrode of the transistor S2 and the source electrode of the transistor S4.

4. The hybrid-functional bridgeless topology circuit adopting GaN devices according to claim 3, wherein: The transistor is a GaN HEMT or a Si MOSFET.

5. The hybrid functional bridgeless topology circuit using GaN devices according to any one of claims 1-4, characterized in that: It further includes another energy storage capacitor CB1, which is connected in series with the energy storage capacitor CB. One end of the energy storage capacitor CB1 is connected between the drain electrode of the GaN HEMT M3 and the positive terminal of the energy storage capacitor CB, and the other end is connected to the resonant capacitor Cra.

6. The hybrid functional bridgeless topology circuit using GaN devices according to claim 5, characterized in that: CB1 is a ceramic capacitor and CB is an electrolytic capacitor.

7. The hybrid functional bridgeless topology circuit using GaN devices according to claim 5, characterized in that: The transformer Ta further includes a resonant inductor Lm, and the resonant inductor Lm is connected in parallel with the series primary winding.

8. The hybrid functional bridgeless topology circuit using GaN devices according to claim 7, characterized in that: L pa = L r , N P1 = N P2 , L M = 3 to 8 · L r .

9. The control method of the hybrid function bridge-less topology circuit using GaN devices according to any one of claims 1-8, characterized in that: (1) When it is judged that the AC input voltage is in the positive half cycle, first turn off M3 and M4, or turn off M3 and turn on M4, and enter the PFC energy storage stage. At this time, the current flow direction is: the first AC input terminal → Lpa → Dpa1 → NP1 → M2 → K2 → the second AC input terminal; At this time, LLC is in the first half cycle, and M2 conducts to form a loop. The current flow direction is: CB → Cra → Lr → LM → M2 → CB, The corresponding current flow direction of the transformer secondary side in the first half cycle is: the same-named end of Nsa → S1 → Co → S4 → the different-named end of Nsa; When the current of the PFC inductor Lpa reaches the preset threshold, the controller turns on M4 and turns off M3, injects the energy of the PFC inductor into the energy storage capacitor CB through M1 and M3, and at the same time, the LLC resonant cavity enters the second half cycle resonant state. When entering the PFC boost stage, the PFC current flow direction at this time is: the first AC input terminal → Lpa → Dpa1 → NP1 → M1 → M3 → CB → K2 → the second AC input terminal; At this time, LLC is in the second half cycle, and M1 conducts to form a loop. The current flow direction is: the first AC input terminal → Lpa → Dpa1 → NP2 → Lr → Cra → CB → K2 → the second AC input terminal, The corresponding current flow direction of the transformer secondary side in the second half cycle is: the different-named end of Nsa → S3 → Co → S2 → the same-named end of Nsa; (2) When it is determined that the AC input voltage is in the negative half cycle, M3 is turned off, and both K1 and M4 are turned on, entering the PFC energy storage stage. At this time, the current flow direction is: the second AC input terminal → K1 → M1 → NP1 → Dpa2 → Lpa → the first AC input terminal; At this time, LLC is in the first half cycle, and M1 conducts to form a loop. The current flow direction is: CB → Cra → Lr → LM → → M1 → M4 → CB, The corresponding current flow direction of the secondary side of the transformer in the first half cycle is: the same name terminal of Nsa → S1 → Co → S4 → the different name terminal of Nsa; When the PFC inductor current reverses and reaches the threshold, the controller turns on M3 and turns off M4, injects energy into the energy storage capacitor CB through M2 and M3, and at the same time, when the LLC resonant cavity switches to the second half cycle working state and enters the PFC boost stage, the PFC current flow direction at this time is: the second AC input terminal → K1 → M3 → CB → M2 → NP1 → Dpa2 → Lpa → the first AC input terminal; At this time, LLC is in the second half cycle, and M2 conducts to form a loop. The current flow direction is: the source of M2 → LM → Lr → Cra → CB → the drain of M2, The corresponding current flow direction of the secondary side of the transformer in the second half cycle is: the different name terminal of Nsa → S3 → Co → S2 → the same name terminal of Nsa.

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