Circuit for outputting two groups of staggered clock signals and application

Abstract

The invention relates to a circuit for outputting two groups of staggered clock signals. The circuit comprises a clock signal modulation circuit and two AND gate branches, and each AND gate branch is connected with a NOT gate branch; a first signal and a second signal which are staggered are output, and after the first signal, the second signal and a basic clock signal are input into two AND gate branches respectively, two driving signals which are staggered with each other are output to form a first group of clock driving signals; and after the two driving signals pass through the respective NOT gate branches, the other two staggered driving signals are output to form a second group of clock driving signals. The circuit simultaneously outputs two groups of clock driving signals which are mutually staggered by 180 degrees, one group outputs the clock driving signals which are mutually staggered by 180 degrees and have the duty ratio smaller than 50%, and the circuit is suitable for push-pull power conversion topology application; and one group outputs clock signals which are mutually staggered by 180 degrees and have the duty ratio greater than 50%, and is suitable for power topology application of two paths of BUCK or two paths of BOOST and the like which are connected in parallel.

Description

Technical Field

[0001] The present invention relates to the field of control circuits. Specifically, it relates to a circuit for outputting two sets of interleaved clock signals and its applications. Background Art

[0002] PWM (Pulse Width Modulation), abbreviated as pulse width modulation, is a very effective technology for controlling analog circuits using the digital output of a microprocessor. It is widely used in measurement, communication, industrial control, etc. The characteristic of a PWM signal is to output a high level or a low level, and it is commonly used as a clock signal. The frequency of PWM refers to the number of times the signal goes from high level to low level and then back to high level within 1 second, and it also represents how many cycles there are in 1 second; the duty cycle of PWM is the ratio of the time of the high level to the entire cycle time within one cycle. Therefore, a PWM chip can provide a clock drive signal that repeats continuously to control the signal transmission switch in the application circuit.

[0003] Affected by the international situation, the supply of foreign high-end PWM chips cannot meet the demand, and there is an urgent need for various power topology PWM drive control devices. The existing PWM chips output a single clock drive signal, only one drive signal that switches between high and low levels. If the power output circuit involves two switching transistors, two clock oscillators need to be set up to output two different drive signals, and an additional delay circuit needs to be set up to control one of the drive signals to stagger the high / low levels of the two drive signals, which has certain instability. It can be seen that the existing circuit for outputting two drive signals has a complex design, high cost, and poor stability.

[0004] The above problems are worthy of solution. Summary of the Invention

[0005] In order to overcome the problems of the complex circuit structure of the existing clock drive output circuit and the poor stability of the two interleaved drive signals, the present invention provides a circuit for outputting two sets of interleaved clock signals and its applications.

[0006] The technical solution of the present invention is as follows:

[0007] A circuit for outputting two groups of interleaved clock signals, including a clock signal modulation circuit, the input end of the clock signal modulation circuit obtains a basic clock signal; the clock signal modulation circuit includes a single positive-edge flip-flop and a first NOT gate, the basic clock signal is input into the single-edge flip-flop and then outputs a first signal, the first signal is input into the first NOT gate and then outputs a second signal interleaved with the first signal; the clock signal modulation circuit further includes two AND gate branches, and each AND gate branch is connected to a NOT gate branch; after the first signal and the second signal are respectively input into the two AND gate branches together with the basic clock signal, two interleaved driving signals are output to form a first group of clock driving signals; after the two driving signals pass through their respective NOT gate branches, another two interleaved driving signals are output to form a second group of clock driving signals.

[0008] According to the present invention of the above solution, the two driving signals of the first group of clock driving signals are interleaved by 180°, and the duty cycles are both less than 50%; the two driving signals of the second group of clock driving signals are interleaved by 180°, and the duty cycles are both greater than 50%.

[0009] According to the present invention of the above solution, it further includes a clock oscillation circuit, and the clock oscillation circuit is used to output the basic clock signal to the clock signal modulation circuit.

[0010] According to the present invention of the above solution, the clock oscillation circuit includes an operational amplifier U101, the positive input end of the operational amplifier U101 is connected to a voltage dividing branch, the negative input end of the operational amplifier U101 is connected to a charge and discharge branch, the output end of the operational amplifier U101 outputs the basic clock signal, and the output end is connected to the positive input end through a feedback branch; when the basic clock signal is at a high level, the charge and discharge branch charges to raise the voltage of the negative input end until it reaches the first voltage value of the positive input end, and the basic clock signal turns to a low level; when the basic clock signal is at a low level, the charge and discharge branch discharges to lower the voltage of the negative input end until it reaches the second voltage value of the positive input end, and the basic clock signal turns to a high level.

[0011] Further, the voltage dividing branch includes a second resistor R102 and a fourth resistor R104, the charge and discharge branch includes a first resistor R101, a charging capacitor C101 and a fifth resistor R105, and the feedback branch includes a third resistor R103;

[0012] The positive input terminal is connected to the second resistor R102, the third resistor R103, and the fourth resistor R104, and the negative input terminal is connected to the charging capacitor C101, the first resistor R101, and the fifth resistor R105; the other ends of the first resistor R101 and the second resistor R102 are both connected to the reference voltage terminal; the other ends of the third resistor R103 and the fifth resistor R105 are both connected to the output terminal.

[0013] Further, the other ends of the charging capacitor C101 and the fourth resistor R104 are both grounded; a first diode D101 is provided between the fifth resistor R105 and the output terminal; the driving terminal of the operational amplifier is connected to the reference voltage terminal.

[0014] Furthermore, when the basic clock signal is at a high level, the first voltage value at the positive input terminal is:

[0015]

[0016] When the basic clock signal is at a low level, the second voltage value at the positive input terminal is:

[0017]

[0018] According to the present invention of the above solution, the charging duration of the charge and discharge branch is equal to the high-level time of the basic clock signal; the discharging duration of the charge and discharge branch is equal to the low-level time of the basic clock signal;

[0019] So as to adjust the high-level time and the low-level time of the basic clock signal by adjusting the parameters of the first resistor R101, the charging capacitor C101, and the fifth resistor R105 of the charge and discharge branch.

[0020] The present invention also provides a power topology circuit with dual-channel PWM control, including two-channel PMW control circuits and an output circuit. The two-channel PWM control circuits input the first set of clock driving signals or the second set of clock driving signals of the circuit that outputs two sets of interleaved clock signals in the above solution, and output two interleaved drive control signals to two switching tubes on the output circuit, so that the output circuit outputs different powers.

[0021] According to the present invention of the above solution, the output circuit is a dual-channel BOOST parallel power circuit, and two input terminals of the two-channel PMW control circuits connected thereto respectively input two drive signals that are interleaved by 180° and have a duty cycle greater than 50%.

[0022] Further, the output circuit is a push-pull power circuit, and two input terminals of the two connected PMW control circuits respectively input two driving signals that are staggered by 180° from each other and have a duty cycle of less than 50%.

[0023] For the present invention according to the above solution, its beneficial effects are as follows:

[0024] The clock driving output circuit of the present invention has a simple structure and can output two groups of clock driving signals that are staggered by 180 degrees at the same time. One group outputs clock driving signals that are staggered by 180 degrees and have a duty cycle of less than 50%; the other group outputs clock signals that are staggered by 180 degrees and have a duty cycle of greater than 50%.

[0025] Therefore, the clock driving output circuit of the present invention can provide different driving signals and can meet the requirements of PWM control circuits with different duty cycles at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is the circuit structure diagram of Embodiment 1 of the present invention;

[0027] Figure 2 is Figure 1 the enlarged circuit diagram of the clock oscillator in

[0028] Figure 3 is Figure 1 the enlarged circuit diagram of the clock signal modulator in

[0029] Figure 4 is the waveform diagram of the basic clock signal output by the clock oscillator;

[0030] Figure 5 is the waveform diagram of the relevant signals of the clock signal modulator;

[0031] Figure 6 is the circuit structure diagram of Embodiment 2;

[0032] Figure 7 is Figure 6 the enlarged diagram of Circuit 1 in

[0033] Figure 8 is Figure 6 the enlarged diagram of Circuit 2 in

[0034] Figure 9 is Figure 6 the enlarged diagram of Circuit 3 in

[0035] Figure 10 is the waveform diagram of the relevant signals of Circuit 1 and Circuit 2 in Embodiment 2;

[0036] Figure 11 is the circuit structure diagram of Embodiment 3;

[0037] Figure 12 is Figure 11 the enlarged view of Circuit 4 in

[0038] Figure 13 is Figure 11 the enlarged view of Circuit 5 in

[0039] Figure 14 is Figure 11 the enlarged view of Circuit 6 in

[0040] Figure 15 is the waveform diagram of the relevant signals of Circuit 4 and Circuit 5 in Embodiment 3. Specific Embodiment

[0041] In order to better understand the purpose, technical solution and technical effect of the present invention, the present invention will be further explained below with reference to the drawings and embodiments. It should be noted that: similar reference numerals and letters denote similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, it is declared that the embodiments described below are only used to explain the present invention and are not used to limit the present invention.

[0042] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time.

[0043] The terms "first", "second", "third", "fourth" and "fifth" are only used for the purpose of convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of technical features.

[0044] Embodiment 1

[0045] As Figure 1 and Figure 3 shown, a circuit for outputting two groups of interleaved clock signals includes a clock signal modulation circuit, and the input end of the clock signal modulation circuit obtains a basic clock signal CLK; the basic clock signal CLK is as Figure 4 shown, its high-level time is t on_CLK , and its low-level time is t off_CLK ; therefore, the frequency f CLK of the basic clock signal CLK has:

[0046]

[0047] The duty cycle D CLK of the basic clock signal CLK has:

[0048]

[0049] The clock signal modulation circuit includes a single positive-edge flip-flop U201 and a first NOT gate U202. The single positive-edge flip-flop U201 is triggered only at the rising edge of the basic clock signal CLK. After the basic clock signal CLK is input into the single-edge flip-flop, a first signal A is output. After the first signal A is input into the first NOT gate U202, a second signal B that is staggered with the first signal A is output. It can be seen that the frequency of the first signal A is half of the frequency of the basic clock signal CLK, that is, f CLK / 2, and the duty cycle is 50%; the frequency and duty cycle of the second signal B are the same as those of the first signal A, but the high and low levels of the second signal B are opposite to those of the first signal A.

[0050] Specifically, the circuit connection is as follows: The basic clock signal CLK is input into the second pin of the single positive-edge flip-flop U201. The fourth pin of the single positive-edge flip-flop U201 outputs the first signal A, and this pin is connected to the third pin of the first NOT gate U202. The fourth pin of the first NOT gate U202 outputs the second signal B, and the second signal B is fed back to the first pin of the single positive-edge flip-flop U201.

[0051] In the present invention, the clock signal modulation circuit further includes two AND gate branches, and each AND gate branch is connected to a NOT gate branch. An AND gate is provided on the AND gate branch. A first AND gate U203 is provided on one AND gate branch and is connected to a second NOT gate U204; a second AND gate U205 is provided on the other gate branch and is connected to a third NOT gate U206.

[0052] After the first signal A and the second signal B are respectively input into the two AND gate branches together with the basic clock signal CLK, two mutually staggered drive signals are output, forming a first group of clock drive signals. That is, the first signal A and the basic clock signal CLK pass through the first AND gate U203 to output a first drive signal A_OUT1, and the second signal B and the basic clock signal CLK pass through the second NOT gate U204 to output a second drive signal B_OUT1. Under the output characteristics of the AND gate, the waveforms of the first drive signal A_OUT1 and the second drive signal B_OUT1 are shown in Figure 5 (the part of A_OUT1 and B_OUT1). It can be seen that both the first drive signal A_OUT1 and the second drive signal B_OUT1 have: a high-level time of t on_CLK , and a low-level time of t on_CLK +2t off_CLK , so there is: the duty cycle D of the first drive signal A_OUT1 and the second drive signal B_OUT1 OUT1 There is:

[0053]

[0054] And D CLK <1, so D OUT1 <0.5;

[0055] Therefore, the first set of clock drive signals output are completely staggered by 180 degrees, with a frequency of f CLK / 2, and the first drive signal A_OUT1 and the second drive signal B_OUT1 with a duty cycle less than 0.5. The high-level signals of the first drive signal A_OUT1 and the second drive signal B_OUT1 output are staggered in sequence. As the drive signals of the switch tubes, they can alternately turn on the two switch tubes. The clock drive signal with a duty cycle less than 50% is applicable to the push-pull power conversion topology application.

[0056] The first drive signal A_OUT1 outputs the third drive signal A_OUT2 through the second NOT gate U204. The third drive signal A_OUT2 has opposite high and low levels to the first drive signal A_OUT1. The duty cycle of the third drive signal A_OUT2 is greater than 50%, and the time points of the switching of their level signals are the same. The second drive signal B_OUT1 outputs the fourth drive signal B_OUT2 through the third NOT gate U206. The fourth drive signal B_OUT2 has opposite high and low levels to the second drive signal B_OUT1. The duty cycle of the fourth drive signal B_OUT2 is greater than 50%, and the time points of the switching of their level signals are the same.

[0057] That is, the waveforms of the third drive signal A_OUT2 and the fourth drive signal B_OUT2 are shown in Figure 5 (the part of A_OUT2 and B_OUT2), and there is: the high-level time is t on_CLK +2t off_CLK , the low-level time is t on_CLK , and the duty cycle D OUT2 There is:

[0058]

[0059] Since 0 < D CLK <1, so 0.5 < D OUT2 <1.

[0060] Therefore, the second set of clock drive signals output are completely staggered by 180 degrees, with a frequency of f CLK / 2, and the third drive signal A_OUT2 and the fourth drive signal B_OUT2 with a duty cycle greater than 0.5. Similarly, the third drive signal A_OUT2 and the fourth drive signal B_OUT2 can alternately turn on the two switch tubes; the clock drive signal with a duty cycle greater than 50% is applicable to the power topologies such as two-way BUCK or two-way BOOST in parallel.

[0061] Taking the AND gate and NOT gate of one path as an example to illustrate the circuit connection relationship: The first signal A is input to the first pin of the first AND gate U203, the basic clock signal CLK is input to the second pin of the first AND gate U203, the fourth pin of the first AND gate U203 outputs the first driving signal A_OUT1, and is connected to the third pin of the second NOT gate U204, and the third driving signal A_OUT2 is output from the fourth pin of the second NOT gate U204.

[0062] As Figure 1 and Figure 2 shown, in an alternative embodiment, a clock oscillation circuit is further included, and the clock oscillation circuit is configured to output the basic clock signal CLK to the clock signal modulation circuit. The clock oscillation circuit includes an operational amplifier U101, the positive input terminal of the operational amplifier U101 is connected to a voltage dividing branch, the negative input terminal U101-4 of the operational amplifier U101 is connected to a charge and discharge branch, the output terminal of the operational amplifier U101 outputs the basic clock signal CLK, and the output terminal is connected to the positive input terminal U101-3 through a feedback branch.

[0063] When the basic clock signal CLK is at a high level, the charge and discharge branch charges to boost the negative input terminal U101-4 until it reaches the first voltage value of the positive input terminal U101-3, and the basic clock signal CLK turns to a low level;

[0064] When the basic clock signal CLK is at a low level, the charge and discharge branch discharges to lower the negative input terminal until it reaches the second voltage value of the positive input terminal U101-3, and the basic clock signal CLK turns to a high level.

[0065] Among them, the voltage dividing branch includes a second resistor R102 and a fourth resistor R104, the charge and discharge branch includes a first resistor R101, a charging capacitor C101, and a fifth resistor R105, and the feedback branch includes a third resistor R103; the positive input terminal is connected to the second resistor R102, the third resistor R103, and the fourth resistor R104, and the negative input terminal is connected to the charging capacitor C101, the first resistor R101, and the fifth resistor R105; the other ends of the first resistor R101 and the second resistor R102 are both connected to the reference voltage terminal; the other ends of the third resistor R103 and the fifth resistor R105 are both connected to the output terminal.

[0066] The other end of the charging capacitor C101 and the other end of the fourth resistor R104 are both grounded; a first diode D101 is provided between the fifth resistor R105 and the output terminal; the driving terminal of the operational amplifier is connected to the reference voltage terminal.

[0067] In the above clock oscillation circuit, when the basic clock signal CLK is at a high level, the first voltage value of the positive input terminal is:

[0068]

[0069] When the basic clock signal CLK is at a low level, the second voltage value at the positive input terminal is as follows:

[0070]

[0071] When the basic clock signal CLK is at a high level, the reference voltage charges the charging capacitor C101 through the first resistor R101, causing the voltage at the negative input terminal U101-4 to rise. When it rises to voltage, the basic clock signal CLK flips to a low level. Then, the charging capacitor C101 starts to discharge through the fifth resistor R105, causing the voltage at the negative input terminal U101-4 to drop. When it drops to voltage, the basic clock signal CLK flips to a high level. This process repeats to generate a basic clock signal CLK. For the waveform diagram, please refer to Figure 4 . The upper curve in the figure represents the voltage at the negative input terminal U101-4.

[0072] Therefore, in this embodiment, the charging duration of the charge and discharge branch is equal to the high-level time of the basic clock signal CLK; the discharging duration of the charge and discharge branch is equal to the low-level time of the basic clock signal CLK; by adjusting the parameters of the first resistor R101, the charging capacitor C101, and the fifth resistor R105 in the charge and discharge branch, the high-level time and the low-level time of the basic clock signal CLK can be adjusted. Specifically, adjusting the parameters of the charging capacitor C101 and the first resistor R101 can adjust the high-level time t on_CLK ; adjusting the parameters of the charging capacitor C101 and the fifth resistor R105 can adjust the low-level time t off_CLK .

[0073] Embodiment 2

[0074] As Figures 6 to 9 shown, an application embodiment of a circuit for outputting two sets of interleaved clock signals in a BOOST parallel power topology PWM control circuit. Specifically, a power topology circuit with dual-channel PWM control includes two channels of PMW control circuits and an output circuit, and the output circuit is a dual-channel BOOST parallel power circuit. This circuit is applicable to drive signals with interleaved 180° and a duty cycle greater than 50%.

[0075] The two PWM control circuits are Circuit 1 and Circuit 2 respectively, both of which are current-mode PWM control circuits. The third drive signal A_OUT2 and the fourth drive signal B_OUT2 of the second group of clock drive signals are respectively input to the input terminals of Circuit 1 and Circuit 2. Circuit 1 and Circuit 2 output two interleaved drive control signals to two switching transistors (Q401, Q402) on the dual BOOST parallel power circuit, so that the dual BOOST parallel power circuit outputs different powers.

[0076] In this embodiment, in Figure 6 where R is a resistor, C is a capacitor, D is a diode, and L is an inductor; U303 and U306 are NOT gates, Q301 and Q302 are switches (which can be MOS transistors, bipolar transistors, etc.), U301 and U304 are integrated operational amplifiers, U302 and U305 are NAND gates, U307 and U308 are drive amplifiers, TR401 and TR402 are current samplers (which can be current transformers, Hall sensors, etc.), and Q401 and Q402 are switching transistors.

[0077] Circuit 3 is a dual BOOST parallel power circuit. The switching transistors Q401 and Q402 need to be turned on and off alternately by 180 degrees and can apply the third drive signal A_OUT2 and the fourth drive signal B_OUT2 of the second group of clock drive signals output in Embodiment 1.

[0078] In the dual BOOST parallel power circuit, a current sampler TR401 is connected in series on the branch of the switching transistor Q401, and a current sampler TR402 is connected in series on the branch of the switching transistor Q402. The current sampler TR401 outputs a voltage signal ISA that can reflect the current waveform of the switching transistor Q401, and the current sampler TR402 outputs a voltage signal ISB that can reflect the current waveform of the switching transistor Q402. The COMP signal is the output signal of the output voltage error comparator (the circuit of this device is omitted). When the actual output voltage is greater than the designed voltage, the COMP voltage becomes smaller; when the actual output voltage is less than the designed voltage, the COMP voltage becomes larger.

[0079] The principle of generating the drive for the switching transistor Q401 by the third drive signal A_OUT2 and the current sampling signal ISA through Circuit 1 is as follows:

[0080] 1. The third drive signal A_OUT2, the current sampling signal ISA of the switching transistor Q401, and the voltage error signal COMP generate the drive signal DRVA of the switching transistor Q401 through Circuit 1; the fourth drive signal B_OUT2, the current sampling signal ISB of the switching transistor Q402, and the voltage error signal COMP generate the drive signal DRVB of Q402 through Circuit 2; since the third drive signal A_OUT2 and the fourth drive signal B_OUT2 are signals staggered by 180 degrees from each other, the generated drive signals DRVA and DRVB are also staggered signals from each other.

[0081] 2. As Figure 10 shown, the third drive signal A_OUT2 and the fourth drive signal B_OUT2 of the circuit that outputs two groups of staggered clock signals pass through the NOT gates U303 and U306 to output the signals -A_OUT2 and -B_OUT2 (see the waveform part of "-A_OUT2, -B_OUT2" in Figure 10 .

[0082] 3. At the moment t0, when the signal -A_OUT2 is at a high level, the U301-3 terminal is pulled low through the switch Q301, so the U301-3 terminal outputs a low level, and after passing through the integrated operational amplifier U301, the U301-1 terminal outputs a low level. After the signal -A_OUT2 and the U301-1 terminal enter the NAND gate U302, the U302-4 terminal outputs a low level, and the switching transistor Q401 is turned off. At the moment t1, when the signal -A_OUT2 is at a low level and the U301-1 terminal is also at a low level, at this time, the signal -A_OUT2 and the U301-1 terminal pass through the NAND gate U302, and the U302-4 terminal outputs a high level, and the switching transistor Q401 is turned on.

[0083] 4. Since the switching transistor is turned on, the voltage of the current sampling signal ISA starts to climb. Then the voltage of the U301-3 terminal starts to climb, and before rising to the COMP voltage (at the moment t2), the U301-1 terminal of the comparator still outputs a low level. During this period, the signal -A_OUT2 and the U301-1 terminal always output a low level, so the U302-4 terminal always outputs a high level, and the switching transistor is in the on state. When the voltage of the U301-3 terminal exceeds the COMP voltage, the voltage of the comparator U301-1 flips to a high level, then the U302-4 terminal outputs a low level to turn off the drive of the switching transistor. Therefore, the time from when the signal -A_OUT2 starts to output a low level (at the moment t1) to when the voltage of the U301-3 terminal rises to COMP (at the moment t2) is the on time of the switching transistor.

[0084] 5. When the U301-1 terminal outputs a high level at time t2, due to the positive feedback effect of resistor R302 and diode D301, the U301-3 terminal and the U301-1 terminal will be locked at the high level until the next cycle - when -A_OUT2 changes from low level to high level at t6, the voltage of the U301-3 terminal is pulled down by switch Q301, and the U301-1 terminal will be reset and unlocked to the low level. A working cycle is completed from t0 to t6. After t6, the next cycle begins.

[0085] 6. As can be seen from the above, the switching frequency of switch Q401 is the frequency of the third driving signal A_OUT2, and the turn - on time is equal to the time when the current signal rises to the voltage error signal COMP, thus realizing current - type PWM control. The rise time of the U301-3 terminal will not exceed the turn - on time of the third driving signal A_OUT2 at most. Therefore, the duty cycle of the third driving signal A_OUT2 is the open - loop duty cycle of switch Q401.

[0086] The driving principle of switch Q402 generated by the fourth driving signal B_OUT2 and the current sampling signal ISB through circuit 2 is the same as above, and will not be elaborated here.

[0087] In this embodiment, when the actual output voltage is lower than the designed voltage, the voltage error signal COMP becomes larger. The slope of the ISA current sampling signal is fixed. Therefore, the time required for the voltage of the U301-3 terminal to rise to COMP becomes larger, and the turn - on time of switch Q401 becomes larger, that is, the driving duty cycle becomes larger; then the output voltage will increase until it reaches the designed value. Similarly, when the actual voltage is higher than the designed voltage, the COMP voltage becomes smaller, the time for the voltage of the U301-3 terminal to rise to COMP becomes shorter, the driving time of switch Q401 becomes shorter, the duty cycle becomes smaller, and the output voltage will decrease until it reaches the designed value.

[0088] Embodiment Three

[0089] As Figures 11 to 14 shown, an application embodiment of the circuit for outputting two groups of interleaved clock signals on the push - pull topology PWM control circuit. Specifically, a power topology circuit with dual - channel PWM control includes two - channel PMW control circuits and an output circuit, and the output circuit is a push - pull power circuit. This circuit is applicable to driving signals with an interleaved 180° and a duty cycle less than 50%.

[0090] The two - channel PWM control circuits are circuit 4 and circuit 5 respectively, both of which are current - type PWM control circuits. The first driving signal A_OUT1 and the second driving signal B_OUT1 of the first group of clock driving signals are respectively input to the input terminals of circuit 4 and circuit 5. Circuit 4 and circuit 5 respectively control two switches (Q601, Q602) on the push - pull power circuit so that the output circuit outputs different powers.

[0091] The frequencies of the first drive signal A_OUT1 and the second drive signal B_OUT1 are the switching frequencies of the power switching transistors in the push-pull topology, and the duty cycles of the first drive signal A_OUT1 and the second drive signal B_OUT1 are the open-loop duty cycles of the power switching transistors in the push-pull topology. For the circuit diagram, please refer to Figure 11 , where R is a resistor, C is a capacitor, D is a diode, and L is an inductor in the figure; U503 and U506 are NOT gates, Q501 and Q502 are switches (which can be MOS transistors, bipolar transistors, etc.), U501 and U504 are integrated operational amplifiers, U502 and U505 are NAND gates, U507 and U508 are drive amplifiers, TR601 and TR602 are current samplers (which can be current transformers, Hall sensors, etc.), and Q601 and Q602 are switches.

[0092] Circuit 6 is the push-pull primary power circuit. The switches Q601 and Q602 need to be turned on and off alternately by 180 degrees. The duty cycles of the first drive signal A_OUT1 and the second drive signal B_OUT1 of the first set of clock drive signals output in the first embodiment are less than 50%, which are suitable as the drive signals for Circuit 6. Moreover, the duty cycles of the first drive signal A_OUT1 and the second drive signal B_OUT1 are the maximum drive duty cycles of the switches Q601 and Q602. Therefore, the drive duty cycles of the switches Q601 and Q602 will not exceed 50% at most, avoiding the common conduction of the switches Q601 and Q602.

[0093] In this embodiment, a current sampler TR601 is connected in series on the branch of the switch Q601, and a current sampler TR602 is connected in series on the branch of the switch Q602. The current sampler TR601 outputs a voltage signal ISA1 that can reflect the current waveform of the switch Q601, and the current sampler TR602 outputs a voltage signal ISB1 that can reflect the current waveform of the switch Q602.

[0094] As Figure 15 shown, the circuit principle and signal output process of this embodiment are the same as those of the second embodiment, and will not be elaborated here.

[0095] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0096] The above embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A circuit for outputting two groups of interleaved clock signals, characterized in that It includes a clock signal modulation circuit, and the input end of the clock signal modulation circuit obtains a basic clock signal; The clock signal modulation circuit includes a single positive-edge trigger and a first NOT gate. After the basic clock signal is input into the single-edge trigger, a first signal is output. After the first signal is input into the first NOT gate, a signal that is inverted from the second signal is output; The clock signal modulation circuit further includes two AND gate branches, and each AND gate branch is connected to a NOT gate branch; After the first signal and the second signal are respectively input into the two AND gate branches together with the basic clock signal, two interleaved drive signals are output, forming a first group of clock drive signals; After the two drive signals pass through their respective NOT gate branches, another two interleaved drive signals are output, forming a second group of clock drive signals.

2. The circuit for outputting two groups of interleaved clock signals according to claim 1, wherein The two drive signals of the first group of clock drive signals are interleaved by 180°, and their duty cycles are both less than 50%; the two drive signals of the second group of clock drive signals are interleaved by 180°, and their duty cycles are both greater than 50%.

3. The circuit for outputting two groups of interleaved clock signals according to claim 1, wherein It further includes a clock oscillation circuit, and the clock oscillation circuit is used to output the basic clock signal to the clock signal modulation circuit.

4. The circuit for outputting two groups of interleaved clock signals according to claim 1, wherein The clock oscillation circuit includes an operational amplifier. The positive input end of the operational amplifier is connected to a voltage dividing branch, the negative input end of the operational amplifier is connected to a charge-discharge branch, the output end of the operational amplifier outputs the basic clock signal, and the output end is connected to the positive input end through a feedback branch; When the basic clock signal is at a high level, the charge-discharge branch charges to raise the voltage of the negative input end until it reaches the first voltage value of the positive input end, and then the basic clock signal turns to a low level; When the basic clock signal is at a low level, the charge-discharge branch discharges to lower the voltage of the negative input end until it reaches the second voltage value of the positive input end, and then the basic clock signal turns to a high level.

5. The circuit for outputting two groups of interleaved clock signals according to claim 4, wherein The voltage dividing branch includes a second resistor and a fourth resistor, the charge-discharge branch includes a first resistor, a charging capacitor, and a fifth resistor, and the feedback branch includes a third resistor; The positive input end is connected to the second resistor, the third resistor, and the fourth resistor, and the negative input end is connected to the charging capacitor, the first resistor, and the fifth resistor; the other ends of the first resistor and the second resistor are both connected to a reference voltage terminal; the other ends of the third resistor and the fifth resistor are both connected to the output end.

6. The circuit for outputting two groups of interleaved clock signals according to claim 5, characterized in that, When the basic clock signal is at a high level, the first voltage value of the positive input end is: When the basic clock signal is at a low level, the second voltage value of the positive input end is: Wherein, VREF represents a voltage value, R102 represents the resistance value of the second resistor, R103 represents the resistance value of the third resistor, and R104 represents the resistance value of the fourth resistor.

7. The circuit for outputting two groups of interleaved clock signals according to claim 4 or 6, characterized in that, The charging duration of the charge-discharge branch is equal to the high-level time of the basic clock signal; the discharging duration of the charge-discharge branch is equal to the low-level time of the basic clock signal; So that by adjusting the parameters of the first resistor, the charging capacitor, and the fifth resistor of the charge-discharge branch, the high-level time and the low-level time of the basic clock signal can be adjusted.

8. A power topology circuit with dual - path PWM control, comprising two - path PMW control circuits and an output circuit, characterized in that, The two-way PWM control circuit inputs the first set of clock drive signals or the second set of clock drive signals of the circuit that outputs two sets of interleaved clock signals as described in any one of claims 1 to 7, and outputs two interleaved drive control signals to two switching transistors on the output circuit, so that the output circuit outputs different powers.

9. The power topology circuit with dual-channel PWM control according to claim 8, wherein The output circuit is a two-way BOOST parallel power circuit, and two drive signals that are 180° interleaved with each other and have a duty cycle greater than 50% are respectively input to two input terminals of the two-way PMW control circuit connected thereto.

10. The power topology circuit with dual-channel PWM control according to claim 8, characterized in that, The output circuit is a push-pull power circuit, and two drive signals that are 180° interleaved with each other and have a duty cycle less than 50% are respectively input to two input terminals of the two-way PMW control circuit connected thereto.

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