A programmable communication device and a method for preparing a multi-chip microsystem including the same

Abstract

The present application relates to the technical field of integrated circuit packaging. The present application proposes a method for preparing a programmable communication device and a multi-chip microsystem including the same. The programmable communication device includes a control unit and a signal guiding array. The control unit is provided with input, output and path repair ports. The output port is used to output the communication path configuration signal. The path repair port receives an external input signal when a communication failure occurs, and drives the control unit to regenerate the communication path configuration signal to achieve path self-repair. The signal guiding array includes a plurality of guiding switches, and a plurality of chips are arranged on the periphery of the signal guiding array. The guiding switches are connected to the output ports, and a communication path is established between the chips according to the configuration signal. The preparation method can construct a multi-chip microsystem including a programmable communication device. The present application has the dynamic configuration and fault self-recovery capabilities of the communication path, can support the functional reconstruction and stable operation of the multi-chip microsystem, and is suitable for high reliability requirements in complex application scenarios.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit packaging, and in particular to a method for preparing a programmable communication device and a multi-chip microsystem including the same. Background Art

[0002] As the integration scale of microsystems in intelligent computing, signal processing, and edge applications continues to expand, the complexity of their system construction continues to increase. Integrating multiple chips on a silicon adapter board as needed and achieving high-speed interconnection between the chips through local communication structures has become an important way to build multi-chip microsystems. This type of multi-chip integration structure helps to improve the modularity and process compatibility of the system, and shows advantages in supporting partitioned deployment, functional separation, and scalable architecture.

[0003] However, in existing multi-chip microsystems, the communication paths between chiplets often rely on fixed interconnection methods determined before packaging. Once the communication path is configured, it is difficult to modify it during system operation, which makes the communication topology tend to be solidified and lacks flexible path reconstruction capabilities. This static interconnection method limits the system's adaptability in multi-task switching and multi-scenario configuration, makes it difficult to meet the flexible requirements of loading different functional combinations on demand, and reduces the scalability and reusability of the microsystem. In addition, most current designs do not have an abnormality detection and response mechanism for the communication path. During the system operation cycle, once the communication path is broken or the connection is unstable due to factors such as stress mismatch, electromigration, and material fatigue, it will usually cause the corresponding functional unit to fail, and may also affect the interruption of the entire system task chain, resulting in insufficient reliability of the microsystem under long-term operation or extreme working conditions, and it is difficult to meet the application scenarios with strict requirements for high stability, high maintainability, and high adaptability.

[0004] Therefore, there is an urgent need to propose a communication device with the ability to dynamically configure communication paths and self-recovery of connection status, as a key module for chip-to-chip interconnection in microsystems, to support the functional reconstruction and operational stability of multi-chip microsystems and meet the long-term usage requirements in complex application environments. Summary of the Invention

[0005] The purpose of the present invention is to address the deficiencies in the above-mentioned prior art and provide a programmable communication device and a method for preparing a multi-chip microsystem including the same, so as to solve the problems in the prior art of low functional flexibility of the communication structure and inability to respond to path failures.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] The present application provides a programmable communication device, including a control unit and a signal steering array. The control unit includes an input port and multiple output ports, the output port is used to output a communication path configuration signal; the control unit also includes a path repair port, the path repair port is used to receive an external input signal when a communication path fails, and the control unit regenerates the communication path configuration signal based on the input signal to achieve self-repair of the communication path. The signal steering array includes multiple steering switches, which are connected to the output ports. Multiple chips are arranged at the outer edge of the signal steering array, and the steering switches establish programmable selective communication paths between the chips based on the communication path configuration signal.

[0008] This application achieves on-demand establishment and dynamic reconstruction of inter-chiplet communication paths by establishing a configurable connection mechanism between the control unit and the signal steering array, solving the problem of fixed communication devices and unresponsiveness to path anomalies in the prior art. The control unit generates a communication path configuration signal based on the input signal and distributes it to the steering switch to achieve precise control of the signal path. The steering switch is distributed within the signal steering array as a switching node. The combination of its switch states determines the formation of the communication path. Instead of relying on preset wiring, the path is constructed through dynamic configuration, enhancing the functional adaptability and flexibility of the communication device. When a path fails during system operation, the control unit receives an external input signal through the path repair port, updates the communication path configuration signal, drives the steering switch to reestablish the connection relationship, quickly completes the restoration of the communication path, and ensures that the system task chain is not interrupted. This mechanism supports the dynamic configuration of communication relationships based on system functions and adaptively reconstructs connections when failures occur. It breaks the static limitations of traditional interconnect structures, builds a reconfigurable and recoverable communication system, and improves the robustness and scalability of multi-chiplet microsystems.

[0009] Furthermore, the control unit can output different combinations of communication path configuration signals to establish communication paths between corelets corresponding to different system functions. By adjusting the connection state of the guidance switch, this mechanism can establish targeted communication paths between corelets based on task requirements, enabling flexible organization and rapid reconfiguration of functional modules, and improving the system's adaptability to multiple application scenarios.

[0010] Furthermore, the steering switch is composed of at least two NMOS transistors and an inverter. This structure has the characteristics of fast response speed and simple control logic, which facilitates stable conduction and reliable disconnection of the communication path and is suitable for large-scale communication connection control between chiplets.

[0011] Furthermore, the types of pilot switches include single-pole single-throw switches and single-pole double-throw switches.

[0012] Furthermore, the control signal lines in the signal steering array are arranged in a layered manner and are provided with decoupling capacitors and pull-up resistors or pull-down resistors to achieve fast switching of the steering switches.

[0013] Furthermore, a metal layer is provided in the signal guiding array, and the metal layer is located in the angle area between the control signal line and the transmission signal line of the guiding switch, so as to reduce the crosstalk effect of the control signal jump on the data transmission path.

[0014] Furthermore, the signal guidance array supports expansion according to a 1×2 or 2×2 topology, enabling orderly extension of communication devices in both horizontal and vertical directions, meeting the flexible integration requirements of multi-chip systems at different scales.

[0015] The present application also provides a method for preparing a multi-chip microsystem including a programmable communication device. The multi-chip microsystem includes the above-mentioned programmable communication device, and the preparation method includes the following steps:

[0016] S1. preparing a bare chip of a programmable communication device;

[0017] S2, preparing through silicon vias on a first silicon wafer;

[0018] S3, preparing a rewiring layer on the surfaces of the first silicon wafer and the second silicon wafer;

[0019] S4, placing multiple chips and programmable communication device bare chips on the upper surfaces of the first silicon wafer and the second silicon wafer respectively and bonding them together;

[0020] S5, preparing micro bumps on the lower surface of the first silicon wafer and the upper surface of the second silicon wafer, and then bonding the first silicon wafer and the second silicon wafer together;

[0021] S6. Slicing the bonded wafers and packaging them to obtain a microsystem with a programmable communication device.

[0022] Furthermore, in S1 , laser heat treatment is performed on the signal guide array region to enhance the thermal stability and connection reliability of the metal wiring structure in the guide switch region.

[0023] Furthermore, the laser heat treatment uses a laser beam with a wavelength of 532 nm, a pulse width of 60 ns, a pulse energy of 100 μJ, and a spot diameter of 15 μm.

[0024] Furthermore, in S4, cross-shaped alignment marks are set on the upper surfaces of the first silicon wafer and the second silicon wafer to assist in the precise positioning and bonding alignment of the core particle and the programmable communication device bare chip, thereby improving assembly accuracy and interconnection consistency.

[0025] Furthermore, in S4, before the core particle and the programmable communication device bare chip are bonded, a filling material is provided between the core particle and the first silicon wafer or the second silicon wafer to enhance the heat conduction performance after bonding and improve the heat dissipation efficiency of the microsystem packaging structure.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] (1) This application constructs a communication path configuration mechanism in which a control unit outputs a configuration signal and drives a guide switch to dynamically conduct. This mechanism breaks the limitation of traditional microsystems that rely on pre-package wiring for communication connections, making the communication structure still variable after packaging. Compared with existing fixed interconnect structures, this solution supports flexible switching of inter-chip communication relationships during operation based on task changes or functional reconstruction requirements, significantly improving the system's configuration freedom and scenario adaptability.

[0028] (2) This application introduces a path repair port as an external response interface for abnormal communication status. After receiving the fault input signal, the control unit can regenerate the path configuration signal, thereby controlling the guide switch to adjust the connection status and achieve structural recovery of the communication path. This method effectively replaces the existing system's processing method that requires external bypass or manual intervention to restore communication, and improves the system's adaptability and long-term operational stability in channel failure scenarios.

[0029] (3) This application arranges the core particles around the edge of the guide switch array and enables the guide structure to expand at the topological level, forming a communication device skeleton that can grow horizontally or vertically. This design enables the communication device to have good modular scalability while maintaining overall controllability, and can adapt to the packaging requirements of multi-type and multi-scale core particle systems. It is significantly superior to existing point-to-point fixed connection solutions that cannot adapt to structural expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the basic unit structure of a programmable communication device provided by the present invention;

[0031] Figure 2 for Figure 1 Schematic diagram of the structure of a single-pole single-throw switch in a programmable communication device;

[0032] Figure 3 for Figure 1 Schematic diagram of the single-pole double-throw switch structure in a programmable communication device;

[0033] Figure 4 For the present invention Figure 1 Schematic diagram of the structure of the expanded 1×2 programmable communication device;

[0034] Figure 5 For the present invention Figure 1 Schematic diagram of the structure of the expanded 2×2 programmable communication device;

[0035] Figure 6 A schematic diagram of a three-dimensional partial structure of a multi-chip microsystem including a programmable communication device provided by the present invention;

[0036] Figure 7 for Figure 6 Schematic diagram of the three-dimensional structure of the multi-core microsystem after encapsulation;

[0037] Figure 8 for Figure 7 Flowchart of the preparation method of multi-core particle microsystem.

[0038] Icons: 1-control unit; 2-signal steering array; 3-steering switch; 4-chip; 5-programmable communication device bare chip; 6-first silicon wafer; 7-second silicon wafer; 8-through silicon via; 9-rewiring layer; 10-FR-4 packaging substrate. DETAILED DESCRIPTION

[0039] In order to make the implementation process of the present invention clearer, it will be described in detail below with reference to the accompanying drawings.

[0040] Example 1:

[0041] The present invention provides a programmable communication device, such as Figure 1 As shown, the programmable communication device includes a control unit 1 and a signal steering array 2. The control unit 1 includes an input port and multiple output ports. The output port is used to output communication path configuration signals. The control unit 1 also includes a path repair port. The path repair port is used to receive external input signals when a communication path failure occurs. The control unit 1 regenerates the communication path configuration signals based on the input signals to achieve self-repair of the communication path. The signal steering array 2 includes multiple steering switches 3, which are connected to the output ports. Multiple chiplets 4 are arranged at the outer edge of the signal steering array 2. The steering switches 3 establish programmable selective communication paths between the chiplets 4 based on the communication path configuration signals.

[0042] In this embodiment, the programmable communication device control unit 1 is equipped with a total of 20 ports. Port Ix represents the signal input port of the programmable communication device control unit 1, which is used to receive function setting signals from the system host computer or external controller. Ports O1-O10 and C11-C42 represent the output ports of the programmable communication device control unit 1, which are used to output the communication path configuration signal generated after the control unit 1 encodes and decodes the input signal Ix. The control unit 1 also includes a path repair port Ixx, which receives an external input signal to trigger repair when a communication path between chiplets 4 fails. After encoding and decoding the input signal, the control unit 1 outputs a new communication path configuration signal to the corresponding output port, controlling the conduction state of the guide switch 3, thereby establishing or switching the communication path between the chiplets 4.

[0043] The signal steering array 2 of the programmable communication device is provided with 20 steering switches 3, and the steering switches 3 are represented as S1-S 10 、C 11 -C 42 , respectively connected one-to-one with the output ports of the control unit 1, establishing a matching relationship. The guidance switch 3 is used to establish communication paths or switch paths between cores 4, supporting configurations for various structural scenarios such as point-to-point communication, multi-input selection, and cross-link switching. To support system expansion and path redundancy, the signal guidance array 2 in this embodiment can also reserve several unconnected channels and vacant interfaces for future expansion of core 4 nodes, addition of redundant conduction paths, or integration of relay modules, providing excellent structural scalability and path fault tolerance.

[0044] The guide switch 3 includes two types: single-pole single-throw switch and single-pole double-throw switch, which are respectively suitable for on-off control of the communication path and multi-channel path switching. Figure 2 and Figure 3 As shown, the low-power control circuit uses NMOSFET transistors and inverters, offering advantages such as fast response, low power consumption, and excellent signal integrity. Control unit 1 can output signals using either 1.8V or 3.3V standard IO levels. To improve system wiring compatibility, all control lines are layered and equipped with decoupling capacitors and pull-up or pull-down resistors to achieve fast, stable switching and state retention. Steering switch 3 turns on when the NMOSFET gate voltage is high and turns off when the NMOSFET gate voltage is low.

[0045] like Figure 2 As shown in the figure, the structure of the SPST switch consists of two NMOSFET transistors (Q1, Q2) and an inverter. Figure 2 (a) is the ON state of the SPST switch, Figure 2(b) is the off state of the SPST switch. The SPST switch sets the signal input port P in and signal output port P out , O x It is the control signal output by the programmable communication device control unit 1. x When it is high, the inverter outputs a low level, turning Q1 on and Q2 off, and the signal from P in Port input and through P out Port output, forming a communication path; when O x When it is low, the inverter outputs a high level, at which time Q1 is turned off and Q2 is turned on, and P in The port is connected to ground, disconnecting the communication path and creating a high-isolation state. This switch structure, through the combined control of Q1 and Q2, provides a low-resistance path in the on state and bypasses the signal to suppress interference in the off state, thereby improving the stability and anti-interference capability of the communication path.

[0046] like Figure 3 As shown in Figure 1, the SPDT switch structure is composed of two SPST switches, including four NMOSFET transistors (Q1, Q2, Q3, Q4) and an inverter. It has two input ports P in1 、P in2 and an output port P out , O x is the control signal. x When it is high, Q1 and Q4 are turned on, and Q2 and Q3 are turned off. Figure 3 As shown in (a), the signal from P in1 The port is output to P through the steering switch 3 out port; when O x When it is low, Q2 and Q3 are turned on, and Q1 and Q4 are turned off. Figure 3 As shown in (b), the signal from P in2 Port transfer to P out This structure is suitable for the selective control of the situation where there are multiple input channels in the communication path of the core particle 4. It can flexibly switch the communication direction according to the control signal to ensure the selectivity and mutual exclusion of the path.

[0047] To reduce the interference of control signals on data signal lines during the switching process of the steering switch 3, a metal layer design is introduced into the wiring structure of the signal steering array 2. This metal layer is located in the angle region between the control signal line and the transmission signal line, shielding the electromagnetic radiation of the control signal. It can effectively isolate the electromagnetic coupling path and suppress the crosstalk effect caused by high-frequency jumps, thereby improving the anti-interference capability and signal integrity of the communication link between the core particles 4. The metal layer can be made of aluminum, copper, or a metalized composite material, with excellent conductivity and electromagnetic shielding properties. It can be integrated into the signal steering array 2 structure using standard CMOS-compatible processes or multi-layer wiring processes. Furthermore, this metal layer also has a distributed capacitance adjustment function. In a structure with multiple interwoven signal lines, asymmetric distributed capacitance often exists between the control signal and data paths, which can easily lead to signal rising edge distortion and jitter. By introducing a metal layer in the middle and grounding it or maintaining it at a constant potential, the mutual capacitance between the control signal line and the transmission signal line can be balanced, thereby improving signal edge integrity and suppressing high-frequency reflections. In addition, the metal layer can also form a charge release channel during high-speed steering switch switching, reduce ground bounce noise caused by voltage mutations, and enhance the overall electromagnetic compatibility performance of the system.

[0048] The control unit 1 generates different control commands and outputs different combinations of communication path configuration signals to establish communication paths between the chiplets 4 corresponding to different system functions. In this embodiment, four chiplets 4 are provided, represented by C1, C2, C3, and C4 respectively. The following lists four task configurations for functions A, B, C, and D to illustrate the communication path configuration logic and self-repair process:

[0049] Under function A configuration, the control unit 1 receives the signal I1, completes the signal encoding and decoding internally, and outputs high level to the output ports O1, C11, C41, O4, C21, C31, and the other ports output low level. 11 、C 41 With S4, C 21 、C 31 The guiding switch 3 is turned on and the other guiding switches 3 are turned off, thus constructing two independent communication paths C1-C4 and C2-C3, and realizing parallel task distribution under system function A. When the communication path is broken due to environmental stress such as high temperature and high impact, the control unit 1 can receive the path repair signal I through the path repair port. 11 After completing the signal encoding and decoding in the control unit 1, a control signal is generated, which outputs a high level to O7, C12, C42 and O9, C22, C32, and the other ports output a low level to drive S7, C 12 、C 42 With S9, C 22 、C 32The guiding switch 3 of the signal path is turned on, and the other guiding switches 3 are turned off, replacing the original path, completing the path reconstruction and signal path self-repair, and realizing the stable operation of function A.

[0050] Under function B configuration, control unit 1 receives signal I2 and controls output ports O3, C11, C21, O5, C31, C41 to be high level, and the remaining ports output low level, driving S3, C 11 、C 21 With S5, C 31 、C 41 The other pilot switches 3 are turned on, and the communication paths C1-C2 and C3-C4 are formed to realize the communication structure required by the system function B. If the path fails, the control unit 1 receives the path repair signal I 22 , thus outputting high level to O8, C12, C22 and O10, C32, C42, and the rest of the ports output low level, turning on S8, C 12 、C 22 With S 10 、C 32 、C 42 , the remaining guide switches 3 are turned off, a backup path is constructed, and stable operation of function B is achieved.

[0051] Under the function C configuration, the control unit 1 receives the signal I3 and controls the output ports O2, C11, C31 and O6, C41, C21 to be high level, and the other ports output low level, driving S2, C 11 、C 31 With S6, C 41 、C 21 The other guide switches 3 are turned on, and the communication paths of C1-C3 and C2-C4 are built, which is suitable for asymmetric functional communication structure. When a circuit breaker occurs in the communication path C1-C3, the control unit 1 receives the path repair signal I 33 , thus outputting high level to O6, C41, C21 and O8, O9, C12, C32, and the other ports output low level, turning on S6, C 41 、C 21 Compared with S8, S9, C 12 、C 32 , the remaining guiding switches 3 are turned off, and the C1-C3 path is re-established to achieve path recovery of function C.

[0052] In the function D configuration, the control unit 1 receives the signal I4 and controls the output ports O1, O3, C41, C11 and O4, O5, C21, C31 to be high level, and the other ports output low level to drive S1, S3, C 41 、C 11 With S4, S5, C 21 、C 31When a circuit breaker occurs in the communication path between C1-C3 or C3-C4, the control unit 1 receives the path repair signal I 44 , thus outputting high level to O7, O8, C42, C12 and O9, O10, C22, C32, and the rest of the ports output low level, turning on S7, S8, C 42 、C 12 Compared with S9, S 10 、C 22 、C 32 , the remaining steering switches 3 are turned off, and the signal routing path between C1, C2, C3 and C4 is rebuilt to complete the replacement construction of the complete path and realize the path recovery of function D.

[0053] Through the above-described functional configuration, the programmable communication device structure described in this embodiment can output different combinations of communication path configuration signals based on system functional requirements, establishing programmable communication connections between corelets 4, and is suitable for organizing and reconfiguring communication for a variety of functional tasks. In the event of a communication path failure, the control unit 1 can control the switching state of the backup pilot switch 3 based on external input signals to complete the configuration of an alternative communication path, thereby maintaining communication continuity between corelets 4. This structure provides flexible path configuration and self-recovery capabilities for communication paths, which helps improve the functional reconfigurability and operational stability of the microsystem.

[0054] Example 2:

[0055] This embodiment provides a programmable communication device with two-dimensional topology expansion capability, such as Figure 4 、 Figure 5 As shown, based on the basic communication unit described in Example 1, it expands horizontally and vertically through a modular array approach, forming a grid-like interconnect architecture covering more cores 4. This structure is suitable for microsystem integration applications with a large number of cores 4, clear task area divisions, or high communication density requirements. It can support flexible path configuration and cross-regional communication scheduling between multiple modules, improving the structural adaptability and functional reconfigurability of the microsystem under large-scale integration.

[0056] like Figure 4As shown, in a 1×2 topology, the programmable communication device includes two parallel signal guidance arrays 2, each used to connect to corelets 4 in different functional areas, with a total of six corelets 4. The left signal guidance array 2 connects C1, C5, and C6, and the right signal guidance array 2 connects C2, C3, and C4. The two signal guidance arrays 2 are interconnected via a central path, forming a connected path configuration network. The control unit 1 controls the guidance switches 3 in the signal guidance array 2 to turn on or off, and flexibly establishes communication paths between corelets 4 according to the working principle described in Example 1 based on system functional requirements. For example, when a communication path needs to be established between C1 and C3, C1-C2-C3 can be configured as the signal path; when communication is required between C2 and C6, the path C2-C1-C6 can be configured as the signal path. If a connection in one of these paths fails, the control unit 1 can reconfigure the guide switch 3 combination based on external input path anomaly signals, establishing alternate paths such as C1-C4-C3 or C2-C5-C6, thereby rapidly restoring the communication link. This structure supports both intra-regional and inter-regional communication configurations, offering high path flexibility and structural reuse, making it suitable for multi-tasking and regional collaboration applications.

[0057] like Figure 5 As shown, in a 2×2 topology, the programmable communication device structure consists of multiple signal guiding arrays 2 arranged in a horizontal and vertical array configuration, forming a two-dimensional grid-like path configuration. Eight cores 4 are distributed along the periphery of the signal guiding arrays 2, with cores 4 designated C1-C8. Each signal guiding array 2 connects to adjacent cores 4 and other signal guiding arrays 2 via multiple internal guiding switches 3, forming a programmable communication interconnection device structure. A control unit 1 uniformly outputs a set of communication path configuration signals, which act on the control nodes of each guiding switch 3 in the two-dimensional array to drive the combined conduction of row and column guiding paths. By configuring the combined configuration of guiding switches 3, the desired communication paths can be established between multiple cores 4, enabling signal forwarding and task chain reconfiguration within or across regions. For example, a communication path between C1 and C6 can be constructed through control path configuration. When a communication path fails, the control unit 1 receives an external fault identification signal through the path repair port and generates a new communication path configuration signal, enabling other guide switch 3 combinations, such as C1-C8-C7-C6, to complete the connection switching and achieve dynamic self-repair of the path. This structure is suitable for multi-module integrated systems requiring high communication density and regional coordination, and can support the parallel processing and dynamic scheduling of complex tasks in microsystems.

[0058] This topology expansion scheme, while continuing the basic communication logic and control mechanisms of Example 1, achieves scalability and layout flexibility for the communication device through structural replication of the signal steering array 2 and unified configuration of control paths. This structure improves the organizational density and functional mapping capabilities between chiplets 4 within the microsystem, while also enhancing path-level redundancy and the ability to handle exceptions during communication. It is suitable for multi-chiplet microsystem integration scenarios that support regional deployment, dynamic task scheduling, and stable system operation.

[0059] Example 3:

[0060] This embodiment provides a multi-chip microsystem including a programmable communication device and a method for preparing the same, aiming to realize the application of the programmable communication device described in Example 1 or Example 2 in microsystem integration. Based on the 1×2 programmable communication device in Example 2, the structure of the multi-chip microsystem is as follows: Figure 6 and Figure 7 shown. Figure 6 The three-dimensional microsystem structure before dicing is shown. The system includes six cores 4 and one 1×2 programmable communication device bare chip 5, which are respectively arranged on the surfaces of a first silicon wafer 6 and a second silicon wafer 7, and a vertical communication path is formed with the help of silicon through vias 8 and a rewiring layer 9. Figure 7 This diagram shows the overall structure of the microsystem after dicing and packaging. The periphery forms a complete package structure, and the internal communication paths and functional chips are integrated into the microsystem packaging unit. This structure ensures programmable configuration of the communication paths while ensuring compact packaging integration and stable communication interconnection.

[0061] Based on the above structural layout, this embodiment further proposes a method for preparing a multi-chip microsystem including a programmable communication device, such as Figure 8 As shown, the specific steps include:

[0062] S1. Prepare a programmable communication device bare chip 5. This programmable communication device bare chip 5 is a communication device unit with a 1×2 structure. It is monolithically integrated on a single silicon wafer using a triple-well CMOS process. It integrates the signal steering array 2 and the control unit 1 to meet the performance requirements of low insertion loss and high isolation. The silicon wafer is then precisely cut using a 1.5kW laser. N uniformly sized and structurally complete 1×2 programmable communication device bare chips 5 are obtained for subsequent microsystem integration and packaging.

[0063] S2. Prepare a through silicon via 8 on the first silicon wafer 6; on the surface of the first silicon wafer 6 with a thickness of 155 μm, use a laser device with a frequency of 50 kHz, a wavelength of 400 nm, a pulse width of 60 ns, a pulse energy of 400 μJ, and a spot diameter of 10 μm to etch a conical through silicon via 8; then fill the through hole with polymer, and ablate the polymer with a laser with a power of 2 kW to obtain a through hole with an insulating inner wall structure; on the surface of the inner wall of the through hole, adopt a physical vapor deposition process, in an argon protection environment, use TiN as a sputtering target, and deposit a TiN barrier layer on the condition of a RF source frequency of 13.56 MHz, a pre-sputtering power of 50 W, a sputtering power of 25 W, and a sputtering time of 8 minutes; continue to use physical vapor deposition technology to prepare a metal seed layer on the barrier layer, and use CuSO4 with a concentration of 0.3 mol / L as the electroplating solution, at a current density of 50 A / cm 2 The metal filling is completed under the conditions of , and finally a conical silicon via 8 structure with metal conduction capability and insulation coating characteristics is formed.

[0064] S3. Prepare a rewiring layer 9 on the surface of the first silicon wafer 6 and the second silicon wafer 7; use the Damascene process to sequentially deposit the rewiring layer 9 on the upper and lower surfaces of the first silicon wafer 6 and the upper surface of the second silicon wafer 7. First, a silicon nitride diffusion barrier layer and a SiO2 dielectric layer are deposited on the upper and lower surfaces of the first silicon wafer 6 and the upper surface of the second silicon wafer 7, respectively. Then, a patterning process is performed on the SiO2 dielectric layer, and the excess dielectric layer outside the patterned area is etched to form a wiring channel. Then, a new diffusion barrier layer and a metal seed layer are deposited in the etched patterned area, and electroplating is performed using the electroplating conditions in step 2. Copper is selected as the material to complete the wiring metal filling. Finally, the surfaces of the first silicon wafer 6 and the second silicon wafer 7 are subjected to chemical mechanical polishing to remove excess material and obtain a rewiring layer 9 structure with a smooth surface.

[0065] S4, placing multiple chips 4 and programmable communication device bare chips 5 on the upper surfaces of the first silicon wafer 6 and the second silicon wafer 7 respectively and bonding them; before placement, using the negative marking process to prepare cross-shaped alignment markers on the passive areas of the upper surfaces of the first silicon wafer 6 and the second silicon wafer 7, respectively, with a line length of 140μm and a line width of 30μm, for accurately locating the layout positions of the chips 4 and the communication device chips; then, mounting the chips 4 according to the positions of the alignment markers, placing 6N chips 4 and N programmable communication device bare chips 5 on the first silicon wafer 6 and the second silicon wafer 7 respectively. In designated areas on the upper surfaces of a silicon wafer 6 and a second silicon wafer 7, C1, C2, C3, C4, and a programmable communication device bare chip 5 are placed on the upper surface of the first silicon wafer 6, wherein the programmable communication device bare chip 5 is placed in the center position, and C5 and C6 are placed on the upper surface of the second silicon wafer 7; after placement is completed, a hot pressing process is used to firmly bond all the core particles 4 and the programmable communication device bare chip 5 to the surfaces of the first silicon wafer 6 and the second silicon wafer 7, and epoxy resin is applied to the surrounding areas for reinforcement to prevent displacement or vibration during the subsequent packaging process.

[0066] S5. Prepare micro-bumps on the lower surface of the first silicon wafer 6 and the upper surface of the second silicon wafer 7, and then bond the first silicon wafer 6 and the second silicon wafer 7 together; adopt a ball planting process to electroplate copper micro-bumps on the lower surface of the first silicon wafer 6 and the upper surface of the second silicon wafer 7, respectively, and the electroplating rate is controlled to be 0.3μm / min. The obtained micro-bumps are cylindrical as a whole and are used to realize electrical connection between the first silicon wafer 6 and the second silicon wafer 7; after completing the preparation of the micro-bumps, use a hot pressing bonding process to align and firmly connect the first silicon wafer 6 and the second silicon wafer 7 under the conditions of a bonding pressure of 300kPa, a bonding temperature of 250℃, and a temperature rise rate of 5℃ / min to ensure stable and reliable interconnection of the microstructure.

[0067] S6. Slice the bonded wafers and package them to obtain a microsystem with a programmable communication device. A 2kW laser is used to precisely cut the bonded wafers to obtain N three-dimensional reconstructed microsystem units with communication functionality. Each unit contains six chips 4 and one programmable communication device bare chip 5. After dicing, the resulting microsystem units are integrated onto an FR-4 packaging substrate 10 and packaged in a housing, ultimately forming a highly integrated multi-chip microsystem with functional reconfiguration and communication path self-repair capabilities.

[0068] Before completing the laser cutting of the silicon wafer in step 1 to prepare the programmable communication device bare chip 5, laser heat treatment can be performed on the wiring area of ​​the guide switch 3 in the signal guiding array 2 to improve the operational stability of the programmable communication device bare chip 5. This area typically contains multiple metal wires and electrical connection nodes, with a dense structure and complex layout, which is prone to microscopic defects during the deposition process and local morphology control. By using a laser with controllable pulse energy for local heating before cutting, irradiating the guide switch 3 wiring area with a laser beam having a wavelength of 532nm, a pulse width of 60ns, a pulse energy of 100μJ, and a spot diameter of 15μm, the metal wires undergo microscopic morphological reshaping, resulting in smoother wire edges and more uniform cross-sectional thickness. This reduces contact impedance fluctuations caused by uneven current density and improves the conduction stability and long-term conductivity reliability of the guide switch 3 area. Furthermore, the local thermal field changes caused by laser irradiation can also release residual stress in the wiring area, preventing structural cracking or delamination caused by stress concentration during subsequent high-temperature processes or environmental loads, effectively improving the overall thermal stability and packaging reliability of the microsystem structure. This processing method is particularly suitable for programmable communication device structures with high integration density of the signal guidance array 2 and small wire spacing. It can enhance the functional stability and environmental adaptability of key areas without changing the original structural layout.

[0069] In step 4, before attaching the core 4 and the programmable communication device bare chip 5 to the surface of the first silicon wafer 6 or the second silicon wafer 7, a filler material can be placed between the contact interfaces. This filler material can be a pre-applied thermally conductive epoxy, a highly thermally conductive silicone doped with metal oxide particles, or a metal adhesive with a low melting point. These materials exhibit excellent thermal conductivity and are suitable for thermocompression bonding processes. They can optimize the thermal conduction path between the core 4 and the programmable communication device bare chip 5 and enhance mounting stability. The filler material also has cushioning properties, with elastic fillers uniformly dispersed within it and forming a micron-scale pore structure, which provides compressibility and interfacial compliance during thermocompression bonding. This structure mitigates localized uneven contact between the core 4 and the programmable communication device bare chip 5 and the silicon wafer caused by thickness deviation, surface unevenness, or fluctuations in loading pressure, helping to improve interfacial bonding quality and structural stability during the mounting process and reducing the risk of bonding defects. The filler material can be applied in zones as needed, targeting areas with a higher thermal load at the bottom of the core 4, rather than covering the entire bottom of the core 4. This ensures efficient heat conduction in key areas while reducing material usage and preventing filler materials from interfering with the hot pressing welding process, thereby improving process consistency and the controllability of the thermal management path. Depending on the size and power density of the core particle 4 in actual applications, the thickness of the filler material can be regionally regulated, with a preferred range of 50-200 microns to achieve a comprehensive balance between thermal conductivity, packaging strength, and fitting accuracy. As a supplement to hot pressing welding and epoxy resin reinforcement measures, this design helps improve the system's thermal control capabilities and long-term structural stability under high-load operating conditions.

[0070] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A programmable communication device comprising a control unit and a signal steering array, characterized in that: The control unit includes an input port and multiple output ports, wherein the output port is used to output a communication path configuration signal. The control unit also includes a path repair port, wherein the path repair port is used to receive an external input signal when a communication path fails. The control unit regenerates the communication path configuration signal based on the input signal to achieve self-repair of the communication path. The signal steering array includes multiple steering switches, which are connected to the output ports. Multiple chiplets are arranged at the outer edge of the signal steering array, and the steering switches establish programmable selective communication paths between the chiplets based on the communication path configuration signal. The control unit can output different combinations of the communication path configuration signals to construct communication paths between the chiplets corresponding to different system functions. The steering switches are composed of at least two NMOS transistors and an inverter, and the types of the steering switches include single-pole single-throw switches and single-pole double-throw switches. The control signal lines in the signal steering array adopt a layered wiring method and are provided with decoupling capacitors and pull-up resistors or pull-down resistors. The signal steering array is provided with a metal layer, which is located in the angle area between the control signal lines and the transmission signal lines of the steering switches.

2. The programmable communication device according to claim 1, wherein: The signal steering array supports expansion according to a 1×2 or 2×2 topology.

3. A method for preparing a multi-chip microsystem including a programmable communication device, characterized in that: The microsystem comprises the programmable communication device according to claim 1, and the preparation method comprises the following steps: S1. preparing a bare chip of a programmable communication device; S2, preparing through silicon vias on a first silicon wafer; S3, preparing a rewiring layer on the surfaces of the first silicon wafer and the second silicon wafer; S4, placing multiple chips and the programmable communication device bare chip on the upper surfaces of the first silicon wafer and the second silicon wafer respectively and bonding them together; S5, preparing micro bumps on the lower surface of the first silicon wafer and the upper surface of the second silicon wafer, and then bonding the first silicon wafer and the second silicon wafer together; S6. Slicing the bonded wafers and packaging them to obtain a multi-chip microsystem with a programmable communication device.

4. The method for preparing a multi-chip microsystem including a programmable communication device according to claim 3, characterized in that: In S1, laser heat treatment is performed on the signal guiding array region.

5. The method for preparing a multi-chip microsystem including a programmable communication device according to claim 4, characterized in that: The laser heat treatment uses a laser beam with a wavelength of 532 nm, a pulse width of 60 ns, a pulse energy of 100 μJ, and a spot diameter of 15 μm.

6. The method for preparing a multi-chip microsystem including a programmable communication device according to claim 5, characterized in that: In S4, cross-shaped alignment marks are provided on the upper surfaces of the first silicon wafer and the second silicon wafer to assist in the precise positioning and bonding alignment of the core and the programmable communication device bare chip.

7. The method for preparing a multi-chip microsystem including a programmable communication device according to claim 6, characterized in that: In S4 , before the core particle and the programmable communication device bare chip are bonded together, a filling material is provided between the core particle and the first silicon wafer or the second silicon wafer.

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