Transmission protocol processing module and method for conversion protocol card

Abstract

The invention discloses a transmission protocol processing module for a conversion protocol card. The transmission protocol processing module comprises a gate array logic controller FPGA; data receiving is completed between the FPGA and the protocol conversion module, and data communication connection is established between the FPGA and the transmission system through the transmission interface circuit. A communication protocol conversion product is designed based on full hardware, software program operation is avoided, and the product stability is greatly improved.

Description

Technical Field

[0001] The present invention relates to the protocol conversion technology of hot rolling production lines, and more specifically, to a transmission protocol processing module and method for converting protocol cards. Background Art

[0002] The basic automation system of the 1580 hot rolling production line of steel enterprises adopts the Siemens TDC system, while the drive system adopts Mitsubishi's MELVEC inverters. Therefore, Mitsubishi's special communication protocol must be used. Since protocol conversion is required for information exchange between the basic automation system and the drive system, currently available communication protocol conversion products on the market do not support Mitsubishi's special communication protocol, and most communication protocol conversion products are developed based on single-chip microcomputers or embedded system CPU processors, with general stability. Summary of the Invention

[0003] Aiming at the defects existing in the prior art, the purpose of the present invention is to provide a transmission protocol processing module and method for converting protocol cards, which designs a communication protocol conversion product based on all-hardware, without software programs running, greatly improving the stability of the product.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions:

[0005] The first aspect of the present invention provides a transmission protocol processing module for converting protocol cards, including a field programmable gate array (FPGA) of a gate array logic controller;

[0006] Receiving data is completed between the FPGA of the gate array logic controller and the protocol conversion module, and a data communication connection is established with the drive system through a drive interface circuit.

[0007] Preferably, the FPGA of the gate array logic controller includes:

[0008] JTAC2 interface and AS interface for providing program downloading;

[0009] Dip switches SW2, SW3 and pull-up resistors RP2, RP3 for implementing parameter settings of the transmission protocol SDLC and completing the configuration of the number of inverters on the slave network of the inverter;

[0010] Chip U8 for receiving the actual value of the inverter sent by the protocol conversion module and performing data interaction with the protocol conversion module through shared memory.

[0011] Preferably, the drive interface circuit is an optoelectronic conversion module of the DLR-CN3000 type.

[0012] Preferably, the wavelength of the optoelectronic conversion module is 850 nm;

[0013] The transmission bandwidth is 3 MHz·km;

[0014] The transmission loss > 12 db;

[0015] The maximum transmission distance is 800 m;

[0016] The signal type is TTL(5V);

[0017] The current consumption is 60 mA.

[0018] The second aspect of the present invention provides a transmission protocol processing method based on the transmission protocol processing module provided in the first aspect of the present invention, including the following steps:

[0019] S1, receiving symbols at the data link layer;

[0020] S2, parsing data at the data link layer;

[0021] S3, sending the user data parsed at the data link layer to the shared memory;

[0022] S4, controlling the transmission main protocol and monitoring the transmission state.

[0023] Preferably, the receiving of symbols at the data link layer in step S1 is specifically:

[0024] Organizing and transmitting data in the frame format of the data link layer;

[0025] Preferably, the frame format specifically includes:

[0026] F field, frame start and end flags;

[0027] A field, the address of the communication partner;

[0028] C field, used to distinguish the type of frame;

[0029] I field, user data;

[0030] FCS field, CRC check code.

[0031] Preferably, the parsing of data at the data link layer in step S2 is specifically:

[0032] Encoding each bit in the bit stream of the data link layer for transmission according to the format;

[0033] The encoding formats are Non NRZI and NRZI.

[0034] Preferably, in the Non NRZI encoding format, 1 is represented by one level and 0 is represented by another level;

[0035] In the NRZI encoding format, a non-inverted level represents 1 and an inverted level represents 0.

[0036] Preferably, the user data sent to the shared memory after parsing at the data link layer in step S3 is specifically as follows:

[0037] When the sending end sends information other than the F field, if five consecutive 1s are encountered, a 0 is automatically inserted;

[0038] When the receiving end receives data other than the F field, if five consecutive 1s are received, the subsequent 0 is automatically deleted to restore the original form of the information;

[0039] The processed data is sent to the shared memory.

[0040] A transmission protocol processing module and method for a conversion protocol card provided by the present invention achieve full hardware implementation of protocol conversion, can be generalized from general to specific protocol conversion, have high anti-interference and stability through module isolation design, and also have power isolation and redundancy design. Description of the Drawings

[0041] Figure 1 is a schematic diagram of the transmission protocol processing module of the present invention;

[0042] Figure 2 is a circuit schematic diagram of the transmission protocol processing module of the present invention;

[0043] Figure 3 is a schematic diagram of the transmission interface circuit in the transmission protocol processing module of the present invention;

[0044] Figure 4 is a schematic diagram of the Non NRZI and NRZI coding formats in the transmission protocol processing method of the present invention;

[0045] Figure 5 is a schematic diagram of step S4 in the transmission protocol processing method of the present invention. Detailed Embodiments

[0046] In order to better understand the above technical solutions of the present invention, the technical solutions of the present invention will be further described below in conjunction with the drawings and embodiments.

[0047] Combined with Figure 1 and Figure 2 as shown, a transmission protocol processing module for a conversion protocol card provided by the present invention includes a gate array logic controller 1.

[0048] The transmission protocol processing is carried out by the gate array logic controller FPGA EP4CE6E22I8N. The information exchange with the protocol conversion circuit is realized by means of the shared memory configured in the protocol conversion FPGA chip (the shared memory is configured in the FPGA chip and the on-chip memory is utilized), which is fully implemented in hardware without the operation of software programs, greatly improving the product stability. The gate array logic controller 1 receives data with the protocol conversion module and establishes a data communication connection with the drive system through the drive interface circuit.

[0049] The gate array logic controller FPGA includes:

[0050] XT3 provides a crystal oscillator for the gate array logic controller FPGA.

[0051] The JTAC2 interface 2 and the AS interface 3 are used to provide program downloading. The JTAC2 interface 2 and the AS interface 3 are in standby for each other and complete the same function.

[0052] The DIP switches SW2, SW3 and the pull-up resistors RP2, RP3 are used to realize the parameter setting of the transmission protocol SDLC and complete the configuration of the number of inverters on the slave network of the frequency converter.

[0053] The chip U8 EP4CE6E22I8N is used to receive the actual value of the frequency converter sent by the protocol conversion module and perform data interaction with the protocol conversion module through the shared memory. At the same time, it reads the set data of the frequency converter sent by the PLC from the shared memory of the protocol processing module to realize two-way data exchange. The chip U8 also completes functions such as displaying the status and fault indication of the drive frequency converter.

[0054] Combined Figure 3 As shown, the drive interface circuit is an optoelectronic conversion module of the DLR-CN3000 type.

[0055] The wavelength of the optoelectronic conversion module is 850 nm.

[0056] The transmission bandwidth is 3 MHz·km.

[0057] The transmission loss > 12 db.

[0058] The maximum transmission distance is 800 m.

[0059] The signal type is TTL (5V).

[0060] The current consumption is 60 mA.

[0061] The present invention also provides a transmission protocol processing method based on the transmission protocol processing module of the present invention, including the following steps:

[0062] S1, receiving the code elements of the data link layer;

[0063] The frame format of the data link layer organizes and transmits data. The frame format is shown in the following table:

[0064] Number of bits 8 8 8 8×n 16 8 Symbol F A C I FCS F Name Start flag field Address field Control field Information field Check field Start flag field

[0065] F field: Frame start and end flags, used to separate frames. The value is fixed as "01111110" (7EH).

[0066] A field: The address of the communication partner.

[0067] C field: Used to distinguish frame types. There are three types of frames: data frames (I frames), supervision frames (S frames), and unnumbered frames (U frames). The control field of each type of frame has different definitions.

[0068] I field: User data.

[0069] FCS field: CRC check code, calculated based on the A, C, and I fields. The CRC polynomial is:

[0070] g(x) = x 16 + x 15 + x 2 + 1

[0071] S2, data parsing of the data link layer;

[0072] The bits in the bit stream of the data link layer are encoded and transmitted in a certain format;

[0073] Supports two encoding formats: Non NRZI (standard format) and NRZI.

[0074] Combined Figure 4 As shown, in the Non NRZI encoding format, 1 is represented by one level (such as high level), and 0 is represented by another level (such as low level).

[0075] In the NRZI encoding format, (at the moment of adoption) no level inversion represents 1, and level inversion represents 0.

[0076] S3, the user data after data link layer parsing is sent to the shared memory;

[0077] The protocol stipulates that 01111110 is the starting flag byte. To prevent the same byte from appearing in other fields, 0-bit insertion and deletion techniques are adopted. Specifically:

[0078] When the sender sends information other than the F field, if it encounters 5 consecutive 1s, it automatically inserts a 0;

[0079] When the receiver receives data other than the F field, if it continuously receives 5 consecutive 1s, it automatically deletes the subsequent 0 to restore the original form of the information;

[0080] The data processed as above is sent to the shared memory.

[0081] S4, Transmission main protocol control and transmission status monitoring;

[0082] If an error occurs during the sending process, the protocol usually uses an exception end character, or a failure sequence, to invalidate this frame. It is stipulated that the failure character is 8 consecutive 1s. The 0-bit insertion and deletion techniques are not used in the failure sequence. The protocol stipulates that no data interval is allowed within a frame. Between two frames, the transmitter can continuously output the flag sequence or continuous high level, which is called the idle signal.

[0083] Each transmission network group is allowed to contain one master station and multiple slave stations (transmission devices). Each slave station is assigned a unique address. These addresses are consecutive and start from 0. The master station distinguishes each slave station according to these addresses.

[0084] All slave stations are divided into several groups. The master station cyclically sends control commands to each group of slave stations and waits for the status returned by the specified slave station within the group. That is to say, during each communication process, the master station sends a group of control commands at a time, but only one slave station within the group returns the status. This processing is to avoid conflicts among slave stations. The master station uses a cyclic method within the group to specify the slave station that needs to return the status.

[0085] For example, if a transmission network contains 10 transmission devices with address numbers from 0 to 9 and is grouped in a way that each group has 8 devices, with group numbers from 0 to 1, then group 0 contains transmission devices numbered 0 to 7, and group 1 contains transmission devices numbered 8 to 9. The communication process is as Figure 5 shown. When the master station does not receive the information returned by the specified slave station for 5 consecutive times, it marks that slave station as faulty.

[0086] Through the implementation and use on the 1580 hot rolling production line, the present invention solves the conversion between the general protocol and the special protocol and is realized through all-hardware design, greatly improving the stability. At the same time, the high anti-interference ability of this product makes it have a broad application prospect.

[0087] Those of ordinary skill in the art in this technical field should recognize that the above embodiments are only used to illustrate the present invention and are not intended to limit the present invention. As long as it is within the scope of the essential spirit of the present invention, changes and modifications to the above embodiments will fall within the scope of the claims of the present invention.

Claims

1. A transmission protocol processing module for a protocol conversion card, characterized in that: including a gate array logic controller FPGA; Receiving data is completed between the gate array logic controller FPGA and the protocol conversion module, and a data communication connection is established with the drive system through the drive interface circuit.

2. The transmission protocol processing module for converting protocol cards according to claim 1, wherein The gate array logic controller FPGA includes: JTAC2 interface and AS interface for providing program download; Dip switches SW2, SW3 and pull-up resistors RP2, RP3 for implementing parameter settings of the drive protocol SDLC and completing the configuration of the number of inverters on the slave network of the frequency converter; Chip U8 for receiving the actual value of the frequency converter sent by the protocol conversion module and performing data interaction with the protocol conversion module through shared memory.

3. The transmission protocol processing module for converting protocol cards according to claim 1, wherein: The drive interface circuit is an optoelectronic conversion module of the DLR-CN3000 type.

4. The transmission protocol processing module for converting protocol cards according to claim 3, characterized in that: The wavelength of the optoelectronic conversion module is 850 nm; The transmission bandwidth is 3 MHz·km; The transmission loss > 12 db; The maximum transmission distance is 800 m; The signal type is TTL(5V); The current consumption is 60 mA.

5. A transmission protocol processing method for a transmission protocol processing module according to any one of claims 1-4, characterized in that, including the following steps: S1, receiving code elements of the data link layer; S2, parsing data of the data link layer; S3, sending the user data parsed by the data link layer to the shared memory; S4, controlling the main drive protocol and monitoring the drive status.

6. The transmission protocol processing method according to claim 5, characterized in that The specific process of receiving code elements of the data link layer in step S1 is as follows: The data is organized and transmitted in the frame format of the data link layer.

7. The transmission protocol processing method according to claim 6, characterized in that The frame format specifically includes: F field, frame start and end flags; A field, the address of the communication partner; C field, used to distinguish the type of frame; I field, user data; FCS field, CRC check code.

8. The transmission protocol processing method according to claim 7, wherein The specific process of parsing data of the data link layer in step S2 is as follows: Each bit in the bit stream of the data link layer is encoded and transmitted according to the format; The encoding formats are Non NRZI and NRZI.

9. The transmission protocol processing method according to claim 8, wherein: In the Non NRZI encoding format, 1 is represented by one level and 0 is represented by another level; In the NRZI encoding format, no level inversion represents 1 and level inversion represents 0.

10. The transmission protocol processing method according to claim 9, characterized in that, The specific process of sending the user data parsed by the data link layer to the shared memory in step S3 is as follows: When the sending end sends other information except the F field, if it encounters 5 consecutive 1s, it automatically inserts a 0; When the receiving end receives data except the F field, if it continuously receives 5 consecutive 1s, it automatically deletes the subsequent 0 and restores the original form of the information; The data processed as above is sent to the shared memory.

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