MTP devices and electronic devices

Abstract

The present invention relates to the field of semiconductor technology, and specifically to an MTP device and electronic device, comprising a first tunneling transistor, a second tunneling transistor, a selection transistor, and a capacitor formed on a substrate, wherein the back gates of the first tunneling transistor and the second tunneling transistor are isolated from each other; the first tunneling transistor and the second tunneling transistor share a floating gate, which serves as the lower electrode of the capacitor; the capacitor also includes an intergate dielectric layer and a control gate, the control gate vertically opposing the floating gate, and controlling the potential of the floating gate through capacitive coupling between the floating gate and the control gate; the first tunneling transistor is used to implement programming, and the second tunneling transistor is used to implement erasure. The device can effectively reduce the impact of F-N tunneling on the gate oxide dielectric between the floating gate and the substrate, significantly increase the number of operable times of the memory cell of the MTP device, and thereby effectively increase the service life of the MTP device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an MTP device and electronic equipment. Background Art

[0002] Multi-Time Programmable Memory (MTP) is a non-volatile memory that retains stored data after a power outage and can be used to store, read, and erase data multiple times. It is widely used in personal computers, electronic devices, mobile storage, and other fields.

[0003] CMOS-based MTP devices are often integrated into chips as embedded non-volatile memory to meet the specific performance requirements of the main logic device, such as storage array size, read / write speed, and read / write voltage. Embedded MTP devices offer advantages such as low cost, low power consumption, and high reliability, and are widely used in power management chips and sensor calibration chips.

[0004] In order to be compatible with CMOS technology and reduce costs, MTP devices usually adopt a single-layer floating gate structure. Figure 1 and Figure 2 As shown, the basic memory cell of the conventional MTP device includes a conventional floating gate transistor 100, a conventional select transistor 200, and a conventional MOS capacitor 300. The conventional MOS capacitor 300 includes a PW 301, a conventional floating gate 302, a gate oxide dielectric 303, and a doped region 304. The doped region 304 is disposed around the conventional floating gate 302. The PW 301 serves as the CG electrode terminal (i.e., the bottom electrode) of the conventional MOS capacitor 300, and the conventional floating gate 302 serves as the FG electrode terminal (i.e., the top electrode) of the conventional MOS capacitor 300.

[0005] The operating principle of existing MTP devices is as follows: voltage is applied to the CG electrode of the MOS capacitor 300 to control the potential of the FG electrode via capacitive coupling. Programming is performed using HCI (hot carrier injection) at the floating-gate transistor 100, and erasure is performed using FN tunneling. The select transistor 200 selects the desired bit for both write and erase operations. Both programming and erasing in MTP devices with a single-layer floating gate structure require electrons to pass through the gate oxide dielectric of the floating-gate transistor. As the number of write and erase cycles increases, this electron tunneling behavior can severely impact the gate oxide quality, ultimately affecting the overall device lifespan. Summary of the Invention

[0006] The object of the present invention is to provide an MTP device and a preparation method thereof, which can effectively reduce the influence of FN tunneling on the gate oxide dielectric between the floating gate and the substrate, significantly increase the number of operable times of the memory cell of the MTP device, and thus effectively increase the service life of the MTP device.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] In a first aspect, the present invention provides an MTP device, comprising a first tunneling transistor, a second tunneling transistor, a selection transistor and a capacitor formed on a substrate, wherein the back gates of the first tunneling transistor and the second tunneling transistor are isolated from each other; the first tunneling transistor and the second tunneling transistor share a floating gate, and the floating gate serves as the lower electrode of the capacitor. The capacitor also includes an intergate dielectric layer and a control gate, and the control gate is vertically opposite to the floating gate, and the potential of the floating gate is controlled by capacitive coupling between the floating gate and the control gate; the first tunneling transistor is used to implement programming, and the second tunneling transistor is used to implement erasure.

[0009] Furthermore, an isolation protrusion is formed on the surface of the substrate, and the isolation protrusion is located between the first tunneling transistor and the second tunneling transistor;

[0010] The areas of the lower surface of the floating gate and the lower surface of the control gate corresponding to the isolation protrusion are formed into an upwardly protruding curved surface structure.

[0011] Furthermore, it also includes a first shallow trench isolation structure formed in the well region of the substrate, which separates the well region into a first area and a second area through the first shallow trench isolation structure. The selection transistor and the first tunneling transistor are located in the first area, and the second tunneling transistor is located in the second area.

[0012] Furthermore, it includes a first lead-out structure and a second lead-out structure, wherein the doping type of the first lead-out structure and the second lead-out structure is the same as the doping type of the well region;

[0013] The first lead-out structure is located in the first region, and the first lead-out structure is connected to the back gate of the first tunneling transistor;

[0014] The second lead-out structure is located in the second region, and the second lead-out structure is connected to the back gate of the second tunneling transistor.

[0015] Furthermore, the first lead-out structure is located on one side of the first tunneling transistor or the selection transistor, and is isolated from the first tunneling transistor or the selection transistor via a second shallow trench isolation structure.

[0016] Furthermore, the first lead-out structure is connected to the first back end, the second lead-out structure is connected to the second back end, the selection gate of the selection transistor is connected to the word line, the drain region of the selection transistor is connected to the bit line, the source region of the selection transistor is connected to the source region of the first tunneling transistor, and is connected to the source end.

[0017] Furthermore, an electric field is applied between the control gate and the first back end toward the control gate, so that electrons in the well region below the first tunneling transistor tunnel into the floating gate, thereby achieving programming;

[0018] An electric field is applied between the floating gate and the second back end toward the back gate of the second tunneling transistor, so that electrons stored in the floating gate are tunneled into the well region below the second tunneling transistor, thereby achieving erasure.

[0019] Furthermore, a projection area of ​​the lower surface of the control gate in the vertical direction is located within a projection area of ​​the upper surface of the floating gate in the vertical direction.

[0020] Furthermore, a first spacer structure is formed on a side surface of the floating gate, and a second spacer structure is formed on a side surface of the selection gate of the selection transistor.

[0021] In a second aspect, the present invention provides an electronic device comprising the above-mentioned MTP device.

[0022] The unexpected beneficial effects of the present invention are as follows:

[0023] In the present invention, the back gates of the first and second tunneling transistors are isolated from each other, and they share a floating gate. The floating gate serves as the lower electrode of the capacitor. The capacitor also includes an intergate dielectric layer and a control gate. The control gate is vertically opposed to the floating gate, and the potential of the floating gate is controlled by capacitive coupling between the floating gate and the control gate. The first tunneling transistor is used for programming, i.e., applying an electric field toward the control gate causes electrons in the well region below the first tunneling transistor to tunnel into the floating gate, thereby achieving programming. The second tunneling transistor is used for erasing, i.e., applying an electric field toward the back gate of the second tunneling transistor causes electrons stored in the floating gate to tunnel into the well region below the second tunneling transistor, thereby achieving erasure. This solves the problem of conventional MTP devices requiring electrons to pass through the gate oxide dielectric of the floating gate transistor for both programming and erasing. It effectively reduces the impact of FN tunneling on the gate oxide dielectric between the floating gate and the substrate, significantly increases the number of operable memory cells in the MTP device, and thus effectively increases the service life of the MTP device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the top structure of an existing MTP device is shown.

[0025] Figure 2 Shown Figure 1 Cross-sectional view along the AA direction.

[0026] Figure 3 A schematic diagram of the top structure of the MTP device according to an embodiment of the present invention is shown.

[0027] Figure 4 Shown Figure 3 A cross-sectional view of an embodiment along the AA direction.

[0028] Figure 5 Shown Figure 3 A cross-sectional view of another embodiment along the AA direction.

[0029] Figure 6 Shown Figure 3 A cross-sectional view of an embodiment along direction BB.

[0030] Figure 7 Shown Figure 3 Cross-sectional view along CC direction.

[0031] Figure 8 A circuit connection diagram of the MTP device according to an embodiment of the present invention is shown.

[0032] In the figure, 1 is a first tunneling transistor, 2 is a second tunneling transistor, 3 is a selection transistor, 31 is a selection gate, 32 is a second spacer structure, 33 is a second gate oxide layer, 4 is a capacitor, 41 is a floating gate, 42 is a control gate, 43 is a gate dielectric layer, 44 is a first spacer structure, 45 is a first gate oxide layer, 5 is a first lead structure, 6 is a second lead structure, 7 is an isolation protrusion, 8 is a first shallow trench isolation structure, 9 is a second shallow trench isolation structure, 10 is a substrate, 11 is a well region, and 12 is a protective layer.

[0033] 100—existing floating gate transistor, 200—existing selection transistor, 300—existing MOS capacitor, 301—PW, 302—existing floating gate, 303—gate oxide dielectric, 304—doped region. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art will readily appreciate the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the various details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are intended only to illustrate the present invention and are not intended to limit the scope of protection of the present invention.

[0035] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0036] In the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like indicate positions or locations based on those shown in the accompanying drawings. These terms are intended solely to facilitate and simplify the description of the present invention and are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used solely for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0037] In one embodiment, please refer to Figure 3 、 Figure 4 and Figure 5 As shown, the present invention provides an MTP device, including a first tunneling transistor 1, a second tunneling transistor 2, a selection transistor 3 and a capacitor 4 formed on a substrate 10, wherein the back gates of the first tunneling transistor 1 and the second tunneling transistor 2 are isolated from each other; the first tunneling transistor 1 and the second tunneling transistor 2 share a floating gate 41, and the floating gate 41 serves as the lower electrode of the capacitor 4. The capacitor 4 also includes an intergate dielectric layer 43 and a control gate 42, and the control gate 42 is vertically opposite to the floating gate 41, and the potential of the floating gate 41 is controlled by capacitive coupling between the floating gate 41 and the control gate 42; the first tunneling transistor 1 is used to implement programming, and the second tunneling transistor 2 is used to implement erasure.

[0038] In traditional single-layer floating-gate MTP devices, programming and erasing operations are performed within the same floating-gate transistor region. Electron tunneling can severely impact the quality of the gate oxide dielectric layer between the floating gate 41 and the substrate 10. The present invention separates the programming and erasing functions into two separate tunneling transistors, first 1 and second 2. These two tunneling transistors operate independently, reducing the number of writes and erases required for a single transistor and the cumulative damage to the gate oxide dielectric caused by FN tunneling. This significantly increases the number of operable memory cells in the MTP device, effectively extending the device's service life.

[0039] The present invention uses the floating gate 41 as the lower electrode of the capacitor 4, and together with the control gate 42, forms a capacitor structure, and controls the potential of the floating gate 41 through capacitive coupling. This design effectively increases the capacitive coupling ratio, making the control of the floating gate potential more accurate and efficient. At the same time, since the control gate 42 and the floating gate 41 are arranged relative to each other, see Figure 3 As shown, the control gate 42 and the floating gate 41 have the same direction, and both laterally cover the first tunneling transistor 1 and the second tunneling transistor 2. As a result, the relative area between the floating gate 41 and the control gate 42 can be made larger in a smaller chip area, thereby achieving a higher capacitive coupling efficiency, which is beneficial to reducing the chip area.

[0040] The MTP device structure described in this invention eliminates the need for a new photomask and can be implemented through simple optimization of existing processes. In chip manufacturing, photomasks are expensive and complex to produce. Avoiding the need for a new photomask reduces process steps, lowers production costs and cycle time, improves production efficiency, and enhances product competitiveness in the market.

[0041] As a preferred embodiment of the present invention, see Figure 5 As shown, an isolation protrusion 7 is formed on the surface of the substrate 10, and the isolation protrusion 7 is located between the first tunneling transistor 1 and the second tunneling transistor 2. The lower surface of the floating gate 41 and the lower surface of the control gate 42 corresponding to the isolation protrusion 7 are formed into an upwardly convex curved surface structure, which can increase the relative area between the control gate 42 and the floating gate 41.

[0042] Since the lower surfaces of the floating gate 41 and the control gate 42 correspond to the isolation protrusion 7 and form an upwardly convex curved structure, the relative area between the two is effectively increased. , where C is the capacitance, Where d is the dielectric constant, S is the relative area of ​​the plates, and d is the plate spacing. When the dielectric constant and plate spacing remain unchanged, an increase in relative area S increases the capacitance C. This means that more charge can be stored under the same voltage conditions, improving capacitive coupling efficiency and making the control gate 42 more sensitive and precise in controlling the potential of the floating gate 41, thereby optimizing the electrical performance of the MTP device.

[0043] The isolation protrusion 7 also strengthens the back-gate isolation between the first tunneling transistor 1 and the second tunneling transistor 2. Not only does it physically separate the back gates of the two tunneling transistors, but it also, combined with the curved structures of the floating gate 41 and control gate 42, further enhances the isolation effect. Electrically, this reduces leakage and signal interference between the two back gates, ensuring the independence and stability of programming operations for the first tunneling transistor 1 and erasing operations for the second tunneling transistor 2, thereby improving the accuracy and reliability of data storage and processing in the MTP device.

[0044] This preferred embodiment achieves improved functionality through clever structural design without significantly increasing the overall chip area. The isolation protrusion 7 is used to change the shapes of the floating gate 41 and the control gate 42, increasing the relative area and improving capacitance performance while strengthening back-gate isolation.

[0045] Furthermore, the isolation protrusion 7 is made of silicon dioxide SiO2, silicon nitride Si3N4 or tantalum oxide Ta2O5.

[0046] Silicon dioxide is a commonly used insulating material in semiconductor manufacturing, boasting excellent insulating properties. It effectively blocks current conduction between the back gates of the first tunneling transistor 1 and the second tunneling transistor 2, preventing leakage and ensuring isolation between the two back gates, guaranteeing the independence of programming and erasing operations. Its chemical properties are stable, making it less susceptible to chemical reactions with surrounding materials during the complex manufacturing process and subsequent use of MTP devices, maintaining the stability of its structure and performance. Furthermore, silicon dioxide exhibits excellent compatibility with common semiconductor materials such as the substrate 10, floating gate 41, and control gate 42, making it easily integrated into the overall device structure. It is also easy to process during photolithography and etching processes, allowing for precise control of its shape and size.

[0047] Silicon nitride also has excellent insulation properties and a relatively high dielectric constant. In addition to achieving effective isolation between the back gates, it can also, to a certain extent, enhance the capacitive coupling effect between the floating gate 41 and the control gate 42, thereby improving the electrical performance of the device. Silicon nitride has good mechanical properties and high hardness. It can withstand certain external forces during device manufacturing and use without being easily damaged, providing stable support for the device structure. At the same time, silicon nitride has good chemical stability and is resistant to a variety of chemical substances. It can adapt to the various chemical treatment steps in the MTP device manufacturing process, ensuring the reliability and long-term stability of the device.

[0048] Tantalum oxide is a high-dielectric-constant material. Using tantalum oxide as the isolation bump material significantly increases the capacitance between the floating gate 41 and the control gate 42. At smaller device sizes, this significantly improves capacitive coupling efficiency, enabling more sensitive and precise regulation of the floating gate 41 potential by the control gate 42, thereby enhancing the read / write speed and storage performance of the MTP device. Tantalum oxide also exhibits strong thermal stability, maintaining stable performance even at high temperatures. This ensures that the isolation bump performance is not affected by the high-temperature manufacturing processes (such as annealing) and heat generated during use, maintaining normal device operation.

[0049] As a preferred embodiment of the present invention, see Figure 4As shown, the substrate 10 is provided with a well region 11 and a first shallow trench isolation structure 8 formed in the well region 11. The well region 11 is separated into a first region and a second region by the first shallow trench isolation structure 8. The selection transistor 3 and the first tunneling transistor 1 are located in the first region, and the second tunneling transistor 2 is located in the second region.

[0050] The first shallow trench isolation structure 8 separates the well region 11, placing the select transistor 3 and the first tunneling transistor 1 in the first region, and the second tunneling transistor 2 in the second region. This layout isolates transistors with different functions from each other, reducing electrical interference between them. During operation of the MTP device, the gating operation of the select transistor 3, the programming operation of the first tunneling transistor 1, and the erasing operation of the second tunneling transistor 2 do not generate signal crosstalk due to their close proximity, ensuring that each transistor can operate independently and stably, improving the accuracy of device data storage and processing.

[0051] Shallow trench isolation (STI) structures are a mature technology in semiconductor manufacturing. Using the first STI structure 8 for region demarcation facilitates compatibility with existing CMOS manufacturing processes. During the manufacturing process, existing photolithography, etching, and filling steps can be utilized to create the first STI structure 8 and well region 11, reducing process complexity and manufacturing costs. This design, based on mature processes, helps improve the production efficiency and yield of MTP devices, promoting their large-scale production and application.

[0052] The well region 11 and the first shallow trench isolation structure 8 extend from the surface of the substrate 10 into the interior of the substrate 10 and terminate within the interior of the substrate 10. The substrate 10 is of a first doping type, and the well region 11 is of a second doping type. In one embodiment, the first doping type is, for example, P-type doping, and the second doping type is, for example, N-type doping, forming a PN junction structure. This PN junction can effectively adjust the threshold voltage of the transistor and optimize the electrical performance of the transistor. For the selection transistor 3, the first tunneling transistor 1, and the second tunneling transistor 2, appropriate threshold voltages ensure that they are accurately turned on and off in different operating states (programming, erasing, and reading), thereby improving the read and write speed and reliability of the MTP device. Furthermore, the PN junction also provides a certain degree of isolation, further reducing leakage between different regions and improving the overall performance of the device.

[0053] Furthermore, a first tunneling transistor 1 and a selection transistor 3 are formed in the well region 11 of the first region. Figure 6As shown, the first tunneling transistor 1 includes a source region S1 and a drain region D1 located in the well region 11, and a gate stack located above the well region 11. The selection transistor 3 includes a source region S2 and a drain region D2 located in the well region 11, and a gate stack located above the well region 220. The source regions S1, S2 and the drain regions D1, D2 are doped regions in the well region 11. For example, for an N-type MOSFET, the source region and the drain region are N-type doped; for a P-type MOSFET, the source region and the drain region are P-type doped. In this embodiment, the first tunneling transistor 1 and the selection transistor 3 are P-type MOSFETs, and the source regions S1, S2 and the drain regions D1, D2 are P-type doped.

[0054] The gate stack of the first tunneling transistor 1 includes a first gate oxide layer 45 and a floating gate 41, wherein the first gate oxide layer 45 is sandwiched between the well region 11 and the floating gate 41. The gate stack of the select transistor 3 includes a second gate oxide layer 33 and a select gate 31, wherein the second gate oxide layer 33 is sandwiched between the well region 11 and the select gate 31.

[0055] As a preferred embodiment of the present invention, see Figure 3 、 Figure 6 and Figure 7 As shown, the MTP device further includes a first lead-out structure 5 and a second lead-out structure 6. The doping type of the first lead-out structure 5 and the second lead-out structure 6 is the same as the doping type of the well region 11. The first lead-out structure 5 is located in the first region and is connected to the back gate of the first tunneling transistor 1. The second lead-out structure 6 is located in the second region and is connected to the back gate of the second tunneling transistor 2. The back gate of the first tunneling transistor 1 is the well region 11 located below the first tunneling transistor 1, and the back gate of the second tunneling transistor 2 is the well region 11 located below the second tunneling transistor 2.

[0056] The first lead-out structure 5 and the second lead-out structure 6 have the same doping type as the well region 11, ensuring good electrical compatibility. Taking N-type doping as an example, the same type of doping reduces contact resistance and makes current transmission smoother. The first lead-out structure 5 is connected to the back gate of the first tunneling transistor 1, and the second lead-out structure 6 is connected to the back gate of the second tunneling transistor 2. This connection method provides a stable electrical connection for the back gate. During programming and erasing operations, the back gate voltage can be accurately controlled to optimize the electrical performance of the tunneling transistor. A stable back gate voltage ensures that electrons can be effectively injected from the control gate 42 into the floating gate 41 during programming, and that electrons can be smoothly removed from the floating gate 41 during erasing, thereby improving the read and write accuracy and reliability of the MTP device.

[0057] From a manufacturing perspective, the same doping type for the lead-out structure and well region facilitates integration. Using the same doping process in semiconductor manufacturing simplifies the process, reduces process steps and parameter adjustments, and reduces process complexity and costs. Furthermore, this design helps improve process consistency and repeatability, ensuring similar performance across batches of MTP devices. This improves product yield and reliability, facilitating large-scale production and application.

[0058] Furthermore, the first lead-out structure 5 and the second lead-out structure 6 are N+ doped regions formed on the surface of the substrate 10 .

[0059] The N+ doped region has a high concentration of electrons and high conductivity. As an extraction structure, it can significantly reduce contact resistance when connected to the well region 11 and the back gate of the tunneling transistor. During the operation of the MTP device, this facilitates fast and efficient current transmission, reducing voltage drop and energy loss caused by resistance. During programming or erasing operations, current can reach the back gate more smoothly, ensuring that the back gate voltage can respond quickly and reach the expected value, thereby improving operation speed and accuracy.

[0060] The high-doping concentration N+ doping region provides a large number of carriers, enhancing the conductivity of the lead-out structure. In MTP devices, programming and erasing operations involve the tunneling and transfer of electrons. Good conductivity ensures that these electrons can be replenished or removed in a timely manner, maintaining a stable back-gate voltage, thereby ensuring the normal operation of the tunneling transistor and improving the overall electrical performance and reliability of the MTP device.

[0061] In semiconductor manufacturing processes, N+ doping is a common and mature technology. Using the N+ doped region as the lead-out structure facilitates integration with existing CMOS manufacturing processes. In the same process flow, existing process steps such as lithography, ion implantation, and annealing can be used to prepare the N+ doped region, eliminating the need to develop additional complex new processes. This reduces process costs and development cycles, and improves production efficiency and yield. Furthermore, by precisely controlling parameters such as the ion implantation dose, energy, and annealing conditions, the doping concentration, depth, and range of the N+ doped region can be accurately controlled. This allows the electrical properties of the lead-out structure to be precisely adjusted according to the design requirements of the MTP device during the manufacturing process, ensuring stable and consistent performance across devices produced in different batches.

[0062] The N+ doped region forms a good ohmic contact with the well region 11 and the tunneling transistor back gate. This stable connection ensures that the electrical connection between the lead-out structure and the back gate will not easily fail during the long-term use of the MTP device. Even after multiple program and erase cycles, temperature fluctuations, and other external factors, the connection remains reliable, ensuring the stability and service life of the device.

[0063] Further, see Figure 6 As shown, the first lead-out structure 5 is located on one side of the first tunneling transistor 1 or the select transistor 3 and is isolated from the first tunneling transistor 1 or the select transistor 3 via a second shallow trench isolation structure 9. In one embodiment, the first lead-out structure 5 is located on one side of the first tunneling transistor 1 and is isolated from the drain region D1 of the first tunneling transistor 1 via the second shallow trench isolation structure 9.

[0064] The second shallow trench isolation structure 9 physically separates the first lead structure 5 from the first tunneling transistor 1 or the select transistor 3. This effectively prevents material diffusion or short circuits between different structures during the manufacturing process. Diffusion between materials is unavoidable in semiconductor manufacturing processes such as high temperatures and chemical treatments, but the shallow trench isolation structure prevents this diffusion, ensuring the integrity and independence of each structure. Furthermore, physical isolation prevents accidental contact between structures due to external forces or other factors, improving the structural stability and long-term reliability of the MTP device.

[0065] Further, see Figure 6 and Figure 8 As shown, the first lead-out structure 5 is connected to the first back end NW, the second lead-out structure 6 is connected to the second back end BG, the select gate 31 of the select transistor 3 is connected to the word line (Word Line), the drain region D2 of the select transistor 3 is connected to the bit line (Bit Line), and the source region S2 of the select transistor 3 is connected to the source region S1 of the first tunneling transistor 1 and is connected to the source end.

[0066] As a preferred embodiment of the present invention, an electric field toward the control gate 42 is applied between the control gate 42 and the first back end NW, so that the electrons in the well region 11 below the first tunneling transistor 1 tunnel into the floating gate 41, thereby realizing programming; and an electric field toward the back gate of the second tunneling transistor 2 is applied between the floating gate 41 and the second back end BG, so that the electrons stored in the floating gate 41 tunnel into the well region 11 below the second tunneling transistor 2, thereby realizing erasure.

[0067] Exemplarily, a programming voltage is applied to the control gate CG, the programming voltage is 5V, the voltage applied to the select gate SG, i.e., the word line WL, is 1V, the voltage applied to the first back end NW is 0V, the voltage applied to the second back end BG is 5V, and the voltage applied to the bit line BL is 0V. A sufficiently large upward electric field is formed between the control gate CG and the first back end NW, so that the electrons in the well region 11 below the first tunneling transistor 1 pass upward through the first gate oxide layer 45 of the first tunneling transistor 1 into the floating gate 41 by means of FN tunneling, thereby realizing programming.

[0068] An erase voltage is applied to the control gate CG, which is -5V. A voltage of 1V is applied to the select gate SG, i.e., the word line WL. A voltage of 0V is applied to the first back end NW, a voltage of 5V is applied to the second back end BG, and a voltage of 0V is applied to the bit line BL. A sufficiently large downward electric field is formed between the second back end BG and the floating gate FG, so that the electrons in the floating gate FG pass downward through the first gate oxide layer 45 of the second tunneling transistor 2 into the well region 11 by means of FN tunneling, thereby achieving erasure.

[0069] A read voltage (e.g., 0V) is applied to the control gate CG. A negative voltage (e.g., -3V) is applied to the select gate SG (word line WL). A 0V voltage is applied to the first back terminal NW and the second back terminal BG. The current in the bit line BL is read and compared with the reference current Iref to determine the storage type. When electrons are stored in the floating gate FG, corresponding to a low threshold voltage, the current Id generated in the bit line BL is extremely large, indicating a "1." When no electrons are stored in the floating gate FG, corresponding to a high threshold voltage, the current Id generated in the bit line BL is extremely small, indicating a "0."

[0070] As a preferred embodiment of the present invention, the projection area of ​​the lower surface of the control gate 42 in the vertical direction is located within the projection area of ​​the upper surface of the floating gate 41 in the vertical direction.

[0071] This arrangement allows the electric field generated by the voltage applied to the control gate 42 to more evenly cover the floating gate 41. During programming and erasing operations, the uniform electric field distribution ensures more stable injection and removal of electrons from the floating gate 41. During programming, electrons more evenly migrate upward from the well region 11 through the first gate oxide layer 45 of the first tunneling transistor 1 via FN tunneling, entering the floating gate 41 and avoiding localized charge accumulation. During erasing, electrons also migrate downward from the floating gate 11 through the first gate oxide layer 45 of the second tunneling transistor 2 via FN tunneling in a more orderly manner. This effectively improves the accuracy of data storage in the MTP device, reduces the probability of data errors, and enhances the read and write performance of the MTP device.

[0072] If the projected area of ​​the control gate 42 is larger than the projected area of ​​the floating gate 41, this can lead to electric field concentration at the edge of the floating gate 41. As the number of erase / write cycles increases, this edge electric field concentration accelerates aging and damage to the intergate dielectric layer 43, impacting the device's lifespan. The optimized structure avoids this electric field concentration at the edge of the floating gate 41, reduces the localized high electric field stress in the intergate dielectric layer 43, and reduces the risk of breakdown or performance degradation of the intergate dielectric layer 43. This significantly extends the number of erase / write cycles and overall lifespan of the MTP device, improving product reliability.

[0073] As a preferred embodiment of the present invention, see Figure 6As shown, a first spacer structure 44 is formed on the side of the floating gate 41 , and a second spacer structure 32 is formed on the side of the selection gate 31 of the selection transistor 3 .

[0074] The first sidewall spacer 44 on the side of the floating gate 41 and the second sidewall spacer 32 on the side of the select gate 31 effectively isolate different device regions. In semiconductor devices, electrical interference may exist between adjacent regions. The sidewall spacer can reduce this interference and improve the stability and reliability of the device. In MTP devices, the operating states of the floating gate 41 and the select gate 31 are interconnected. Good isolation ensures that the floating gate 41 and the select gate 31 operate independently and accurately, avoiding signal crosstalk and improving the accuracy of data storage and reading.

[0075] The presence of the spacer structure can also improve the electric field distribution at the gate edge. At the gate edge, the electric field tends to concentrate, which can lead to device performance degradation or even breakdown. The first spacer structure 44 and the second spacer structure 32 can modulate the electric field, making the electric field distribution more uniform, reducing the electric field intensity at the gate edge, reducing the adverse effects of electric field concentration, and improving the device's voltage resistance and service life.

[0076] Furthermore, the sidewall spacer structure provides physical protection for the floating gate 41 and select gate 31. During semiconductor manufacturing, subsequent process steps may damage the already formed device structure. The sidewall spacer acts as a protective layer, reducing the occurrence of such damage and ensuring the integrity and stability of the device structure. During processes such as etching and deposition, the sidewall spacer prevents accidental corrosion of the floating gate 41 and select gate 31, ensuring consistent and reliable device performance.

[0077] As a preferred embodiment of the present invention, see Figures 4 to 7 As shown, a protection layer 12 is formed on the substrate 10 , and the protection layer 12 covers the first tunneling transistor 1 , the second tunneling transistor 2 and the selection transistor 3 .

[0078] In one embodiment, the present invention further provides an electronic device, which includes the MTP device described in any one of the above embodiments.

[0079] The unexpected technical effects of this application are:

[0080] In the MTP device of the present application, the back gates of the first tunneling transistor 1 and the second tunneling transistor 2 are isolated from each other, and the first tunneling transistor 1 and the second tunneling transistor 2 share a floating gate 41, with the floating gate 41 serving as the lower electrode of the capacitor 4. The capacitor 4 also includes an intergate dielectric layer 43 and a control gate 42, and the control gate 42 is vertically opposite to the floating gate 41. The potential of the floating gate 41 is controlled by capacitive coupling between the floating gate 41 and the control gate 42; the first tunneling transistor 1 is used to implement programming, that is, an electric field is applied toward the control gate 42, so that the electrons in the well region 11 below the first tunneling transistor 1 tunnel into the floating gate 41 by means of FN, thereby implementing programming; the second tunneling transistor 2 is used to implement erasure, that is, an electric field is applied toward the back gate of the second tunneling transistor 2, so that the electrons stored in the floating gate 41 tunnel into the well region 11 below the second tunneling transistor 2, thereby implementing erasure. This solves the problem that both programming and erasing of traditional MTP devices require electrons to pass through the gate oxide dielectric of the floating gate transistor, effectively reduces the impact of FN tunneling on the gate oxide dielectric between the floating gate 41 and the substrate 10, significantly increases the number of operable times of the memory cell of the MTP device, and thus effectively increases the service life of the MTP device.

[0081] Furthermore, an isolation protrusion 7 is formed on the surface of the substrate 10, and the isolation protrusion 7 is located between the first tunneling transistor 1 and the second tunneling transistor 2. The areas on the lower surfaces of the floating gate 41 and the control gate 42 corresponding to the isolation protrusion 7 are formed into an upwardly convex curved surface structure, which can increase the relative area between the control gate 42 and the floating gate 41, thereby storing more charge under the same voltage conditions, improving the capacitive coupling efficiency, and making the control gate 42 more sensitive and precise in controlling the potential of the floating gate 41, thereby optimizing the electrical performance of the MTP device.

[0082] The above embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Any equivalent substitution or modification made by those skilled in the art based on the present invention is within the protection scope of the present invention.

Claims

1. An MTP device, characterized in that: The invention comprises a first tunneling transistor (1), a second tunneling transistor (2), a selection transistor (3) and a capacitor (4) formed on a substrate (10), wherein the back gates of the first tunneling transistor (1) and the second tunneling transistor (2) are isolated from each other; The first tunneling transistor (1) and the second tunneling transistor (2) share a floating gate (41), the floating gate (41) serving as a lower electrode of the capacitor (4), the capacitor (4) further comprising an inter-gate dielectric layer (43) and a control gate (42), the control gate (42) being vertically opposed to the floating gate (41), and the potential of the floating gate (41) being controlled by capacitive coupling between the floating gate (41) and the control gate (42); The first tunneling transistor (1) is used to implement programming, and the second tunneling transistor (2) is used to implement erasure.

2. The MTP device according to claim 1, wherein: An isolation protrusion (7) is formed on the surface of the substrate (10), and the isolation protrusion (7) is located between the first tunneling transistor (1) and the second tunneling transistor (2); The areas of the lower surface of the floating gate (41) and the lower surface of the control gate (42) corresponding to the isolation protrusion (7) are formed into an upwardly protruding curved surface structure.

3. The MTP device according to claim 1, wherein: The invention also includes a first shallow trench isolation structure (8) formed in the well region (11) of the substrate (10), wherein the well region (11) is separated into a first region and a second region by the first shallow trench isolation structure (8), the selection transistor (3) and the first tunneling transistor (1) are located in the first region, and the second tunneling transistor (2) is located in the second region.

4. The MTP device according to claim 3, wherein: It also includes a first lead-out structure (5) and a second lead-out structure (6), wherein the doping type of the first lead-out structure (5) and the second lead-out structure (6) is the same as the doping type of the well region (11); The first lead-out structure (5) is located in the first region, and the first lead-out structure (5) is connected to the back gate of the first tunneling transistor (1); The second lead-out structure (6) is located in the second region, and the second lead-out structure (6) is connected to the back gate of the second tunneling transistor (2).

5. The MTP device according to claim 4, wherein: The first lead-out structure (5) is located on one side of the first tunneling transistor (1) or the selection transistor (3), and is isolated from the first tunneling transistor (1) or the selection transistor (3) via a second shallow trench isolation structure (9).

6. The MTP device according to claim 4, wherein: The first lead-out structure (5) is connected to the first back end NW, the second lead-out structure (6) is connected to the second back end BG, the selection gate (31) of the selection transistor (3) is connected to the word line WL, the drain region D2 of the selection transistor (3) is connected to the bit line BL, and the source region S2 of the selection transistor (3) is connected to the source region S1 of the first tunneling transistor (1) and is also connected to the source end.

7. The MTP device according to claim 6, wherein: An electric field is applied between the control gate (42) and the first back end NW toward the control gate (42), so that electrons in the well region (11) below the first tunneling transistor (1) tunnel into the floating gate (41), thereby achieving programming; An electric field is applied between the floating gate (41) and the second back end BG toward the back gate of the second tunneling transistor (2), so that electrons stored in the floating gate (41) tunnel into the well region (11) below the second tunneling transistor (2), thereby achieving erasure.

8. The MTP device according to claim 1, wherein: The projection area of ​​the lower surface of the control gate (42) in the vertical direction is located within the projection area of ​​the upper surface of the floating gate (41) in the vertical direction.

9. The MTP device according to claim 1, wherein: A first sidewall structure (44) is formed on the side of the floating gate (41), and a second sidewall structure (32) is formed on the side of the selection gate (31) of the selection transistor (3).

10. An electronic device, characterized in that: The device comprises the MTP device according to any one of claims 1 to 9.

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