Super junction IGBT device and preparation method thereof

Abstract

The present invention relates to the field of semiconductor technology, and more specifically, to a superjunction IGBT device and a method for preparing the same. The superjunction IGBT device comprises: a collector layer, a buffer layer, a voltage-resistant layer, and a top composite structure arranged in sequence; the top composite structure comprises a top base layer and a gate structure, the top base layer having a groove, and the gate structure formed in the groove; wherein the voltage-resistant layer comprises a first voltage-resistant region and a second voltage-resistant region that are alternately distributed, and the second voltage-resistant region and the first voltage-resistant region form an interdigitated distribution. The second voltage-resistant region and the first voltage-resistant region in the superjunction IGBT device form an interdigitated distribution. During the device shutdown process, the second voltage-resistant region and the first voltage-resistant region in the interdigitated distribution can be utilized to effectively increase the resistance of the carrier extraction path, thereby reducing the current drop rate during the device shutdown phase, thereby suppressing the shutdown voltage spike and improving the problem of device failure due to overvoltage breakdown.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a super junction IGBT device and a method for preparing the same. Background Art

[0002] A super junction IGBT device is a new type of power semiconductor device that combines the super junction (SJ) structure and insulated gate bipolar transistor (IGBT) technology. It has N-column regions and P-column regions arranged alternately along the horizontal direction (i.e., a super junction structure).

[0003] When the super junction structure is subjected to reverse bias, a transverse electric field will be generated at the PN junction of the N column region and the P column region. During the device shutdown phase, the device is very likely to be broken down and fail. Summary of the Invention

[0004] The purpose of the present invention includes providing a super junction IGBT device and a preparation method thereof, wherein the second voltage-resistant region and the first voltage-resistant region in the super junction IGBT device prepared by the preparation method form a finger-shaped distribution. During the device shutdown process, the second voltage-resistant region and the first voltage-resistant region with a finger-shaped distribution can be utilized to effectively increase the resistance of the carrier extraction path, so as to reduce the current drop rate in the device shutdown stage, thereby suppressing the shutdown voltage spike and improving the problem of device failure due to overvoltage breakdown.

[0005] The embodiments of the present invention can be implemented as follows:

[0006] In a first aspect, the present invention provides a super junction IGBT device, comprising: a collector layer, a buffer layer, a voltage-resistant layer, and a top composite structure arranged in sequence;

[0007] The top composite structure includes a top base layer and a gate structure, wherein the top base layer has a groove and the gate structure is formed in the groove; wherein,

[0008] The voltage-resistant layer includes first voltage-resistant regions and second voltage-resistant regions that are alternately distributed, and the second voltage-resistant regions and the first voltage-resistant regions are distributed in an interdigitated manner.

[0009] In an optional embodiment, the first voltage-resistant region includes multiple first long fingers and multiple first short fingers, and the second voltage-resistant region includes multiple second long fingers and multiple second short fingers; along the first direction, the multiple second long fingers and the multiple second short fingers are arranged alternately in sequence, and the multiple first long fingers and the multiple first short fingers are arranged alternately in sequence; along the second direction, the multiple second long fingers are arranged in one-to-one correspondence with the multiple first short fingers, and the multiple second short fingers are arranged in one-to-one correspondence with the multiple first long fingers; wherein the first direction and the second direction are distributed at an angle, and the collector layer, the buffer layer, the voltage-resistant layer, and the top composite structure are arranged in sequence along the first direction.

[0010] In an optional embodiment, the trench extends into the second voltage-resistant region, and the bottom of the gate structure is wrapped by the second voltage-resistant region.

[0011] In an optional embodiment, the gate structure includes polysilicon and a gate oxide layer wrapped around the polysilicon.

[0012] In an optional embodiment, the gate structure further includes a gate conductor disposed on top of the polysilicon.

[0013] In an optional embodiment, the top base layer includes a carrier storage region, a second base region, and a first base region and a source region; wherein the carrier storage region and the second base region are successively arranged on the side of the voltage-resistant layer away from the buffer layer, the first base region and the source region are arranged on the side of the second base region away from the carrier storage region, and the source region is adjacent to the gate structure.

[0014] In an optional embodiment, the super junction IGBT device further includes an emitter conductor, wherein the emitter conductor covers the top of the source region and the first base region.

[0015] In an optional embodiment, the super junction IGBT device further includes a collector conductor, which is arranged on a side of the collector layer facing away from the buffer layer.

[0016] In a second aspect, the present invention provides a method for preparing a super junction IGBT device, which is used to prepare the super junction IGBT device of any of the aforementioned embodiments; the method for preparing the super junction IGBT device comprises:

[0017] forming a voltage-resistant layer on the substrate, wherein the voltage-resistant layer includes a first voltage-resistant region and a second voltage-resistant region, and the second voltage-resistant region and the first voltage-resistant region are arranged in an interdigitated shape;

[0018] forming an epitaxial layer on the voltage-resistant layer and forming a trench in the epitaxial layer;

[0019] forming a gate structure in the trench;

[0020] A top base layer is formed on the epitaxial layer.

[0021] In an optional embodiment, when forming the groove, the groove is extended into the second voltage-resistant region;

[0022] A gate oxide layer is formed in the trench, and then polysilicon is backfilled in the gate oxide layer.

[0023] The beneficial effects of the super junction IGBT device of the embodiment of the present invention include: the super junction IGBT device provided by the embodiment of the present invention has a second voltage-resistant region and a first voltage-resistant region distributed in a finger-like shape. During the process of device shutdown, the second voltage-resistant region and the first voltage-resistant region distributed in a finger-like shape can be utilized to effectively increase the resistance of the carrier extraction path, so as to reduce the current drop rate in the shutdown stage of the device, thereby suppressing the shutdown voltage spike and improving the problem of device failure due to overvoltage breakdown.

[0024] The beneficial effects of the preparation method of the super junction IGBT device of the embodiment of the present invention include: the preparation method provided by the embodiment of the present invention can be used to prepare a super junction IGBT device in which the second voltage-resistant region and the first voltage-resistant region are distributed in a finger-like manner, and since the second voltage-resistant region and the first voltage-resistant region are distributed in a finger-like manner, the device prepared by this method can utilize the second voltage-resistant region and the first voltage-resistant region distributed in a finger-like manner during the shutdown process to effectively increase the resistance of the carrier extraction path, so as to reduce the current drop rate in the shutdown stage of the device, thereby suppressing the shutdown voltage spike and improving the problem of device failure due to overvoltage breakdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 Schematic diagram of the structure of a super junction IGBT device in an embodiment of the present invention;

[0027] Figure 2 Schematic diagram of the structure of the substrate in an embodiment of the present invention;

[0028] Figure 3 Schematic diagram of forming a second short finger and a first long finger on a substrate in an embodiment of the present invention;

[0029] Figure 4 Schematic diagram of alternately forming first long fingers and first short fingers, and alternately forming second short fingers and second long fingers on a substrate in an embodiment of the present invention;

[0030] Figure 5 Schematic diagram of forming a first voltage-resistant region and a second voltage-resistant region in a substrate in an embodiment of the present invention;

[0031] Figure 6 Schematic diagram of forming an epitaxial layer on a voltage-resistant layer in an embodiment of the present invention;

[0032] Figure 7is a schematic diagram of forming a gate structure on an epitaxial layer according to an embodiment of the present invention;

[0033] Figure 8 Schematic diagram of forming a carrier storage region and a second base region in an epitaxial layer in an embodiment of the present invention;

[0034] Figure 9 Schematic diagram of forming a first base region and a source region on a second base region in an embodiment of the present invention;

[0035] Figure 10 is a schematic diagram of forming a gate conductor and an emitter conductor in an embodiment of the present invention;

[0036] Figure 11 Schematic diagram of substrate thinning in an embodiment of the present invention;

[0037] Figure 12 Schematic diagram of forming a buffer layer and a collector layer in an embodiment of the present invention.

[0038] Icon: 1-collector conductor; 2-gate conductor; 3-emitter conductor; 10-collector layer; 20-buffer layer; 30-first voltage-resistant region; 301-first long finger; 302-first short finger; 31-second voltage-resistant region; 311-second long finger; 312-second short finger; 32-carrier storage region; 40-source region; 41-first base region; 42-second base region; 5-gate structure; 50-gate oxide layer; 51-polysilicon; 100-substrate; 101-epitaxial layer; 200-super junction IGBT device. DETAILED DESCRIPTION

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0041] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0042] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0043] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0044] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0045] The super junction IGBT device provided in the related art has N column regions and P column regions alternately arranged in a lateral direction (ie, a super junction structure).

[0046] The inventors discovered that when a superjunction structure is subjected to reverse bias, a transverse electric field is generated at the PN junction between the N-pillar and P-pillar regions. Prior to breakdown, the entire N-pillar and P-pillar regions of the device are nearly completely depleted laterally. Consequently, during the device's shutdown phase, the alternating N-pillar and P-pillar regions rapidly deplete laterally. This leads to excessive carrier extraction within the device, resulting in a rapid drop in the device's shutdown current and an excessively large shutdown voltage spike, easily leading to overvoltage breakdown and device failure.

[0047] To address the aforementioned issues, this embodiment provides a novel super-junction IGBT device that reduces the rate at which the device's turn-off current decreases, thereby reducing the turn-off voltage spike and alleviating the problem of device failure due to overvoltage breakdown. The super-junction IGBT device of this embodiment is described in detail below with reference to the accompanying drawings.

[0048] Please refer to Figure 1 This embodiment provides a super junction IGBT device 200, which includes a collector layer 10, a buffer layer 20, a voltage-resistant layer, and a top composite structure arranged in sequence; the top composite structure includes a top base layer and a gate structure 5, the top base layer has a groove, and the gate structure 5 is formed in the groove; wherein, the voltage-resistant layer includes alternately distributed second voltage-resistant regions 31 and first voltage-resistant regions 30, and the second voltage-resistant regions 31 and the first voltage-resistant regions 30 are distributed in an interdigitated manner.

[0049] During the shutdown process of the super junction IGBT device 200, the second voltage-resistant region 31 and the first voltage-resistant region 30 distributed in a finger-like manner can be utilized to effectively increase the resistance of the carrier extraction path, so as to reduce the current drop rate in the device shutdown phase, thereby suppressing the shutdown voltage spike and improving the problem of device failure due to overvoltage breakdown.

[0050] Furthermore, the second voltage-resistant region 31 and the first voltage-resistant region 30 are of the first conductive type and the second conductive type, respectively, that is, the second voltage-resistant region 31 is of the first conductive type, and the first voltage-resistant region 30 is of the second conductive type; wherein the first conductive type can refer to one of the N-type and the P-type, and the second conductive type can refer to the other of the N-type and the P-type.

[0051] The second pressure-resistant area 31 and the first pressure-resistant area 30 form an interdigitated distribution, which may mean that: the second pressure-resistant area 31 and the first pressure-resistant area 30 both have a structure showing an alternating distribution of long and short fingers; wherein the second pressure-resistant area 31 includes a plurality of second long fingers 311 and a plurality of second short fingers 312, and the first pressure-resistant area 30 includes a plurality of first long fingers 301 and a plurality of first short fingers 302; along the first direction a, the plurality of second long fingers 311 and the plurality of second short fingers 312 are alternately arranged in sequence, and the plurality of first long fingers 301 and the plurality of first short fingers 302 are alternately arranged in sequence; along the second In direction b, multiple second long fingers 311 are arranged in one-to-one correspondence with multiple first short fingers 302, and multiple second short fingers 312 are arranged in one-to-one correspondence with multiple first long fingers 301; the length of the second long finger 311 along the second direction b is greater than the length of the second short finger 312 along the second direction b, and the length of the first long finger 301 along the second direction b is greater than the length of the first short finger 302 along the second direction b; wherein, the first direction a and the second direction b are distributed at an angle, and the collector layer 10, the buffer layer 20, the voltage-resistant layer, and the top composite structure are arranged in sequence along the first direction a.

[0052] Since the length of the first short finger 302 is smaller than the length of the first long finger 301, and the length of the second short finger 312 is smaller than the length of the second long finger 311, the width (i.e., area) of at least part of the first voltage-resistant region 30 and the second voltage-resistant region 31 is reduced, that is, the width of at least the first short finger 302 and the second short finger 312 is reduced; therefore, the corresponding resistance at least at the first short finger 302 and the second short finger 312 is increased; when the device is turned off, a larger resistance can be used to effectively slow down the speed of carrier extraction and reduce the current drop rate in the device shutdown phase, thereby suppressing the shutdown voltage spike and improving the problem of device failure due to overvoltage breakdown.

[0053] Optionally, the first direction a is perpendicular to the second direction b. Of course, in other embodiments, the first direction a and the second direction b may have a certain angle therebetween, for example, 0.5°, 1°, etc., which is not specifically limited here.

[0054] Optionally, the pressure-resistant layer includes multiple first pressure-resistant areas 30 and multiple second pressure-resistant areas 31; wherein, the two ends of the second long finger 311 of the second pressure-resistant area 31 extend relative to the second short finger 312, the two ends of the first long finger 301 of a part of the first pressure-resistant area 30 extend relative to the first short finger 302, and one end of the first long finger 301 of another part of the first pressure-resistant area 30 extends relative to the first short finger 302, and the other end of the corresponding first long finger 301 is flush with the first short finger 302.

[0055] Of course, in other embodiments, both ends of the second long finger 311 of a part of the second pressure-resistant zone 31 extend relative to the second short finger 312, and one end of the second long finger 311 of another part of the second pressure-resistant zone 31 extends relative to the second short finger 312, and the other end of the corresponding second long finger 311 is flush with the second short finger 312.

[0056] The number of second long fingers 311 and second short fingers 312 of the second pressure-resistant zone 31 can be selected as needed; in this embodiment, the second pressure-resistant zone 31 includes 5 second long fingers 311 and 6 second short fingers 312. Along the first direction, both ends of the second pressure-resistant zone 31 are second short fingers 312, and one of them is set in the buffer layer 20, and the other is used to set the top base layer.

[0057] Of course, in other embodiments, the number of the second long fingers 311 can also be 1, 2, 3, 4, 6, etc., and accordingly, the number of the second short fingers 312 can be one more or one less than the second long fingers 311.

[0058] Similarly, the number of first long fingers 301 and first short fingers 302 of the first pressure-resistant zone 30 can be selected as needed; in this embodiment, the first pressure-resistant zone 30 includes 6 first long fingers 301 and 5 first short fingers 302. Along the first direction, both ends of the first pressure-resistant zone 30 are first long fingers 301, and one of them is set in the buffer layer 20, and the other is used to set the top base layer.

[0059] Of course, in other embodiments, the number of the first long fingers 301 may also be 1, 2, 3, 4, 6, etc., and correspondingly, the number of the first short fingers 302 may be one more or one less than the second long fingers 311 .

[0060] The inventors further discovered that during the shutdown process of the superjunction IGBT device 200 , the electric field at the bottom of the trench of the top base layer is relatively high, which can easily lead to breakdown of the gate structure 5 at the bottom of the trench and cause device failure.

[0061] To improve the above problems, please refer to Figure 1In this embodiment, the trench is extended into the second voltage-sustaining region 31, and the bottom of the gate structure 5 is wrapped by the second voltage-sustaining region 31. This can reduce the electric field at the bottom of the trench, improve the problem of gate structure 5 being broken down by high electric fields, and improve device reliability.

[0062] The depth of the groove can be set as needed. In this embodiment, the groove extends into the second short finger 312 connected to the top base layer, and does not extend into the second long finger 311 connected to the second short finger 312.

[0063] Of course, in other embodiments, the groove extends into the second short finger 312 connected to the top base layer, and further extends into the second long finger 311 connected to the second short finger 312 .

[0064] The gate structure 5 of this embodiment includes polysilicon 51 and a gate oxide layer 50 surrounding the polysilicon 51. The bottom of the polysilicon 51 and the bottom of the gate oxide layer 50 are both located at the bottom of the trench extending into the second voltage-sustaining region 31. This effectively reduces the problem of device failure caused by gate oxide breakdown when the device is turned off.

[0065] Of course, in other embodiments, only the bottom of the gate oxide layer 50 may be disposed at the bottom of the trench extending into the second voltage-sustaining region 31 .

[0066] The gate structure 5 of this embodiment further includes a gate conductor 2 disposed on top of the polysilicon 51 .

[0067] Furthermore, the top base layer includes a carrier storage region 32, a second base region 42, and a first base region 41 and a source region 40; wherein, the carrier storage region 32 and the second base region 42 are sequentially arranged on the side of the voltage-resistant layer away from the buffer layer 20, and the carrier storage region 32 covers the second voltage-resistant region 31 and the first voltage-resistant region 30; the first base region 41 and the source region 40 are arranged on the side of the second base region 42 away from the carrier storage region 32, and the source region 40 is adjacent to the gate structure 5.

[0068] Furthermore, the super junction IGBT device 200 further includes an emitter conductor 3 and a collector conductor 1 . The emitter conductor 3 covers the top of the source region 40 and the first base region 41 . The collector conductor 1 is arranged on a side of the collector layer 10 away from the buffer layer 20 .

[0069] Optionally, the buffer region, the polysilicon 51 , the carrier storage region 32 and the source region 40 are all of the first conductivity type; the collector layer 10 , the first base region 41 and the second base region 42 are all of the second conductivity type.

[0070] This embodiment further provides a method for manufacturing the super junction IGBT device 200, which includes:

[0071] A voltage-resistant layer is formed on the substrate 100, wherein the voltage-resistant layer includes a second voltage-resistant region 31 and a first voltage-resistant region 30, and the second voltage-resistant region 31 and the first voltage-resistant region 30 are arranged in an interdigitated shape;

[0072] forming an epitaxial layer 101 on the voltage-resistant layer, and forming a trench in the epitaxial layer 101;

[0073] forming a gate structure 5 in the trench;

[0074] A top base layer is formed on the epitaxial layer 101 .

[0075] This preparation method can be used to prepare a super junction IGBT device 200 in which the second voltage-resistant region 31 and the first voltage-resistant region 30 are distributed in a finger-like manner. Since the second voltage-resistant region 31 and the first voltage-resistant region 30 are distributed in a finger-like manner, the device prepared by this method can utilize the second voltage-resistant region 31 and the first voltage-resistant region 30 distributed in a finger-like manner during the shutdown process to effectively increase the resistance of the carrier extraction path, thereby reducing the current drop rate in the shutdown phase of the device, thereby suppressing the shutdown voltage spike and improving the problem of device failure due to overvoltage breakdown.

[0076] Alternatively, see Figure 2 、 Figure 3 、 Figure 4 and Figure 5 The method for forming a voltage-resistant layer includes: alternately forming second short fingers 312 and second long fingers 311 along a first direction on a substrate 100; while forming the second short fingers 312, forming first long fingers 301 disposed opposite to the second short fingers 312 along a second direction; and while forming the second long fingers 311, forming first short fingers 302 disposed opposite to the second long fingers 311 along the second direction. In this way, an interdigitated structure with interlaced long and short fingers can be efficiently formed.

[0077] Alternatively, see Figure 6 and Figure 7 When forming a trench in the epitaxial layer, the trench is extended into the second voltage-sustaining region 31; a gate oxide layer 50 is formed in the trench, and polysilicon 51 is backfilled into the gate oxide layer 50 to form the gate structure 5. This allows the bottom of the trench and the bottom of the gate structure 5 to be surrounded by the second voltage-sustaining region 31, thereby reducing the electric field at the bottom of the trench and improving the problem of gate oxide breakdown failure when the device is turned off.

[0078] Alternatively, see Figure 8 and Figure 9 The preparation method of the top base layer includes: forming a carrier storage region 32 and a second base region 42 in sequence at a position where no trench is set in the epitaxial layer 101, and then forming a first base region 41 and a source region 40 distributed side by side in the second base region 42, and making the source region 40 adjacent to the gate structure 5.

[0079] Alternatively, see Figure 10 The method for preparing the super junction IGBT device 200 further includes, after forming the top base layer, preparing a groove in the portion of the gate oxide layer 50 exposed from the top of the trench, and then preparing a gate conductor 2 at the groove, and making the gate conductor 2 contact the top of the polysilicon 51.

[0080] Alternatively, see Figure 10 The method for preparing the super junction IGBT device 200 further includes forming an emitter conductor 3 on top of the first base region 41 and the source region 40 after forming the top base layer.

[0081] Alternatively, see Figure 11 and Figure 12 The method for preparing the super junction IGBT device 200 also includes: thinning the side of the substrate 100 away from the voltage-resistant layer, and sequentially arranging a buffer layer 20 and a collector layer 10 on the side of the substrate 100 away from the voltage-resistant layer, and arranging a collector conductor 1 on the collector layer 10.

[0082] To sum up, the second voltage-resistant region 31 and the first voltage-resistant region 30 in the super junction IGBT device 200 of the present invention form a finger-shaped distribution. During the device shutdown process, the second voltage-resistant region 31 and the first voltage-resistant region 30 in the finger-shaped distribution can be utilized to effectively increase the resistance of the carrier extraction path, so as to reduce the current drop rate in the device shutdown phase, thereby suppressing the shutdown voltage spike and improving the problem of device failure due to overvoltage breakdown.

[0083] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. A super junction IGBT device, characterized in that: include: A current collecting layer (10), a buffer layer (20), a voltage-resistant layer, and a top composite structure are sequentially arranged; The top composite structure comprises a top base layer and a gate structure (5), the top base layer has a groove, and the gate structure (5) is formed in the groove; wherein, The pressure-resistant layer comprises first pressure-resistant regions (30) and second pressure-resistant regions (31) that are alternately distributed, and the second pressure-resistant regions (31) and the first pressure-resistant regions (30) form an interdigitated distribution; The first voltage-resistant region (30) includes a plurality of first long fingers (301) and a plurality of first short fingers (302), and the second voltage-resistant region (31) includes a plurality of second long fingers (311) and a plurality of second short fingers (312); along the first direction, the plurality of second long fingers (311) and the plurality of second short fingers (312) are arranged alternately in sequence, and the plurality of first long fingers (301) and the plurality of first short fingers (302) are arranged alternately in sequence; along the second direction, the plurality of second long fingers (311) and the plurality of first short fingers (302) are arranged in a one-to-one correspondence, and the plurality of second short fingers (312) and the plurality of first long fingers (301) are arranged in a one-to-one correspondence; wherein the first direction and the second direction are distributed at an angle, and the collector layer (10), the buffer layer (20), the voltage-resistant layer, and the top composite structure are arranged in sequence along the first direction; Wherein, along the first direction, both ends of the second voltage-resistant area (31) are the second short fingers (312), one of which is provided on the buffer layer (20), and the other is used to provide the top base layer; Along the first direction, both ends of the first pressure-resistant area (30) are the first long fingers (301), one of which is provided on the buffer layer (20), and the other is used to provide the top base layer; The top base layer includes a carrier storage region (32), a second base region (42), a first base region (41) and a source region (40); wherein the carrier storage region (32) and the second base region (42) are sequentially arranged on a side of the voltage-resistant layer away from the buffer layer (20), the first base region (41) and the source region (40) are arranged on a side of the second base region (42) away from the carrier storage region (32), and the source region (40) is adjacent to the gate structure (5).

2. The super junction IGBT device according to claim 1, wherein: The trench extends into the second voltage-resistant region (31), and the bottom of the gate structure (5) is wrapped by the second voltage-resistant region (31).

3. The super junction IGBT device according to claim 2, characterized in that: The gate structure (5) comprises polysilicon (51) and a gate oxide layer (50) wrapped around the outside of the polysilicon (51).

4. The super junction IGBT device according to claim 3, characterized in that: The gate structure (5) further comprises a gate conductor (2) arranged on top of the polysilicon (51).

5. The super junction IGBT device according to claim 4, characterized in that: The super junction IGBT device further comprises an emitter conductor (3), wherein the emitter conductor (3) covers the top of the source region (40) and the first base region (41).

6. The super junction IGBT device according to claim 1, wherein: The super junction IGBT device further comprises a collector conductor (1), wherein the collector conductor (1) is arranged on a side of the collector layer (10) facing away from the buffer layer (20).

7. A method for preparing a super junction IGBT device, characterized in that: The method for preparing the super junction IGBT device is used to prepare the super junction IGBT device according to any one of claims 1 to 6; the method for preparing the super junction IGBT device comprises: A voltage-resistant layer is formed on a substrate (100), wherein the voltage-resistant layer comprises a first voltage-resistant region (30) and a second voltage-resistant region (31), and the second voltage-resistant region (31) and the first voltage-resistant region (30) are arranged in an interdigitated distribution; forming an epitaxial layer (101) on the voltage-resistant layer, and forming a groove in the epitaxial layer (101); forming a gate structure (5) in the trench; A top base layer is formed on the epitaxial layer (101).

8. The method for preparing a super junction IGBT device according to claim 7, wherein: When forming the groove, extending the groove into the second voltage-resistant area (31); A gate oxide layer (50) is formed in the trench, and polysilicon (51) is backfilled in the gate oxide layer (50).

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