Transistor structure, semiconductor device and forming method thereof

Abstract

Some embodiments described include a transistor structure, a semiconductor device, and methods of forming the same. The semiconductor device includes a transistor structure. A transistor structure (tunneling fin field effect transistor structure) includes different combinations of doped semiconductor regions forming a source region, a drain region, and a channel region of the transistor structure. Different combinations of the doped semiconductor regions include different types of dopants, different concentrations of dopants, and / or dopant gradients that vary differences in bandgap levels across one or more junction regions of the transistor structure to increase threshold voltage and / or reduce leakage in the transistor structure.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a transistor structure, a semiconductor device, and a method of forming a semiconductor device. Background Art

[0002] Fin-based transistors (such as fin field effect transistors (finFETs) and nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors)) are three-dimensional structures that include a channel region that extends above a semiconductor substrate as a three-dimensional structure within a fin (or a portion thereof). A gate structure for controlling the flow of charge carriers within the channel region surrounds the fin of semiconductor material. As an example, in a finFET, the gate structure surrounds three sides of the fin (and thus surrounds the channel region), enabling enhanced control of the channel region (and thus enabling switching of the finFET). Source and drain regions (e.g., epitaxial regions) are located on opposite sides of the gate structure and / or the channel region. Summary of the Invention

[0003] Some embodiments of the present disclosure provide a transistor structure. The transistor structure includes a conductive core that includes a conductive material. The transistor structure includes a first dielectric sidewall of a first dielectric material along a first side of the conductive core. The transistor structure includes a second dielectric sidewall of a second dielectric material along a second opposite side of the conductive core, wherein the second dielectric material is different from the first dielectric material. The transistor structure includes a fin-shaped intrinsic semiconductor region having an interface region that is connected to and located beneath the first and second dielectric sidewalls. The transistor structure includes a first doped semiconductor region that includes a first dopant along a first side of the fin-shaped intrinsic semiconductor region, the first side of the fin-shaped intrinsic semiconductor region being adjacent to the first dielectric sidewall. The transistor structure includes a second doped semiconductor region that includes a second dopant along a second opposite side of the fin-shaped intrinsic semiconductor region, the second opposite side of the fin-shaped intrinsic semiconductor region being adjacent to the second dielectric sidewall, wherein the dopant type of the second dopant is different from the dopant type of the first dopant.

[0004] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a tunnel fin-based transistor, and the tunnel fin-based transistor includes a gate structure, a source region, a drain region, and a channel region. The source region is located below the gate structure and adjacent to a first side of the gate structure. The drain region is located below the gate structure and adjacent to a second opposite side of the gate structure. The channel region is located between the source region and the drain region. The channel region includes a first portion having a first thickness near the source region and a second portion having a second thickness near the drain region, where the second thickness is different from the first thickness.

[0005] Some embodiments of the present disclosure provide a method of forming a semiconductor device. The method of forming a semiconductor device includes forming a dummy gate structure on and above a fin structure, where the dummy gate structure includes a gate electrode layer surrounded by multiple sidewalls, and the multiple sidewalls include a first dielectric layer on the gate electrode layer. The method of forming a semiconductor device includes forming a source region including a first doped semiconductor region having a p-type dopant in the fin structure below the dummy gate structure and adjacent to a first side of the dummy gate structure. The method of forming a semiconductor device includes forming a drain region including a second doped semiconductor region having a first n-type dopant below the dummy gate structure and adjacent to a second opposite side of the dummy gate structure. The method of forming a semiconductor device includes removing the gate electrode layer. The method of forming a semiconductor device includes removing a portion of the first dielectric layer to expose a portion of the fin structure adjacent to the source region and a second dielectric layer of the multiple sidewalls. The method of forming a semiconductor device includes forming a pocket region including a third doped semiconductor region having a second n-type dopant in the portion of the fin structure adjacent to the source region. The method includes forming a third dielectric layer above the pocket region and along the second dielectric layer. The method of forming a semiconductor device includes forming a gate structure between the third dielectric layer and the remaining portion of the first dielectric layer, where forming the gate structure includes forming one or more layers of a conductive material between the third dielectric layer and the remaining portion of the first dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of some embodiments of the present disclosure may be best understood when read in conjunction with the following detailed description with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figure 1 is a diagram of an example environment in which the systems and / or methods described in some embodiments of the present disclosure may be implemented;

[0008] Figure 2A and Figure 2B is a diagram related to a semiconductor device including a transistor structure described in some embodiments of the present disclosure;

[0009] Figure 3A , Figure 3B , Figure 4A , Figure 4B , FIG. 5A to FIG. 5C , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , FIG. 8A to FIG. 8C and Fig. 9 is a diagram of one or more embodiments described in some embodiments of the present disclosure;

[0010] FIG. 10A to FIG. 10I , FIG. 11A to FIG. 11C and FIG. 12A to FIG. 12C is a series of diagrams illustrating examples of semiconductor manufacturing operations for forming one or more portions of a semiconductor device including a transistor structure described in some embodiments of the present disclosure;

[0011] Fig.13 is a graph of example performance data of transistor structures described in some embodiments of the present disclosure;

[0012] Fig.14 is described in some embodiments of the present disclosure Figure 1 diagrams of example elements of one or more devices;

[0013] Fig.15 is a flow chart of an example process associated with forming the semiconductor devices described in some embodiments of the present disclosure.

[0014]

Explanation of symbols

[0015] 100: Instance environment

[0016] 102, 104, 106, 108, 110, 112, 114: Tools

[0017] 116: Wafer / die transport tool

[0018] 200:Semiconductor devices

[0019] 202: Installation area

[0020] 204:Substrate

[0021] 206: Fin-shaped structure

[0022] 208:STI Zone

[0023] 210: dummy gate structure

[0024] 212: Gate electrode layer

[0025] 214: Hard Mask Layer

[0026] 216: Overlay

[0027] 218: Source region

[0028] 220: Drain region

[0029] 222: TFET structure

[0030] 224: Gate structure

[0031] 226: Channel region

[0032] 300, 400, 500, 600, 700, 800, 900: Embodiments

[0033] 302, 304, 402, 404, 406, 408, 410, 702, 902: Doped semiconductor regions

[0034] 306: Conductive core

[0035] 308, 310: Conductive layers

[0036] 312, 314, 320: Dielectric layers

[0037] 316: Interface region

[0038] 318: Sidewall spacer layer

[0039] 322: Overlap region

[0040] 324: Underlap region

[0041] 802, 804, 806, 808: Portions

[0042] 1000, 1100, 1200: Semiconductor manufacturing operations

[0043] 1002, 1008, 1010, 1102: Cavities

[0044] 1004, 1006, 1012, 1202: Masks

[0045] 1300: Performance data

[0046] 1302: Bandgap energy level

[0047] 1304: Location

[0048] 1308, 1310: Differences

[0049] 1312, 1314: Regions

[0050] 1400: Device

[0051] 1410: Bus

[0052] 1420: Processor

[0053] 1430: Memory

[0054] 1440: Input component

[0055] 1450: Output component

[0056] 1460: Communication component

[0057] 1500: Process

[0058] 1510, 1520, 1530, 1540, 1550, 1560, 1570, 1580: Blocks

[0059] A - A, B - B, C - C, D - D: References

[0060] D1, D2, D3, D4, D6: Widths

[0061] D5: Distance

[0062] D7, D8: Thicknesses Detailed implementation manners

[0063] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify some embodiments of this disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, some embodiments of this disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0064] In addition, for ease of description, in some embodiments of this disclosure, spatial relative terms such as "under", "below", "lower", "above", "upper" and the like may be used to describe the relationship between one component or feature and another component or feature as illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used in some embodiments of this disclosure may be interpreted accordingly.

[0065] The types of finFET structures include metal oxide semiconductor finFET (MOSFET) structures and tunneling finFET (TFET) structures. Through the quantum mechanical tunneling that relies on charge carriers passing through the junction region between the source region and the channel region, the TFET structure can have lower power consumption than the MOSFET structure. In addition, the subthreshold slope (SS) of the TFET can increase relative to the MOSFET to provide better control of the current and reduced leakage.

[0066] In some cases, the width of the channel region of the TFET structure is consistent between the source region and the drain region of the TFET structure. Additionally or alternatively, the dopant profile of the source region and / or the drain region can be symmetric (e.g., the same type of dopant) and / or uniform (e.g., consistent in terms of dopant concentration). In such cases, the difference in the bandgap energy levels on one or more junction regions of the TFET structure can form an energy barrier that charge carriers cannot overcome to flow through the channel region without increasing the voltage applied to the gate of the TFET structure (e.g., the threshold voltage). Increasing the voltage may not meet the threshold corresponding to the available supply voltage in the semiconductor device that includes the TFET structure.

[0067] Some embodiments of the present disclosure include a semiconductor device and a manufacturing method that includes the TFET structure. The TFET structure includes different combinations of doped semiconductor regions that form the source region, the drain region, and the channel region of the TFET. The different combinations of doped semiconductor regions include different types of dopants, different concentrations of dopants, and / or dopant gradients that change the difference in the bandgap energy levels on one or more junction regions of the TFET structure.

[0068] In this way, the performance of the TFET structure is improved, making the TFET structure compatible with the available power supply. In addition, leakage within the TFET structure can be reduced to improve the quality and / or reliability of the TFET structure.

[0069] Figure 1 is a diagram of an example environment 100 in which the systems and / or methods described in some embodiments of the present disclosure can be implemented. As Figure 1As shown, the example environment 100 may include multiple semiconductor processing tools 102-114 and a wafer / die transfer tool 116. The multiple semiconductor processing tools 102-114 may include a deposition tool 102, an exposure tool 104, a developer tool 106, an etch tool 108, a planarization tool 110, an electroplating tool 112, an ion implantation tool 114, and / or another type of semiconductor processing tool. The tools included in the example environment 100 may be included in a semiconductor cleanroom, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility, and other examples.

[0070] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer over and / or on a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the deposition tool 102 includes an epitaxial tool for forming layers and / or regions of a device by epitaxial growth. In some embodiments, the example environment 100 includes multiple types of deposition tools 102.

[0071] The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source such as an ultraviolet (UV) light source (e.g., a deep UV light source, an extreme UV (EUV) light source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include a pattern for forming one or more structures of a semiconductor device, can include a pattern for etching various parts of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or an exposure tool of a similar type.

[0072] The developer tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop the pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by dissolving the exposed or unexposed portions of the photoresist layer via the use of a chemical developer.

[0073] The etch tool 108 is a semiconductor processing tool capable of etching various types of substrates, wafers, or semiconductor device materials. For example, the etch tool 108 can include a wet etch tool, a dry etch tool, and / or the like. In some embodiments, the etch tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etch tool 108 can use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which can involve using an ionized gas to etch one or more portions isotropically or directionally.

[0074] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool for polishing or planarizing a layer or surface of a deposited or electroplated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free polishing) to polish or planarize the surface of the semiconductor device. The planarization tool 110 may utilize a polishing pad and a retainer ring (e.g., typically having a diameter larger than that of the semiconductor device) with a polishing and corrosive chemical slurry. The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by the retainer ring. The dynamic polishing head may rotate about different axes of rotation to remove material and flatten any irregular topography of the semiconductor device, thereby smoothing or planarizing the semiconductor device.

[0075] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or the like.

[0076] The ion implantation tool 114 is a semiconductor processing tool for implanting ions into a substrate such as a semiconductor wafer. The ion implantation tool 114 generates ions from a source material (such as a gas or a solid) in an arc chamber. The source material is provided into the arc chamber, and an arc voltage discharges between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes are used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam may be directed toward the substrate such that the ions are implanted beneath the surface of the substrate to dope the substrate.

[0077] The wafer / die transfer tool 116 includes a mobile robot, a robotic arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated material handling system (AMHS), and / or another type of device for transferring substrates and / or semiconductor devices between the semiconductor processing tools 102-114, for transferring substrates and / or semiconductor devices between processing chambers of the same semiconductor processing tool, and / or for transferring substrates and / or semiconductor devices to other locations (such as wafer racks, storage rooms, and / or the like) and transferring substrates and / or semiconductor devices from other locations. In some embodiments, the wafer / die transfer tool 116 can be a programmed device for traveling a specific path and / or can operate semi-autonomously or autonomously. In some embodiments, the example environment 100 includes multiple wafer / die transfer tools 116.

[0078] For example, the wafer / die transfer tool 116 can be included in a cluster tool or another type of tool (which includes multiple processing chambers) and can be used to transfer substrates and / or semiconductor devices between multiple processing chambers; transfer substrates and / or semiconductor devices between a processing chamber and a buffer region; transfer substrates and / or semiconductor devices between a processing chamber and an interface tool (such as an equipment front end module (EFEM)); and / or transfer substrates and / or semiconductor devices between a processing chamber and a transfer carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some embodiments, the wafer / die transfer tool 116 can be included in a multi-chamber (or cluster) deposition tool 102, which can include a pre-cleaning processing chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or by-products from substrates and / or semiconductor devices) and multiple types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations). In these embodiments, as described in some embodiments of the present disclosure, the wafer / die transfer tool 116 is used to transfer substrates and / or semiconductor devices between the processing chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partial vacuum) between the processing operations in the processing chambers and / or in the deposition tool 102.

[0079] In some embodiments and as combined with Figures 3A to 15As described in more detail elsewhere in some embodiments of the present disclosure, a series of semiconductor manufacturing operations are performed by a plurality of semiconductor processing tools 102-114 and / or a wafer / die transfer tool 116. The series of semiconductor manufacturing operations includes forming a dummy gate structure on and above a fin structure, wherein the dummy gate structure includes a gate electrode layer surrounded by a plurality of sidewalls, and the plurality of sidewalls includes a first dielectric layer on the gate electrode layer. The series of semiconductor manufacturing operations includes forming a source region including a first doped semiconductor region having a p-type dopant in the fin structure below the dummy gate structure and adjacent to a first side of the dummy gate structure. The series of semiconductor manufacturing operations includes forming a drain region including a second doped semiconductor region having a first n-type dopant below the dummy gate structure and adjacent to a second opposite side of the dummy gate structure. The series of semiconductor manufacturing operations includes removing the gate electrode layer. The series of semiconductor manufacturing operations includes removing a portion of the first dielectric layer to expose a portion of the fin structure adjacent to the source region and a second dielectric layer of the plurality of sidewalls. The series of semiconductor manufacturing operations includes forming a pocket region including a third doped semiconductor region having a second n-type dopant in the portion of the fin structure adjacent to the source region. The series of semiconductor manufacturing operations includes forming a third dielectric layer above the pocket region and along the second dielectric layer. The series of semiconductor manufacturing operations includes forming a gate structure between the third dielectric layer and the remaining portion of the first dielectric layer, wherein forming the gate structure includes forming one or more layers of a conductive material between the third dielectric layer and the remaining portion of the first dielectric layer.

[0080] Figure 1 The number and configuration of devices shown in are provided as one or more examples. In practice, there may be more devices, fewer devices, different devices, or devices configured differently than those shown in Figure 1 In addition, Figure 1 Two or more of the devices shown in may be implemented within a single device, or Figure 1 A single device shown in may be implemented as multiple distributed devices. Additionally or alternatively, a set of devices (e.g., one or more devices) of the example environment 100 may perform one or more functions described as being performed by another set of devices of the example environment 100.

[0081] Figure 2A And Figure 2B Are diagrams related to semiconductor devices including transistor structures described in some embodiments of the present disclosure. Specifically, Figure 2A And Figure 2BIllustrate an example device region 202 of the semiconductor device 200 that includes one or more transistors or other devices. The transistors may include fin-based transistors such as fin field effect transistors (finFETs), nanostructure transistors, and / or other types of transistors. In some embodiments, the device region 202 includes a p-type metal oxide semiconductor (PMOS) region, an n-type metal oxide semiconductor (NMOS) region, a complementary metal oxide semiconductor (CMOS) region, and / or another type of device region. FIG. 3A to FIG. 12C Includes Figure 2A And Figure 2B A schematic cross-sectional view of each part of the device region 202 of the semiconductor device 200 illustrated in, and corresponding to, various processing stages of forming a fin-based transistor in the device region 202 of the semiconductor device 200.

[0082] As Figure 2A Shown in the isometric view of, the semiconductor device 200 includes a substrate 204. The substrate 204 includes a silicon (Si) substrate, a substrate formed of a silicon-containing material, a Group III-V compound semiconductor material substrate (such as gallium arsenide (GaAs)), a silicon on insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, or another type of semiconductor substrate. The substrate 204 may include a circular / round substrate having a diameter of about 200 mm, a diameter of about 300 mm, or another diameter (such as 450 mm) and other examples. Alternatively, the substrate 204 may be any polygon, square, rectangle, curved, or otherwise non-circular workpiece, such as a polygonal substrate.

[0083] The fin structure 206 is included above (and / or extends above) the substrate 204 of the device region 202. The fin structure 206 can provide an active region for forming one or more devices (e.g., fin-based transistors). In some embodiments, the fin structure 206 comprises a silicon (Si) material or another elemental semiconductor material, such as germanium (Ge). In some embodiments, the fin structure 206 comprises an alloy semiconductor material, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or a combination thereof. In some embodiments, the channel region is part of and / or adjacent to the fin structure 206.

[0084] The fin structure 206 is fabricated by suitable semiconductor processing techniques, such as masking, lithography, and / or etching processes, among other examples. As an example, the fin structure 206 can be formed by etching away a portion of the substrate 204 to form a recess in the substrate 204. The recess can then be filled with recessed or etched isolation material to form a shallow trench isolation (STI) region 208 between the substrate 204 and above the fin structure 206. Other fabrication techniques can be used for the STI region 208 and / or the fin structure 206. The STI region 208 can electrically isolate adjacent active regions in the fin structure 206. The STI region 208 can comprise a dielectric material, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. The STI region 208 can comprise, for example, a multi-layer structure having one or more liner layers.

[0085] A dummy gate structure 210 (or multiple dummy gate structures 210) is included in the device region 202 above the fin structure 206 (e.g., substantially perpendicular to the fin structure 206). The dummy gate structure 210 engages the fin structure 206 on three or more sides of the fin structure 206. In Figure 2A the depicted example, the dummy gate structure 210 comprises a gate electrode layer 212, a hard mask layer 214, and / or a capping layer 216, among other examples. In some embodiments, the dummy gate structure 210 further comprises a gate dielectric layer, one or more spacer layers, and / or another suitable layer. The respective layers of the dummy gate structure 210 can be formed by suitable deposition techniques and patterned by suitable lithography and etching techniques.

[0086] As described herein, the term "dummy" refers to a sacrificial structure that will be removed in a subsequent stage and replaced by another structure (such as a high-k dielectric and a metal gate structure) in a replacement gate process. The replacement gate process refers to fabricating a gate structure in a subsequent stage of the overall gate fabrication process. Thus, Figure 2A the configuration of the semiconductor device 200 illustrated in may include an intermediate configuration, and additional semiconductor processing operations may be performed on the semiconductor device 200 to further process the semiconductor device 200.

[0087] The gate electrode layer 212 may include polysilicon (PO) material or another suitable material. The gate electrode layer 212 may be formed by a suitable deposition process (such as LPCVD or PECVD and other examples). The hard mask layer 214 may include any material suitable for patterning the gate electrode layer 212 on the substrate 204 with specific features / sizes, such as silicon nitride (Si x N y ) and other examples. The capping layer 216 may include a dielectric oxide layer. The dielectric oxide layer may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods.

[0088] In some embodiments, the respective layers of the dummy gate structure 210 are first deposited as blanket layers. Then, the blanket layers are patterned via a process including lithography and etching processes to remove portions of the blanket layers and retain the remaining portions above the STI regions 208 and the fin structures 206 to form the dummy gate structure 210.

[0089] The source region 218 and the drain region 220 are disposed in opposite regions of the fin structure 206 relative to the dummy gate structure 210. The source region 218 and / or the drain region 220 are semiconductor regions in which impurities (e.g., dopants) are introduced into a semiconductor material (e.g., silicon or III-V material) to change the conductivity, charge carrier concentration, and / or electron behavior of the semiconductor region.

[0090] In some embodiments, the dopant includes a p-type dopant, and the aforementioned p-type dopant generates a large number of positive charge holes within the lattice of the semiconductor region (e.g., in other words, this region is a hole-rich semiconductor region). Examples of p-type dopants include group III chemical elements such as boron (B), gallium (Ga), and / or aluminum (Al). Additionally, the concentration of the p-type dopant may be selected based on the desired conductivity, charge carrier concentration, and / or electron behavior of the semiconductor region. As an example, the selected concentration of the p-type dopant in a heavily doped semiconductor region (e.g., a P+ semiconductor region) may be on the order of about 1×10 18 atoms per cubic centimeter (atoms / cm 3) to about 1×10 20 atoms / cm 3 In addition or alternatively, the selected concentration of p-type dopants in a moderately doped semiconductor region (e.g., a P semiconductor region) can be in the range of about 1×10 16 atoms per cubic centimeter (atoms / cm 3 ) to about 1×10 18 atoms / cm 3 In addition or alternatively, the selected concentration of p-type dopants in a lightly doped semiconductor region (e.g., a P- semiconductor region) can be in the range of about 1×10 14 atoms per cubic centimeter (atoms / cm 3 ) to about 1×10 16 atoms / cm 3 However, other chemical elements and / or concentration ranges associated with p-type dopants are also within the scope of some embodiments of the present disclosure.

[0091] In some embodiments, the dopant includes an n-type dopant that generates a large number of electrons within the lattice of a semiconductor region (e.g., in other words, this region is an electron-rich semiconductor region). Examples of n-type dopants include Group V chemical elements such as phosphorus (P), arsenic (As), and / or antimony (Sb). In addition, the concentration of the n-type dopant can be selected based on the desired conductivity, charge carrier concentration, and / or electron behavior of the semiconductor region. As an example, the selected concentration of the n-type dopant in a heavily doped semiconductor region (e.g., an N+ semiconductor region) can be in the range of about 1×10 18 atoms per cubic centimeter (atoms / cm 3 ) to about 1×10 20 atoms / cm 3 In addition or alternatively, the selected concentration of the n-type dopant in a moderately doped semiconductor region (e.g., an N semiconductor region) can be in the range of about 1×10 16 atoms per cubic centimeter (atoms / cm 3 ) to about 1×10 18 atoms / cm 3 In addition or alternatively, the concentration of the n-type dopant selected for a lightly doped semiconductor region (e.g., an N- semiconductor region) can be in the range of about 1×10 14 atoms per cubic centimeter (atoms / cm 3 ) to about 1×10 16 atoms / cm 3 However, other chemical elements and / or concentration ranges associated with n-type dopants are also within the scope of some embodiments of the present disclosure.

[0092] Figure 2B FIG. shows an isometric view of an example TFET structure 222 in device region 202 after a replacement gate process. As Figure 2B As shown in Figure 2B , the TFET structure 222 includes a gate structure 224. After a replacement gate process, a portion of one or more layers of the gate structure 224 including a conductive material can be formed on and / or within the fin structure 206. Additionally, below the gate structure 224, a channel region 226 can be included as part of the fin structure 206. The channel region 226 can be a path for enabling current and / or charge to flow between the source region 218 and the drain region 220 to achieve the operability of the TFET structure 222.

[0093] As described in more detail in connection with FIG. 3A to FIG. 12C and elsewhere in some embodiments of the present disclosure, semiconductor regions proximate to or included as part of the fin structure 206, the source region 218, and / or the drain region 220 can include different types of dopants (e.g., asymmetric dopants) and / or dopant concentrations to improve the performance of the TFET structure 222. The improved performance can include reducing the threshold voltage and / or leakage within the TFET structure 222 and other examples.

[0094] Figure 2B Further shown are references A-A, B-B, C-C, and D-D, which are used as FIG. 3A to FIG. 12C references for the cross-sectional views in FIG. 3A to FIG. 12C . Reference A-A corresponds to a cross-sectional view through the fin structure 206. Reference B-B corresponds to a cross-sectional view through the gate structure 224 proximate to the upper portion of the fin structure 206. Reference C-C corresponds to a cross-sectional view through the gate structure 224 proximate to the lower portion of the fin structure 206. Reference D-D corresponds to a cross-sectional view through the STI region 208 between the fin structures 206.

[0095] As indicated above, Figure 2A and Figure 2B are provided as examples. Other examples can be different from what is described with respect to Figure 2A and Figure 2B described above.

[0096] Figure 3A and Figure 3B are diagrams of an example embodiment 300 described in some embodiments of the present disclosure. Embodiment 300 shows an example of a semiconductor device 200, where the source region 218 includes a doped semiconductor region 302 and the drain region 220 includes a doped semiconductor region 304. The doped semiconductor region 302 and the doped semiconductor region 304 include different dopant types (e.g., are asymmetrically doped).

[0097] As Figure 3AAs shown, the semiconductor device 200 includes a gate structure 224, a fin structure 206 located below the gate structure, a source region 218 along a first side of the fin structure 206, and a drain region 220 along a second side of the fin structure 206. In addition, as Figure 3A shown, the channel region 226 is an undoped region of the fin structure 206 that is between the doped semiconductor region 302 and the drain region 220. In other words, the channel region 226 is an intrinsic fin semiconductor region.

[0098] The source region 218 includes a doped semiconductor region 302 (a doped region of silicon or another III-V material and other examples) implanted with a p-type dopant. In addition, the doped semiconductor region 302 can be a heavily doped semiconductor region (e.g., a P semiconductor region containing a high concentration of p-type dopant as described above).

[0099] The drain region 220 includes a doped semiconductor region 304 (a doped region of silicon or another III-V material and other examples) implanted with an n-type dopant. In addition, the doped semiconductor region 304 can be a heavily doped drain region (e.g., an N semiconductor region containing a high concentration of n-type dopant as described above).

[0100] The gate structure 224 can include a conductive core 306 (a layer of low-resistance conductive material such as tungsten (W), silver (Ag), or cobalt (Co) and other examples). In some embodiments, the gate structure 224 includes a conductive layer 308 surrounding the conductive core 306. The conductive layer 308 (e.g., a first conductive layer) can include a conductive material such as aluminum (Al), titanium (Ti), tantalum (Ta), or a conductive compound such as titanium aluminide (TiAl) or titanium nitride (TiN) and other examples. In addition, in some embodiments, the gate structure 224 includes a conductive layer 310 surrounding the conductive layer 308. The conductive layer 310 (e.g., a second conductive layer) can include a conductive material such as aluminum (Al), titanium (Ti), tantalum (Ta), or a conductive compound such as titanium aluminide (TiAl) or titanium nitride (TiN) and other examples. The gate structure 224 can include different configurations (e.g., different layer arrangements, different numbers of layers, different layer thicknesses, and / or different material combinations) of the conductive core 306, the conductive layer 308, and / or the conductive layer 310 to "tune" the performance of the gate structure 224.

[0101] As Figure 3AAs further shown, the gate structure includes a dielectric layer 312 and a dielectric layer 314. The dielectric layer 312 (e.g., a first dielectric sidewall) may include a high-k dielectric material (e.g., a material having a higher dielectric constant than silicon dioxide), such as hafnium oxide (HfO2), zirconium dioxide (ZrO2), or lanthanum aluminum oxide (LaAlO3), among other examples. The dielectric layer 314 (e.g., a second dielectric sidewall) may include a low-k dielectric material (e.g., a material having a lower dielectric constant than silicon dioxide), such as silicon oxynitride (SiON) or silicon carbon oxynitride (SiCON), among other examples. As Figure 3A As further shown, the fin structure 206 (e.g., a fin intrinsic semiconductor region) includes an interface region 316 that is connected to the dielectric layers 312 and 314 located below the conductive core 306.

[0102] In some embodiments, as Figure 3A shown in the cross-sectional view (reference A-A), a sidewall spacer layer 318 is located on the dielectric layer 312 and the dielectric layer 314. The sidewall spacer layer 318 may include silicon nitride (SiN) or silicon carbonitride (SiCN), among other examples. Additionally, as Figure 3A shown, a dielectric layer 320 (e.g., an interlayer dielectric (ILD)) is located on the sidewall spacer layer 318. The dielectric layer 320 may include a low-k dielectric material, such as porous silicon dioxide (SiO2), among other examples.

[0103] Figure 3B A cross-sectional view (reference B-B and reference C-C) showing the TFET structure 222 is presented. Specifically, as shown in the cross-sectional view (reference C-C), the TFET structure 222 includes an overlap region 322 where the doped semiconductor region 302 overlaps with the gate structure 224 (e.g., portions of the doped semiconductor region 302 and the gate structure 224 protrude within a common region). As further shown in the cross-sectional view (reference C-C), a portion of the dielectric layer 312 is located within the overlap region 322.

[0104] In some embodiments and based on the combination of FIG. 10A to FIG. 10I 、 FIG. 12A to FIG. 12CAnd as described elsewhere in some embodiments of the present disclosure, the width of the overlap region 322 is controlled by one or more semiconductor processing operations that form the profile of the doped semiconductor region 302 and / or the profile of the gate structure 224. In contrast to another TFET structure that does not include this configuration, the TFET structure 222 that includes the overlap region 322 can have an increased threshold voltage at which quantum tunneling begins and at which the TFET structure 222 conducts current in the channel region 226. This increased threshold voltage can reduce the power consumption of the TFET structure 222, increase the switching speed of the TFET structure 222, and / or improve the noise tolerance of the TFET structure 222 to maintain signal integrity within a semiconductor device that includes the TFET structure 222 and other examples.

[0105] In addition, as shown in the cross-sectional view (refer to C-C), the TFET structure 222 includes an underlap region 324, where the doped semiconductor region 304 and the gate structure 224 are underlapped (e.g., no portions of the doped semiconductor region 304 and the gate structure 224 protrude within a common region). As shown in the cross-sectional view (refer to C-C), a portion of the dielectric layer 314 is located within the underlap region 324.

[0106] In some embodiments and based on the combination FIG. 10A to FIG. 10I 、 FIG. 12A to FIG. 12C And as described elsewhere in some embodiments of the present disclosure, the width of the underlap region 324 is controlled by one or more semiconductor processing operations that form the profile of the doped semiconductor region 304 and / or an oxidation process used to form the dielectric layer 314. In contrast to another TFET structure that does not include this configuration, the TFET structure 222 that includes the underlap region 324 can have a reduced leakage or flow of current within the TFET structure 222 during the off state. This reduced leakage can improve the power efficiency of the TFET structure 222, reduce the heat generated by the TFET structure 222, increase the switching speed of the TFET structure 222, and / or improve the reliability of a semiconductor device that includes the TFET structure 222 and other examples.

[0107] As combined with Figure 3A and Figure 3B described, embodiment 300 includes a TFET structure (e.g., TFET structure 222) having a P-I-N structure that controls the flow of charge carriers through the channel region 226. In other words, as an example, the TFET structure 222 includes a P-I junction region located between the doped semiconductor region 302 (e.g., a P semiconductor region) and the fin structure 206 (e.g., an intrinsic semiconductor region) and an I-N junction region located between the fin structure and the doped semiconductor region 304 (e.g., an N semiconductor region).

[0108] As combined with Figure 3A and Figure 3B As described, a structure (e.g., TFET structure 222) includes a conductive core (e.g., conductive core 306) of a conductive material. The structure includes a first dielectric sidewall (e.g., dielectric layer 312) of a first dielectric material along a first side of the conductive core. The structure includes a second dielectric sidewall (e.g., dielectric layer 314) of a second dielectric material along a second opposite side of the conductive core, where the second dielectric material is different from the first dielectric material. The structure includes a fin-shaped intrinsic semiconductor region (e.g., fin structure 206) having an interface region (e.g., interface region 316) that is connected to and located below the first and second dielectric sidewalls. The structure includes a first doped semiconductor region (e.g., doped semiconductor region 302) that includes a first dopant along a first side of the fin-shaped intrinsic semiconductor region, the first side being adjacent to the first dielectric sidewall. The structure includes a second doped semiconductor region (e.g., doped semiconductor region 304) that includes a second dopant along a second opposite side of the fin-shaped intrinsic semiconductor region, the second opposite side being adjacent to the second dielectric sidewall, where the second dopant includes a dopant type different from the first dopant.

[0109] As indicated above, Figure 3A and Figure 3B are provided as examples. Other examples may be different from those described with respect to Figure 3A and Figure 3B what is described.

[0110] Figure 4A and Figure 4B are diagrams of an example embodiment 400 described in some embodiments of the present disclosure. Embodiment 400 shows an example of a semiconductor device 200, where a source region 218 includes a doped semiconductor region 402 and a doped semiconductor region 406. Contrary to the doped semiconductor region 302 moderately doped with p-type dopants as described in connection with Figure 3A and Figure 3B the doped semiconductor region 402 is heavily doped with p-type dopants (e.g., the doped semiconductor region 402 is a P+ semiconductor region including a high concentration of p-type dopants as described above). In addition, the doped semiconductor region 404 is moderately doped with n-type dopants (e.g., the doped semiconductor region 404 is an N semiconductor region including a moderate concentration of n-type dopants as described above).

[0111] Figure 4A shows a cross-sectional view of the TFET structure 222 (reference A-A). As Figure 4AAs shown, the source region 218 includes a doped semiconductor region 406 (e.g., a "skirt") along the perimeter of the doped semiconductor region 402. Additionally, the doped semiconductor region 406 is moderately doped with an n-type dopant (e.g., the doped semiconductor region 406 is an N semiconductor region containing a moderate concentration of n-type dopant as described above). Since the doped semiconductor region 402 contains a p-type dopant and the doped semiconductor region 406 contains an n-type dopant, the source region 218 contains opposite-type dopants.

[0112] Additionally, as shown, the drain region 220 includes a doped semiconductor region 408 along the perimeter of the doped semiconductor region 404. Further, the doped semiconductor region 408 is lightly doped with an n-type dopant (e.g., the doped semiconductor region 408 is an N− semiconductor region containing a moderate concentration of n-type dopant as described above). Since the doped semiconductor region 404 contains an n-type dopant and the doped semiconductor region 408 contains an n-type dopant, the drain region 220 contains the same dopant type. Additionally, since the doped semiconductor region 404 is an N+ semiconductor region and the doped semiconductor region 408 is an N− semiconductor region, the drain region 220 contains a doping gradient.

[0113] The concentration ratio of the dopants in the doped semiconductor region 404 and the doped semiconductor region 408 can be selected to reduce and / or minimize the bipolar current (e.g., the synchronous flow of electrons and holes) in the TFET structure 222. For example, to reduce and / or minimize the bipolar current in the TFET structure 222, the selected ratio of the n-type dopant in the doped semiconductor region 408 to the n-type dopant in the doped semiconductor region 404 can be included in the range of about 1:100 to 50:100. However, other values and ranges of the concentration ratio are also within the scope of some embodiments of the present disclosure.

[0114] As Figure 4A further shown, the TFET structure 222 further includes a doped semiconductor region 410 (e.g., a "pocket"), which is close to the interface region 316 and is located between the doped semiconductor region 402 and the fin structure 206 (e.g., the fin intrinsic semiconductor region). In some embodiments, the doped semiconductor region 410 is heavily doped with an n-type dopant (e.g., the doped semiconductor region 410 is an N+ region containing a high concentration of n-type dopant as described above).

[0115] Figure 4B A cross-sectional view (reference B-B) and a cross-sectional view (reference C-C) of the TFET structure 222 are shown. The cross-sectional view (reference B-B) shows the doped semiconductor region 410. Additionally, as shown in the cross-sectional view (reference B-B), the gate structure 224 has a width D1 (e.g., the gate length). The cross-sectional view (reference C-C) shows the doped semiconductor region 402, the doped semiconductor region 404, the doped semiconductor region 406, and the doped semiconductor region 408.

[0116] One or more of the dimensions may be related. For example, the width D1 of the gate structure 224 (e.g., the gate length) may be related to the width D2 of the doped semiconductor region 408. In some embodiments, the values of the related dimensions may be design and / or performance choices. Additionally or alternatively, as part of miniaturizing the TFET structure 222, one or more scaling ratios of the related dimensions may be determined by the processing capabilities of semiconductor processing tools 102-114 as described in connection with Figure 1 and / or the control of semiconductor manufacturing process steps as described in connection with FIG. 10A to FIG. 10I and / or FIG. 12A to FIG. 12C described in more detail.

[0117] As an example, the ratio of width D2 to width D1 (D2:D1) may be included in the range of about 3:10 to about 5:10. If the ratio of width D2 to width D1 is less than about 3:10, the amount of current flowing in the TFET structure 222 during the off state may increase to a level that fails to meet the leakage performance threshold. If the ratio D2:D1 is between about 3:10 and 5:10, the TFET structure 222 may meet the performance threshold and may be manufacturable. If the ratio D2:D1 is greater than about 5:10, the processing capabilities of one or more semiconductor processing tools and / or semiconductor manufacturing process steps may be insufficient to form the gate structure 224. However, other values and ranges of the ratio D2:D1 are also within the scope of some embodiments of the present disclosure.

[0118] In some embodiments, including the doped semiconductor region 402 and the doped semiconductor region 406 in the TFET structure 222 facilitates vertical tunneling within the channel region 226. In addition to the benefits achieved via the embodiments 300 of Figure 3A and Figure 3B , the vertical tunneling facilitated by the embodiment 400 may further increase the threshold voltage to achieve additional reduction in power consumption, increase in switching speed, and / or improvement in noise tolerance in a semiconductor device including the TFET structure 222. Additionally, including the doped semiconductor region 404 and the doped semiconductor region 408 in the embodiment 400 may further reduce leakage in the TFET structure 222 to achieve additional improvement in power efficiency, reduction in generated heat, increase in switching speed, and / or improvement in reliability of a semiconductor device including the TFET structure 222.

[0119] As described in connection with Figure 4A and Figure 4BAs described, embodiment 400 includes a TFET structure (e.g., TFET structure 222) having a P-N-I-N-N structure that controls the flow of charge carriers through channel region 226. In other words, by way of example, TFET structure 222 includes a P-N junction region between doped semiconductor region 402 (e.g., P+ semiconductor region) and doped semiconductor region 406 (e.g., N semiconductor region), an N-I junction region between doped semiconductor region 406 and fin structure 206 (intrinsic semiconductor region), an I-N junction region between fin structure 206 and doped semiconductor region 408 (e.g., N- semiconductor region), and an N-N junction region between doped semiconductor region 408 and doped semiconductor region 404 (e.g., N+ semiconductor region).

[0120] As indicated above, Figure 4A and Figure 4B are provided by way of example. Other examples may differ from what is described with respect to Figure 4A and Figure 4B what is described.

[0121] FIG. 5A to FIG. 5C is a diagram of example embodiment 500 described in some embodiments of the present disclosure. As described in connection with Figure 4A , Figure 4B and elsewhere in some embodiments of the present disclosure, embodiment 500 shows an example of TFET structure 222, where source region 218 includes doped semiconductor region 402 and doped semiconductor region 406. Additionally, as shown, drain region 220 includes doped semiconductor region 404 described in connection with Figure 4A , Figure 4B and elsewhere in some embodiments of the present disclosure. However, drain region 220 of embodiment 500 does not include doped semiconductor region 408 described in connection with Figure 4A and Figure 4B described.

[0122] Figure 5A shows a cross-sectional view (reference A-A) of TFET structure 222, including, for example, relevant dimensions width D3 (e.g., the width of sidewall spacer layer 318), width D4 (e.g., the width of dielectric layer 314 along interface region 316), and distance D5 (e.g., the overlap distance of source region 218 as measured from the top of fin structure 206).

[0123] In some embodiments, as part of miniaturizing TFET structure 222, one or more of the relevant dimensions may have a scalable ratio determined by the processing capabilities of semiconductor processing tools 102-114 described in connection with Figure 1 and / or by the processing capabilities of semiconductor processing tools 102-114 described in connection with FIG. 10A to FIG. 10I and / or FIG. 12A to FIG. 12CA more detailed definition of semiconductor manufacturing process steps is described. For example, the ratio of width D4 to width D3 (D4:D3) can be greater than about 3:5. If the ratio D4:D3 is less than about 3:5, the processing capacity of the etching tool (e.g., Figure 1 etching tool 108) and / or the capacity of the exposure tool (e.g., exposure tool 104) can be exceeded and cause manufacturing defects within the TFET structure 222.

[0124] Additionally or alternatively, as another example, the ratio of distance D5 to width D3 (D5:D3) can be less than about 3:5. If the ratio D5:D3 is greater than about 3:5, the processing capacity of the etching tool can be exceeded and cause manufacturing defects at the top of the fin structure 206, thereby degrading the quality of the dielectric layer 312 and / or the dielectric layer 314.

[0125] Additionally or alternatively, the values of the relevant dimensions can be designed gated by the process and / or processing capacity of one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools 102 - 114 as described in conjunction with Figure 1 ). For example, if distance D3 is selected to be less than zero (e.g., a negative distance), the sidewall spacer layer 318 may not be usable as a contact etch stop layer (CESL), and the contact etch stop layer will be rendered incompatible with the processes performed by one or more semiconductor processing tools forming the TFET structure 222.

[0126] The dimensions (distance D3, distance D4, and distance D5) are provided as one or more examples. However, other ratios, values, and / or ranges of the dimensions (distance D3, distance D4, and distance D5) are also within the scope of some embodiments of the present disclosure.

[0127] Figure 5B A cross-sectional view of the TFET structure 222 is shown (reference C-C). The concentration ratio of the dopants in the doped semiconductor region 402 and the doped semiconductor region 406 can be selected to increase the tunneling current in the TFET structure 222. For example, to increase the tunneling current in the TFET structure 222, the selected ratio of the p-type dopant in the doped semiconductor region 402 to the n-type dopant in the doped semiconductor region 406 can be included in the range of about 1:10 to about 1:1. However, other values and ranges of the concentration ratio are also within the scope of some embodiments of the present disclosure.

[0128] Figure 5C A cross-sectional view of the TFET structure 222 is shown (reference D-D), e.g., a cross-section through the STI region 208 as described in conjunction with Figure 2B . As shown in Figure 5C , the length that the gate structure 224 extends towards the bottom of the source region 218 includes width D6.

[0129] In some embodiments, as part of miniaturizing the TFET structure 222, one or more scalable ratios of relevant dimensions may be defined by the processing capabilities of semiconductor processing tools 102-114 as described in connection with Figure 1 and / or by semiconductor manufacturing processing steps as described in connection with FIG. 10A to FIG. 10I and / or FIG. 12A to FIG. 12C described in more detail. Additionally or alternatively, the values of the relevant dimensions may be design and / or performance choices.

[0130] For example, in some embodiments, the width D6 is selected such that the ratio of width D6 to width D1 (D6:D1) (e.g., the ratio of width D6 to the width of the gate structure 224 or the gate length, as described in connection with Figure 4B described) is included in the range of about zero to about 3:10. Selecting the ratio D6:D1 to be less than about zero (e.g., width D6 is "negative") may not form the TFET structure 222 and / or may be incompatible with the semiconductor manufacturing process flow used to form the TFET structure 222. Selecting the ratio D6:D1 between about zero and about 3:10 can provide an overlap of the gate structure 224 and the source region 218 (e.g., Figure 3B overlap region 322), and this overlap enables the threshold voltage performance (e.g., V th ) and / or the on-current performance (e.g., I on ) of the TFET structure 222 to meet the performance threshold. Selecting the ratio D6:D1 to be greater than about 3:10 can reduce the overlap of the gate structure 224 and the source region 218, such that the threshold voltage performance (e.g., V th ) and / or the on-current performance (e.g., I on ) of the TFET structure 222 cannot meet the performance threshold. However, other values and ranges of the ratio D6:D1 are also within the scope of some embodiments of the present disclosure.

[0131] As described in connection with FIG. 5A to FIG. 5C described, embodiment 500 includes a TFET structure (e.g., TFET structure 222) having a P-N-I-N structure, and this P-N-I-N structure controls the charge carrier flow through the channel region 226. In other words, by way of example, the TFET structure 222 includes a P-N junction region between a doped semiconductor region 402 (e.g., a P+ semiconductor region) and a doped semiconductor region 406 (e.g., an N semiconductor region), an N-I junction region between the doped semiconductor region 406 and the fin structure 206 (intrinsic semiconductor region), and an I-N junction region between the fin structure 206 and a doped semiconductor region 404 (e.g., an N+ semiconductor region).

[0132] As indicated above, FIG. 5A to FIG. 5Care provided as examples. Other examples may differ from those described with respect to FIG. 5A to FIG. 5C the content described.

[0133] Fig. 6A and Figure 6B are diagrams of example embodiment 600 described in some embodiments of the present disclosure. Similar to Figure 3A and Figure 3B embodiment 300, embodiment 600 shows an example of a semiconductor device 200, wherein the source region 218 includes a doped semiconductor region 302.

[0134] In contrast to Figure 3A and Figure 3B embodiment 300, the configuration of the dielectric layer 312 and the dielectric layer 314 on the interface region 316 has been changed (e.g., in embodiment 600, the width of the dielectric layer 312 has been reduced, while the width of the dielectric layer 314 has been increased).

[0135] In some embodiments, the change in the configuration of the dielectric layer 312 and / or the dielectric layer 314 on the interface region 316 (e.g., the change in the width of the dielectric layer 312 and / or the dielectric layer 314 on the interface region) is used to fine-tune the performance characteristics of a TFET structure 222 having a source region 218 and a drain region 220 that are asymmetrically doped (e.g., including a doped semiconductor region 302 and a doped semiconductor region 304 having different dopant types).

[0136] As indicated above, Fig. 6A and Figure 6B are provided as examples. Other examples may differ from those described with respect to Fig. 6A and Figure 6B the content described.

[0137] Fig. 7A and Figure 7B are diagrams of example embodiment 700 described in some embodiments of the present disclosure. In addition to the features described in connection with Figure 4A , Figure 4B and elsewhere in some embodiments of the present disclosure, embodiment 700 includes a doped semiconductor region 702 near the top of the fin-shaped structure 206. In other words, the channel region 226 includes a wider doped region (e.g., the doped semiconductor region 410 plus the doped semiconductor region 702).

[0138] As Fig. 7AAs shown, doped semiconductor region 702 is close to interface region 316. Additionally or alternatively, doped semiconductor region 702 is adjacent to doped semiconductor region 410. Additionally or alternatively, doped semiconductor region 702 is located between doped semiconductor region 402 and doped semiconductor region 406. In some embodiments, doped semiconductor region 702 is lightly doped with an n-type dopant (e.g., doped semiconductor region 702 is an N-semiconductor region containing a moderate concentration of n-type dopant as described above).

[0139] As Figure 7B shown, doped semiconductor region 702 is adjacent to an intrinsic semiconductor region (e.g., an undoped region) that is part of fin structure 206. To reduce the resistance of channel region 226 and improve the performance of TFET structure 222, a selected ratio of the n-type dopant in doped semiconductor region 702 to the n-type dopant in doped semiconductor region 410 can be included in the range of about 3:10 to about 8:10. However, other values and ranges of the concentration ratio are also within the scope of some embodiments of the present disclosure.

[0140] As indicated above, Fig. 7A and Figure 7B are provided as examples. Other examples may be different from those described with respect to Fig. 7A and Figure 7B described.

[0141] FIG. 8A to FIG. 8C is a diagram of exemplary embodiment 800 described in some embodiments of the present disclosure. Contrary to the aspect of channel region 226 described in connection with FIG. 3A to FIG. 7B channel region 226 includes portions having different widths and / or materials having different bandgap materials.

[0142] Fig. 8A shows an example of channel region 226 including portions having different widths. As Fig. 8A shown in the cross-sectional view (reference B-B), channel region 226 includes portion 802 close to source region 218 and portion 804 close to drain region 220. In some embodiments, portion 802 and portion 804 include the same semiconductor material (e.g., silicon (Si)).

[0143] Portion 802 may have a thickness D7 that is reduced relative to the thickness D8 of portion 804. By having a thickness D7 that is reduced relative to thickness D8, the electric field across channel region 226 can have a gradient (e.g., the potential close to source region 218 can increase relative to the potential close to drain region 220). This gradient can increase the probability of charge carriers tunneling from source region 218 into channel region 226 (e.g., increase the saturation current (I sat)),thereby improving the speed performance of the semiconductor device including the TFET structure 222. In addition, this gradient can reduce the probability of charge carriers tunneling from the drain region 220 to the channel region 226, thereby reducing the leakage within the TFET structure 222. This reduced leakage can improve the power efficiency of the TFET structure 222, reduce the heat generated by the TFET structure 222, increase the switching speed of the TFET structure 222, and / or improve the reliability of the semiconductor device including the TFET structure 222 and other examples.

[0144] In some embodiments, as part of miniaturizing the TFET structure 222, the scalable ratio D7:D8 of the thickness can be defined by the processing capabilities of the semiconductor processing tools 102-114 as described in connection with Figure 1 and / or by the semiconductor manufacturing processing steps described in more detail in connection with FIG. 11A to FIG. 11C Alternatively, the scalable ratio D7:D8 of the thickness can be selected based on the desired gradient of the potential across the channel region 226.

[0145] As an example, in some embodiments, the ratio D7:D8 can be less than about 8:10. If the ratio D7:D8 is greater than about 8:10, the potential change (e.g., gradient) across the channel region 226 may not be sufficient to increase the probability of charge carriers tunneling from the source region 218 to the channel region 226 and reduce the probability of charge carriers tunneling from the drain region 220 to the channel region 226. If the ratio D7:D8 is less than about 8:10, the potential change across the channel region 226 may be sufficient to increase the probability of charge carriers tunneling from the source region 218 to the channel region 226 and reduce the probability of charge carriers tunneling from the drain region 220 to the channel region 226.

[0146] Alternatively, the thickness D7 can be greater than about 2 nanometers (nm). Selecting the thickness D7 to be less than about 2 nanometers can reduce the amount of silicon available to supply atoms as carrier sources, thereby reducing the mobility of charge carriers within the TFET structure 222. Selecting the thickness to be greater than about 2 nanometers can provide sufficient silicon for supplying atoms as carrier sources, thereby supporting the desired mobility of charge carriers within the TFET structure 222.

[0147] The values and ratios associated with the thickness D7 and the thickness D8 are provided as examples. However, other values and ratios associated with the thickness D7 and the thickness D8 are also within the scope of some embodiments of the present disclosure.

[0148] Figure 8B An example showing a portion of the TFET structure 222 including different bandgap materials. As Figure 8BAs shown in the cross-sectional view (refer to B-B), a portion 806 of the TFET structure 222 (e.g., including a source region 218 and a portion of the channel region 226) includes a low bandgap material, and a portion 808 of the TFET structure 222 (e.g., including a portion of the underlap region 324) includes a high bandgap material. The low bandgap material of portion 806 may include germanium (Ge), silicon germanium (SiGe), indium antimonide (InSb), indium arsenide (InAs), or gallium antimonide (GaSb) and other examples. The high bandgap material of portion 808 may include silicon (Si), indium phosphide (InP), gallium phosphide (GaP), or gallium arsenide (GaAs) and other examples.

[0149] The difference in energy levels at the interface between portion 806 and portion 808 can create an energy barrier that reduces the probability of charge carriers tunneling from the drain region 220 into the channel region 226, thereby reducing leakage within the TFET structure 222. This reduced leakage can improve the power efficiency of the TFET structure 222, reduce the heat generated by the TFET structure 222, increase the switching speed of the TFET structure 222, and / or increase the reliability of the semiconductor device including the TFET structure 222 and other examples.

[0150] Figure 8C An example of the TFET structure 222 is shown, which combines portions with different widths and materials with different bandgap materials as described in connection with Fig. 8A and Figure 8B In addition, Figure 8C the TFET structure 222 of Fig. 8A and Figure 8B can combine one or more features described in connection with Figure 8C Thus, the TFET structure 222 as shown in Fig. 8A and Figure 8B can achieve the combined performance benefits described in connection with

[0151] As described in connection with FIG. 2A to FIG. 8C in some embodiments, a semiconductor device (e.g., semiconductor device 200) includes a tunnel fin-based transistor (e.g., TFET structure 222), the tunnel fin-based transistor includes a gate structure (e.g., gate structure 224), a source region (e.g., source region 218) located below the gate structure and adjacent to the first side of the gate structure, a drain region (e.g., drain region 220) located below the gate structure and adjacent to the second opposite side of the gate structure, and a channel region (e.g., channel region 226) located between the source region and the drain region. The channel region includes a first portion (e.g., portion 802 having a thickness D7) having a first thickness near the source region and a second portion (e.g., the portion having a thickness D8) having a second thickness near the drain region, where the second thickness is different from the first thickness.

[0152] As indicated above, FIG. 8A to FIG. 8C is provided as an example. Other examples may differ from that regarding FIG. 8A to FIG. 8C the content described.

[0153] Fig. 9 is a diagram of an example implementation 900 described in some embodiments of the present disclosure. In addition to including features described in conjunction with Figure 4A , Figure 4B and elsewhere in some embodiments of the present disclosure, the TFET structure 222 of implementation 900 includes a doped semiconductor region 902 (e.g., a capping layer) located between the dielectric layer 312 and a portion 802 of the channel region 226.

[0154] Fig. 9 The cross-sectional views (refer to B-B and refer to C-C) of th show the doped semiconductor region 902. In some embodiments, the doped semiconductor region 902 is lightly doped with an n-type dopant (e.g., the doped semiconductor region 902 is an N-semiconductor region containing a moderate concentration of n-type dopant as described above). In some embodiments, the doped semiconductor region 902 increases the likelihood of charge carriers tunneling vertically within the TFET structure 222, thereby further improving the threshold voltage performance (e.g., V on ) and / or the on-current performance (e.g., I

[0155] The doped semiconductor region 902 includes a high bandgap material. In addition, as described in more detail in conjunction with FIG. 11A to FIG. 11C , the doped semiconductor region 902 can be a regrown layer epitaxially grown on the portion 802.

[0156] The high bandgap material can include silicon (Si), indium phosphide (InP), gallium phosphide (GaP), or gallium arsenide (GaAs), among other examples. In some embodiments, the doped semiconductor region 902 and the channel region 226 (e.g., the fin structure 206) include the same high bandgap material. Alternatively, in some embodiments, the doped semiconductor region 902 and the channel region 226 include different high bandgap materials.

[0157] As indicated above, Fig. 9 is provided as an example. Other examples may differ from that regarding Fig. 9 the content described.

[0158] Figures 2A to 9Describe different embodiments of a semiconductor device 200 including a TFET structure 222. The TFET structure 222 can include a combination of two or more doped semiconductor regions having the same n-type dopant (e.g., the same electron-rich dopant) (e.g., a combination of two or more of doped semiconductor region 404, doped semiconductor region 406, doped semiconductor region 408, doped semiconductor region 410, doped semiconductor region 702, and / or doped semiconductor region 902). In some embodiments, two or more of doped semiconductor region 404, doped semiconductor region 406, doped semiconductor region 408, doped semiconductor region 410, doped semiconductor region 702, and / or doped semiconductor region 902 share the same n-type dopant (e.g., the same chemical element such as phosphorus (P), arsenic (As), and / or antimony (Sb)). In contrast, in some embodiments, two or more of doped semiconductor region 404, doped semiconductor region 406, doped semiconductor region 408, doped semiconductor region 410, doped semiconductor region 702, and / or doped semiconductor region 902 have different n-type dopants (e.g., different electron-rich dopants). Additionally, as described in connection with Figures 2A to 9 the concentration of the n-type dopant can vary in each of doped semiconductor region 404, doped semiconductor region 406, doped semiconductor region 408, doped semiconductor region 410, doped semiconductor region 702, and / or doped semiconductor region 902.

[0159] Furthermore, the TFET structure 222 can have at least one doped semiconductor region with a p-type dopant (e.g., doped semiconductor region 302 and / or doped semiconductor region 402). Additionally, the channel region of the TFET structure 222 (e.g., channel region 226 in fin structure 206) can include portions having different widths (e.g., portion 802 and portion 804) and / or containing different combinations of materials.

[0160] In this manner, using different combinations of the features described in connection with Figures 2A to 9 the performance of the TFET structure 222 can be improved and / or adjusted such that the threshold voltage performance of the TFET structure 222 (e.g., V th ) is compatible with the available power supply in the semiconductor device 200. Additionally, leakage in the semiconductor device 200 can be reduced.

[0161] FIG. 10A to FIG. 10I is a series of examples of semiconductor manufacturing operations 1000 for forming one or more portions of a semiconductor device (e.g., semiconductor device 200) including a transistor structure. One or more portions of the transistor structure can correspond to the TFET structure 222 of embodiment 700 as described in connection with Fig. 7A and Figure 7B described. Additionally, in some embodiments, in connection with Figure 1 One or more of the described semiconductor processing tools 102-114 perform one or more of the semiconductor manufacturing operations 1000.

[0162] As Fig. 10A shown, a series of semiconductor manufacturing operations 1000 includes forming a dummy gate structure 210 on and / or above a fin structure 206. As part of forming the dummy gate structure 210, deposition tool 102, exposure tool 104, developer tool 106, etch tool 108, planarization tool 110, and / or plating tool 112 can be used to perform a combination of operations described in Figure 1 order to form a dielectric layer 314, a gate electrode layer 212, a hard mask layer 214, and / or a sidewall spacer layer 318.

[0163] As Fig. 10B shown, as part of forming a source region (e.g., source region 218), a series of semiconductor manufacturing operations 1000 includes forming a doped semiconductor region 404. As part of forming the doped semiconductor region 404, a mask 1004 is formed that masks portions of the dummy gate structure 210 and / or the fin structure 206. For example, deposition tool 102 can be used to form a photoresist layer over and / or on the dummy gate structure 210 and the fin structure 206. Exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Developer tool 106 can be used to develop portions of the photoresist layer and remove these portions to form the mask 1004.

[0164] In addition, as part of forming the doped semiconductor region 404, a cavity 1002 is formed in the fin structure 206. In some embodiments, the pattern in the photoresist layer is used to etch the fin structure 206 to form the cavity 1002. In these embodiments, deposition tool 102 can be used to form a photoresist layer over and / or on the fin structure 206. Exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Developer tool 106 can be used to develop portions of the photoresist layer and remove these portions to expose the pattern. Etch tool 108 can be used to etch the fin structure 206 based on the pattern to form the cavity 1002 in the fin structure 206. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or another type of etch operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, the hard mask layer serves as an alternative technique for etching the fin structure 206 based on the pattern.

[0165] In addition, as part of forming the doped semiconductor region 404, an ion implantation tool 114 can be used to perform an ion implantation operation that implants ions of an n-type dopant below the surface of the cavity 1002. In some embodiments, the ion implantation operation implants a moderate concentration of the n-type dopant.

[0166] As Fig. 10C shown, a series of semiconductor manufacturing operations 1000 includes forming a doped semiconductor region 402. In some embodiments, a deposition tool 102 is used to form a semiconductor material in the cavity 1002 during an epitaxial growth operation. Alternatively, the deposition tool 102 can be used to form a semiconductor material in the cavity 1002 using a PVD operation, an ALD operation, a CVD operation, an oxidation operation, another type of deposition operation described in Figure 1 combination, and / or another suitable deposition operation.

[0167] In addition, as part of forming the doped semiconductor region 404, an ion implantation tool 114 can be used to perform an ion implantation operation that implants ions of a p-type dopant into the semiconductor material. In some embodiments, the ion implantation operation implants a high concentration of the p-type dopant.

[0168] As Fig. 10D shown, a series of semiconductor manufacturing operations 1000 includes forming a doped semiconductor region 408. As part of forming the doped semiconductor region 408, a mask 1006 is formed that masks portions of the dummy gate structure 210 and / or the fin structure 206. For example, a deposition tool 102 can be used to form a photoresist layer over and / or on the dummy gate structure 210 and the fin structure 206. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool 106 can be used to develop portions of the photoresist layer and remove these portions to form the mask 1006.

[0169] In addition, as part of forming the doped semiconductor region 408, a cavity 1008 is formed in the fin structure 206. In some embodiments, a pattern in a photoresist layer is used to etch the fin structure 206 to form the cavity 1002. In these embodiments, a deposition tool 102 can be used to form a photoresist layer over and / or on the fin structure 206. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool 106 can be used to develop portions of the photoresist layer and remove these portions to expose the pattern. An etch tool 108 can be used to etch the fin structure 206 based on the pattern to form the cavity 1002 in the fin structure 206. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or another type of etch operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer serves as an alternative technique for etching the fin structure 206 based on the pattern.

[0170] In addition, as part of forming the doped semiconductor region 408, an ion implantation tool 114 can be used to perform an ion implantation operation that implants ions of an n-type dopant beneath the surface of the cavity 1008. In some embodiments, the ion implantation operation implants a low concentration of n-type dopant.

[0171] As Fig. 10E shown, a series of semiconductor manufacturing operations 1000 includes forming a doped semiconductor region 406. In some embodiments, a deposition tool 102 is used to form semiconductor material in the cavity 1008 during an epitaxial growth operation. Alternatively, the deposition tool 102 can be used to form semiconductor material in the cavity 1008 using a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a combined Figure 1 described another type of deposition operation, and / or another suitable deposition operation.

[0172] In addition, as part of forming the doped semiconductor region 406, an ion implantation tool 114 can be used to perform an ion implantation operation that implants ions of an n-type dopant into the semiconductor material. In some embodiments, the ion implantation operation implants a high concentration of n-type dopant.

[0173] As Fig.10F shown, a series of semiconductor manufacturing operations 1000 includes forming a dielectric layer 320 over and / or on the fin structure 206. As part of forming the dielectric layer 320, a deposition tool 102 can be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combined Figure 1Deposit the dielectric layer 320 in another type of deposition operation described and / or another suitable deposition operation. In some embodiments, the planarization tool 110 can be used to planarize the dielectric layer 320 after depositing the dielectric layer 320.

[0174] In addition, as Fig.10F shown in, a series of semiconductor manufacturing operations 1000 includes performing a gate replacement process that includes removing the hard mask layer 214 and the gate electrode layer 212 to form a cavity 1010 in the dielectric layer 314. In some embodiments, a pattern in a photoresist layer is used to etch (e.g., remove) the hard mask layer 214 and / or the gate electrode layer 212 to form the cavity 1010. In these embodiments, the deposition tool 102 can be used to form a photoresist layer over and / or on the dielectric layer 314, the sidewall spacer layer 318, and / or the dielectric layer 320. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 can be used to develop portions of the photoresist layer and remove these portions to expose the pattern. The etch tool 108 can be used to etch the hard mask layer 214 and / or the gate electrode layer 212 based on the pattern to form the cavity 1010 in the dielectric layer 314. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or another type of etch operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, the hard mask layer serves as an alternative technique for etching the hard mask layer 214 and / or the gate electrode layer 212 based on the pattern.

[0175] As Figure 10G shown in, a series of semiconductor manufacturing operations 1000 includes forming a doped semiconductor region 410. As part of forming the doped semiconductor region 410, a mask 1012 is formed that masks portions of the fin structure 206, the dielectric layer 314, the sidewall spacer layer 318, and / or the dielectric layer 320. As an example, the deposition tool 102 can be used to form a photoresist layer over and / or on portions of the fin structure 206, the dielectric layer 314, the sidewall spacer layer 318, and / or the dielectric layer 320. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 can be used to develop portions of the photoresist layer and remove these portions to form the mask 1012.

[0176] In addition, as Figure 10GAs shown in and as part of a series of semiconductor manufacturing operations 1000, a portion of the dielectric layer 314 is removed to expose a portion of the fin structure 206. As an example, in some embodiments, an etching tool 108 can be used to perform an etching operation that removes a portion of the dielectric layer 314 to expose a portion of the fin structure 206. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation.

[0177] In addition, as part of forming the doped semiconductor region 410, an ion implantation tool 114 can be used to perform an ion implantation operation that implants ions of an n-type dopant into the exposed portion of the fin structure 206. In some embodiments, the ion implantation operation implants a high concentration of n-type dopant.

[0178] As Fig. 10H shown in, a series of semiconductor manufacturing operations 1000 includes forming a dielectric layer 312 above and / or on the doped semiconductor region 410 and along the sidewall spacer layer 318. As part of forming the dielectric layer 312, a deposition tool 102 can be used to deposit the dielectric layer 312 in a PVD operation, an ALD operation, a CVD operation, an epitaxial growth operation, an oxidation operation, combined Figure 1 with another type of deposition operation described above and / or another suitable deposition operation. In some embodiments, a planarization tool 110 can be used to planarize the dielectric layer 312 after depositing the dielectric layer 312.

[0179] As Fig.10I shown in, a series of semiconductor manufacturing operations 1000 includes forming a gate structure 224 above and / or on the dielectric layer 312 and the dielectric layer 314 and on the dielectric layer 312 and the dielectric layer 314. As part of forming the gate structure 224, a deposition tool 102 can be used to deposit the conductive layer 310, the conductive layer 308, and / or the conductive core 306 in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, as combined above Figure 1 with another deposition operation described above and / or another suitable deposition operation. In some embodiments, a seed layer is deposited before depositing the conductive layer 310, the conductive layer 308, and / or the conductive core 306. In some embodiments, a planarization tool 110 can be used to planarize the conductive layer 310, the conductive layer 308, and / or the conductive core 306 after depositing the conductive layer 310, the conductive layer 308, and / or the conductive core 306.

[0180] Although FIG. 10A to FIG. 10IA series of semiconductor manufacturing operations 1000 are described as follows for a configuration: The source region 218 and the drain region 220 of the TFET structure 222 contain specific dopant configurations, which are provided as examples only, and "opposite" configurations may exist. For example, a series of similar operations may be performed as part of forming the configuration of the TFET structure 222, where the doped semiconductor region 402 contains an n-type dopant, the doped semiconductor region 404 contains a p-type dopant, and the doped semiconductor region 410 contains a p-type dopant. Additionally or alternatively, a series of similar operations may be performed as part of forming the configuration of the TFET structure 222, where the doped semiconductor region 406 contains a p-type dopant, and the doped semiconductor region 408 contains a p-type dopant.

[0181] As indicated above, FIG. 10A to FIG. 10I is provided as an example. Other examples may be different from what is described with respect to FIG. 10A to FIG. 10I what is described.

[0182] FIG. 11A to FIG. 11C is a diagram of an example series of semiconductor manufacturing operations 1100 for forming one or more portions of a semiconductor device (e.g., semiconductor device 200) that includes the transistor structures described in some embodiments of the present disclosure. One or more portions of the transistor structure may correspond to the TFET structure 222 of embodiment 800 as described in connection with FIG. 8A to FIG. 8C described. Additionally or alternatively, one or more portions of the transistor structure may correspond to the TFET structure 222 of embodiment 900 as described in connection with Fig. 9 described. In some embodiments, one or more of the semiconductor manufacturing operations 1100 are performed in conjunction with one or more of the semiconductor processing tools 102 - 114 described in connection with Figure 1 described.

[0183] As Fig.11AAs shown, a series of semiconductor manufacturing operations 1100 includes forming a portion 802 of a fin structure 206. Forming the portion 802 may include, for example, trimming the fin structure 206 using selective etching and forming cavities 1102 on opposite sides of the fin structure 206 for regrowth purposes. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on the fin structure 206. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool 106 may be used to develop portions of the photoresist layer and remove these portions to expose the pattern. An etch tool 108 may be used to selectively etch the fin structure 206 based on the pattern to form cavities 1102 in the fin structure 206. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or another type of etch operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer serves as an alternative technique for etching the fin structure 206 based on the pattern.

[0184] As Fig. 11B shown, a series of semiconductor manufacturing operations 1100 includes forming a doped semiconductor region 902 (e.g., a capping layer). In some embodiments, as part of forming the doped semiconductor region 902, a deposition tool 102 is used to form a semiconductor material in the cavity 1102 during an epitaxial growth operation. Alternatively, the deposition tool 102 may be used to form a semiconductor material in the cavity 1102 using a PVD operation, an ALD operation, a CVD operation, an oxidation operation, another type of deposition operation described in conjunction Figure 1 herewith, and / or another suitable deposition operation.

[0185] In some embodiments, forming a semiconductor material in the cavity 1102 includes the deposition tool 102 directly forming the doped semiconductor region 902 by depositing a semiconductor material containing a high concentration of n-type dopant.

[0186] Alternatively, in some embodiments, forming a semiconductor material in the cavity 1102 includes the deposition tool 102 forming an intrinsic (e.g., undoped) semiconductor material in the cavity 1102. In such embodiments, after the semiconductor material is formed in the cavity 1102 by the deposition tool 102, an ion implantation tool 114 may be used to perform an ion implantation operation that implants ions of an n-type dopant into the intrinsic semiconductor material as part of forming the doped semiconductor region 902. In some embodiments, the ion implantation operation implants a high concentration of n-type dopant.

[0187] As Fig. 11CAs shown, a series of semiconductor manufacturing operations 1100 include forming a dielectric layer 312 over and / or on a doped semiconductor region 902. As an example, in some embodiments, a deposition tool 102 may be used to deposit the dielectric layer 312 in a PVD operation, an ALD operation, a CVD operation, an epitaxial growth operation, an oxidation operation, another type of deposition operation described in conjunction with Figure 1 and / or another suitable deposition operation. In some embodiments, a planarization tool 110 may be used to planarize the dielectric layer 312 after depositing the dielectric layer 312.

[0188] As Fig. 11C further shown, a series of semiconductor manufacturing operations 1100 include forming a gate structure 224 over and / or on the dielectric layer 312 and the dielectric layer 314. As part of forming the gate structure 224, a deposition tool 102 may be used to deposit one or more conductive layers (e.g., the conductive layer 310, the conductive layer 308, and / or the conductive core 306) in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, another deposition operation described in conjunction with Figure 1 and / or another suitable deposition operation. In some embodiments, a seed layer is deposited before depositing one or more conductive layers. In some embodiments, a planarization tool 110 may be used to planarize one or more conductive layers after depositing one or more conductive layers.

[0189] As indicated above, FIG. 11A to FIG. 11C is provided as an example. Other examples may be different from what is described with respect to FIG. 11A to FIG. 11C .

[0190] FIG. 12A to FIG. 12C is a diagram of an example series of semiconductor manufacturing operations 1200 for forming one or more portions of a semiconductor device (e.g., the semiconductor device 200) that includes transistor structures described in some embodiments of the present disclosure. One or more portions of the transistor structure may correspond to the TFET structure 222 of the embodiment 700 described in conjunction with Fig. 7A and Figure 7B . In some embodiments, one or more of the series of semiconductor manufacturing operations 1200 are performed using one or more of the semiconductor processing tools 102-114 described in conjunction with Figure 1 .

[0191] As Fig. 12AAs shown, a series of semiconductor manufacturing operations 1200 includes forming a mask 1202 that masks portions of fin structures 206, dielectric layer 314, sidewall spacer layer 318, and / or dielectric layer 320. As an example, deposition tool 102 can be used to form a photoresist layer over and / or on portions of fin structures 206, dielectric layer 314, sidewall spacer layer 318, and / or dielectric layer 320. Exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Developer tool 106 can be used to develop and remove portions of the photoresist layer to form mask 1012.

[0192] In addition, as Fig. 12A shown and as part of a series of semiconductor manufacturing operations 1200, a portion of dielectric layer 314 is removed to expose a portion of fin structure 206. As an example, in some embodiments, etch tool 108 can be used to perform an etch operation that removes portions of dielectric layer 314 to expose portions of fin structure 206. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or another type of etch operation.

[0193] As Fig. 12B shown, a series of semiconductor manufacturing operations 1200 includes an implantation operation (e.g., an implantation operation for forming doped semiconductor regions 410 and 702 as described in connection with Fig. 7A and Figure 7B ). As part of the implantation operation, ion implantation tool 114 can be used to perform an ion implantation operation that directly implants ions of an n-type dopant into the exposed portion of fin structure 206 and through dielectric layer 314. In some embodiments, dielectric layer 314 modifies the concentration of the n-type dopant on fin structure 206 (e.g., allowing a higher concentration of the n-type dopant in the exposed portion of fin structure 206 and a lower concentration of the n-type dopant in the portion of fin structure 206 directly beneath dielectric layer 314).

[0194] As Fig. 12C shown, a series of semiconductor manufacturing operations 1200 includes forming dielectric layer 312 over and / or on doped semiconductor region 410 and along sidewall spacer layer 318. As part of forming dielectric layer 312, deposition tool 102 can be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, in combination with Figure 1Deposit the dielectric layer 312 in another type of deposition operation described and / or another suitable deposition operation. In some embodiments, the planarization tool 110 can be used to planarize the dielectric layer 312 after depositing the dielectric layer 312.

[0195] As Fig. 12C Further shown in, a series of semiconductor manufacturing operations 1200 include forming a gate structure 224 above and / or on the dielectric layer 312 and the dielectric layer 314. As part of forming the gate structure 224, the deposition tool 102 can be used to deposit the conductive layer 310, the conductive layer 308, and / or the conductive core 306 in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, another deposition operation described above in connection with Figure 1 Another deposition operation and / or another suitable deposition operation. In some embodiments, a seed layer is deposited before depositing the conductive layer 310, the conductive layer 308, and / or the conductive core 306. In some embodiments, the planarization tool 110 can be used to planarize the conductive layer 310, the conductive layer 308, and / or the conductive core 306 after depositing the conductive layer 310, the conductive layer 308, and / or the conductive core 306.

[0196] As indicated above, FIG. 12A to FIG. 12C is provided as an example. Other examples may be different from those described with respect to FIG. 12A to FIG. 12C what is described.

[0197] Fig.13 is a diagram of example performance data 1300 of a transistor structure described in some embodiments of the present disclosure. In some embodiments, the transistor structure corresponds to a TFET structure 222 having a P-N-I-N-N structure as described in connection with Figure 4A and Figure 4B described. The example performance data 1300 includes a bandgap energy level 1302 associated with a position 1304 across a fin structure (e.g., fin structure 206).

[0198] The foregoing data includes the difference in bandgap energy levels across regions and / or junction regions of the fin structure, and will include a difference 1308 of a transistor structure having a uniform channel (e.g., an intrinsic silicon channel) and a difference 1310 of a transistor structure having a non-uniform channel (e.g., a TFET structure 222 including a doped semiconductor region 402, a doped semiconductor region 406, an intrinsic region of the fin structure 206, a doped semiconductor region 408, and a doped semiconductor region 404) for comparison.

[0199] Fig.13Region 1312 is shown (e.g., the source-to-channel region near the source side). As shown in region 1312, the steepness of the gap between the energy levels associated with difference 1308 is greater than the steepness of the gap between the energy levels associated with difference 1310. Additionally, within region 1312, the width of the gap associated with difference 1308 is less than the width of the gap associated with difference 1310. For the P-N-I-N-N structure within region 1312, this difference in steepness and / or width can help increase the charge carrier flow (e.g., current).

[0200] Fig.13 Region 1314 is further shown (e.g., the channel-to-drain region near the drain side), where difference 1310 increases relative to difference 1308. As shown in region 1314, the steepness of the gap between the energy levels associated with difference 1308 is less than the steepness of the gap between the energy levels associated with difference 1310. For the P-N-I-N-N structure within region 1314, this difference in steepness can help decrease the charge carrier flow (e.g., current).

[0201] As indicated above, Fig.13 is provided as an example. Other examples may be different from what is described with respect to Fig.13 what is described.

[0202] Fig.14 is an example element of one or more devices described in some embodiments of the present disclosure. Device 1400 may correspond to one or more of the semiconductor processing tools 102 - 114 and / or the wafer / die transfer tool 116 described in connection with Figure 1 In some embodiments, one or more of the semiconductor processing tools 102 - 114 and / or the wafer / die transfer tool 116 may include one or more devices 1400 and / or one or more elements of device 1400. As Figure 1 shown in Fig.14 , device 1400 may include a bus 1410, a processor 1420, a memory 1430, an input element 1440, an output element 1450, and / or a communication element 1460.

[0203] Bus 1410 may include one or more elements that enable wired and / or wireless communication between the elements of device 1400. Bus 1410 may couple, such as via operative coupling, communication coupling, electrical coupling, and / or electro - coupling, Fig.14Two or more components are coupled together. For example, bus 1410 may include electrical connections (e.g., wires, traces, and / or leads) and / or a wireless bus. Processor 1420 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application specific integrated circuit, and / or another type of processing element. Processor 1420 may be implemented using hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1420 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere in some embodiments of the present disclosure.

[0204] Memory 1430 may include volatile and / or non-volatile memory. For example, memory 1430 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 1430 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 1430 may be a non-transitory computer-readable medium. Memory 1430 may store information related to the operation of device 1400, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 1430 may include one or more memories such as those coupled (e.g., communicatively coupled) via bus 1410 to one or more processors (e.g., processor 1420). The communicative coupling between processor 1420 and memory 1430 may enable processor 1420 to read and / or process information stored in memory 1430 and / or store information in memory 1430.

[0205] Input component 1440 may enable device 1400 to receive input, such as user input and / or sensed input. For example, input component 1440 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or an actuator. Output component 1450 may enable device 1400 to provide output, such as via a display, a speaker, and / or a light emitting diode. Communication component 1460 may enable device 1400 to communicate with other devices via a wired connection and / or a wireless connection. For example, communication component 1460 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0206] Apparatus 1400 may perform one or more operations or processes described in some embodiments of this disclosure. For example, a non-transitory computer-readable medium (e.g., memory 1430) may store an instruction set (e.g., one or more instructions or program codes) for execution by processor 1420. Processor 1420 may execute the instruction set to perform one or more operations or processes described in some embodiments of this disclosure. In some embodiments, execution of the instruction set by one or more processors 1420 causes one or more processors 1420 and / or apparatus 1400 to perform one or more operations or processes described in some embodiments of this disclosure. In some embodiments, hardware circuitry may be used in place of or in combination with the instructions to perform one or more operations or processes described in some embodiments of this disclosure. Additionally or alternatively, processor 1420 may be used to perform one or more operations or processes described in some embodiments of this disclosure. Thus, the embodiments described in some embodiments of this disclosure are not limited to any particular combination of hardware circuitry and software.

[0207] Fig.14 The number and configuration of the elements shown therein are provided as examples. Apparatus 1400 may include more elements, fewer elements, different elements, or elements configured in a different manner than those shown therein. Additionally or alternatively, a set of elements (e.g., one or more elements) of apparatus 1400 may perform one or more functions described as being performed by another set of elements of apparatus 1400. Fig.14 The number and configuration of the elements shown therein are provided as examples. Apparatus 1400 may include more elements, fewer elements, different elements, or elements configured in a different manner than those shown therein. Additionally or alternatively, a set of elements (e.g., one or more elements) of apparatus 1400 may perform one or more functions described as being performed by another set of elements of apparatus 1400.

[0208] Fig.15 is a flowchart of an example process 1500 associated with forming a semiconductor device (e.g., semiconductor device 200 including TFET structure 222) described in some embodiments of this disclosure. In some embodiments, one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102 - 114) are used to perform Fig.15 one or more process blocks of. Additionally or alternatively, one or more elements of apparatus 1400 (such as processor 1420, memory 1430, input element 1440, output element 1450, and / or communication element 1460) may be used to perform Fig.15 one or more process blocks of.

[0209] As Fig.15As shown, process 1500 may include: forming a dummy gate structure (block 1510) on and above a fin structure. For example, as described in some embodiments of the present disclosure, one or more of semiconductor processing tools 102-114 may be used to form a dummy gate structure (e.g., dummy gate structure 210) on and above a fin structure (e.g., fin structure 206). In some embodiments, the dummy gate structure includes a gate electrode layer (e.g., gate electrode layer 212) surrounded by a multi-layer sidewall, and the multi-layer sidewall includes a first dielectric layer (e.g., dielectric layer 314) located on the gate electrode layer.

[0210] As Fig.15 As further shown, process 1500 may include: forming a source region including a first doped semiconductor region having a p-type dopant in the fin structure below the dummy gate structure and adjacent to a first side of the dummy gate structure (block 1520). For example, as described in some embodiments of the present disclosure, one or more of semiconductor processing tools 102-114 may be used to form a source region (e.g., source region 218) including a first doped semiconductor region (e.g., doped semiconductor region 402) having a p-type dopant in the fin structure below the dummy gate structure and adjacent to a first side of the dummy gate structure.

[0211] As Fig.15 As further shown, process 1500 may include: forming a drain region including a second doped semiconductor region having a first n-type dopant below the dummy gate structure and adjacent to a second opposite side of the dummy gate structure (block 1530). For example, as described in some embodiments of the present disclosure, one or more of semiconductor processing tools 102-114 may be used to form a drain region (e.g., drain region 220) including a second doped semiconductor region (e.g., doped semiconductor region 406) having a first n-type dopant below the dummy gate structure and adjacent to a second opposite side of the dummy gate structure.

[0212] As Fig.15 As further shown, process 1500 may include: removing the gate electrode layer (block 1540). For example, as described in some embodiments of the present disclosure, one or more of semiconductor processing tools 102-114 may be used to remove the gate electrode layer.

[0213] As Fig.15As further shown, process 1500 may include: removing a portion of the first dielectric layer to expose a portion of the fin structure adjacent to the source region and a second dielectric layer of the multi-layer sidewalls (block 1550). For example, as described in some embodiments of the present disclosure, one or more of semiconductor processing tools 102-114 may be used to remove a portion of the first dielectric layer to expose a portion of the fin structure adjacent to the source region and a second dielectric layer (e.g., sidewall spacer layer 314) of the multi-layer sidewalls.

[0214] As Fig.15 As further shown, process 1500 may include: forming a pocket region including a third doped semiconductor region having a second n-type dopant in a portion of the fin structure adjacent to the source region (block 1560). For example, as described in some embodiments of the present disclosure, one or more of semiconductor processing tools 102-114 may be used to form a pocket region including a third doped semiconductor region (e.g., doped semiconductor region 410) having a second n-type dopant in a portion of the fin structure adjacent to the source region.

[0215] As Fig.15 As further shown, process 1500 may include: forming a third dielectric layer above the pocket region and along the second dielectric layer (block 1570). For example, as described in some embodiments of the present disclosure, one or more of semiconductor processing tools 102-114 may be used to form a third dielectric layer (e.g., dielectric layer 312) above the pocket region and along the second dielectric layer.

[0216] As Fig.15 As further shown, process 1500 may include: forming a gate structure between the third dielectric layer and the remaining portion of the first dielectric layer (block 1580). For example, as described in some embodiments of the present disclosure, one or more of semiconductor processing tools 102-114 may be used to form a gate structure (e.g., gate structure 224) between the third dielectric layer and the remaining portion of the first dielectric layer. In some embodiments, forming the gate structure includes: forming one or more layers of a conductive material (e.g., conductive layer 308 and / or conductive layer 310) between the third dielectric layer and the remaining portion of the first dielectric layer.

[0217] Process 1500 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in other places in combination with one or more other processes described in some embodiments of the present disclosure.

[0218] In a first embodiment, process 1500 includes: forming a first portion of a fin structure (e.g., portion 802) to include a first thickness (e.g., thickness D7) and forming a second portion of the fin structure (e.g., portion 804) to include a second thickness (e.g., thickness D8), where the second thickness is greater than the first thickness.

[0219] In a second embodiment, either alone or in combination with the first embodiment, process 1500 includes: forming a cover layer (e.g., doped semiconductor region 902) on a surface of the first portion using an epitaxial growth operation.

[0220] Although Fig.15 example blocks of process 1500 are shown, in some embodiments, process 1500 includes more blocks, fewer blocks, different blocks, or blocks configured in a different manner than Fig.15 those depicted. Additionally or alternatively, two or more of the blocks of process 1500 may be performed in parallel.

[0221] Some embodiments of the present disclosure include a semiconductor device that includes a TFET structure and a manufacturing method. The TFET structure includes different combinations of doped semiconductor regions that form the source region, drain region, and channel region of the TFET. The different combinations of doped semiconductor regions include different types of dopants, different concentrations of dopants, and / or dopant gradients that change the difference in bandgap energy levels across one or more junction regions of the TFET structure.

[0222] In this way, the performance of the TFET structure is improved such that the TFET structure is compatible with the available power supply. Additionally, leakage within the TFET structure can be reduced to improve the quality and / or reliability of the TFET structure.

[0223] As described in more detail above, some embodiments of the present disclosure provide a transistor structure. The transistor structure includes a conductive core including a conductive material. The transistor structure includes a first dielectric sidewall of a first dielectric material along a first side of the conductive core. The transistor structure includes a second dielectric sidewall of a second dielectric material along a second opposite side of the conductive core, where the second dielectric material is different from the first dielectric material. The transistor structure includes a fin-like intrinsic semiconductor region having an interface region that is connected to and located under the first and second dielectric sidewalls. The transistor structure includes a first doped semiconductor region including a first dopant along a first side of the fin-like intrinsic semiconductor region, the first side of the fin-like intrinsic semiconductor region being adjacent to the first dielectric sidewall. The transistor structure includes a second doped semiconductor region including a second dopant along a second opposite side of the fin-like intrinsic semiconductor region, the second opposite side of the fin-like intrinsic semiconductor region being adjacent to the second dielectric sidewall, where the dopant type of the second dopant is different from the dopant type of the first dopant. In some embodiments, the first dielectric material includes a high-k dielectric material, and the second dielectric material includes a low-k dielectric material. In some embodiments, the second dopant is a first electron-rich dopant. The transistor structure further includes a third doped semiconductor region including a second electron-rich dopant, where the third doped semiconductor region is along the perimeter of the first doped semiconductor region, and where the third doped semiconductor region is located between the first doped semiconductor region and the fin-like intrinsic semiconductor region. In some embodiments, the concentration of the second electron-rich dopant is less than the concentration of the first electron-rich dopant. In some embodiments, the transistor structure further includes a fourth doped semiconductor region including a third electron-rich dopant, where the fourth doped semiconductor region is adjacent to the interface region, and where the fourth doped semiconductor region is located between the first doped semiconductor region and the fin-like intrinsic semiconductor region. In some embodiments, the concentration of the third electron-rich dopant is greater than the concentration of the second electron-rich dopant. In some embodiments, the transistor structure further includes a fifth doped semiconductor region including a fourth electron-rich dopant, where the fifth doped semiconductor region is adjacent to the interface region, and where the fifth doped semiconductor region is located between the fourth doped semiconductor region and the second doped semiconductor region. In some embodiments, the concentration of the fourth electron-rich dopant is less than the concentration of the third electron-rich dopant. In some embodiments, the transistor structure further includes a sixth doped semiconductor region including a fifth electron-rich dopant, where the sixth doped semiconductor region is located between the second doped semiconductor region and the fin-like intrinsic semiconductor region, and where the concentration of the fifth electron-rich dopant is less than the concentration of the first electron-rich dopant. In some embodiments, at least two of the first electron-rich dopant, the second electron-rich dopant, the third electron-rich dopant, the fourth electron-rich dopant, and the fifth electron-rich dopant are the same electron-rich dopant.In some embodiments, at least two of the first electron-rich dopant, the second electron-rich dopant, the third electron-rich dopant, the fourth electron-rich dopant, and the fifth electron-rich dopant are different electron-rich dopants.

[0224] As described in more detail above, some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a tunnel fin-based transistor, and the tunnel fin-based transistor includes a gate structure, a source region, a drain region, and a channel region. The source region is located below the gate structure and adjacent to a first side of the gate structure. The drain region is located below the gate structure and adjacent to a second opposite side of the gate structure. The channel region is located between the source region and the drain region. The channel region includes a first portion having a first thickness near the source region and a second portion having a second thickness near the drain region, where the second thickness is different from the first thickness. For example, the second thickness is greater than the first thickness. In some embodiments, the source region contains a p-type dopant, and the drain region contains an n-type dopant. In some embodiments, the first portion includes a first semiconductor material having a first bandgap energy level, and the second portion includes a second semiconductor material having a second bandgap energy level, where the second bandgap energy level is greater than the first bandgap energy level. In some embodiments, the first portion and the second portion include the same semiconductor material. In some embodiments, the semiconductor device further includes a capping layer located on the first portion, where the capping layer is doped with an n-type dopant. In some embodiments, the first portion includes a first semiconductor material. The semiconductor device further includes a capping layer located on the first portion, where the capping layer includes a second semiconductor material different from the first semiconductor material, and the second semiconductor material is doped with an n-type dopant.

[0225] As described in more detail above, some embodiments of the present disclosure provide a method of forming a semiconductor device. The method of forming a semiconductor device includes forming a dummy gate structure over and on a fin structure, wherein the dummy gate structure includes a gate electrode layer surrounded by a multi-layer sidewall, and the multi-layer sidewall includes a first dielectric layer on the gate electrode layer. The method of forming a semiconductor device includes forming a source region including a first doped semiconductor region having a p-type dopant in the fin structure below the dummy gate structure and adjacent to a first side of the dummy gate structure. The method of forming a semiconductor device includes forming a drain region including a second doped semiconductor region having a first n-type dopant below the dummy gate structure and adjacent to a second opposite side of the dummy gate structure. The method of forming a semiconductor device includes removing the gate electrode layer. The method of forming a semiconductor device includes removing a portion of the first dielectric layer to expose a portion of the fin structure adjacent to the source region and a second dielectric layer of the multi-layer sidewall. The method of forming a semiconductor device includes forming a pocket region including a third doped semiconductor region having a second n-type dopant in the portion of the fin structure adjacent to the source region. The method of forming a semiconductor device includes forming a third dielectric layer over the pocket region and along the second dielectric layer. The method of forming a semiconductor device includes forming a gate structure between the third dielectric layer and the remaining portion of the first dielectric layer, wherein forming the gate structure includes forming one or more layers of a conductive material between the third dielectric layer and the remaining portion of the first dielectric layer. In some embodiments, the method of forming a semiconductor device further includes forming a first portion of the fin structure to include a first thickness and forming a second portion of the fin structure to include a second thickness, wherein the second thickness is greater than the first thickness. In some embodiments, the method of forming a semiconductor device further includes forming a cover layer on a surface of the first portion using an epitaxial growth operation.

[0226] As used in some embodiments of the present disclosure, the term "and / or" when used in conjunction with multiple items is intended to individually cover each of the multiple items and to cover any and all combinations of the multiple items. For example, "A and / or B" covers "A and B", "A and not B", and "B and not A".

[0227] As used in some embodiments of the present disclosure, depending on the context, "meeting a threshold value" may refer to a value greater than the threshold value, greater than or equal to the threshold value, less than the threshold value, less than or equal to the threshold value, equal to the threshold value, not equal to the threshold value, or the like.

[0228] The foregoing describes the features of several embodiments, enabling those skilled in the art to better understand various aspects of some embodiments of the present disclosure. Those skilled in the art should understand that they can readily use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or attaining the same advantages as the embodiments introduced in some embodiments of the present disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of some embodiments of the present disclosure, and various changes, substitutions, and alterations can be made to some embodiments of the present disclosure without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. A transistor structure, characterized in that, Comprising: A conductive core comprising a conductive material; A first dielectric sidewall comprising a first dielectric material along a first side of the conductive core; A second dielectric sidewall comprising a second dielectric material along a second opposite side of the conductive core, wherein the second dielectric material is different from the first dielectric material; A fin-shaped intrinsic semiconductor region having an interface region that is connected to the first and second dielectric sidewalls and is located below the conductive core; A first doped semiconductor region comprising a first dopant along a first side of the fin-shaped intrinsic semiconductor region, the first side of the fin-shaped intrinsic semiconductor region being close to the first dielectric sidewall; and A second doped semiconductor region comprising a second dopant along a second opposite side of the fin-shaped intrinsic semiconductor region, the second opposite side of the fin-shaped intrinsic semiconductor region being close to the second dielectric sidewall, wherein a dopant type of the second dopant is different from a dopant type of the first dopant.

2. The transistor structure according to claim 1, wherein Wherein the second dopant is a first electron-rich dopant, and wherein the transistor structure further comprises: A third doped semiconductor region comprising a second electron-rich dopant, wherein the third doped semiconductor region is along a periphery of the first doped semiconductor region, and wherein the third doped semiconductor region is located between the first doped semiconductor region and the fin-shaped intrinsic semiconductor region.

3. The transistor structure according to claim 2, wherein Wherein a concentration of the second electron-rich dopant is less than a concentration of the first electron-rich dopant.

4. The transistor structure according to claim 2, characterized in that, Further comprising: A fourth doped semiconductor region comprising a third electron-rich dopant, wherein the fourth doped semiconductor region is close to the interface region, and wherein the fourth doped semiconductor region is located between the first doped semiconductor region and the fin-shaped intrinsic semiconductor region.

5. The transistor structure according to claim 4, characterized in that, Further comprising: A fifth doped semiconductor region comprising a fourth electron-rich dopant, wherein the fifth doped semiconductor region is close to the interface region, and wherein the fifth doped semiconductor region is located between the fourth doped semiconductor region and the second doped semiconductor region.

6. The transistor structure according to claim 5, characterized in that Further comprising: A sixth doped semiconductor region comprising a fifth electron-rich dopant, wherein the sixth doped semiconductor region is located between the second doped semiconductor region and the fin-shaped intrinsic semiconductor region, and wherein a concentration of the fifth electron-rich dopant is less than a concentration of the first electron-rich dopant.

7. A semiconductor device, characterized in that, Comprising: A tunnel fin-based transistor comprising: A gate structure; A source region located below the gate structure and close to a first side of the gate structure; A drain region located below the gate structure and close to a second opposite side of the gate structure; and A channel region located between the source region and the drain region, the channel region comprising: A first portion having a first thickness near the source region; and A second portion having a second thickness near the drain region, wherein the second thickness is different from the first thickness.

8. The semiconductor device according to claim 7, wherein, Wherein the source region comprises a p-type dopant, and wherein the drain region comprises: An n-type dopant.

9. The semiconductor device according to claim 7, wherein, Wherein the first portion comprises a first semiconductor material having a first bandgap energy level, wherein the second portion comprises a second semiconductor material having a second bandgap energy level, and wherein the second bandgap energy level is greater than the first bandgap energy level.

10. A method of forming a semiconductor device, characterized in that, Comprising: A dummy gate structure is formed on and above a fin structure, wherein the dummy gate structure includes a gate electrode layer surrounded by a multi-layer sidewall, and the multi-layer sidewall includes a first dielectric layer located on the gate electrode layer; A source region including a first doped semiconductor region having a p-type dopant is formed in the fin structure below the dummy gate structure and adjacent to a first side of the dummy gate structure; A drain region including a second doped semiconductor region having a first n-type dopant is formed below the dummy gate structure and adjacent to a second opposite side of the dummy gate structure; The gate electrode layer is removed; A part of the first dielectric layer is removed to expose a part of the fin structure adjacent to the source region and a second dielectric layer of the multi-layer sidewall; A pocket region including a third doped semiconductor region having a second n-type dopant is formed in the part of the fin structure adjacent to the source region; A third dielectric layer is formed above the pocket region and along the second dielectric layer; and A gate structure is formed between the third dielectric layer and a remaining part of the first dielectric layer, wherein forming the gate structure includes forming one or more layers of a conductive material between the third dielectric layer and the remaining part of the first dielectric layer.

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