Integrated circuit device

Abstract

An integrated circuit device includes: a rear insulating layer; a nanosheet stack structure disposed on the rear insulating layer and including a plurality of nanosheets; the source electrode / drain electrode regions are respectively positioned on two sides of the nanosheet stacking structure in the first horizontal direction; a gate electrode on the nanosheet stack structure extending in a second horizontal direction crossing the first horizontal direction; a contact plug connected to at least one of the pair of source / drain regions; a rear contact plug passing through the rear insulating layer and connected to at least one of the pair of source / drain regions; and a spacer layer including a contact spacer layer surrounding a portion of a side surface of the rear contact plug.

Description

Technical Field

[0001] The inventive concept relates to an integrated circuit device, and more particularly, to an integrated circuit device having a power delivery network (PDN). Background Art

[0002] With the development of electronic technology, the scaling down of integrated circuit devices is rapidly progressing. To effectively transmit power to highly integrated circuit devices, integrated circuit devices having a PDN are currently being developed. Summary of the Invention

[0003] According to an embodiment of the inventive concept, an integrated circuit device includes: a back insulating layer; a nanosheet stack structure disposed on the back insulating layer and including a plurality of nanosheets; a pair of source / drain regions respectively located on both sides of the nanosheet stack structure in a first horizontal direction; a gate electrode on the nanosheet stack structure and extending in a second horizontal direction crossing the first horizontal direction; a contact plug connected to at least one of the pair of source / drain regions; a back contact plug passing through the back insulating layer and connected to at least one of the pair of source / drain regions; and a spacer layer including a contact spacer layer surrounding a part of a side surface of the back contact plug.

[0004] According to an embodiment of the inventive concept, an integrated circuit device includes: a nanosheet stack structure including a plurality of nanosheets; a pair of source / drain regions respectively connected to both ends of each of the plurality of nanosheets in a first horizontal direction; a gate electrode on the nanosheet stack structure and extending in a second horizontal direction crossing the first horizontal direction; an inter-gate insulating layer at least partially surrounding the gate electrode and the pair of source / drain regions; a contact plug passing through the inter-gate insulating layer and connected to one of the pair of source / drain regions; an etch stop layer covering surfaces of the pair of source / drain regions and a bottom surface of the inter-gate insulating layer; a cover insulating layer covering the etch stop layer and the inter-gate insulating layer; a back insulating layer covering the cover insulating layer; a back contact plug passing through the back insulating layer and the cover insulating layer and connected to the other of the pair of source / drain regions; and a spacer layer including a contact spacer layer surrounding a part of a side surface of the back contact plug and located between the cover insulating layer and the back contact plug.

[0005] According to an embodiment of the inventive concept, an integrated circuit device includes: a nanosheet stack structure including a plurality of nanosheets; a pair of source / drain regions including a source region and a drain region, wherein the source region and the drain region are respectively connected to both ends of each of the plurality of nanosheets in a first horizontal direction; a gate electrode on the nanosheet stack structure and extending in a second horizontal direction crossing the first horizontal direction; a gate insulating layer at least partially surrounding the gate electrode and the pair of source / drain regions; an etch stop layer covering a surface of the pair of source / drain regions and a bottom surface of the gate insulating layer; a capping insulating layer covering the etch stop layer and the gate insulating layer; a back insulating layer disposed under the capping insulating layer; a back contact plug passing through the back insulating layer and the capping insulating layer and connected to the source region; a contact plug passing through the gate insulating layer and the etch stop layer and connected to the drain region; a placeholder structure passing through the capping insulating layer and connected to the drain region; and a spacer layer including a contact spacer layer and a placeholder spacer layer, wherein the contact spacer layer surrounds a portion of a side surface of the back contact plug and is located between the capping insulating layer and the back contact plug, and the placeholder spacer layer surrounds a portion of a side surface of the placeholder structure and is located between the capping insulating layer and the placeholder structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other aspects of the inventive concept will become more apparent by describing embodiments of the inventive concept in detail with reference to the accompanying drawings, in which:

[0007] Figure 1 is a layout of an integrated circuit device according to an embodiment;

[0008] Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 25A and Figure 25B are cross - sectional views showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept;

[0009] Figure 26A and Figure 26B are cross - sectional views showing an integrated circuit device according to an embodiment of the inventive concept;

[0010] Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A and Figure 29B are cross - sectional views showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept;

[0011] Figure 30A and Figure 30B are cross - sectional views showing an integrated circuit device according to an embodiment of the inventive concept;

[0012] Figure 31A and Figure 31B are cross - sectional views showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept;

[0013] Figure 32A and Figure 32B are cross - sectional views showing an integrated circuit device according to an embodiment of the inventive concept;

[0014] Figure 33A and Figure 33B are cross - sectional views showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept; and

[0015] Figure 34A and Figure 34B are cross - sectional views showing an integrated circuit device according to an embodiment of the inventive concept. Detailed Description

[0016] Figure 1is a layout of the integrated circuit device 1 according to an embodiment of the inventive concept.

[0017] Referring to Figure 1 , the integrated circuit device 1 includes a plurality of nanosheet stack structures NSS, a plurality of gate electrodes GL, and a plurality of source / drain regions SD. The plurality of nanosheet stack structures NSS may be arranged in rows and columns in a first horizontal direction (X direction) and a second horizontal direction (Y direction). For example, the plurality of nanosheet stack structures NSS may extend in the first horizontal direction (X direction) and may be arranged in the second horizontal direction (Y direction). The first horizontal direction (X direction) and the second horizontal direction (Y direction) may be orthogonal to each other. The plurality of gate electrodes GL may be spaced apart from each other in the first horizontal direction (X direction) and may extend in the second horizontal direction (Y direction).

[0018] Each of the plurality of nanosheet stack structures NSS may include a plurality of nanosheets N1, N2, and N3 (refer to Figure 26A ) that are stacked on one another while being spaced apart from each other in a vertical direction (Z direction). In the first horizontal direction (X direction), the source / drain regions SD may be disposed on both sides of each of the plurality of nanosheet stack structures NSS. The source / drain regions SD may be connected to each of the plurality of nanosheets N1, N2, and N3 (refer to Figure 26A ) included in each of the nanosheet stack structures NSS adjacent to each other in the first horizontal direction (X direction). In an embodiment of the inventive concept, the source / drain regions SD may be interposed between a pair of nanosheet stack structures NSS adjacent to each other in the first horizontal direction (X direction) among the plurality of nanosheet stack structures NSS. For example, the plurality of nanosheet stack structures NSS and the plurality of source / drain regions SD may be alternately arranged in the first horizontal direction (X direction).

[0019] Contact plugs CA may be connected above some of the plurality of source / drain regions SD, and back contact plugs BCA may be connected below some of the plurality of source / drain regions SD. In an embodiment of the inventive concept, in the first horizontal direction (X direction), the contact plugs CA may be connected to the source / drain regions SD disposed on one side of the plurality of nanosheet stack structures NSS, and the back contact plugs BCA may be connected to the source / drain regions SD disposed on the other side of the plurality of nanosheet stack structures NSS. In an embodiment of the inventive concept, the contact plugs CA may be connected above some of the plurality of source / drain regions SD, and the back contact plugs BCA may be connected below the remaining source / drain regions SD. However, the inventive concept is not limited thereto. For example, each of the contact plugs CA and the back contact plugs BCA may be connected to at least one of the plurality of source / drain regions SD.

[0020] The integrated circuit device 1 may include a plurality of logic units. The logic units may be configured in various ways, including a plurality of circuit elements, such as transistors and resistors. The logic units may be configured as, for example, AND (AND), NAND (NAND), OR (OR), NOR (NOR), exclusive OR (exclusive OR), exclusive NOR (XNOR), inverter (INV), adder (ADD), buffer (BUF), delay element (DLY), filter (FIL), multiplexer (MXT / MXIT), OR / AND / inverter (OR / AND / INVERTER, OAI), AND / OR (AND / OR, AO), AND / OR / inverter (AND / OR / INVERTER, AOI), D flip-flop, reset flip-flop, master-slave flip-flop, or latch, and the logic units may be standard cells configured to perform logic functions.

[0021] Figures 2A to 25B is a cross-sectional view showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept. Specifically, Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 20A 、 Figure 21A 、 Figure 22A 、 Figure 23A 、 Figure 24A and Figure 25A are cross-sectional views taken along line A-A' in Figure 1 , Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 19B 、 Figure 20B 、Figure 21B , Figure 22B , Figure 23B , Figure 24B and Figure 25B are cross-sectional views taken along line B-B' in Figure 1 .

[0022] Referring together to Figure 2A and Figure 2B , a plurality of sacrificial semiconductor layers 106S and a plurality of nanosheet semiconductor layers are alternately stacked one by one on a substrate 110. The plurality of sacrificial semiconductor layers 106S and the plurality of nanosheet semiconductor layers may include different semiconductor materials. In an embodiment of the inventive concept, the plurality of nanosheet semiconductor layers may include a single material. In an embodiment of the inventive concept, the plurality of nanosheet semiconductor layers may include the same material as the material of the substrate 110. In an embodiment of the inventive concept, the plurality of sacrificial semiconductor layers 106S may include SiGe, and the plurality of nanosheet semiconductor layers may include Si. However, the inventive concept is not limited thereto.

[0023] The plurality of sacrificial semiconductor layers 106S may all be formed to have the same thickness. However, the inventive concept is not limited thereto. In an embodiment of the inventive concept, among the plurality of sacrificial semiconductor layers 106S, the thickness of the sacrificial semiconductor layer 106S closest to the substrate 110 may be greater than the thickness of each of the remaining sacrificial semiconductor layers 106S.

[0024] The substrate 110 may include an elemental semiconductor material (such as Si or Ge) or a compound semiconductor material (such as SiGe, SiC, GaAs, InAs, or InP). In an embodiment of the inventive concept, the substrate 110 may include at least one of a group III-V material and a group IV material. The group III-V material may be a binary, ternary, or quaternary compound including at least one group III element and at least one group V element. In an embodiment of the inventive concept, when an n-type metal oxide semiconductor (NMOS) transistor is formed on a portion of the substrate 110, a portion of the substrate 110 may include any one of the group III-V materials exemplified above. In an embodiment of the inventive concept, when a p-type metal oxide semiconductor (PMOS) transistor is formed on a portion of the substrate 110, a portion of the substrate 110 may include Ge. In one example, the substrate 110 may have a semiconductor-on-insulator (SOI) structure. The substrate 110 may include a conductive region, such as an impurity-doped well or an impurity-doped structure.

[0025] Etch a stacked structure of the plurality of sacrificial semiconductor layers 106S and the plurality of nanosheet semiconductor layers and a portion of the substrate 110 to form a plurality of fin active regions FA in the substrate 110. The plurality of fin active regions FA may protrude upward from a main surface of the substrate 110 in a vertical direction (Z direction). In an embodiment of the inventive concept, the plurality of fin active regions FA may extend in a first horizontal direction (X direction). In an embodiment of the inventive concept, each of the plurality of fin active regions FA may have the same width in a second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction).

[0026] A surface of the substrate 110 on which the plurality of fin active regions FA are formed (i.e., an active surface of the substrate 110) may be referred to as a front surface. In the present specification, the front surface of the substrate 110 may be the surface facing upward in the Figures 2A to 34B midplane. For example, the front surface of the substrate 110 may be referred to as the top surface of the substrate 110. In the present specification, a surface of the substrate 110 opposite to the front surface (i.e., a non-active surface of the substrate 110) may be referred to as a back surface of the substrate 110. In the present specification, the back surface of the substrate 110 may be the surface facing downward in the Figures 2A to 34B midplane. For example, the back surface of the substrate 110 may be referred to as the bottom surface of the substrate 110.

[0027] A nanosheet stack structure NSS (which is a stacked structure of the plurality of sacrificial semiconductor layers 106S and the plurality of nanosheets N1, N2, and N3) may be disposed on each of the plurality of fin active regions FA. The plurality of nanosheet stack structures NSS may be formed by removing a portion of the plurality of nanosheet semiconductor layers by etching. The plurality of nanosheet stack structures NSS may be arranged at a pitch of about 30 nm to about 50 nm in the second horizontal direction (Y direction).

[0028] Form a device isolation layer 120 to fill at least a portion of a space between the plurality of fin active regions FA. In an embodiment of the inventive concept, the device isolation layer 120 may fill a lower portion of the space between the plurality of fin active regions FA, and the plurality of fin active regions FA may protrude in a vertical direction (Z direction) beyond a top surface of the device isolation layer 120. The device isolation layer 120 may include, for example, a material including at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0029] Refer together to Figure 3A and Figure 3B, a plurality of dummy gate structures DGS having a stacked structure with a plurality of dummy insulating layers D145 and a plurality of dummy gate electrodes D150 are formed on the plurality of fin-type active regions FA in which the plurality of nanosheet stacked structures NSS and the plurality of sacrificial semiconductor layers 106S are formed. The plurality of dummy insulating layers D145 extend to cross at least a part of the plurality of fin-type active regions FA. The plurality of dummy gate structures DGS may be parallel to each other and spaced apart from each other in a first horizontal direction (X direction), and may extend in a second horizontal direction (Y direction).

[0030] The dummy insulating layer D145 and the dummy gate electrode D150 are sequentially formed to cover the exposed surfaces of the plurality of nanosheet stacked structures NSS and the plurality of sacrificial semiconductor layers 106S (which cover the plurality of fin-type active regions FA), the exposed surfaces of the plurality of fin-type active regions FA, and the top surface of the device isolation layer 120, and then patterned to form the dummy gate structures DGS such that only necessary portions of the dummy insulating layer D145 and the dummy gate electrode D150 remain, and a gate spacer 155 covering the side surfaces of each of the plurality of dummy gate structures DGS is formed. The dummy insulating layer D145 may include an oxide, and the dummy gate electrode D150 may include a semiconductor material. However, the inventive concept is not limited thereto. In an embodiment of the inventive concept, the dummy insulating layer D145 may include silicon oxide, and the dummy gate electrode D150 may include polysilicon. The gate spacer 155 may include silicon nitride. However, the inventive concept is not limited thereto. The gate spacer 155 may include a single layer or a stacked structure of two or more layers.

[0031] Refer together to Figure 4A and Figure 4B , by removing portions of the plurality of nanosheet stacked structures NSS and portions of the plurality of sacrificial semiconductor layers 106S, a plurality of source / drain recesses 160RS may be formed to expose portions of the plurality of fin-type active regions FA, and each fin-type active region FA is disposed between a pair of dummy gate structures DGS adjacent to each other in the first horizontal direction (X direction). In an embodiment of the inventive concept, in the process of forming the plurality of source / drain recesses 160RS, the upper portions of the plurality of fin-type active regions FA may be partially removed. After removing portions of the plurality of nanosheet stacked structures NSS, the plurality of nanosheet stacked structures NSS may be arranged in rows and columns in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0032] Refer together to Figure 5A and Figure 5B, after locally removing portions of the plurality of fin-type active regions FA exposed at bottom surfaces of the plurality of source / drain recesses 160RS, a placeholder structure PH is formed in a space from which the locally removed exposed portions of the plurality of fin-type active regions FA have been removed. In an embodiment of the inventive concept, the placeholder structure PH may include a semiconductor material. For example, the placeholder structure PH may include a compound semiconductor such as SiGe. The placeholder structure PH may have a horizontal width of about 7 nm to about 20 nm. The placeholder structure PH may have a height of about 30 nm to about 70 nm.

[0033] Refer together to Figure 6A and Figure 6B , the plurality of source / drain regions 160 are formed to fill portions of the plurality of source / drain recesses 160RS by epitaxially growing a semiconductor material both from exposed side surfaces of each of the plurality of nanosheets N1, N2, and N3 and from exposed surfaces of the fin-type active regions FA. In an embodiment of the inventive concept, when an upper portion of the plurality of fin-type active regions FA is partially removed in a process of forming the plurality of source / drain recesses 160RS, the plurality of source / drain regions 160 may be formed to extend inwardly from top surfaces of the plurality of fin-type active regions FA. In an embodiment of the inventive concept, the source / drain regions 160 may be formed such that their top surfaces have an angular shape, that is, a facet. The source / drain regions 160 may have a horizontal width of about 15 nm to about 30 nm.

[0034] Since the plurality of placeholder structures PH are formed after locally removing portions of the plurality of fin-type active regions FA exposed at bottom surfaces of the plurality of source / drain recesses 160RS and the plurality of source / drain regions 160 are formed to fill portions of the plurality of source / drain recesses 160RS, each of the plurality of source / drain regions 160 may be aligned with a corresponding placeholder structure PH among the plurality of placeholder structures PH in a vertical direction (Z direction).

[0035] In an embodiment of the inventive concept, some of the plurality of source / drain regions 160 and other portions may include different materials, and some of the plurality of source / drain regions 160 including different materials and other portions may be formed by performing separate epitaxial growth processes, respectively. For example, some of the plurality of source / drain regions 160 may include Ge. In an embodiment of the inventive concept, some of the plurality of source / drain regions 160 may have a multi-layer structure including a semiconductor material including Si and a semiconductor material including Ge. For example, other source / drain regions of the plurality of source / drain regions 160 may include Si but not Ge. In an embodiment of the inventive concept, other source / drain regions of the plurality of source / drain regions 160 may have a multi-layer structure including a semiconductor material including Si, a semiconductor material such as Si, or a compound semiconductor material such as SiC.

[0036] In an embodiment of the inventive concept, the source / drain region 160 in the case of forming an NMOS transistor and the source / drain region 160 in the case of forming a PMOS transistor may include different materials from each other and may be formed by performing respective epitaxial growth processes.

[0037] Each of the plurality of source / drain regions 160 may include a source region 160A and a drain region 160B. In an embodiment of the inventive concept, the source region 160A and the drain region 160B may be alternately arranged in a first horizontal direction (X direction). The source region 160A and the drain region 160B may be connected to both ends of each of the plurality of nanosheets N1, N2, and N3 in the first horizontal direction (X direction), respectively. For example, the source region 160A may be connected to one end of each of the plurality of nanosheets N1, N2, and N3, and the drain region 160B may be connected to the other end (e.g., the opposite end) of each of the plurality of nanosheets N1, N2, and N3.

[0038] Refer to together Figure 7A and Figure 7B After forming the plurality of source / drain regions 160, an etch stop layer 165 is formed to cover the surfaces of the plurality of source / drain regions 160. The etch stop layer 165 may conformally cover the surfaces of the plurality of source / drain regions 160 and the top surface of the device isolation layer 120. For example, the etch stop layer 165 may include a nitride. In an embodiment of the inventive concept, the etch stop layer 165 may include silicon nitride.

[0039] An inter-gate insulating layer 180 is formed to cover the etch stop layer 165 and fill the space between the plurality of dummy gate structures DGS. The inter-gate insulating layer 180 may fill the space between the plurality of dummy gate structures DGS and surround the plurality of source / drain regions 160. For example, the inter-gate insulating layer 180 fills the space between adjacent dummy gate structures DGS. The inter-gate insulating layer 180 may include a silicon oxide layer. In an embodiment of the inventive concept, the inter-gate insulating layer 180 may have a stacked structure of two or more layers, the two or more layers including a first layer containing silicon nitride and a second layer containing silicon oxide. The etch stop layer 165 may be interposed between the source / drain region 160 and the inter-gate insulating layer 180.

[0040] Referring together Figure 7A , Figure 7B and Figures 8A to 8B , the plurality of dummy gate electrodes D150 and the plurality of dummy insulating layers D145 are removed and the plurality of sacrificial semiconductor layers 106S remaining on the fin-type active region FA are removed to form a plurality of removal spaces RS. When the plurality of dummy gate electrodes D150 and the plurality of dummy insulating layers D145 are removed, the plurality of sacrificial semiconductor layers 106S between the plurality of nanosheets N1, N2, and N3 are exposed on the fin-type active region FA, and the plurality of sacrificial semiconductor layers 106S may be removed through the space from which the plurality of dummy gate electrodes D150 and the plurality of dummy insulating layers D145 have been removed. The plurality of removal spaces RS may be spaces formed when the plurality of dummy gate electrodes D150, the plurality of dummy insulating layers D145, and the plurality of sacrificial semiconductor layers 106S are removed.

[0041] Referring together Figure 9A and Figure 9B , the plurality of gate insulating layers 145 are formed on the surface exposed to the plurality of removal spaces RS, and the plurality of gate electrodes 150 are formed on the plurality of gate insulating layers 145 to fill at least part of the plurality of removal spaces RS. The plurality of gate electrodes 150 may extend parallel to each other in a second horizontal direction (Y direction).

[0042] The gate insulating layer 145 may include, for example, silicon oxide, a high-k material, or a combination thereof. For example, the gate insulating layer 145 may have a stacked structure of an interfacial layer and a high-k layer. In an embodiment of the inventive concept, the interfacial layer may include a low-k layer having a dielectric constant of about 9 or less, such as silicon oxide, silicon oxynitride, or a combination thereof. In an embodiment of the inventive concept, the interfacial layer may be omitted. The high-k layer may include a material having a dielectric constant greater than that of silicon oxide. The high-k layer may include a metal oxide or a metal oxynitride. The high-k layer may include a material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k layer may have a dielectric constant of about 10 to about 25.

[0043] The high-k layer may include, for example, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, lanthanum aluminate, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, lead zinc niobate, and combinations thereof. However, the inventive concept is not limited thereto. The high-k layer may be formed by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process. The high-k layer may have a thickness of about to about . However, the inventive concept is not limited thereto.

[0044] The gate electrode 150 may include a metal-containing layer for controlling the work function and a metal-containing layer for gap filling that fills a removal space on the metal-containing layer for controlling the work function. The metal-containing layer for controlling the work function may include, for example, at least one of titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and / or palladium (Pd). In an embodiment of the inventive concept, the gate electrode 150 may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-fill metal layer are stacked in sequence. The metal nitride layer and the metal layer may include, for example, at least one of Ti, tantalum (Ta), W, Ru, Nb, Mo, and Hf. The gap-fill metal layer may include, for example, a W layer or an aluminum (Al) layer. In an embodiment of the inventive concept, the gate electrode 150 may include a stacked structure of TiAlC / TiN / W, a stacked structure of TiN / TaN / TiAlC / TiN / W, or a stacked structure of TiN / TaN / TiN / TiAlC / TiN / W. However, the inventive concept is not limited thereto.

[0045] The gate electrode 150 includes a plurality of sub-gate portions 150S and a main gate portion 150M. Each of the plurality of sub-gate portions 150S is formed in the space between each of the plurality of nanosheets N1, N2, and N3 and between the fin-type active region FA and the first nanosheet N1 of the plurality of nanosheets N1, N2, and N3. The main gate portion 150M is connected to the plurality of sub-gate portions 150S and covers the nanosheet stack structure NSS including the plurality of nanosheets N1, N2, and N3. In an embodiment of the inventive concept, a plurality of insulating spacers may be disposed at both ends of each of the plurality of sub-gate portions 150S, and the gate insulating layer 145 is therebetween.

[0046] A plurality of gate capping layers 175 may be formed on the plurality of gate electrodes 150 and the gate insulating layer 145. The plurality of gate capping layers 175 may respectively cover the plurality of gate electrodes 150. The gate capping layer 175 may include, for example, a nitride. In an embodiment of the inventive concept, the top surfaces of the plurality of gate capping layers 175 and the top surface of the inter-gate insulating layer 180 may be substantially coplanar with each other at substantially the same vertical level. For example, the plurality of gate insulating layers 145, the plurality of gate electrodes 150, and the plurality of gate capping layers 175 may fill all of the plurality of removal spaces RS. For example, after forming the plurality of gate insulating layers 145 on the surfaces exposed to the plurality of removal spaces RS, forming the plurality of gate electrodes 150 that fill the plurality of removal spaces RS and cover the plurality of gate insulating layers 145, and removing the portions of the plurality of gate insulating layers 145 that fill the upper portions of the plurality of removal spaces RS and the portions of the plurality of gate electrodes 150 that fill the upper portions of the plurality of removal spaces RS, the plurality of gate capping layers 175 may be formed to fill the upper portions of the plurality of removal spaces RS. The plurality of gate electrodes 150, the plurality of gate capping layers 175, the plurality of gate insulating layers 145, and the plurality of gate spacers 155 may respectively form a plurality of gate structures.

[0047] Referring together Figure 10A and Figure 10B , the contact plug CA is formed to pass through the inter-gate insulating layer 180 and the etch stop layer 165 and contact and electrically connect to the corresponding source / drain region 160. In addition, a gate contact plug may be formed to pass through the gate capping layer 175 and contact and electrically connect to the gate electrode 150.

[0048] In an embodiment of the inventive concept, the contact plug CA and the gate contact plug may include a conduction barrier layer and a conductive core layer covering the conduction barrier layer. The conduction barrier layer may include, for example, Ti, Ta, TiN, TaN, or a combination thereof, and the conductive core layer may include, for example, Co, W, copper (Cu), Ru, iridium (Ir), Mo, or a combination thereof.

[0049] In an embodiment of the inventive concept, the contact plug CA may be connected to the drain region 160B among the plurality of source / drain regions 160, but may not be connected to the source region 160A. For example, the contact plug CA may pass through the inter-gate insulating layer 180 and may contact and be electrically connected to the drain region 160B among the plurality of source / drain regions 160.

[0050] Referring together Figure 11A and Figure 11B , a lower portion of the substrate 110 is partially removed to expose the dummy structure PH and the device isolation layer 120. The lower portion of the substrate 110 may be partially removed by performing a back-lap process or a backgrinding process. A portion of the substrate 110 may be interposed between the device isolation layer 120 and the dummy structure PH in a second horizontal direction (Y direction). In the process of partially removing the lower portion of the substrate 110, a lower portion of the dummy structure PH may also be partially removed. For example, after partially removing the lower portion of the substrate 110, the dummy structure PH may have a height of about 25 nm to about 60 nm.

[0051] Referring together Figure 12A and Figure 12B , a lower portion of the exposed dummy structure PH is partially removed to form a dummy recess PHR. The dummy recess PHR may extend upward from the bottom surface of the substrate 110 toward an upper portion of the dummy recess PHR. The substrate 110 may surround the dummy recess PHR. The dummy recess PHR may be defined by the substrate 110 and the dummy structure PH.

[0052] Referring together Figure 13A and Figure 13B , a hard mask material layer 210P is formed to fill the dummy recess PHR and cover the bottom surface of the substrate 110 and the bottom surface of the device isolation layer 120. The hard mask material layer 210P may include a material having an etching selectivity with respect to the substrate 110 and the device isolation layer 120. In an embodiment of the inventive concept, the hard mask material layer 210P may include a material having an etching selectivity with respect to each of the substrate 110, the device isolation layer 120, and the dummy structure PH. For example, the hard mask material layer 210P may include TiN, AlO, or AlN. However, the inventive concept is not limited thereto. In an embodiment of the inventive concept, the hard mask material layer 210P may include a material that can be removed by a wet etching process.

[0053] Referring together Figure 13A , Figure 13B , Figure 14A and Figure 14B, a portion of the hard mask material layer 210P is removed to form a hard mask layer 210 that fills the placeholder recess PHR. The hard mask layer 210 can be formed by partially removing the lower portion of the hard mask material layer 210P until the substrate 110 and the device isolation layer 120 are exposed. In an embodiment of the inventive concept, the hard mask layer 210 can be formed by performing a wet etching process to partially remove the lower portion of the hard mask material layer 210P. The hard mask layer 210 can be formed to have a thickness of about 5 nm to about 8 nm.

[0054] Referring together to Figure 15A and Figure 15B , the lower portion of the substrate 110 is partially removed to form a substrate recess 110R. The side surfaces of the hard mask layer 210 and a portion of the side surfaces of the placeholder structure PH can be exposed in the substrate recess 110R. The substrate recess 110R can be formed by performing an etching process that has an etching selectivity with respect to the hard mask layer 210, the placeholder structure PH, and the device isolation layer 120 to partially remove the lower portion of the substrate 110. In an embodiment of the inventive concept, the substrate recess 110R can be formed by performing a dry etching process and a wet etching process together to partially remove the lower portion of the substrate 110. The substrate recess 110R can be defined by the bottom surface of the substrate 110, the side surfaces of the hard mask layer 210, and the side surfaces of the placeholder structure PH.

[0055] In an embodiment of the inventive concept, after partially removing the lower portion of the substrate 110 to form the substrate recess 110R, the bottom surface of the substrate 110 can be at a first vertical level LV1. The first vertical level LV1 can be the lowest vertical level of the etch stop layer 165. The first vertical level LV1 can be lower than the lowermost end of the source / drain region 160. The first vertical level LV1 can be lower than the top surface of the substrate 110.

[0056] Referring together to Figure 15A , Figure 15B , Figure 16A and Figure 16B , the device isolation layer 120 is removed to further expose the side surfaces of the hard mask layer 210 and a portion of the side surfaces of the placeholder structure PH. After removing the device isolation layer 120, the etch stop layer 165 can be exposed. For example, portions of the side surfaces of the hard mask layer 210 and the placeholder structure PH that are lower than the first vertical level LV1 can be exposed.

[0057] Referring together to Figure 17A and Figure 17B, a spacer material layer 220P is formed to cover the bottom surface of the substrate 110, the bottom surface of the etch stop layer 165, the side and bottom surfaces of the hard mask layer 210, and the side surfaces of the placeholder structure PH. The spacer material layer 220P can be formed to conformally cover the bottom surface of the substrate 110, the bottom surface of the etch stop layer 165, the side and bottom surfaces of the hard mask layer 210, and the side surfaces of the placeholder structure PH. For example, the spacer material layer 220P can be formed to not completely fill the substrate recess 110R. The spacer material layer 220P can include a material having an etch selectivity with respect to the substrate 110 and the placeholder structure PH. For example, the spacer material layer 220P can include silicon oxide, silicon oxynitride, silicon oxycarbide, or silicon carbonitride. However, the inventive concept is not limited thereto. The spacer material layer 220P can be formed to have a thickness of about 5 nm to about 10 nm.

[0058] Refer together to Figure 17A , Figure 17B , Figure 18A and Figure 18B , anisotropic etching is performed to remove a part of the spacer material layer 220P to form a spacer layer 220. The spacer layer 220 can cover the side surfaces of the hard mask layer 210 and the lower portions of the side surfaces of the placeholder structure PH. For example, the spacer layer 220 can expose the hard mask layer 210. In an embodiment of the inventive concept, in the process of removing a part of the spacer material layer 220P to form the spacer layer 220, the lower portions of the substrate 110 and the inter-gate insulating layer 180 can be partially removed. For example, the lower portion of the inter-gate insulating layer 180 can be partially removed such that a part of the bottom surface of the inter-gate insulating layer 180 can be at a second vertical level LV2 that is higher than the remaining part of the bottom surface of the inter-gate insulating layer 180. The second vertical level LV2 is higher than the first vertical level LV1.

[0059] Refer together to Figure 19A and Figure 19B , the exposed part of the substrate 110 between the spacer layers 220 is removed to form a substrate hole 110H that exposes the gate insulating layer 145 surrounding the lowermost sub-gate part 150S among the plurality of sub-gate parts 150S.

[0060] In an embodiment of the inventive concept, the substrate hole 110H may be formed as follows: by performing a dry etching process to remove a portion of the substrate 110 until the gate insulating layer 145 surrounding the lowermost sub-gate portion 150S among the plurality of sub-gate portions 150S is exposed; and then performing a wet etching process to expose the gate insulating layer 145 and remove another portion of the substrate 110. The uppermost end of the substrate hole 110H (i.e., the lowermost end of the gate insulating layer 145 surrounding the lowermost sub-gate portion 150S among the plurality of sub-gate portions 150S) may be at a third vertical level LV3 higher than the second vertical level LV2.

[0061] Refer together to Figure 20A and Figure 20B , a covering insulating material layer 230P is formed to fill the substrate hole 110H and cover the inter-gate insulating layer 180, the spacer layer 220, and the hard mask layer 210. The covering insulating material layer 230P may include a nitride. In an embodiment of the inventive concept, the covering insulating material layer 230P may include silicon nitride. The covering insulating material layer 230P may be formed to have a predetermined thickness to cover the spacer layer 220 and the hard mask layer 210. For example, the bottom surface of the covering insulating material layer 230P may be at a vertical level lower than the lowermost end of the spacer layer 220 and the lowermost end of the hard mask layer 210.

[0062] Refer together to Figure 20A , Figure 20B , Figure 21A and Figure 21B , a lower portion of the covering insulating material layer 230P is partially removed to form a covering insulating layer 230. The covering insulating layer 230 may be formed by partially removing the lower portion of the covering insulating material layer 230P until the hard mask layer 210 is exposed. For example, the covering insulating layer 230 may be formed by performing a chemical mechanical polishing (CMP) process to partially remove the lower portion of the covering insulating material layer 230P.

[0063] Refer together to Figure 22A and Figure 22B , a post-insulating layer 240 is formed to cover the bottom of the covering insulating layer 230 and the bottom of the hard mask layer 210. The post-insulating layer 240 may include an oxide. For example, the post-insulating layer 240 may include silicon oxide. In an embodiment of the inventive concept, the post-insulating layer 240 may include a high density plasma (HDP) oxide or a tetraethyl orthosilicate (TEOS) oxide.

[0064] Refer together to Figure 23A and Figure 23B, a portion of the rear insulating layer 240 is removed to form a rear through hole 240H that penetrates the rear insulating layer 240. The hard mask layer 210 may be exposed in the rear through hole 240H. For example, the bottom surface of the hard mask layer 210 may be the top surface of the rear through hole 240H. The rear through hole 240H may not overlap with the source / drain region 160 connected to the contact plug CA in the vertical direction (Z direction), but may overlap with the source / drain region 160 not connected to the contact plug CA. In an embodiment of the inventive concept, the hard mask layer 210 exposed in the rear through hole 240H may cover the bottom surface of the placeholder structure PH under the source region 160A. For example, the rear through hole 240H may overlap with the source region 160A in the vertical direction (Z direction), but may not overlap with the drain region 160B.

[0065] Refer to together Figure 23A , Figure 23B , Figure 24A and Figure 24B , the hard mask layer 210 and the placeholder structure PH are removed through the rear through hole 240H to expose the source / drain region 160. The rear through hole 240H may be an extended through hole 240HE having a space from which the hard mask layer 210 and the placeholder structure PH are removed. The source / drain region 160 may be exposed through the extended through hole 240HE.

[0066] The extended through hole 240HE may not overlap with the source / drain region 160 connected to the contact plug CA in the vertical direction (Z direction), but may overlap with the source / drain region 160 not connected to the contact plug CA. In an embodiment of the inventive concept, the source region 160A may be exposed in the extended through hole 240HE. For example, the extended through hole 240HE may overlap with the source region 160A in the vertical direction (Z direction), but may not overlap with the drain region 160B.

[0067] Refer to together Figure 25A and Figure 25B , a portion of the source / drain region 160 exposed through the extended through hole 240HE is removed. For example, for example, a portion of the source region 160A exposed through the extended through hole 240HE may be removed.

[0068] Figure 26A and Figure 26B are cross-sectional views showing an integrated circuit device 1 according to an embodiment of the inventive concept. Specifically, Figure 26A is a cross-sectional view taken along line A-A' of Figure 1 , Figure 26B is a cross-sectional view taken along line B-B' of Figure 1 .

[0069] Refer to together Figure 26A andFigure 26B , an integrated circuit device 1 is formed by forming a back contact plug 250 that fills the extended through hole 240HE. The back contact plug 250 may include a back conduction barrier layer that covers the surfaces of the source / drain regions 160 exposed in the extended through hole 240HE, the surface of the substrate 110, the surface of the spacer layer 220, and the surface of the back insulation layer 240. The back contact plug 250 may additionally include a back conduction core layer that covers the back conduction barrier layer and fills the extended through hole 240HE. In an embodiment of the inventive concept, the back conduction barrier layer may conformally cover the surfaces of the source / drain regions 160 exposed in the extended through hole 240HE, the surface of the substrate 110, the surface of the spacer layer 220, and the surface of the back insulation layer 240. The back conduction barrier layer may include, for example, Ti, Ta, TiN, TaN, or a combination thereof, and the back conduction core layer may include, for example, Co, W, Cu, Ru, Ir, Mo, or a combination thereof. The back contact plug 250 may be Figure 1 the back contact plug BCA shown.

[0070] The integrated circuit device 1 may be a logic semiconductor chip. For example, the integrated circuit device 1 may be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0071] In the present specification, a logic semiconductor chip refers to a non-memory semiconductor chip that performs logic operations. For example, a logic semiconductor chip may include logic units. In an embodiment of the inventive concept, a logic semiconductor chip may include both logic units and storage units.

[0072] Referring together to Figure 1 , Figure 26A and Figure 26B , the integrated circuit device 1 includes a back insulation layer 240, a covering insulation layer 230 and a substrate 110 on the back insulation layer 240, the plurality of nanosheet stack structures NSS on the covering insulation layer 230 and the substrate 110, and the plurality of gate electrodes 150 that extend parallel to each other in a second horizontal direction (Y direction) crossing a first horizontal direction (X direction) on the substrate 110, the covering insulation layer 230, and the plurality of nanosheet stack structures NSS. The gate electrode 150 may be Figure 1 the gate electrode GL shown.

[0073] The substrate 110 may have the plurality of substrate holes 110H passing through the substrate 110, and the covering insulating layer 230 may fill the plurality of substrate holes 110H. In an embodiment of the inventive concept, the integrated circuit device 1 may include a multi-gate metal oxide semiconductor field effect transistor (MOSFET) formed through a nanosheet stack structure NSS. The nanosheet stack structure NSS may be referred to as a channel region. In an embodiment of the inventive concept, the multi-gate MOSFET included in the integrated circuit device 1 may be formed through an upper portion of the substrate 110 and the nanosheet stack structure NSS. For example, the upper portion of the substrate 110 and the nanosheet stack structure NSS may constitute a channel region. The channel region may extend in a first horizontal direction (X direction). The plurality of gate insulating layers 145 may be interposed between the channel region and the plurality of gate electrodes 150.

[0074] In the present specification, the integrated circuit device 1 is described as including a multi-gate MOSFET. However, the inventive concept is not limited thereto. For example, it may be apparent to those skilled in the art that the integrated circuit device 1 may include a single-gate MOSFET formed through a fin-type active region FA (refer to Figure 2A and Figure 2B ) instead of a multi-gate MOSFET formed through the nanosheet stack structure NSS. When the integrated circuit device 1 includes a single-gate MOSFET formed through the fin-type active region FA (instead of a multi-gate MOSFET formed through the nanosheet stack structure NSS), the fin-type active region FA may be referred to as a channel region.

[0075] Each of the plurality of nanosheet stack structures NSS may include a plurality of nanosheets N1, N2, and N3, which are arranged to be spaced apart from a top surface of the substrate 110 in a vertical direction (Z direction). The plurality of nanosheets N1, N2, and N3 may extend parallel to the top surface of the substrate 110. Each of the plurality of nanosheets N1, N2, and N3 may have a length of about 5 nm to about 30 nm in the first horizontal direction (X direction).

[0076] The plurality of nanosheets N1, N2, and N3 constituting one nanosheet stack structure NSS are sequentially stacked on the top surface of the substrate 110. In the present example, a case where one nanosheet stack structure NSS includes three nanosheets N1, N2, and N3 is shown. However, the inventive concept is not limited thereto. For example, the plurality of nanosheets N1, N2, and N3 may include a single material. In an embodiment of the inventive concept, the plurality of nanosheets N1, N2, and N3 may include the same material as that of the substrate 110.

[0077] On the substrate 110 and the plurality of nanosheet stack structures NSS, the plurality of gate electrodes 150 may extend parallel to each other in a second horizontal direction (Y direction) intersecting a first horizontal direction (X direction). At least a portion of each of the plurality of gate electrodes 150 may overlap with each of the plurality of nanosheet stack structures NSS in a vertical direction (Z direction).

[0078] Each of the plurality of gate electrodes 150 may cover the nanosheet stack structure NSS and surround at least a portion of the plurality of nanosheets N1, N2, and N3. The gate electrode 150 may include a main gate portion 150M and the plurality of sub - gate portions 150S. The main gate portion 150M may cover a side surface of the nanosheet stack structure NSS, and the plurality of sub - gate portions 150S may be connected to the main gate portion 150M and formed in spaces between the substrate 110 and the first nanosheet N1 and between the plurality of nanosheets N1, N2, and N3. A gate insulating layer 145 is formed on the gate electrode 150. The gate insulating layer 145 may be formed between the nanosheet stack structure NSS and the gate electrode 150. For example, the gate insulating layer 145 may be disposed between the main gate portion 150M and the third nanosheet N3 among the plurality of nanosheets N1, N2, and N3, between the plurality of nanosheets N1, N2, and N3 and the plurality of sub - gate portions 150S, between the substrate 110 and the lowermost sub - gate portion 150S among the plurality of sub - gate portions 150S, and between the source / drain regions 160 and the gate electrode 150. The plurality of gate capping layers 175 may be respectively disposed on the plurality of gate electrodes 150. The plurality of gate capping layers 175 may respectively cover the plurality of gate electrodes 150.

[0079] The plurality of gate spacers 155 may respectively cover side surfaces of the plurality of gate electrodes 150. In an embodiment of the inventive concept, the plurality of gate spacers 155 may cover the side surfaces of the plurality of gate electrodes 150, with the plurality of gate insulating layers 145 therebetween. In an embodiment of the inventive concept, the plurality of gate spacers 155 may respectively cover the side surfaces of the plurality of gate electrodes 150 and the side surfaces of the plurality of gate capping layers 175. The uppermost ends of the gate electrodes 150 and the uppermost ends of the gate insulating layers 145 are shown at substantially the same vertical level. However, the inventive concept is not limited thereto. In an embodiment of the inventive concept, the uppermost end of the gate insulating layer 145 may be at a higher vertical level than the uppermost end of the gate electrode 150, but may be at a vertical level substantially the same as the vertical level of the uppermost end of the gate capping layer 175 or at a vertical level lower than the vertical level of the uppermost end of the gate capping layer 175.

[0080] In an embodiment of the inventive concept, the gate spacer 155 may cover two side surfaces of the gate electrode 150 in a first horizontal direction (X direction) and two side surfaces of the gate electrode 150 in a second horizontal direction (Y direction), and may completely surround the gate electrode 150 in a top view. The plurality of gate electrodes 150, the plurality of gate capping layers 175, the plurality of gate insulating layers 145, and the plurality of gate spacers 155 may form the plurality of gate structures, respectively.

[0081] The gate electrode 150 may be formed by using a replacement metal gate (RMG) process. For example, after forming a dummy insulating layer D145 (refer to Figure 3A ) and a dummy gate electrode D150 (refer to Figure 3A ) on the fin-type active region FA, a gate spacer 155 surrounding the dummy insulating layer D145 and the dummy gate electrode D150 may be formed, and after removing the dummy insulating layer D145 and the dummy gate electrode D150, a gate insulating layer 145 and a gate electrode 150 may be formed in the space surrounded by the gate spacer 155.

[0082] The plurality of source / drain regions 160 are formed on the substrate 110. Each of the plurality of source / drain regions 160 is connected to one end of each of the plurality of nanosheets N1, N2, and N3. Each of the plurality of source / drain regions 160 may be formed on a portion of the substrate 110 between a pair of gate electrodes 150 adjacent to each other in a first horizontal direction (X direction). In an embodiment of the inventive concept, the plurality of source / drain regions 160 may extend inward from the top surface of the substrate 110. In an embodiment of the inventive concept, the plurality of source / drain regions 160 may extend inward from the top surface of the substrate 110, but may not extend to the bottom surface of the substrate 110. Each of the plurality of source / drain regions 160 may include a source region 160A and a drain region 160B. In an embodiment of the inventive concept, the source region 160A and the drain region 160B may be alternately arranged in a first horizontal direction (X direction).

[0083] An etch stop layer 165 may conformally cover the surfaces of the plurality of source / drain regions 160, and an inter-gate insulating layer 180 may fill the space between the plurality of gate structures. In an embodiment of the inventive concept, the inter-gate insulating layer 180 may cover the etch stop layer 165, may fill the space between the plurality of gate structures, and may surround the plurality of source / drain regions 160.

[0084] The contact plug CA can pass through the inter-gate insulating layer 180 and the etch stop layer 165 and be electrically connected to the source / drain region 160. In an embodiment of the inventive concept, the contact plug CA can be electrically connected to the drain region 160B, but may not be electrically connected to the source region 160A. In some embodiments, the contact plug CA can be formed to have a tapered shape, where the horizontal width of the contact plug CA decreases as it extends from the top to the bottom in the vertical direction (Z direction).

[0085] The plurality of spacer layers 220 can be disposed on the bottom surface of the substrate 110, and the substrate 110 can have a substrate hole 110H that exposes the gate insulating layer 145 surrounding the lowermost sub-gate portion 150S among the plurality of sub-gate portions 150 through a portion of the substrate 110 that is exposed between a pair of adjacent spacer layers 220. The substrate hole 110H can have a horizontal width of about 7 nm to about 20 nm in a first horizontal direction (X direction). The covering insulating layer 230 can fill the substrate hole 110H under the inter-gate insulating layer 180 and the etch stop layer 165. The post-insulating layer 240 can cover the bottom of the covering insulating layer 230 and the bottom of the hard mask layer 210.

[0086] The extended vias 240HE can pass through the back insulating layer 240, the capping insulating layer 230, and the substrate 110 and extend into at least some of the plurality of source / drain regions 160. The back contact plugs 250 can fill the extended vias 240HE and can be connected to the source / drain regions 160. The back contact plugs 250 can pass through the back insulating layer 240 and the capping insulating layer 230 and be connected to the source / drain regions 160. The spacer layer 220 or the spacer layer 220 and the substrate 110 can be interposed between the back contact plugs 250 and the capping insulating layer 230. For example, the back contact plugs 250 can extend from the bottom surface of the source / drain regions 160 into the source / drain regions 160 by about 10 nm to about 20 nm. The back contact plugs 250 can extend from the bottom surface of the back insulating layer 240 through the back surface of the substrate 110 to the source / drain regions 160. The back insulating layer 240, the spacer layer 220, and the substrate 110 can surround the back contact plugs 250 and / or the dummy structure PH. The spacer layer 220 surrounding the back contact plugs 250 or the dummy structure PH can be interposed between the back insulating layer 240 and the substrate 110. The thickness of the spacer layer 220 covering the back contact plugs 250 or the dummy structure PH can be about 5 nm to about 10 nm in the horizontal direction. In an embodiment of the inventive concept, the back contact plugs 250 can be connected to the source region 160A, but may not be connected to the drain region 160B among the plurality of source / drain regions 160. The dummy structure PH can be connected to the drain region 160B, but may not be connected to the source region 160A among the plurality of source / drain regions 160. The spacer layer 220 surrounding the back contact plugs 250 can be referred to as a contact spacer layer, and the spacer layer 220 surrounding the dummy structure PH can be referred to as a dummy spacer layer. For example, the plurality of spacer layers 220 can include a contact spacer layer and a dummy spacer layer.

[0087] In an embodiment of the inventive concept, the back contact plug 250 may have a narrowed shape in which the horizontal width of the back contact plug 250 decreases as it extends from the bottom to the top in the vertical direction (Z direction). For example, the back contact plug 250 may have a horizontal width of about 30 nm to about 60 nm at the lowermost end and may have a horizontal width of about 10 nm to about 15 nm at the portion contacting the source / drain region 160. At the portion where the back contact plug 250 contacts the source / drain region 160, the horizontal width of the back contact plug 250 may be smaller than the horizontal width of the source / drain region 160. For example, the back contact plug 250 may have a horizontal width of about 12 nm to about 18 nm at the lowermost end portion contacting the spacer layer 220. In an embodiment of the inventive concept, the back contact plug 250 may have an indented portion that is recessed inward at a portion contacting the spacer layer 220. The indented portion of the back contact plug 250 may be at a vertical level that is higher than the lowermost vertical level of the spacer layer 220 and lower than the uppermost vertical level of the spacer layer 220.

[0088] The uppermost end of the spacer layer 220 may be at a vertical level lower than the uppermost vertical level of the back contact plug 250, and the lowermost end of the spacer layer 220 may be at a vertical level higher than the lowermost vertical level of the back contact plug 250. The uppermost end of the spacer layer 220 may contact the substrate 110 and the etch stop layer 165, and the lowermost end of the spacer layer 220 may contact the back insulating layer 240. The lowermost end of the spacer layer 220 may be at substantially the same vertical level as the bottom surface of the capping insulating layer 230 or the top surface of the back insulating layer 240. The uppermost end of the spacer layer 220 may be at a first vertical level LV1. The spacer layer 220 may have a spacer height H. In an X-Z cross section (i.e., a vertical cross section extending in the first horizontal direction (X direction) and passing through the center of the back contact plug 250 in a plan view) formed by the first horizontal direction (X direction) and the vertical direction (Z direction) and passing through the center of the back contact plug 250 in a plan view, and a Y-Z cross section (i.e., a vertical cross section extending in the second horizontal direction (Y direction) and passing through the center of the back contact plug 250 in a plan view) formed by the second horizontal direction (Y direction) and the vertical direction (Z direction) and passing through the center of the back contact plug 250 in a plan view, the spacer height H of the portion of the spacer layer 220 surrounding the back contact plug 250 may be substantially the same.

[0089] Refer together to Figures 1 to 26B, an integrated circuit device 1 according to an embodiment of the inventive concept includes a back contact plug 250 surrounded by a spacer layer 220 and connected to a source / drain region 160. The spacer layer 220 is formed to surround a placeholder structure PH aligned with the source / drain region 160 in a vertical direction (Z direction), and the back contact plug 250 is formed to fill a space defined by the spacer layer 220. Accordingly, the back contact plug 250 may be aligned with the source / drain region 160 in the vertical direction (Z direction). Since the spacer layer 220 surrounds the back contact plug 250, the structural stability of the back contact plug 250 may be increased.

[0090] Accordingly, since the integrated circuit device 1 according to an embodiment of the inventive concept includes the back contact plug 250 aligned with the source / drain region 160 in the vertical direction (Z direction) and connected to the source / drain region 160, a power delivery network (PDN) capable of performing reliable power delivery may be provided in the integrated circuit device 1.

[0091] Figures 27A to 29B is a cross-sectional view showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept. Specifically, Figure 27A , Figure 28A and Figure 29A are cross-sectional views taken along line A-A' of Figure 1 , Figure 27B , Figure 28B and Figure 29B are cross-sectional views taken along line B-B' of Figure 1 .

[0092] Referring together to Figure 21A , Figure 21B , Figure 27A and Figure 27B , the hard mask layer 210 may be removed to expose the bottom surface of the placeholder structure PH.

[0093] Referring together to Figure 28A and Figure 28B , a post-insulation layer 240a is formed to cover the bottom of the cover insulation layer 230. The post-insulation layer 240a may fill a space from which the Figure 21A and Figure 21B shown hard mask layer 210 has been removed. The post-insulation layer 240a may include an oxide. For example, the post-insulation layer 240a may include silicon oxide. The post-insulation layer 240a may have a structure that fills a space from which the Figure 21A and Figure 21BThe protruding space of the hard mask layer 210 as shown. The protrusion of the post-insulating layer 240a can protrude upward toward the placeholder structure PH to contact the placeholder structure PH and can be surrounded by the spacer layer 220. Since the post-insulating layer 240a includes a protrusion surrounded by the spacer layer 220, the bonding force with the upper structure (such as the capping insulating layer 230 and the spacer layer 220) can be increased.

[0094] Refer together to Figure 29A and Figure 29B , a part of the post-insulating layer 240a is removed to form a post-through hole 240Ha passing through the post-insulating layer 240a. The placeholder structure PH can be exposed in the post-through hole 240Ha. The post-through hole 240Ha may not overlap with the source / drain region 160 connected to the contact plug CA in the vertical direction (Z direction), but may overlap with the source / drain region 160 not connected to the contact plug CA. In an embodiment of the inventive concept, the placeholder structure PH exposed in the post-through hole 240Ha may be located under the source region 160A. For example, the post-through hole 240Ha may overlap with the source region 160A in the vertical direction (Z direction), but may not overlap with the drain region 160B.

[0095] Figure 30A and Figure 30B are cross-sectional views showing an integrated circuit device 1a according to an embodiment of the inventive concept. Specifically, Figure 30A is a cross-sectional view taken along the line A-A' of Figure 1 , Figure 30B is a cross-sectional view taken along the line B-B' of Figure 1 .

[0096] Refer together to Figure 30A and Figure 30B , in a manner similar to the way described with reference to Figures 24A to 26B , an extended through hole 240HEa is formed and a post-contact plug 250a filling the extended through hole 240HEa is formed to form the integrated circuit element 1a.

[0097] Figure 31A and Figure 31B are cross-sectional views showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept. Specifically, Figure 31A is a cross-sectional view taken along the line A-A' of Figure 1 , Figure 31B is a cross-sectional view taken along the line B-B' of Figure 1 .

[0098] Refer together to Figure 31A and Figure 31B , Figure 14A ​​The lower portion of the substrate 110 shown is partially removed to form a substrate recess 110Ra. The side surfaces of the hard mask layer 210 and the partial side surfaces of the dummy structure PH may be exposed to the substrate recess 110Ra. The substrate recess 110Ra may be defined by the bottom surface of the substrate 110, the side surfaces of the hard mask layer 210, and the side surfaces of the dummy structure PH. In an embodiment of the inventive concept, after partially removing the lower portion of the substrate 110 to form the substrate recess 110Ra, the bottom surface of the substrate 110 may be at a fourth vertical level LV4 higher than a first vertical level LV1.

[0099] Figure 32A and Figure 32B are cross-sectional views showing an integrated circuit device 2 according to an embodiment of the inventive concept. Specifically, Figure 32A is a cross-sectional view taken along line Figure 1 A-A' of Figure 32B is a cross-sectional view taken along line Figure 1 B-B' of

[0100] Referring together to Figure 32A and Figure 32B , the integrated circuit device 2 is formed in a manner similar to the manner described with reference to Figures 16A to 26B .

[0101] The uppermost end of the spacer layer 220 may be at the fourth vertical level LV4. In a Y-Z cross-section (i.e., a vertical cross-section extending in the second horizontal direction (Y direction) and passing through the center of the post-contact plug 250 in a plan view) formed by the second horizontal direction (Y direction) and the vertical direction (Z direction) and passing through the center of the post-contact plug 250 in the plan view, the uppermost end of the portion of the spacer layer 220 surrounding the post-contact plug 250 may be at the first vertical level LV1 and may have a first spacer height H1. In an X-Z cross-section (i.e., a vertical cross-section extending in the first horizontal direction (X direction) and passing through the center of the post-contact plug 250 in the plan view) formed by the first horizontal direction (X direction) and the vertical direction (Z direction) and passing through the center of the post-contact plug 250 in the plan view, the uppermost end of the portion of the spacer layer 220 surrounding the post-contact plug 250 may be at the fourth vertical level LV4 higher than the first vertical level LV1 and may have a second spacer height H2 greater than the first spacer height H1.

[0102] Figure 33A and Figure 33B are cross-sectional views showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept. Specifically, Figure 33A is a cross-sectional view taken along line Figure 1 A-A' of Figure 33B is a cross-sectional view taken along line Figure 1Cross-sectional view taken along line B-B'.

[0103] Refer to together Figure 33A and Figure 33B , Figure 14A As shown, the lower part of the substrate 110 is partially removed to form a substrate recess 110Rb. The side surface of the hard mask layer 210 and a partial side surface of the dummy structure PH may be exposed in the substrate recess 110Rb. The substrate recess 110Rb may be defined by the bottom surface of the substrate 110, the side surface of the hard mask layer 210, and the side surface of the dummy structure PH. In an embodiment of the inventive concept, after partially removing the lower part of the substrate 110 to form the substrate recess 110Rb, the bottom surface of the substrate 110 may be at a fifth vertical level LV5 lower than the first vertical level LV1.

[0104] Figure 34A and Figure 34B are cross-sectional views showing an integrated circuit device 3 according to an embodiment of the inventive concept. Specifically, Figure 34A is a cross-sectional view taken along line A-A' of Figure 1 , Figure 34B is a cross-sectional view taken along line B-B' of Figure 1 .

[0105] Refer to together Figure 34A and Figure 34B , the integrated circuit device 3 is formed in a manner similar to that described with reference to Figures 16A to 26B .

[0106] The uppermost end of the spacer layer 220 may be at the first vertical level LV1. In a Y-Z cross-section (i.e., a vertical cross-section extending in the second horizontal direction (Y direction) and passing through the center of the post-contact plug 250 in the plan view) formed by the second horizontal direction (Y direction) and the vertical direction (Z direction), the uppermost end of the portion of the spacer layer 220 surrounding the post-contact plug 250 may be at the first vertical level LV1 and may have a first spacer height H1. In an X-Z cross-section (i.e., a vertical cross-section extending in the first horizontal direction (X direction) and passing through the center of the post-contact plug 250 in the plan view) formed by the first horizontal direction (X direction) and the vertical direction (Z direction), the uppermost end of the portion of the spacer layer 220 surrounding the post-contact plug 250 may be at a fifth vertical level LV5 lower than the first vertical level LV1 and may have a third spacer height H3 smaller than the first spacer height H1.

[0107] Although not shown separately, Figure 32A and Figure 32B the integrated circuit device 2 shown inFigure 34A and Figure 34B the integrated circuit device 3 shown in Figure 30A and Figure 30B the post-insulation layer 240a included in the integrated circuit device 1a shown in, instead of the hard mask layer 210 and the post-insulation layer 240.

[0108] Although the present inventive concept has been described with reference to embodiments of the present inventive concept, those of ordinary skill in the art will understand that various changes in form and detail may be made thereto without departing from the spirit and scope of the present inventive concept.

[0109] This application claims priority to Korean Patent Application No. 10-2024-0006805, filed with the Korean Intellectual Property Office on January 16, 2024, the disclosure of which is hereby incorporated by reference in its entirety.

Claims

1. An integrated circuit device, comprising: A post-insulating layer; A nanosheet stack structure disposed on the post-insulating layer and including a plurality of nanosheets; A pair of source / drain regions respectively located on two sides of the nanosheet stack structure in a first horizontal direction; A gate electrode on the nanosheet stack structure, extending in a second horizontal direction intersecting with the first horizontal direction; A contact plug connected to at least one of the pair of source / drain regions; A post-contact plug passing through the post-insulating layer and connected to at least one of the pair of source / drain regions; And A spacer layer including a contact spacer layer surrounding a part of a side surface of the post-contact plug.

2. The integrated circuit device according to claim 1, wherein a topmost end of the spacer layer is at a vertical level lower than a lowermost end of the pair of source / drain regions.

3. The integrated circuit device according to claim 2, wherein in a vertical cross-section extending in the first horizontal direction and passing through a center of the post-contact plug in a plan view, the topmost end of the spacer layer is at the same vertical level as the topmost end of the spacer layer in a vertical cross-section extending in the second horizontal direction and passing through the center of the post-contact plug in the plan view.

4. The integrated circuit device according to claim 2, wherein in a vertical cross-section extending in the first horizontal direction and passing through a center of the post-contact plug in a plan view, the topmost end of the spacer layer is at a vertical level higher than the topmost end of the spacer layer in a vertical cross-section extending in the second horizontal direction and passing through the center of the post-contact plug in the plan view.

5. The integrated circuit device according to claim 2, wherein in a vertical cross-section extending in the first horizontal direction and passing through a center of the post-contact plug in a plan view, the topmost end of the spacer layer is at a vertical level lower than the topmost end of the spacer layer in a vertical cross-section extending in the second horizontal direction and passing through the center of the post-contact plug in the plan view.

6. The integrated circuit device according to claim 1, wherein a lowermost end of the spacer layer is at the same vertical level as a bottom surface of a capping insulating layer between the post-insulating layer and the nanosheet stack structure.

7. The integrated circuit device according to claim 1, wherein the pair of source / drain regions includes a source region and a drain region, wherein the contact plug is connected to the drain region, and wherein the post-contact plug is connected to the source region.

8. The integrated circuit device according to claim 7, further comprising a dummy structure connected to the drain region, wherein the spacer layer further includes a dummy spacer layer surrounding a part of a side surface of the dummy structure.

9. The integrated circuit device according to claim 1, wherein a topmost end of the spacer layer is at a vertical level lower than a topmost end of the post-contact plug, and a lowermost end of the spacer layer is at a vertical level higher than a lowermost end of the post-contact plug.

10. An integrated circuit device, comprising: A nanosheet stack structure including a plurality of nanosheets; A pair of source / drain regions, respectively connected to both ends in a first horizontal direction of each of the plurality of nanosheets; A gate electrode, on the nanosheet stack structure, extending in a second horizontal direction intersecting with the first horizontal direction; An inter-gate insulating layer, at least partially surrounding the gate electrode and the pair of source / drain regions; A contact plug, connected to one of the pair of source / drain regions through the inter-gate insulating layer; An etch stop layer, covering the surfaces of the pair of source / drain regions and the bottom surface of the inter-gate insulating layer; A covering insulating layer, covering the etch stop layer and the inter-gate insulating layer; A post-insulating layer, covering the covering insulating layer; A post-contact plug, passing through the post-insulating layer and the covering insulating layer and connected to the other of the pair of source / drain regions; And A spacer layer, including a portion surrounding the side surface of the post-contact plug and a contact spacer layer located between the covering insulating layer and the post-contact plug.

11. The integrated circuit device according to claim 10, wherein the lowermost end of the spacer layer is at the same vertical level as the bottom surface of the covering insulating layer, and wherein the uppermost end of the spacer layer is at a vertical level lower than the lowermost end of the pair of source / drain regions.

12. The integrated circuit device according to claim 10, wherein the uppermost end of the spacer layer contacts the etch stop layer, and wherein the lowermost end of the spacer layer contacts the post-insulating layer.

13. The integrated circuit device according to claim 10, wherein the post-contact plug extends into the other of the pair of source / drain regions.

14. The integrated circuit device according to claim 10, wherein the post-contact plug and the other of the pair of source / drain regions are aligned with each other in the vertical direction, and Among them, in a portion where the other of the pair of source / drain regions contacts the post-contact plug, the horizontal width of the post-contact plug is smaller than the horizontal width of the other of the pair of source / drain regions.

15. The integrated circuit device according to claim 10, further comprising a dummy structure passing through the covering insulating layer and connected to one of the pair of source / drain regions, wherein the spacer layer further includes a portion surrounding the side surface of the dummy structure and a dummy spacer layer located between the covering insulating layer and the dummy structure.

16. The integrated circuit device according to claim 10, wherein the height of the spacer layer in a vertical cross-section extending in the first horizontal direction and passing through the center of the post-contact plug in a plan view is greater than the height of the spacer layer in a vertical cross-section extending in the second horizontal direction and passing through the center of the post-contact plug in the plan view.

17. The integrated circuit device according to claim 10, wherein a height of the spacer layer in a vertical cross-section extending in the first horizontal direction and passing through a center of the back contact plug in a plan view is less than a height of the spacer layer in a vertical cross-section extending in the second horizontal direction and passing through the center of the back contact plug in the plan view.

18. An integrated circuit device, comprising: a nanosheet stack structure including a plurality of nanosheets; a pair of source / drain regions including a source region and a drain region, wherein the source region and the drain region are respectively connected to two ends in a first horizontal direction of each of the plurality of nanosheets; a gate electrode on the nanosheet stack structure and extending in a second horizontal direction intersecting with the first horizontal direction; a gate insulating layer at least partially surrounding the gate electrode and the pair of source / drain regions; an etch stop layer covering a surface of the pair of source / drain regions and a bottom surface of the gate insulating layer; a covering insulating layer covering the etch stop layer and the gate insulating layer; a back insulating layer disposed under the covering insulating layer; a back contact plug passing through the back insulating layer and the covering insulating layer and connected to the source region; a contact plug passing through the gate insulating layer and the etch stop layer and connected to the drain region; a dummy structure passing through the covering insulating layer and connected to the drain region; and a spacer layer including a contact spacer layer and a dummy spacer layer, wherein the contact spacer layer surrounds a part of a side surface of the back contact plug and is located between the covering insulating layer and the back contact plug, and the dummy spacer layer surrounds a part of a side surface of the dummy structure and is located between the covering insulating layer and the dummy structure.

19. The integrated circuit device according to claim 18, further comprising a hard mask layer between the dummy structure and the back insulating layer, wherein the dummy spacer layer surrounds a side surface of the hard mask layer.

20. The integrated circuit device according to claim 18, wherein a bottom surface of the dummy structure is at a vertical level higher than a lowermost end of the dummy spacer layer, and wherein the back insulating layer has a protrusion protruding upward toward the dummy structure and surrounded by the dummy spacer layer.

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