Image sensing device and manufacturing method thereof

Abstract

The invention relates to an image sensing device and a manufacturing method thereof. Disclosed is an image sensing device. The image sensing device includes: a substrate; a photoelectric conversion element formed in the substrate; an isolation structure provided between the photoelectric conversion element and an additional photoelectric conversion element provided adjacent to the photoelectric conversion element; a floating diffusion region disposed over an upper portion of the isolation structure; and a floating diffusion region protection layer disposed below the floating diffusion region and contacting an upper portion of the isolation structure.

Description

Technical Field

[0001] Various embodiments of the disclosed technology relate to an image sensing device and a method of manufacturing the same. Background Art

[0002] An image sensing device refers to a semiconductor device that captures an optical image and converts it into an electrical signal. With the development of the automotive, medical, computer, and telecommunications industries, the demand for high-performance image sensing devices is increasing in various devices such as smart phones, digital cameras, gaming devices, the Internet of Things, robots, security cameras, and medical micro cameras.

[0003] The most common types of image sensing devices are charge-coupled device (CCD) image sensing devices and complementary metal-oxide-semiconductor (CMOS) image sensing devices. Summary of the Invention

[0004] The disclosed technology may be implemented in various ways to provide an image sensing device and a method of manufacturing the same, which can improve process variation and pixel uniformity by preventing a floating diffusion region from being etched during a trench formation process.

[0005] In one aspect, there is provided an image sensing device including: a substrate; a photoelectric conversion element formed in the substrate; an isolation structure disposed between the photoelectric conversion element and an additional photoelectric conversion element disposed adjacent to the photoelectric conversion element; a floating diffusion region disposed above an upper portion of the isolation structure; and a floating diffusion region protection layer disposed below the floating diffusion region and contacting the upper portion of the isolation structure.

[0006] In some embodiments, the floating diffusion region protection layer may include at least one of an oxide or a nitride.

[0007] In some embodiments, a transfer transistor may be disposed above the floating diffusion region.

[0008] In some embodiments, the upper portion of the isolation structure may be configured to contact a region of the floating diffusion region protection layer.

[0009] In some embodiments, the width of the floating diffusion region protection layer may be greater than the width of the isolation structure.

[0010] In some embodiments, the width of the floating diffusion region protection layer may be greater than or equal to the width of the floating diffusion region.

[0011] In some embodiments, the height of the isolation structure may be greater than the height of the floating diffusion region.

[0012] In some embodiments, the width of the floating diffusion region protection layer may be greater than the width of the isolation structure and less than the width of the floating diffusion region.

[0013] In some implementations, a floating diffusion region protection layer may be formed above an upper portion of one side of the photoelectric conversion element.

[0014] In some implementations, the etching selectivity of the substrate may be different from the etching selectivity of the floating diffusion region protection layer.

[0015] On the other hand, a method for manufacturing an image sensing device is provided. The method for manufacturing an image sensing device may include the following steps: forming a first substrate; forming a floating diffusion region protection layer on the first substrate; etching a region of the floating diffusion region protection layer; forming a second substrate on the floating diffusion region protection layer; forming a floating diffusion region in the second substrate; and forming a transfer transistor above the floating diffusion region.

[0016] In some implementations, the method may further include the step of forming an isolation structure below the floating diffusion region protection layer.

[0017] In some implementations, the floating diffusion region protection layer may include at least one of an oxide or a nitride.

[0018] In some implementations, the step of forming the floating diffusion region protection layer may include the following steps: depositing a material to form an isolation structure; and etching a portion of the isolation structure.

[0019] In some implementations, an upper portion of the isolation structure may be configured to contact a region of the floating diffusion region protection layer.

[0020] In some implementations, the step of forming the isolation structure may include etching the first substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a block diagram of an image sensing device according to an embodiment of the disclosed technology.

[0022] Figure 2 and Figure 3 is a diagram for showing a unit pixel of an image sensing device according to an embodiment of the disclosed technology.

[0023] Figure 4 is Figure 3 a cross-sectional view of the A-A' portion of

[0024] Figures 5 to 10 is a diagram for describing a manufacturing method of an image sensing device according to an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0025] Features and specific advantages related to particular implementations of the technology disclosed in this patent document are described by way of example implementations with reference to the accompanying drawings.

[0026] As the size of pixels in an image sensing device decreases, the area ratio occupied by a photodiode in one pixel increases. Therefore, the depth of trenches for blocking crosstalk continuously increases.

[0027] If the depth of the formed trenches is deep, etching may be performed on the floating diffusion region, and thus, pixel defect problems may occur.

[0028] In some implementations, by preventing the trench formation process from continuously etching the floating diffusion region, process variations and pixel uniformity can be improved. In some implementations, crosstalk can be improved because a much deeper depth can be etched without considering the margin of the cross-sectional area of the trenches.

[0029] Figure 1 is a block diagram of an image sensing device according to an embodiment.

[0030] Referring to Figure 1 , an image sensing device according to an embodiment may include a pixel array 1100, a row driver 1200, a correlated double sampler (CDS) 1300, an analog-to-digital converter (ADC) 1400, an output buffer 1500, a column driver 1600, a timing controller 1700, and a bias generator 1800. Here, the components of the image sensing device are discussed only as examples, and at least some components may be added or omitted as needed.

[0031] The pixel array 1100 may include a plurality of pixels arranged in multiple rows and multiple columns. In one example, the plurality of pixels may be arranged in a two-dimensional pixel array including rows and columns. In another example, the plurality of pixels may be arranged in a three-dimensional pixel array. The plurality of unit pixels may convert an optical signal into an electrical signal based on a unit pixel or based on a pixel group, where the unit pixels in the pixel group share at least a specific internal circuit. The pixel array 1100 may receive driving signals including a row selection signal, a pixel reset signal, and a transfer signal from the row driver 1200. When receiving the driving signals, the corresponding pixels in the pixel array 1100 may be enabled to perform operations corresponding to the row selection signal, the pixel reset signal, and the transfer signal.

[0032] The row driver 1200 can enable the pixel array 1100 based on commands and control signals provided by the timing controller 1700 to perform specific operations on imaging pixels in the corresponding row. In an embodiment, the row driver 1200 can select one or more imaging pixels arranged in one or more rows of the pixel array 1100. The row driver 1200 can generate a row selection signal to select one or more rows among multiple rows. The row driver 1200 can sequentially enable the pixel reset signal and the transmission signal of the pixels corresponding to at least one selected row. Therefore, as analog signals generated by each pixel of the selected row, the reference signal and the image signal can be sequentially transmitted to the CDS 1300. Here, the reference signal can be an electrical signal provided to the CDS 1300 when the sensing node (e.g., floating diffusion node) of the pixel is reset, and the image signal can be an electrical signal provided to the CDS 1300 when the optical charge generated by the pixel accumulates in the sensing node. The reference signal indicating the unique reset noise of each pixel and the image signal indicating the intensity of the incident light can be collectively referred to as pixel signals.

[0033] The CMOS image sensor can use correlated double sampling (CDS) to remove the undesired offset value (referred to as fixed pattern noise) of the pixel by sampling the pixel signal twice to remove the difference between the two samples. In one example, the correlated double sampling (CDS) can remove the undesired offset value of the pixel by comparing the pixel output voltages obtained before and after the optical charge generated by the incident light accumulates in the sensing node, so that only the pixel output voltage based on the incident light can be measured. In some embodiments of the disclosed technology, the CDS 1300 can sequentially sample and hold the voltage levels of the reference signal and the image signal provided from the pixel array 1100 to each of the multiple column lines. That is, the CDS 1300 can sample and hold the voltage levels of the reference signal and the image signal corresponding to each column of the pixel array 1100.

[0034] The CDS 1300 can transmit the reference signal and the image signal of each column to the ADC 1400 as correlated double sampling signals based on the control signal from the timing controller 1700.

[0035] The ADC 1400 can convert the correlated double sampling signals generated by the CDS 1300 for each column into digital signals and output the digital signals. In some embodiments, the ADC 140 can be implemented as a ramp comparison type ADC. The ramp comparison type ADC can include a comparator circuit for comparing an analog pixel signal with a ramp signal that ramps up or down over time and a timer that counts until the voltage of the ramp signal matches the analog pixel signal. In some embodiments of the disclosed technology, the ADC 1400 can convert the correlated double sampling signals generated by the CDS 1300 for each column into digital signals and output the digital signals.

[0036] The ADC 1400 may include a plurality of column counters corresponding to each column of the pixel array 1100. Each column of the pixel array 1100 is connected to a column counter, and image data may be generated by converting correlated double-sampled signals corresponding to each column into digital signals by using the column counter. In another embodiment of the disclosed technology, the ADC 1400 may include a global counter to convert correlated double-sampled signals corresponding to each column into digital signals by using a global code provided from the global counter.

[0037] The output buffer 1500 may temporarily hold column-based image data provided from the ADC 1400 to output the image data. The image data provided from the ADC 1400 to the output buffer 1500 may be temporarily stored in the output buffer 1500 based on a control signal of the timing controller 1700. The output buffer 1500 may act as an interface for compensating for a data rate difference (or processing rate difference) between the data rate of the image sensing device and the data rate of other connected devices.

[0038] The column driver 1600 may select a column of the output buffer 1500 when receiving a control signal from the timing controller 1700, and sequentially output image data temporarily stored in the selected column of the output buffer 1500. In some embodiments, the column driver 1600 may receive an address signal from the timing controller 1700, and the column driver 1600 may generate a column selection signal based on the address signal and select a column of the output buffer 1500, thereby outputting image data from the selected column of the output buffer 1500 to the outside.

[0039] The timing controller 1700 may control at least one of the row driver 1200, CDS 1300, ADC 1400, output buffer 1500, column driver 1600, and bias generator 1800.

[0040] The timing controller 1700 may provide a clock signal required for operation of each component of the image sensing device, a control signal for timing control, an address signal for selecting a row or a column, and a signal for controlling a voltage level of a bias voltage applied to the pixel array 1100 to at least one of the row driver 1200, CDS 1300, ADC 1400, output buffer 1500, column driver 1600, and bias generator 1800. In an embodiment of the disclosed technology, the timing controller 1700 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, etc.

[0041] The bias generator 1800 may generate a bias voltage for suppressing dark current to be generated in pixels of the pixel array 1100, and may apply the bias voltage to the pixel array 1100.

[0042] The offset voltage can be determined by performing a wafer probe test process of the image sensing device and is stored in a one-time programmable (OTP) memory. For example, the offset voltage can be experimentally determined to have a value that can minimize unnecessary power consumption and maximize the dark current suppression effect without degrading the performance of the image sensing device.

[0043] The bias voltage generator 1800 can generate a voltage corresponding to the offset voltage stored in the OTP memory. In some embodiments, the OTP memory can be included in the image sensing device. In particular, the OTP memory can be included in the bias voltage generator 1800.

[0044] In some embodiments, the offset voltage can include multiple voltage values.

[0045] For example, the multiple voltage values can respectively correspond to multiple operation modes of the image sensing device. The dark current generated under low luminance conditions can be different from the dark current generated under high luminance levels. In order to effectively suppress the dark current in various environments, the bias voltage provided by the bias voltage generator 1800 can vary according to the operation mode.

[0046] In some other implementations, the multiple values can respectively correspond to multiple regions of the pixel array 1100. The dark current generated due to the positions of the individual pixels in the pixel array 1100 can be different from each other. In order to effectively suppress the dark current regardless of the positions of the individual pixels, the bias voltage generated by the bias voltage generator 1800 can vary according to each region.

[0047] The offset voltage can be a negative voltage; however, the scope of the present disclosure is not limited thereto.

[0048] Figure 2 and Figure 3 are diagrams showing a unit pixel of an image sensing device according to an embodiment. Figure 4 is Figure 3 a cross-sectional view taken along line A-A' of

[0049] Referring to Figure 2 and Figure 3, in an embodiment, the pixel array 1100 may include a plurality of unit pixels, and each unit pixel may include a transfer transistor TX, a floating diffusion region FD, a reset transistor RX, a driving transistor DX, a selection transistor SX, and a photodiode, as an example of a light sensing device or a photoelectric conversion device. The photodiode is an example of a device for implementing a photoelectric conversion element, which is configured to convert the received light into a photocurrent amount to generate and accumulate photo charges corresponding to the received incident light amount. Although the photodiode is mentioned as an example of the photoelectric conversion element, other implementations are also possible. For example, the photoelectric conversion element may be implemented as a phototransistor, a photogate, or a pinned photodiode, or a combination thereof.

[0050] The transfer transistor TX may transfer the charge (or photocurrent) accumulated in the photodiode to the floating diffusion region FD in response to a transfer control signal input to the gate.

[0051] The floating diffusion region FD may receive the charge generated by the photodiode through the transfer transistor and store the received charge.

[0052] The reset transistor RX is connected between the power supply voltage Vdd and the floating diffusion region FD, and may reset the floating diffusion region FD by discharging the charge stored in the floating diffusion region FD to the power supply voltage in response to a reset signal RST.

[0053] The driving transistor DX functions as a source follower buffer amplifier and buffers a signal corresponding to the charge charged in the floating diffusion region FD.

[0054] The selection transistor SX performs an addressing function and a switching function for selecting a unit pixel.

[0055] May be formed in Figure 4 The isolation structure 300 may be formed in the lower region of the substrate 100 between the floating diffusion region FD and two adjacent photodiodes 200 below the floating diffusion region protection layer 400 to provide isolation for the two adjacent photodiodes 200. In Figure 4 In this example, two transfer transistors TX along the Figure 3 diagonal line A-A' are located on opposite sides of the FD of the unit pixel, and Figure 4 the floating diffusion region FD and its floating diffusion region protection layer 400 are located between the transfer transistors TX.

[0056] Referring to Figure 3 and Figure 4 , an image sensing device according to an embodiment may include a substrate 100, a photodiode 200, an isolation structure 300, a floating diffusion region FD, and a floating diffusion region protection layer 400.

[0057] In an embodiment, the substrate 100 may include a material containing single crystal silicon.

[0058] The photodiode 200 may be formed in the substrate 100, and an n-type impurity region and a p-type impurity region may be vertically stacked in the photodiode 200. The n-type impurity region and the p-type impurity region may be formed by an ion implantation process.

[0059] The isolation structure 300 may be formed between adjacent photodiodes 200, and may include at least one of a silicon oxynitride (SiON) layer, a silicon oxide (SiO) layer, a silicon nitride (SiN) layer, or a polysilicon (Poly Si).

[0060] The isolation structure 300 may have a backside deep trench isolation (BDTI) structure.

[0061] The isolation structure 300 may be formed to the floating diffusion region protection layer 400 through an etching selectivity difference between the silicon Si of the substrate 100 and the oxide of the floating diffusion region protection layer 400. The upper portion of the isolation structure 300 may be formed to contact an area of the floating diffusion region protection layer 400.

[0062] In the embodiment as Figure 4 shown, the upper end of the isolation structure 300 is located below the lower end of the floating diffusion region FD of the isolation structure 300, closer to the lower end than the upper end of the floating diffusion region FD. In an embodiment, the height of the isolation structure 300 may be formed to be greater than the height of the floating diffusion region FD. The height may refer to the distance between two opposite surfaces of the isolation structure 300 or the floating diffusion region FD.

[0063] The floating diffusion region FD may be formed above the isolation structure 300.

[0064] The floating diffusion region FD may be formed in the cross region C of the unit pixel.

[0065] The transfer transistor TX may be formed above the floating diffusion region FD.

[0066] The floating diffusion region FD may be an n-type impurity region or include an n-type impurity region.

[0067] The floating diffusion region protection layer 400 may be formed between the floating diffusion region FD and the upper portion of the isolation structure 300.

[0068] In an embodiment, the floating diffusion region protection layer 400 may include at least one of an oxide or a nitride. Thus, the floating diffusion region protection layer 400 may include an oxide, a nitride, or a combination of an oxide and a nitride.

[0069] Even if etching is overperformed during the etching process for forming the isolation structure 300 without considering the allowance in the cross region C, the floating diffusion region protective layer 400 can be used to prevent the etching from invading the floating diffusion region FD. In an implementation, even if etching is overperformed during the etching process for forming the isolation structure 300, the floating diffusion region protective layer 400 can be used to stop etching in the floating diffusion region protective layer 400.

[0070] In an implementation, the width of the floating diffusion region protective layer 400 can be formed to be equal to or wider than the width of the floating diffusion region FD so as to prevent the floating diffusion region FD from being etched during the etching process for forming the isolation structure 300.

[0071] In an implementation, the width of the floating diffusion region protective layer 400 can be wider than the width of the isolation structure 300.

[0072] In an implementation, the width of the floating diffusion region protective layer 400 can be wider than the width of the isolation structure 300 and less than the width of the floating diffusion region FD.

[0073] In an implementation, the floating diffusion region protective layer 400 can overlap with the upper portion of the side of the photodiode 200 adjacent to the isolation structure 300.

[0074] Figures 5 to 10 is a diagram for describing a method of manufacturing an image sensing device according to an implementation.

[0075] Referring to Figure 5 , the first substrate 110 can be formed by an epitaxial process.

[0076] The first substrate 110 can be a substrate thinned by a thinning process. In an implementation, the first substrate 110 can be a bulk silicon substrate thinned by a thinning process or include a bulk silicon substrate thinned by a thinning process. In an implementation, the first substrate 110 can include p-type impurities.

[0077] Referring to Figure 6 , the floating diffusion region protective layer 400 can be formed by a process of etching the remaining region of the floating diffusion region protective layer 400 except for the central region of the floating diffusion region protective layer 400.

[0078] Referring to Figure 7 , the floating diffusion region protective layer 400 having a final shape can be formed by a process of etching the remaining region of the floating diffusion region protective layer 400 except for the central region of the floating diffusion region protective layer 400.

[0079] At this time, since it is difficult to deposit silicon (Si) on the oxide that is usually used for the floating diffusion region protective layer 400 by an epitaxial process, it is necessary to appropriately control the critical dimension (CD) of the floating diffusion region protective layer 400 so that the silicon (Si) that has grown on the side surface of the floating diffusion region protective layer 400 can sufficiently cover the floating diffusion region protective layer 400.

[0080] Referring to Figure 8 , by an epitaxial process, the first substrate 110 can be formed, and the second substrate 120 can be formed on the floating diffusion region protective layer 400.

[0081] The second substrate 120 can be a substrate thinned by a thinning process or include a substrate thinned by a thinning process. In an embodiment, the second substrate 120 can be a bulk silicon substrate thinned by a thinning process or include a bulk silicon substrate thinned by a thinning process. In an embodiment, the second substrate 120 can include p-type impurities.

[0082] Referring to Figure 9 , a floating diffusion region (FD) can be formed in the second substrate 120 by an ion implantation process.

[0083] The floating diffusion region (FD) can be formed by implanting n-type dopant ions such as arsenic or phosphorus.

[0084] The transfer transistor (TX) can be formed above the upper part of the floating diffusion region (FD). The transfer transistor (TX) can be formed by forming a gate insulating layer (not shown) and a gate electrode (not shown) on the second substrate 120.

[0085] In an embodiment, the gate electrode (not shown) can include silicon oxide.

[0086] In an embodiment, the gate electrode (not shown) can include one or a combination of materials selected from the group consisting of polysilicon, tungsten, titanium nitride, tantalum, and tantalum nitride.

[0087] Referring to Figure 10 , the isolation structure 300 can be formed below the floating diffusion region (FD). The upper part of the isolation region can contact an area of the floating diffusion region protective layer 400.

[0088] When etching the first substrate 110 to form the isolation structure 300, due to the etching selectivity difference between the silicon (Si) and the oxide of the floating diffusion region protective layer 400, the etching can stop in the floating diffusion region protective layer 400. Therefore, the etching for forming the isolation structure 300 can be performed on the floating diffusion region protective layer 400, and the floating diffusion region (FD) does not need to be etched. Even if the etching is over-executed during the etching process for forming the isolation structure 300 without considering the margin in the cross region C, the floating diffusion region protective layer 400 can be used to prevent etching invasion or etching of the floating diffusion region (FD).

[0089] The isolation structure 300 may include at least one of a silicon oxynitride (SiON) layer, a silicon oxide (SiO) layer, a silicon nitride (SiN) layer, and a polysilicon (Poly Si).

[0090] The isolation structure 300 may be formed in a vertically deeply dug shape to prevent crosstalk, and may be formed by a deep trench isolation (DTI) process.

[0091] Although various embodiments have been described above, variations and improvements of the disclosed embodiments and other embodiments may be made based on the content described or shown in this document.

[0092] Cross-reference to related applications and claims of priority

[0093] This patent document claims the priority and benefits of Korean Patent Application No. 10-2024-0005308, filed on January 12, 2024, the entire content of which is incorporated by reference as part of the disclosure of this patent document.

Claims

1. An image sensing device, the image sensing device comprising: A substrate; A photoelectric conversion element formed in the substrate; An isolation structure disposed between the photoelectric conversion element and an additional photoelectric conversion element disposed adjacent to the photoelectric conversion element; A floating diffusion region disposed above an upper portion of the isolation structure; And A floating diffusion region protection layer disposed below the floating diffusion region and contacting an upper portion of the isolation structure.

2. The image sensing device according to claim 1, Among them, The floating diffusion region protection layer comprises at least one of an oxide or a nitride.

3. The image sensing device according to claim 1, Among them, A transfer transistor is disposed above the floating diffusion region.

4. The image sensing device according to claim 1, Among them, The upper portion of the isolation structure is disposed to contact a region of the floating diffusion region protection layer.

5. The image sensing device according to claim 1, Among them, The width of the floating diffusion region protection layer is greater than the width of the isolation structure.

6. The image sensing device according to claim 1, Among them, The width of the floating diffusion region protection layer is greater than or equal to the width of the floating diffusion region.

7. The image sensing device according to claim 1, Among them, The height of the isolation structure is greater than the height of the floating diffusion region.

8. The image sensing device according to claim 1, Among them, The width of the floating diffusion region protection layer is greater than the width of the isolation structure and less than the width of the floating diffusion region.

9. The image sensing device according to claim 1, Among them, The floating diffusion region protection layer is formed above an upper portion on one side of the photoelectric conversion element.

10. The image sensing device according to claim 1, Among them, The etching selectivity of the substrate is different from the etching selectivity of the floating diffusion region protection layer.

11. A method for manufacturing an image sensing device, the method comprising the steps of: Forming a first substrate; Forming a floating diffusion region protection layer on the first substrate; Etching a region of the floating diffusion region protection layer; Forming a second substrate on the floating diffusion region protection layer; Forming a floating diffusion region in the second substrate; And Forming a transfer transistor above the floating diffusion region.

12. The method according to claim 11, the method further comprising the steps of: Forming an isolation structure below the floating diffusion region protection layer.

13. The method according to claim 11, Among them, The floating diffusion region protection layer comprises at least one of an oxide or a nitride.

14. The method according to claim 12, wherein, The step of forming the floating diffusion region protection layer comprises the steps of: Depositing a material to form the isolation structure; and Etching a portion of the isolation structure.

15. The method according to claim 12, Among them, The upper portion of the isolation structure is disposed to contact a region of the floating diffusion region protection layer.

16. The method according to claim 12, Among them, The step of forming the isolation structure comprises the step of: etching the first substrate.

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