Solar cell, preparation method thereof and photovoltaic module

Abstract

The embodiment of the invention relates to the photovoltaic field, and provides a solar cell and a preparation method thereof, and a photovoltaic module, and the preparation method comprises the steps: forming a first doped semiconductor layer on a first surface of a substrate, and enabling the orthographic projection of the first doped semiconductor layer in a first direction to coincide with the first surface; performing a second doping diffusion process on the second surface of the substrate to form a second doped semiconductor layer on the whole second surface, the side surface where the first surface is connected with the second surface and the edge of the first surface; forming a first dielectric layer on one side, far away from the second surface, of the second doped semiconductor layer; performing laser thermal oxidation treatment on at least a part of the second doped semiconductor layer on the side surface so as to form at least two oxide layers which are arranged at intervals on at least one side surface; and the second doped semiconductor layer is etched, and the remaining second doped semiconductor layer covered by the oxide layer is used as an edge contact part and is in electric contact with the first doped semiconductor layer, so that the hot spot resistance of the solar cell can be improved at least.

Description

Technical Field

[0001] The present application relates to the field of photovoltaics, and particularly to a solar cell, a preparation method thereof, and a photovoltaic module. Background Art

[0002] A solar cell generates carrier pairs by means of incident light and then separates them, so that an electric potential appears between at least two conductive structures of the solar cell, and the electric power of the solar cell can be measured through an external circuit connected to the conductive structure. In order to convert incident light into electric energy, the following photovoltaic module mode is generally adopted, which includes a plurality of solar cells. When installed in a photovoltaic module, a plurality of solar cells are connected in series or in parallel to be assembled into a so-called row or column. A photovoltaic module generally includes a plurality of rows or columns.

[0003] However, when the photovoltaic module is operating, some areas may be shaded. The unshaded areas generate electricity normally, but the shaded areas cannot receive light for power generation. It is equivalent to a resistor, which will consume electric energy and convert it into heat energy, thus forming a hot spot effect. The hot spot effect poses a serious threat to the safe operation of the photovoltaic module and the photovoltaic power station. The high temperature generated by the hot spot will accelerate the aging process of the photovoltaic module, reduce the power generation efficiency of the photovoltaic module, and the long-term high temperature effect will damage the encapsulation material of the photovoltaic module, resulting in a decrease in the sealing performance of the photovoltaic module and further exacerbating the aging of the photovoltaic module.

[0004] Therefore, it is necessary to seek a method to solve the hot spot effect. Summary of the Invention

[0005] Embodiments of the present application provide a solar cell, a preparation method thereof, and a photovoltaic module, which are at least beneficial to improving the anti-hot spot performance of the solar cell.

[0006] According to some embodiments of the present application, on the one hand, an embodiment of the present application provides a method for manufacturing a solar cell, comprising providing a substrate having a first surface and a second surface opposite to each other in a first direction, where the first direction is the thickness direction of the substrate, and further comprising: forming a first doped semiconductor layer doped with a first doping element on the first surface, the positive projection of the first doped semiconductor layer in the first direction coinciding with the first surface; performing a second doping diffusion process on the second surface to form a second doped semiconductor layer doped with a second doping element, the second doped semiconductor layer being located on the entire second surface, the side surface connecting the first surface and the second surface, and the edge of the first surface, and the first doping element and the second doping element having different conductivity types; forming a first dielectric layer on the side of the second doped semiconductor layer away from the second surface; performing a laser thermal oxidation process on at least a part of the second doped semiconductor layer located on the side surface to form at least two oxide layers arranged at intervals in a second direction on at least one side surface, a single oxide layer being at least located on the side surface, and the second direction being orthogonal to the first direction; etching the second doped semiconductor layer to remove the second doped semiconductor layer not covered by the first dielectric layer and the oxide layer, and the remaining second doped semiconductor layer covered by the oxide layer serving as an edge contact portion and being in electrical contact with the first doped semiconductor layer.

[0007] In some embodiments, the second doped semiconductor layer located on the edge of the first surface comprises a to-be-removed portion and a connection portion arranged in sequence in the direction from the center of the first surface to the edge of the first surface, and the connection portion is in contact connection with the second doped semiconductor layer located on the side surface; the step of performing the laser thermal oxidation process further comprises: performing the laser thermal oxidation process on a partial region of the connection portion, such that a single oxide layer is not only located on the side surface but also on the side of the remaining connection portion away from the first surface.

[0008] In some embodiments, the step of forming the first doped semiconductor layer comprises: performing a first doping diffusion process on the first surface to form an initial first doped semiconductor layer doped with the first doping element, and forming an initial second dielectric layer on the surface of the initial first doped semiconductor layer away from the substrate, the initial first doped semiconductor layer being located on the entire first surface, the side surface, and the edge of the second surface; using a first etching process to remove the initial second dielectric layer located on the side surface and the edge of the second surface, and the remaining initial second dielectric layer located on the first surface serving as the second dielectric layer; using the second dielectric layer as an etching stop layer and using a second etching process to remove the initial first doped semiconductor layer located on the side surface and the edge of the second surface, and the remaining initial first doped semiconductor layer located on the first surface serving as the first doped semiconductor layer.

[0009] In some embodiments, the step of forming the first dielectric layer includes: forming an initial first dielectric layer on a surface of the second doped semiconductor layer away from the substrate; using a third etching process to remove the initial first dielectric layer located on the side surface and the edges of the first surface, and the remaining initial first dielectric layer located on the second surface serves as the first dielectric layer.

[0010] In some embodiments, the step of performing the etching process on the second doped semiconductor layer includes: using the first dielectric layer and the oxide layer as etching barriers, and etching the exposed second doped semiconductor layer with a first etching solution, only retaining the second doped semiconductor layer covered by the first dielectric layer and the oxide layer; wherein, the first etching solution includes an additive containing an oxide layer protecting agent.

[0011] In some embodiments, after performing the etching process on the second doped semiconductor layer, the method for manufacturing the solar cell further includes: cleaning the first surface and the second surface with a second etching solution to remove the first dielectric layer and the oxide layer.

[0012] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a solar cell, including: a substrate having a first surface and a second surface opposite to each other in a first direction, the first direction being the thickness direction of the substrate; a first doped semiconductor layer located on the first surface, and a positive projection of the first doped semiconductor layer in the first direction coincides with the first surface; a second doped semiconductor layer located not only on the second surface but also at least on a side surface connecting the first surface and the second surface, using at least the second doped semiconductor layer located on the side surface as an edge contact portion, the second doped semiconductor layer includes at least two edge contact portions arranged at intervals in a second direction on at least one side surface, the second direction being orthogonal to the first direction; wherein, a first doping element doped in the first doped semiconductor layer and a second doping element doped in the second doped semiconductor layer have different conduction types.

[0013] In some embodiments, a positive projection of the substrate on the first surface is an N-sided polygon, N being a positive integer greater than 2, and the substrate includes N side surfaces connected in sequence; the edge contact portions are located on at least one side surface, and multiple edge contact portions located on the same side surface are evenly arranged.

[0014] In some embodiments, the number of edge contact portions located on different side surfaces is different.

[0015] According to some embodiments of the present application, on the other hand, an embodiment of the present application further provides a photovoltaic module, including: a battery string formed by connecting a plurality of solar cells formed by the preparation method of any one of the above-mentioned solar cells, or formed by connecting a plurality of solar cells as described in any one of the above; an encapsulant film for covering the surface of the battery string; a cover plate for covering the surface of the encapsulant film facing away from the battery string; a frame for surrounding the outer peripheral side of the laminate, and the laminate includes the battery string, the encapsulant film and the cover plate.

[0016] The technical solution provided by the embodiment of the present application has at least the following advantages:

[0017] In the preparation method, to reduce the probability of the occurrence of hot spot effect in the solar cell, not only the second doped semiconductor layer located on the second surface is retained, but also at least a part of the second doped semiconductor layer located on the side surface connecting the first surface and the second surface is retained as an edge contact portion, so as to connect the first doped semiconductor layer located on the first surface and the second doped semiconductor layer located on the second surface by means of the edge contact portion. In this way, by using the conductivity of the edge contact portion, a conductive channel is established between the first surface and the second surface of the solar cell. When the solar cell itself has a defect or is blocked and becomes a relatively large load, the conductive channel established by the edge contact portion can serve as a current flow path in the solar cell, so that a small amount of current flows through the electrodes in the solar cell, and then the voltage and current divided by the solar cell as a load will also be correspondingly reduced, thereby reducing the problem of local heating caused by the current to the solar cell, improving the anti-hot spot performance of the solar cell, and further ensuring the safety of the solar cell and increasing the service life of the solar cell. In addition, to further retain at least a part of the second doped semiconductor layer located on the side surface as an edge contact portion, only one process needs to be added between the formation of the second doped semiconductor layer and the etching process of the second doped semiconductor layer, that is, at least the laser thermal oxidation process is performed on a part of the second doped semiconductor layer located on the side surface. Thus, while improving the anti-hot spot performance of the solar cell by means of the edge contact portion, there is no need to prepare an additional film layer to form the edge contact portion. Only by adding a laser thermal oxidation process once can the edge contact portion be finally formed, making the manufacturing process of the solar cell easy to control, simplifying the preparation process of the solar cell, and reducing the preparation cost of the solar cell. Description of the Drawings

[0018] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 FIG. 4 is a process flow chart of a method for preparing a solar cell provided by an embodiment of the present application;

[0020] Figures 2 to 9 FIG. 5 is a partial schematic diagram corresponding to each step in the method for preparing a solar cell provided by an embodiment of the present application;

[0021] Figure 10 FIG. 6 is another process flow chart of the method for preparing a solar cell provided by an embodiment of the present application;

[0022] Figure 11 FIG. 7 is a partial cross-sectional schematic diagram formed after performing a second doping diffusion process on the second surface in the method for preparing a solar cell provided by an embodiment of the present application;

[0023] Figure 12 FIG. 8 is a partial cross-sectional schematic diagram formed after performing a first etching process in the method for preparing a solar cell provided by an embodiment of the present application;

[0024] Figure 13 FIG. 9 is yet another process flow chart of the method for preparing a solar cell provided by an embodiment of the present application;

[0025] Figure 14 FIG. 10 is a partial cross-sectional schematic diagram formed after forming an initial first dielectric layer in the method for preparing a solar cell provided by an embodiment of the present application;

[0026] Figure 15 FIG. 11 is a partial cross-sectional schematic diagram formed after performing a cleaning process in the method for preparing a solar cell provided by an embodiment of the present application;

[0027] Figure 16 For Figure 15 a top view of the structure shown;

[0028] Figure 17 FIG. 12 is still another process flow chart of the method for preparing a solar cell provided by an embodiment of the present application;

[0029] Figure 18A partial cross-sectional schematic diagram after forming a first passivation layer in the method for manufacturing a solar cell provided by an embodiment of the present application;

[0030] Figure 19 A partial cross-sectional schematic diagram after forming a second passivation layer in the method for manufacturing a solar cell provided by an embodiment of the present application;

[0031] Figure 20 A partial cross-sectional schematic diagram after forming a first electrode and a second electrode in the method for manufacturing a solar cell provided by an embodiment of the present application;

[0032] Figure 21 A partial three-dimensional schematic diagram of a photovoltaic module provided by another embodiment of the present application;

[0033] Figure 22 is Figure 21 A cross-sectional schematic diagram along the cross-section direction MM1. Detailed implementation manners

[0034] As can be seen from the background art, it is necessary to seek a method to solve the hot spot effect.

[0035] Through analysis, it is found that one of the possible reasons for the current hot spot effect is that in some cases, when the photovoltaic module operates for a period of time, since the current value of each solar cell in the photovoltaic module depends on the light intensity received by each solar cell, if a part of the solar cells in the photovoltaic module are blocked by leaves or other objects, it may cause the polarity of the solar cell to be reversed, and further may cause the current intensity generated by the solar cell to be less than that of the fully illuminated solar cell, and further cause the power of the battery string where the solar cell is located to be significantly reduced.

[0036] Due to the different areas of the occlusion and the structure of the module, uncontrollable breakdown may occur on the occluded solar cell or adjacent multiple solar cells, and then local overheating may occur, which may cause damage to the solar cell. Since the occluded area may be a local area of the solar cell, the corresponding area has a high current density and strong heat generation, that is, the problem of hot spots, which may generate a large amount of heat in a small area and then damage the solar cell.

[0037] In general anti-hot spot solutions, mainly methods to solve the hot spot effect are sought at the photovoltaic module end. For example, after multiple solar cells are connected in series to form multiple battery strings, and multiple battery strings are connected in series or in parallel to assemble into a photovoltaic module, bypass diodes are arranged between the parallel battery strings. In other words, the bypass diodes are inserted into the circuit in the junction box of the photovoltaic module so that when the solar cell or battery string is blocked, the bypass diodes are activated and the circuit including the damaged solar cell is removed.

[0038] However, the design based on the bypass diode requires that the solar cell does not leak electricity or has low leakage performance. In other words, it is necessary to control the leakage current of the solar cell within a very small control range. Therefore, the manufacturing process requirements for solar cells are relatively high. When manufacturing solar cells, any defect during the manufacturing process may cause the leakage current to exceed the control range, reducing the ability to resist hot spot risks.

[0039] The present application provides a solar cell, a manufacturing method thereof, and a photovoltaic module. In the manufacturing method, to reduce the probability of the occurrence of the hot spot effect in the solar cell, not only the second doped semiconductor layer located on the second surface is retained, but also at least a part of the second doped semiconductor layer located on the side surface connecting the first surface and the second surface is retained as the edge contact portion, so as to connect the first doped semiconductor layer located on the first surface and the second doped semiconductor layer located on the second surface by means of the edge contact portion. In this way, by using the conductivity of the edge contact portion, a conductive channel is established between the first surface and the second surface of the solar cell. When the solar cell itself has defects or is blocked and becomes a relatively large load, the conductive channel established by the edge contact portion can be used as the current flow path in the solar cell, so that a small amount of current flows through the electrodes in the solar cell, and the voltage and current divided by the solar cell as a load will correspondingly decrease. Thereby, the problem of local heating caused by the current to the solar cell can be reduced, the hot spot resistance performance of the solar cell can be improved, and furthermore, the safety of the solar cell can be ensured, and the service life of the solar cell can be extended. In addition, to further retain at least a part of the second doped semiconductor layer located on the side surface as the edge contact portion, only one process needs to be added between the formation of the second doped semiconductor layer and the etching treatment of the second doped semiconductor layer, that is, at least laser thermal oxidation treatment is performed on a part of the second doped semiconductor layer located on the side surface. Thus, while improving the hot spot resistance performance of the solar cell by means of the edge contact portion, there is no need to prepare an additional film layer to form the edge contact portion. Only by adding one laser thermal oxidation treatment can the edge contact portion be finally formed, making the manufacturing process of the solar cell easy to control, simplifying the manufacturing process of the solar cell, and reducing the manufacturing cost of the solar cell.

[0040] In the description of the embodiments of the present application, technical terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "a plurality" is more than two, unless otherwise specifically and clearly defined.

[0041] References to "embodiments" in this specification mean that the particular features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0042] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: the existence of A, the simultaneous existence of A and B, and the existence of B. Additionally, the character " / " in this text generally represents an "or" relationship between the associated objects before and after.

[0043] In the description of the embodiments of the present application, the term "plurality" refers to two or more (including two). Similarly, "multiple groups" refers to two or more groups (including two groups), and "multiple pieces" refers to two or more pieces (including two pieces).

[0044] In the description of the embodiments of the present application, the orientation or positional relationship indicated by technical terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of the present application.

[0045] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "install", "connect", "couple", "fix", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0046] In the accompanying drawings corresponding to the embodiments of the present application, for better understanding and convenience of description, the thickness and area of the layers are enlarged. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component can be "directly" on the surface of the other component, or there can be a third component between the two components. On the contrary, when describing a component on the surface of another component or when a surface of a component forms or is provided with another component, it means that there is no third component between the two components. In addition, when describing a component "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor on a partial edge of the entire surface.

[0047] In the description of the embodiments of the present application, when a certain component "comprises" another component, unless otherwise specified, other components are not excluded, and other components may further be included. In addition, when components such as layers, films, regions, or plates are referred to as "on / located on" another component, it can be "directly on" the other component (i.e., on the surface of the other component with no other components therebetween), or there can be another component therebetween. In addition, when components such as layers, films, regions, plates, etc. are "directly located on" another component, or when components such as layers, films, regions, plates, etc. are located on the surface of another component, it means that no other components are located therebetween.

[0048] The terms used in the description of the various embodiments herein are only for describing specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is also intended to include the plural form, unless the context clearly indicates otherwise. Among them, the component includes components such as layers, films, regions, or plates.

[0049] The embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are presented for the reader to better understand the embodiments of the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present application can still be implemented.

[0050] An embodiment of the present application provides a method for preparing a solar cell. The method for preparing the solar cell provided by an embodiment of the present application will be described in detail below in conjunction with the accompanying drawings.

[0051] Figure 1 is a process flow diagram of a method for preparing a solar cell provided by an embodiment of the present application; Figures 2 to 9 is a partial schematic diagram corresponding to each step in the method for preparing a solar cell provided by an embodiment of the present application.

[0052] With reference to Figures 1 to 11 , the method for preparing a solar cell at least includes the following steps:

[0053] S1: With reference to Figure 2 , provide a substrate 100, the substrate 100 has a first surface 110 and a second surface 120 opposite to each other in a first direction X, and the first direction X is the thickness direction of the substrate 100.

[0054] S2: With reference to Figure 3 , form a first doped semiconductor layer 101 doped with a first doping element on the first surface 110, and the positive projection of the first doped semiconductor layer 101 in the first direction X coincides with the first surface 110.

[0055] S3: With reference to Figure 4 and Figure 5 , perform a second doping diffusion process on the second surface 120 to form a second doped semiconductor layer 102 doped with a second doping element. The second doped semiconductor layer 102 is located on the entire second surface 120, the side wall 130 connecting the first surface 110 and the second surface 120, and the edge of the first surface 110. The conduction types of the first doping element and the second doping element are different.

[0056] Wherein, since the positive projection of the first doped semiconductor layer 101 in the first direction X coincides with the first surface 110, the first doped semiconductor layer 101 has a side wall 111 connected to the side wall 130; the second doped semiconductor layer 102 is located on the side wall 130 connecting the first surface 110 and the second surface 120, so the second doped semiconductor layer 102 is also located on the side wall 111. Figure 4 is a partial cross-sectional view after forming the second doped semiconductor layer 102 and the first dielectric layer 103 in the method for preparing a solar cell provided by an embodiment of the present application; Figure 5 is Figure 4 a top view of the structure shown.

[0057] S4: Continuing to refer to Figure 4 , form a first dielectric layer 103 on the side of the second doped semiconductor layer 102 away from the second surface 120.

[0058] S5: With reference to Figures 4 to 7 , at least perform laser thermal oxidation treatment on a part of the second doped semiconductor layer 102 located on the side wall 130 to form at least two oxide layers 104 arranged at intervals in a second direction Y. A single oxide layer 104 is at least located on the side wall 130, and the second direction Y is orthogonal to the first direction X.

[0059] Wherein, Figure 6 is a partial cross-sectional view after forming the oxide layer 104 in the method for preparing a solar cell provided by an embodiment of the present application; Figure 7is Figure 6 a top view of the structure shown.

[0060] S6: Combine with reference Figures 6 to 9 , etch the second doped semiconductor layer 102 to remove the second doped semiconductor layer 102 not covered by the first dielectric layer 103 and the oxide layer 104. The remaining second doped semiconductor layer 102 covered by the oxide layer 104 serves as the edge contact portion 112 and is in electrical contact with the first doped semiconductor layer 101.

[0061] Among them, Figure 8 is a partial cross-sectional schematic diagram formed after etching the second doped semiconductor layer 102 in the method for manufacturing a solar cell provided by an embodiment of the present application; Figure 9 is Figure 8 a top view of the structure shown. In addition, Figure 8 uses a thick dashed line to demarcate the edge contact portion 112 in the remaining second doped semiconductor layer 102.

[0062] It should be noted that during the process of forming the second doped semiconductor layer 102 in step S3, due to the phenomenon of overplating, the second doped semiconductor layer 102 will be formed on the side surface 130, the side wall 111, and a part of the first surface 110. Generally speaking, in the finally formed solar cell, only the second doped semiconductor layer 102 located on the second surface 120 will be retained, and the second doped semiconductor layer 102 in other regions will be removed.

[0063] However, in the manufacturing method provided by an embodiment of the present application, to reduce the probability of the thermal spot effect occurring after the solar cell is shaded, not only the second doped semiconductor layer 102 located on the second surface 120 is retained, but also at least a part of the second doped semiconductor layer 102 located on a part of the side surface 130 is retained as the edge contact portion 112, so as to connect the first doped semiconductor layer 101 located on the first surface 110 and the second doped semiconductor layer 102 located on the second surface 120 through the edge contact portion 112. In other words, one end of the edge contact portion 112 is in electrical contact with the first doped semiconductor layer 101 located on the first surface 110, and the other end is in electrical contact with the second doped semiconductor layer 102 located on the second surface 120.

[0064] In this way, by utilizing the conductivity of the edge contact portion 112, a conductive channel is established between the first surface 110 and the second surface 120 of the solar cell. When the solar cell itself has defects or is blocked and becomes a relatively large load, the conductive channel established by the edge contact portion 112 can serve as a current flow path in the solar cell, enabling a small amount of current to flow through the electrodes in the solar cell. As a result, the voltage and current allocated to the solar cell as a load will also correspondingly decrease. In other words, based on the formation of the edge contact portion 112, the voltage across the solar cell as a load can be reduced, that is, the voltage between the first surface 110 and the second surface 120, thereby reducing the problem of local heating caused by the current to the solar cell, improving the thermal spot resistance performance of the solar cell, further ensuring the safety of the solar cell, and increasing the service life of the solar cell.

[0065] In addition, to further at least retain the second doped semiconductor layer 102 located on at least a partial region of the side surface 130 and the side wall 111 as the edge contact portion 112, only by adding step S5 between step S4 of forming the first dielectric layer 103 and step S6 of etching the second doped semiconductor layer 102, and at least performing laser thermal oxidation treatment on at least a partial second doped semiconductor layer 102 located on the side surface 130. While improving the thermal spot resistance performance of the solar cell by means of the edge contact portion 112, there is no need to prepare an additional film layer to form the edge contact portion 112. Only by adding one laser thermal oxidation treatment can the edge contact portion 112 be finally formed, making the manufacturing process of the solar cell easy to control, simplifying the manufacturing process of the solar cell, and reducing the manufacturing cost of the solar cell.

[0066] The following will describe in detail each step in the method for manufacturing a solar cell provided in an embodiment of the present application with reference to the accompanying drawings.

[0067] In some embodiments, with reference to Figures 10 to 12 and Figure 3 , Figure 10 is another process flow diagram of the method for manufacturing a solar cell provided in an embodiment of the present application, Figure 11 is a partial cross-sectional schematic diagram formed after performing a second doping diffusion process on the second surface in the method for manufacturing a solar cell provided in an embodiment of the present application, Figure 12 is a partial cross-sectional schematic diagram formed after performing a first etching process in the method for manufacturing a solar cell provided in an embodiment of the present application; forming the first doped semiconductor layer 101 may include the following steps:

[0068] S21: Refer to Figure 11, a first doping diffusion process is performed on the first surface 110 to form an initial first doped semiconductor layer 121 doped with a first doping element, and an initial second dielectric layer 131 is formed on the surface of the initial first doped semiconductor layer 121 away from the substrate 100. The initial first doped semiconductor layer 121 is located at the entire first surface 110, the side surface 130, and the edge of the second surface 120. It should be noted that there will also be a plating phenomenon during the first doping diffusion process, so that the initially formed initial first doped semiconductor layer 121 and the initial second dielectric layer 131 are not only located on the first surface 110. Subsequent deringing treatment is required to form the first doped semiconductor layer 101 that is finally only located on the first surface 110 (refer to Figure 3 ).

[0069] S22: Referring to Figure 11 and Figure 12 , a first etching process is used to remove the initial second dielectric layer 131 located at the edge of the side surface 130 and the second surface 120, and the remaining initial second dielectric layer 131 located on the first surface 110 is used as the second dielectric layer 141.

[0070] In one example, the first etching process can be a chain hydrofluoric acid process. The chain hydrofluoric acid process has a relatively high etching rate for the initial second dielectric layer 131, and the etching rate of the chain hydrofluoric acid process for the initial first doped semiconductor layer 121 is almost 0, that is, the etching rate of the chain hydrofluoric acid process for the initial second dielectric layer 131 is much greater than that of the initial first doped semiconductor layer 121. Therefore, only the initial second dielectric layer 131 located at the edge of the side surface 130 and the second surface 120 can be removed.

[0071] S23: Referring to Figure 12 and Figure 3 , using the second dielectric layer 141 as an etching barrier layer, a second etching process is used to remove the initial first doped semiconductor layer 121 located at the edge of the side surface 130 and the second surface 120, and the remaining initial first doped semiconductor layer 121 located on the first surface 110 is used as the first doped semiconductor layer 101.

[0072] In one example, the second etching process can be an alkali etching process. The alkali etching process has a relatively high etching rate for the initial first doped semiconductor layer 121, and the etching rate of the alkali etching process for the second dielectric layer 141 is almost 0, that is, the etching rate of the alkali etching process for the initial first doped semiconductor layer 121 is much greater than that of the second dielectric layer 141. Therefore, using the second dielectric layer 141 as an etching barrier layer, the initial first doped semiconductor layer 121 not covered by the second dielectric layer 141 is removed, that is, the initial first doped semiconductor layer 121 located at the edge of the side surface 130 and the second surface 120 is removed.

[0073] In some embodiments, with reference to Figure 13 , Figure 14 and Figure 4 , Figure 13 FIG. 202 is yet another process flow diagram of a method for manufacturing a solar cell provided by an embodiment of the present application, Figure 14 FIG. 203 is a partial cross-sectional view after forming an initial first dielectric layer in the method for manufacturing a solar cell provided by an embodiment of the present application; forming the first dielectric layer 103 may include the following steps:

[0074] S41: With reference to Figure 14 , form an initial first dielectric layer 113 on the surface of the second doped semiconductor layer 102 away from the substrate 100. It should be noted that during the second doping diffusion process, there is a phenomenon of overplating, which not only makes the formed second doped semiconductor layer 102 not only located on the first surface 110, but also makes the initial first dielectric layer 113 formed on the surface of the second doped semiconductor layer 102 away from the substrate 100. Subsequently, the initial first dielectric layer 113 needs to be selectively etched to form the final first dielectric layer 103 only on one side of the second doped semiconductor layer 102 away from the second surface 120 (refer to Figure 4 ).

[0075] S42: With reference to Figure 14 and Figure 4 , use a third etching process to remove the initial first dielectric layer 113 located on the side surface 130 and the edge of the first surface 110, and the remaining initial first dielectric layer 113 located on the second surface 120 serves as the first dielectric layer 103.

[0076] In one example, the third etching process may be a chain hydrofluoric acid process. The chain hydrofluoric acid process has a relatively high etching rate for the initial first dielectric layer 113, and the etching rate of the chain hydrofluoric acid process for the second doped semiconductor layer 102 is almost zero, that is, the etching rate of the chain hydrofluoric acid process for the initial first dielectric layer 113 is much greater than that of the second doped semiconductor layer 102. Therefore, only the initial first dielectric layer 113 located on the side surface 130 and the edge of the first surface 110 can be removed.

[0077] In some embodiments, with reference to Figure 2 , the substrate 100 provided in step S1 may be an N-type semiconductor substrate doped with an N-type doping element, the first doping element is a P-type doping element, and the second doping element is an N-type doping element. In some examples, the N-type doping element may be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As); the P-type semiconductor substrate is doped with a P-type element, and the P-type doping element may be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0078] In one example, referring to Figure 3 , in step S2, forming the first doped semiconductor layer 101 doped with the first doping element on the first surface 110 may be: performing a boron diffusion process on the substrate 100. In other words, the first doping diffusion process may be a boron diffusion process, so that at least part of the substrate 100 doped with the element boron (B) is regarded as the first doped semiconductor layer 101. The first doped semiconductor layer 101 can be regarded as a boron diffusion layer, and the material of the initial second dielectric layer 131 may be borosilicate glass.

[0079] In one example, referring to Figure 4 , the second doping diffusion process performed in step S3 may be a phosphorus diffusion process. The material of the formed second doped semiconductor layer 102 may be N-type polysilicon, and the material of the first dielectric layer 103 may be phosphosilicate glass. In other examples, the second doped semiconductor layer may be a composite thin film layer formed by laminating one or several of semiconductor thin films such as amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, hydrogenated microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide, or polysilicon doped with an N-type doping element.

[0080] In other embodiments, the substrate may also be a P-type semiconductor substrate doped with a P-type doping element. The first doping element of the first doped semiconductor layer is an N-type doping element, and the second doping element of the second doped semiconductor layer is a P-type doping element.

[0081] In some embodiments, the solar cell is a single-sided cell. Referring to Figure 2 , in step S1, the first surface 110 may be regarded as the front surface of the solar cell, that is, the first surface 110 can be used as the light-receiving surface for receiving incident light, and the second surface 120 can be used as the backlight surface. In other embodiments, the solar cell is a double-sided cell, then both the first surface and the second surface can be used as the light-receiving surface and can be used to receive incident light. It can be understood that the backlight surface described in an embodiment of the present application can also receive incident light, but the degree of receiving incident light is weaker than that of the light-receiving surface, so it is defined as the backlight surface. Subsequently, the first surface 110 is used as the light-receiving surface and the second surface 120 is used as the backlight surface as an example for description.

[0082] In some embodiments, there are at least the following situations where at least one side surface 130 is connected between the first surface 110 and the second surface 120: In some situations, referring to Figures 2 to 9, the orthographic projection of the base 100 on the first surface 110 can be a rectangle, and the rectangle can include at least two types, such as the corners being right angles or rounded corners. Based on this, there are 4 successively connected side surfaces 130 connected between the first surface 110 and the second surface 120, and any side surface 130 is approximately a plane; in some other cases, the orthographic projection of the base on the first surface can also be a circle or an ellipse, then there is one side surface connected between the first surface and the second surface, and this side surface is approximately a curved surface; in some other cases, the orthographic projection of the base on the first surface can also be an N-sided polygon other than a rectangle, where N is a positive integer greater than 2, then there are N successively connected side surfaces connected between the first surface and the second surface. It should be noted that hereinafter, the case where the orthographic projection of the base 100 on the first surface 110 is a rectangle will be taken as an example for illustration.

[0083] It should be noted that, based on the difference of the side surface 130, the second direction Y has different directions. Figure 5 , Figure 7 and Figure 9 only show one direction of the second direction Y.

[0084] In some embodiments, with reference to Figures 4 to 7 , the second doped semiconductor layer 102 located at the edge II of the first surface 110 includes: a portion to be removed 122 and a connecting portion 132 arranged in sequence along the direction from the center I of the first surface 110 to the edge II of the first surface 110. The connecting portion 132 is in contact connection with the second doped semiconductor layer 102 located on the side surface 130. It should be noted that Figure 6 delineates the edge II and the center I of the first surface 110 with a dashed line, and Figures 4 to 7 both delineate the portion to be removed 122 and the connecting portion 132 in the second doped semiconductor layer 102 located at the edge II of the first surface 110 with a dashed line. With reference to Figure 6 , the edge II of the first surface 110 surrounds the center I of the first surface 110.

[0085] On the above basis, with reference to Figures 4 to 9 , in the step of performing laser thermal oxidation treatment: not only the second doped semiconductor layer 102 located on the side surface 130 is subjected to laser thermal oxidation treatment, but also a partial area of the connecting portion 132 is subjected to laser thermal oxidation treatment, so that a single oxide layer 104 is not only located on the side surface 130, but also on the side of the remaining connecting portion 132 away from the first surface 110. It should be noted that after the etching treatment in step S6, the remaining connecting portion 132 can be used as part of the edge contact portion 112.

[0086] It should be noted that the oxide layer 104 is transformed from the surface of a part of the second doped semiconductor layer 102 under the influence of laser thermal oxidation treatment. In other words, a part of the second doped semiconductor layer 102 is transformed into the oxide layer 104 by laser thermal oxidation treatment. During the subsequent etching process of the second doped semiconductor layer 102 in step S6, there is no need to additionally prepare an etching barrier layer. Using the oxide layer 104 as the etching barrier layer can protect the second doped semiconductor layer 102 covered by the oxide layer 104 from being etched and finally be retained as the edge contact portion 112, which is beneficial to forming a mask layer with the existing film layer to fit the subsequent etching steps and further simplifies the process of manufacturing a solar cell.

[0087] It should be emphasized that during the laser thermal oxidation treatment in step S5, the laser thermal oxidation treatment is also performed on a part of the second doped semiconductor layer 102 located on the first surface 110, that is, the connection portion 132, so that the finally formed oxide layer 104 is not only located on the side surface 130 but also on the first surface 110. In other words, in a cross-section perpendicular to the first surface 110, the cross-sectional shape of the oxide layer 104 is L-shaped, and the cross-sectional shape of the subsequently formed edge contact portion 112 is also L-shaped. In this way, the edge contact portion 112 can be in electrical contact not only with the side surface 130 and the side wall 111 of the first doped semiconductor layer 101 but also with the side of the first doped semiconductor layer 101 away from the first surface 110.

[0088] In some embodiments, with reference to Figure 6 and Figure 7 , along the second direction Y, the ratio of the width of the connection portion 132 to the width of the substrate 100 is not greater than 0.11%. In practical applications, based on specific requirements, the ratio of the width of the connection portion 132 to the width of the substrate 100 can also be designed to be greater than 0.11%. In other words, the manufacturing method provided by an embodiment of the present disclosure does not impose too many restrictions on the width of the connection portion 132 in the second direction Y. It should be noted that when the solar cell has no faults or is not blocked, the solar cell can operate normally. To ensure the normal operation of the solar cell, the size of the finally formed edge contact portion 112 should not be too large, that is, the ability of the edge contact portion 112 to conduct the first doped semiconductor layer 101 and the second doped semiconductor layer 102 should not be too large. Based on this, it is only necessary to design the width of the connection portion 132 in the second direction Y to be small, so that the ratio of the width of the connection portion 132 used to protect the second doped semiconductor layer 102 in the etching process to the width of the substrate 100 is not greater than 0.11% to ensure the normal operation of the solar cell and improve the thermal spot resistance performance of the solar cell when the solar cell itself has faults or is blocked.

[0089] In some examples, along the second direction Y, the width of the connecting portion 132 can be 50 μm to 200 μm. For example, it can be 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm or 190 μm, etc.

[0090] In some examples, along the direction from the central region I to the edge region II of the substrate 100, the width of the substrate 100 can be 180 mm to 185 mm. For example, it can be 181 mm, 182 mm, 183 mm or 184 mm, etc.

[0091] In some embodiments, with reference to Figure 6 and Figure 7 , along the direction from the center I of the first surface 110 to the edge II of the first surface 110, the length of the connecting portion 132 can take any value according to specific requirements. In other words, the preparation method provided by an embodiment of the present disclosure does not impose excessive restrictions on the extension length of the connecting portion 132 on the first surface 110. In some embodiments, with reference to Figures 6 to 9 , along the second direction Y, a plurality of oxide layers 104 located on the same side surface 130 are uniformly arranged, and the interval between two adjacent oxide layers 104 is greater than or equal to 0.5 cm. In this way, it is beneficial to avoid the overly dense arrangement of the oxide layers 104, so as to avoid the overly dense arrangement of the finally formed edge contact portions 112, thereby avoiding too large a conduction ability between the first doped semiconductor layer 101 and the second doped semiconductor layer 102, and ensuring the normal operation of the solar cell when it is free of faults or unobstructed. It should be noted that in practical applications, a plurality of oxide layers located on the same side surface may also be non-uniformly arranged, that is, the intervals between different adjacent oxide layers can be different, and the interval size between adjacent oxide layers can be designed according to specific requirements.

[0092] In some embodiments, with reference to Figures 6 to 9 , the step of etching the second doped semiconductor layer 102 may include: using the first dielectric layer 103 and the oxide layer 104 as an etching mask layer, etching the exposed second doped semiconductor layer 102 with a first etching solution, and only retaining the second doped semiconductor layer 102 covered by the first dielectric layer 103 and the oxide layer 104; wherein, the first etching solution includes an additive containing an oxide layer protective agent. In this way, it is beneficial to ensure that the second doped semiconductor layer 102 covered by the first dielectric layer 103 and the oxide layer 104 is not etched by means of the additive containing an oxide layer protective agent. The remaining second doped semiconductor layer 102 located on the second surface 120 can be used as part of the passivation contact structure to improve the passivation effect on the second surface 120, and the remaining second doped semiconductor layer 102 can be used as the edge contact portion 112 to improve the thermal spot resistance performance of the solar cell.

[0093] In some cases, in the step of forming the first doped semiconductor layer 101 doped with the first doping element in step S2, a second dielectric layer 141 is further formed on the side of the first doped semiconductor layer 101 away from the first surface 110. Based on this, during the process of etching the exposed second doped semiconductor layer 102 with the first etching solution, the second dielectric layer 141 can be used to protect the first doped semiconductor layer 101 and prevent the first etching solution from etching the first doped semiconductor layer 101.

[0094] In some cases, in the step of forming the second doped semiconductor layer 102 doped with the second doping element in step S3, a tunneling layer (not shown in the figure) is further formed between the second surface 120 and the second doped semiconductor layer 102. In some examples, the material of the tunneling layer is silicon oxide. In this way, in the finally formed solar cell, the tunneling layer and the second doped semiconductor layer 102 form a passivation contact structure on the second surface 120, which is beneficial to improving the passivation effect on the second surface 120. Specifically, the second doped semiconductor layer 102 can form a band bending on the second surface 120, and the tunneling layer causes an asymmetric shift in the energy band of the second surface 120, such that the barrier for the majority carriers in the carriers is lower than the barrier for the minority carriers in the carriers. Therefore, the majority carriers can more easily perform quantum tunneling through the tunneling layer, while the minority carriers are difficult to pass through the tunneling layer to achieve selective transport of carriers. In addition, the tunneling layer has a chemical passivation effect. By saturating the dangling bonds on the second surface 120, the defect state density of the substrate 100 can be reduced, and the recombination centers of the substrate 100 can be reduced to lower the carrier recombination rate; the second doped semiconductor layer 102 has a field passivation effect and can form an electrostatic field pointing into the substrate 100 on the second surface 120, causing the minority carriers to escape from the interface, thereby reducing the minority carrier concentration, reducing the carrier recombination rate at the interface of the substrate 100, and increasing the open circuit voltage, short circuit current, and fill factor of the solar cell to improve the photoelectric conversion efficiency of the solar cell.

[0095] In some cases, the first etching solution can be an alkaline solution.

[0096] In some embodiments, with reference to Figure 8 、 Figure 9 、 Figure 15 and Figure 16 , after the etching treatment of the second doped semiconductor layer 102, the method for manufacturing a solar cell may further include: cleaning the first surface 110 and the second surface 120 with a second etching solution to remove the first dielectric layer 103 and the oxide layer 104.

[0097] It should be noted that in the step of cleaning the first surface and the second surface with the second etching solution, the second dielectric layer 141 that is not covered by the edge contact portion 112 is also removed, and the remaining second dielectric layer 141 is only located between the remaining second doped semiconductor layer 102 and the first doped semiconductor layer 101. In practical applications, the second dielectric layer on the first surface may also be retained.

[0098] Among them, Figure 15 is a schematic partial cross-sectional view formed after the cleaning process in the method for manufacturing a solar cell provided by an embodiment of the present application; Figure 16 is Figure 15 a top view of the structure shown. In addition, Figure 15 a thicker dashed line is used to demarcate the edge contact portion 112 in the remaining second doped semiconductor layer 102.

[0099] In some cases, the second etching solution can be an acidic solution.

[0100] In some embodiments, with reference to Figure 17 , Figure 18 , Figure 19 and Figure 20 , Figure 17 is another process flow chart of the method for manufacturing a solar cell provided by an embodiment of the present application, Figure 18 is a schematic partial cross-sectional view after forming the first passivation layer in the method for manufacturing a solar cell provided by an embodiment of the present application, Figure 19 is a schematic partial cross-sectional view after forming the second passivation layer in the method for manufacturing a solar cell provided by an embodiment of the present application, Figure 20 is a schematic partial cross-sectional view after forming the first electrode and the second electrode in the method for manufacturing a solar cell provided by an embodiment of the present application; after cleaning the first surface 110 and the second surface 120 with the second etching solution, the method for manufacturing a solar cell may further include the following steps:

[0101] S7: With reference to Figure 18 , a first passivation layer 105 is formed on the side of the first doped semiconductor layer 101 away from the first surface 110.

[0102] In some cases, continuing to refer to Figure 18 , the second dielectric layer 141 on the surface of the first doped semiconductor layer 101 away from the first surface 110 is not removed, and the first passivation layer 105 is formed on the surface of the second dielectric layer 141 away from the first doped semiconductor layer 101. In practical applications, when the second dielectric layer on the surface of the first doped semiconductor layer away from the first surface is removed, the first passivation layer can be directly formed on the surface of the first doped semiconductor layer away from the first surface.

[0103] In some cases, with continued reference to Figure 18 , the edge contact portion 112 is also located on the first surface 110, and the first passivation layer 105 covers the side of the edge contact portion 112 away from the first surface 110. In practical applications, the edge contact portion may be only located on the side surface. For example, the top surface of the edge contact portion along the first direction may be flush with the surface of the second dielectric layer away from the first surface, and the first passivation layer may be directly formed on the surface of the second dielectric layer away from the first surface and the top surface of the edge contact portion along the first direction.

[0104] In some examples, the first passivation layer 105 may be formed by a deposition process. In some examples, the material of the first passivation layer 105 may be alumina.

[0105] S8: With reference to Figure 19 , a second passivation layer 106 is formed on the first surface 110, the second surface 120, and the side surface 130, and the second passivation layer 106 covers the surface jointly exposed by the first passivation layer 105 and the second doped semiconductor layer 102.

[0106] In some cases, with continued reference to Figure 19 , the raw materials required for forming the second passivation layer 106 can be deposited once with the first surface 110 as the deposition surface, and then the raw materials required for forming the second passivation layer 106 can be deposited once with the second surface 120 as the deposition surface to finally form the second passivation layer 106.

[0107] In some cases, the material of the second passivation layer 106 may be silicon nitride. In other cases, the second passivation layer 106 may also be a laminated structure, and the material of the second passivation layer 106 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0108] S9: With reference to Figure 20 , a first electrode 107 is formed on the first surface 110. The first electrode 107 is sequentially embedded in the second passivation layer 106, the first passivation layer 105, and the second dielectric layer 141 along the first direction X to contact and connect with the first doped semiconductor layer 101; a second electrode 117 is formed on the second surface 120, and the second electrode 117 is embedded in the second passivation layer 106 along the first direction X to contact and connect with the second doped semiconductor layer 102.

[0109] In some cases, the first electrode 107 and the second electrode 117 can be formed by screen printing process respectively. In summary, in the preparation method provided by an embodiment of the present application, in order to reduce the probability of hot spot effect occurring after the solar cell is shaded, not only the second doped semiconductor layer 102 located on the second surface 120 is retained, but also at least a part of the second doped semiconductor layer 102 located on the side surface 130 is retained as the edge contact part 112, so as to connect the first doped semiconductor layer 101 located on the first surface 110 and the second doped semiconductor layer 102 located on the second surface 120 through the edge contact part 112. In this way, by using the conductivity of the edge contact part 112, a conductive channel is established between the first surface 110 and the second surface 120 of the solar cell. When the solar cell itself has defects or is shaded and becomes a relatively large load, the conductive channel established by the edge contact part 112 can be used as the current circulation path in the solar cell, so that a small amount of current flows through the electrodes in the solar cell, and the voltage and current divided by the solar cell as a load will also decrease correspondingly. Thus, the problem of local heating caused by the current to the solar cell can be reduced, so as to improve the anti-hot spot performance of the solar cell, and further ensure the safety of the solar cell and increase the service life of the solar cell. In addition, in order to further retain at least a part of the second doped semiconductor layer 102 located on the side surface 130 as the edge contact part 112, only by adding step S5 between step S4 of forming the first dielectric layer 103 and step S6 of etching the second doped semiconductor layer 102, and performing laser thermal oxidation treatment on at least a part of the second doped semiconductor layer 102 located on the side surface 130, the edge contact part 112 can be finally formed. While improving the anti-hot spot performance of the solar cell by means of the edge contact part 112, there is no need to prepare an additional film layer to form the edge contact part 112. Only by adding a laser thermal oxidation treatment once can the edge contact part 112 be finally formed, making the manufacturing process of the solar cell easy to control, simplifying the preparation process of the solar cell, and reducing the preparation cost of the solar cell.

[0110] Another embodiment of the present application also provides a solar cell, which is prepared by the preparation method of the solar cell provided by the foregoing embodiment. The solar cell provided by another embodiment of the present application will be described in detail below with reference to the drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiment will not be described in detail here.

[0111] With reference to Figure 15 and Figure 16, a solar cell includes: a substrate 100 having a first surface 110 and a second surface 120 opposite to each other in a first direction X, where the first direction X is the thickness direction of the substrate 100; a first doped semiconductor layer 101 located on the first surface 110, and the positive projection of the first doped semiconductor layer 101 in the first direction X coincides with the first surface 110; a second doped semiconductor layer 102 located not only on the second surface 120 but also at least on a side surface 130 connecting the first surface 110 and the second surface 120, and the second doped semiconductor layer 102 at least on the side surface 130 is used as an edge contact portion 112. The second doped semiconductor layer 102 includes at least two edge contact portions 112 spaced apart in a second direction Y and located at least on one side surface 130, and the second direction Y is orthogonal to the first direction X; wherein, the first doping element doped in the first doped semiconductor layer 101 and the second doping element doped in the second doped semiconductor layer 102 have different conductivity types.

[0112] It should be noted that for any edge contact portion 112, the edge contact portion 112 is not only in electrical contact with the side wall 111 of the first doped semiconductor layer 101 but also in electrical contact with the second doped semiconductor layer 102 located on the second surface 120. Thus, by using the conductivity of the edge contact portion 112, a conductive channel is established between the first surface 110 and the second surface 120 of the solar cell. When the solar cell itself has defects or is blocked and becomes a relatively large load, the conductive channel established by the edge contact portion 112 can serve as a current flow path in the solar cell, so that a small amount of current flows through the electrodes in the solar cell, and then the voltage and current divided by the solar cell as a load will also decrease correspondingly, thereby reducing the problem of local heating caused by the current to the solar cell, improving the thermal spot resistance performance of the solar cell, and further ensuring the safety of the solar cell and increasing the service life of the solar cell.

[0113] In addition, the edge contact portion 112 is a part of the second doped semiconductor layer 102, but the edge contact portion 112 is not located on the second surface 120, so the material of the edge contact portion 112 is the same as that of the second doped semiconductor layer 102.

[0114] It should be noted that Figure 15 and Figure 16 take the example that the edge contact portion 112 is located not only on the side surface 130 and the side wall 111 but also on a part of the first surface 110. In actual applications, the edge contact portion can also be only located on the side surface and the side wall. In addition, based on the difference of the side surface 130, the second direction Y has different directions, Figure 16 and only one direction of the second direction Y is shown in

[0115] In some embodiments, with reference to Figure 15 andFigure 16 The orthographic projection of the base 100 on the first surface 110 is an N-sided polygon, where N is a positive integer greater than 2. The base 100 includes N successively connected side surfaces 130; the edge contact portions 112 are located on at least one side surface 130, and multiple edge contact portions 112 located on the same side surface 130 are evenly arranged.

[0116] It should be noted that Figure 16 only takes the orthographic projection of the base 100 on the first surface 110 as a rectangle, that is, N is 4, and the base 100 includes 4 successively connected side surfaces 130 as an example. In practical applications, the orthographic projection of the base on the first surface can be circular, elliptical or an N-sided polygon other than a rectangle. In addition, the fact that multiple edge contact portions 112 located on the same side surface 130 are evenly arranged means that: among multiple edge contact portions 112 located on the same side surface 130, the distance between two adjacent edge contact portions 112 is equal to the distance between another two adjacent edge contact portions 112.

[0117] On this basis, designing that multiple edge contact portions 112 located on the same side surface 130 are evenly arranged is beneficial to ensuring that each area in the solar cell correspondingly has an edge contact portion 112 closest to it. Then, no matter which area inside the solar cell has a fault or is blocked, the current can be quickly discharged through the edge contact portion 112 closest to it, so as to reduce the problem of local heating caused by the current to the solar cell, thereby improving the thermal spot resistance performance of the solar cell.

[0118] In some embodiments, with reference to Figure 15 and Figure 16 , the number of edge contact portions 112 located on different side surfaces 130 can be the same. In other embodiments, the number of edge contact portions located on different side surfaces can also be different. In practical applications, the number of edge contact portions on any side surface can be designed according to actual needs. Figure 16 only takes the number of edge contact portions 112 located on different side surfaces 130 as the same as an example.

[0119] It should be noted that in practical applications, the probabilities of different regions in a solar cell being blocked or having failures may vary. For example, the probability of a failure occurring at the starting soldering point corresponding to a solder strip on the solar cell is greater. Therefore, more edge contact portions 112 can be designed on the side surface 130 close to the starting soldering point on the solar cell, that is, the number of edge contact portions located on different side surfaces is designed to be different, so as to further reduce the voltage at both ends of the solar cell acting as a load, thereby further reducing the heating power of the solar cell, effectively reducing the problem of local heating caused by the current to the solar cell, and further improving the thermal hotspot resistance performance of the solar cell. In this way, it is beneficial to make the final heating probabilities of different regions in the solar cell relatively small, and control the probabilities of the thermal hotspot effect occurring in different regions of the solar cell to be relatively small, so as to improve the overall thermal hotspot resistance performance of the solar cell.

[0120] In some embodiments, with reference to Figure 15 and Figure 16 , taking a certain side surface 130 as the target side surface, along the second direction Y, the ratio of the width of the edge contact portion 112 in contact with the target side surface to the width of the substrate 100 is not greater than 0.11%. In this way, it is beneficial to avoid the size of the edge contact portion 112 being too large, that is, to avoid the ability of the edge contact portion 112 to conduct the first doped semiconductor layer 101 and the second doped semiconductor layer 102 being too strong, so as to ensure the normal operation of the solar cell and improve the thermal hotspot resistance performance of the solar cell when the solar cell itself has a failure or is blocked.

[0121] In some examples, along the second direction Y, the width of the edge contact portion 112 can be 50 μm to 200 μm. For example, it can be 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm or 190 μm, etc.

[0122] In some embodiments, with reference to Figure 15 and Figure 16 , taking a certain side surface 130 as the target side surface, along the direction perpendicular to the target side surface, the length of the edge contact portion 112 in contact with the target side surface can take any value according to specific requirements. In other words, the solar cell provided by another embodiment of the present disclosure does not impose too many restrictions on the extension length of the edge contact portion 112 on the first surface 110. It should be noted that when the substrate 100 includes multiple side surfaces 130, the extension directions of the edge contact portions 112 in contact with different side surfaces 130 on the first surface 110 are different, and the length of the edge contact portion 112 in contact with the target side surface refers to the extension length of the edge contact portion 112 on the first surface 110.

[0123] In some embodiments, with reference toFigure 15 and Figure 16 Along the second direction Y, a plurality of edge contact portions 112 located on the same side surface 130 are evenly arranged, and the interval between two adjacent edge contact portions 112 located on the same side surface 130 is greater than or equal to 0.5 cm. In this way, it is beneficial to avoid the overly dense arrangement of the edge contact portions 112 finally located on the same side surface 130, thereby avoiding an excessive conduction ability between the first doped semiconductor layer 101 and the second doped semiconductor layer 102, and ensuring the normal operation of the solar cell when it is free of faults or unobstructed. It should be noted that in practical applications, the plurality of edge contact portions located on the same side surface may also be unevenly arranged, that is, the intervals between different adjacent edge contact portions may be different, and the interval size between adjacent edge contact portions can be designed according to specific requirements. To sum up, the second doped semiconductor layer 102 is designed to be not only located on the second surface 120, but also at least on the side surface 130, and the second doped semiconductor layer 102 located at least on the side surface 130 is used as the edge contact portion 112. The second doped semiconductor layer 102 includes at least two edge contact portions 112 arranged at intervals along the second direction Y, which is beneficial to establish a conductive channel between the first surface 110 and the second surface 120 by using the edge contact portion 112, so as to improve the thermal spot resistance performance of the solar cell, and further ensure the safety of the solar cell and improve the service life of the solar cell.

[0124] Another embodiment of the present application further provides a photovoltaic module, and the photovoltaic module is used to convert the received light energy into electrical energy. The following will describe in detail the photovoltaic module provided by another embodiment of the present application with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments will not be described in detail here.

[0125] With reference to Figures 15 to 22 , the photovoltaic module includes: a battery string, which is formed by connecting a plurality of solar cells 40 formed by the preparation method of the solar cell provided in the foregoing embodiment, or formed by connecting a plurality of solar cells 40 provided in the foregoing embodiment; an encapsulation adhesive film 41, which is used to cover the surface of the battery string; a cover plate 42, which is used to cover the surface of the encapsulation adhesive film 41 facing away from the battery string; a frame (not shown in the figure), which is used to surround the outer peripheral side of the laminate, and the laminate includes the battery string, the encapsulation adhesive film 41 and the cover plate 42. The solar cells 40 are electrically connected in the form of a whole piece or multiple sub-pieces to form a plurality of battery strings, and the plurality of battery strings are electrically connected in series and / or in parallel. In other words, the solar cell 40 can be a whole piece of battery or a sliced battery, and the sliced battery refers to a battery formed by cutting a complete whole piece of battery through a cutting process.

[0126] Among them, Figure 21 is a partial three-dimensional schematic diagram of a photovoltaic module provided by another embodiment of the present application; Figure 22 is Figure 21A schematic cross-sectional view along the section direction MM1.

[0127] In some embodiments, the solar cell 40 includes, but is not limited to, a PERC cell (Passivated Emitter Rear Cell), a TOPCon cell (Tunnel Oxide Passivated Contact), a HIT / HJT cell (Heterojunction Technology), a thin-film solar cell, a tandem cell, or any combination of cells having a passivated contact structure. Among them, the thin-film solar cell includes, but is not limited to, a perovskite thin-film solar cell, a copper indium selenide thin-film solar cell, a gallium arsenide thin-film solar cell, and a cadmium sulfide thin-film solar cell. The tandem cell includes, but is not limited to, a perovskite cell stacked with a crystalline silicon cell, a perovskite cell stacked with a perovskite cell, and a perovskite cell stacked with a thin-film cell.

[0128] In some embodiments, with reference to Figures 15 to 22 , the photovoltaic module may include a first region (not labeled in the figure) and at least one second region (not labeled in the figure), and the second region is prone to being blocked; the number of edge contact portions 112 on the side 130 of the solar cell located in the first region is a first number, and the number of edge contact portions 112 on the side 130 of the solar cell located in the second region is a second number, and the second number is greater than the first number.

[0129] It should be noted that in practical applications, the probability of being blocked or the probability of failure in different regions of the photovoltaic module will be different. In other words, the probability of the hot spot effect occurring on different solar cells in different regions of the photovoltaic module is different. Based on this, designing more edge contact portions 112 included in the solar cell that is prone to being blocked, that is, more edge contact portions 112 on the side 130 of the solar cell located in the second region, is beneficial to making the final heat generation probability in different regions of the photovoltaic module relatively small, controlling the probability of the hot spot effect occurring in different regions of the photovoltaic module to be relatively small, so as to improve the overall anti-hot spot performance of the photovoltaic module.

[0130] In some embodiments, with reference to Figure 21 and Figure 22 , multiple cell strings can be electrically connected through the solder ribbon 402. Figure 21Only the positional relationship between a plurality of solar cells 40 is schematically shown, that is, the arrangement directions of the electrodes with the same polarity of the solar cells 40 are the same, or in other words, the electrodes with the positive-polarity of each solar cell 40 are arranged towards the same side, so that the welding tapes 402 are respectively connected to different sides of two adjacent solar cells 40. In other embodiments, the solar cells may also be arranged such that the electrodes with different polarities face the same side, that is, the electrodes of adjacent multiple solar cells are sequentially arranged in the order of the first polarity, the second polarity, and the first polarity, and then the welding tapes connect two adjacent solar cells on the same side.

[0131] In some embodiments, no gap is provided between the solar cells, that is, the solar cells overlap each other.

[0132] In some embodiments, the encapsulation adhesive film 41 includes a first encapsulation layer and a second encapsulation layer. The first encapsulation layer covers one of the front or back surfaces of the solar cell 40, and the second encapsulation layer covers the other of the front or back surfaces of the solar cell 40. Specifically, at least one of the first encapsulation layer or the second encapsulation layer may be an organic encapsulation adhesive film such as a polyvinyl butyral (PVB) adhesive film, an ethylene-vinyl acetate copolymer (EVA) adhesive film, a polyethylene octene copolymer elastomer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film. Alternatively, at least one of the first encapsulation layer or the second encapsulation layer may also be an adhesive film such as an EP adhesive film, an EPE adhesive film, or a PVP adhesive film. Among them, the EP adhesive film refers to a co-extruded adhesive film composed of an EVA adhesive film and a POE adhesive film stacked, the EPE adhesive film refers to a co-extruded adhesive film formed by sequentially stacking an EVA adhesive film + a POE adhesive film + an EVA adhesive film, and the PVP adhesive film refers to a co-extruded adhesive film formed by stacking a POE adhesive film + an EVA adhesive film + a POE adhesive film. The co-extruded adhesive film can be prepared by extruding one or more raw materials onto another already formed adhesive film in sequence during the adhesive film processing, or by bonding different types of already formed adhesive films together.

[0133] In some cases, there is a demarcation line between the first encapsulation layer and the second encapsulation layer before lamination. After the lamination process, there will no longer be the concept of the first encapsulation layer and the second encapsulation layer in the formed photovoltaic module, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation adhesive film 41.

[0134] In some embodiments, the cover plate 42 may be a cover plate with a light-transmitting function such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate 42 facing the encapsulation adhesive film 41 may be a concave-convex surface or a suede surface including a plurality of convex structures, so as to increase the utilization rate of incident light. The cover plate 42 includes a first cover plate and a second cover plate. The first cover plate is opposite to the first encapsulation layer, and the second cover plate is opposite to the second encapsulation layer.

[0135] In some embodiments, the surface of the solar cell 40 has a plurality of main grids arranged at intervals along a third direction and a plurality of sub-grids arranged at intervals along a fourth direction. During the process of constructing a battery string using the solar cell 40, the solder tapes 402 are respectively electrically connected to at least one main grid on each of two adjacent solar cells 40. The solder tapes 402 can be electrically connected to the main grids by means of welding treatment to be electrically connected to the pads, or the solder tapes 402 can be pre-fixed above the main grids using glue dots, and electrical connection with the main grids can be achieved through the fusion of the glue dots and the deformation of the solder tapes 402 during the lamination process.

[0136] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application. In practical applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application should be subject to the scope defined by the claims.

Claims

1. A method for preparing a solar cell, providing a substrate having a first surface and a second surface opposite to each other in a first direction, the first direction being the thickness direction of the substrate, characterized in that, Further comprising: forming a first doped semiconductor layer doped with a first doping element on the first surface, the positive projection of the first doped semiconductor layer in the first direction coinciding with the first surface; performing a second doping diffusion process on the second surface to form a second doped semiconductor layer doped with a second doping element, the second doped semiconductor layer being located on the entire second surface, the side surface connecting the first surface and the second surface, and the edge of the first surface, the first doping element and the second doping element having different conduction types; forming a first dielectric layer on the side of the second doped semiconductor layer away from the second surface; performing laser thermal oxidation treatment on at least a part of the second doped semiconductor layer located on the side surface to form at least two oxide layers arranged at intervals in a second direction on at least one side surface, a single oxide layer being at least located on the side surface, the second direction being orthogonal to the first direction; etching the second doped semiconductor layer to remove the second doped semiconductor layer not covered by the first dielectric layer and the oxide layer, and the remaining second doped semiconductor layer covered by the oxide layer being used as an edge contact portion and being in electrical contact with the first doped semiconductor layer.

2. The manufacturing method of the solar cell according to claim 1, characterized in that, The second doped semiconductor layer located at the edge of the first surface includes: a to-be-removed portion and a connection portion arranged in sequence in the direction from the center of the first surface to the edge of the first surface, the connection portion being in contact connection with the second doped semiconductor layer located on the side surface; the step of performing the laser thermal oxidation treatment further includes: performing the laser thermal oxidation treatment on a partial area of the connection portion, so that a single oxide layer is not only located on the side surface, but also on the side of the remaining connection portion away from the first surface.

3. The manufacturing method of the solar cell according to claim 1, characterized in that, The step of forming the first doped semiconductor layer includes: performing a first doping diffusion process on the first surface to form an initial first doped semiconductor layer doped with the first doping element, and forming an initial second dielectric layer on the surface of the initial first doped semiconductor layer away from the substrate, the initial first doped semiconductor layer being located on the entire first surface, the side surface, and the edge of the second surface; using a first etching process to remove the initial second dielectric layer located on the side surface and the edge of the second surface, and the remaining initial second dielectric layer located on the first surface being used as the second dielectric layer; using a second etching process with the second dielectric layer as an etching stop layer to remove the initial first doped semiconductor layer located on the side surface and the edge of the second surface, and the remaining initial first doped semiconductor layer located on the first surface being used as the first doped semiconductor layer.

4. The manufacturing method of the solar cell according to claim 1, characterized in that, The step of forming the first dielectric layer includes: forming an initial first dielectric layer on the surface of the second doped semiconductor layer away from the substrate; using a third etching process to remove the initial first dielectric layer located on the side surface and the edge of the first surface, and the remaining initial first dielectric layer located on the second surface being used as the first dielectric layer.

5. The manufacturing method of the solar cell according to any one of claims 1 to 4, characterized in that, The step of performing the etching process on the second doped semiconductor layer includes: using the first dielectric layer and the oxide layer as etching barriers, and etching the exposed second doped semiconductor layer with a first etching solution, only retaining the second doped semiconductor layer covered by the first dielectric layer and the oxide layer; Wherein, the first etching solution includes an additive containing an oxide layer protective agent.

6. The manufacturing method of the solar cell according to claim 1 or 2, characterized in that, After performing the etching process on the second doped semiconductor layer, the method for manufacturing the solar cell further includes: Performing a cleaning process on the first surface and the second surface with a second etching solution to remove the first dielectric layer and the oxide layer.

7. A solar cell, characterized in that, Including: A substrate having a first surface and a second surface opposite to each other in a first direction, and the first direction is the thickness direction of the substrate; A first doped semiconductor layer located on the first surface, and the orthographic projection of the first doped semiconductor layer in the first direction coincides with the first surface; A second doped semiconductor layer, which is not only located on the second surface but also at least on the side surface connecting the first surface and the second surface. The second doped semiconductor layer located at least on the side surface is used as an edge contact portion. The second doped semiconductor layer includes at least two edge contact portions arranged at intervals in a second direction on at least one side surface, and the second direction is orthogonal to the first direction; Wherein, the first doping element doped in the first doped semiconductor layer and the second doping element doped in the second doped semiconductor layer have different conduction types.

8. The solar cell according to claim 7, characterized in that, The orthographic projection of the substrate on the first surface is an N-sided polygon, N is a positive integer greater than 2, and the substrate includes N side surfaces connected in sequence; the edge contact portion is located on at least one side surface, and multiple edge contact portions located on the same side surface are evenly arranged.

9. The solar cell according to claim 8, wherein, The number of edge contact portions located on different side surfaces is different.

10. A photovoltaic module, characterized in that, Including: A battery string formed by connecting multiple solar cells formed by the method for manufacturing a solar cell according to any one of claims 1 to 6, or formed by connecting multiple solar cells according to any one of claims 7 to 9; An encapsulation adhesive film for covering the surface of the battery string; A cover plate for covering the surface of the encapsulation adhesive film facing away from the battery string; A frame for surrounding the outer periphery of the laminate, and the laminate includes the battery string, the encapsulation adhesive film, and the cover plate.

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