TOPCon battery structure and preparation method thereof

Abstract

The invention belongs to the technical field of solar cells, particularly discloses a TOPCon cell structure and a preparation method thereof, and aims to reduce metal recombination and parasitic absorption and improve the light utilization rate and the cell efficiency. The cell structure comprises an n-type silicon substrate, metal electrodes are arranged on the front and back surfaces of the n-type silicon substrate, and the surface of the n-type silicon substrate is divided into a metalized region and a non-metalized region. The front metallization region is sequentially provided with a p + crystalline silicon layer, a tunneling oxide layer, a p + polycrystalline silicon layer, an aluminum oxide layer and a front antireflection passivation layer; and no p + polycrystalline silicon layer exists in the non-metallization region. The back surface structure is similar but n-type doped. The preparation method comprises the steps of boron diffusion, tunneling oxide layer generation, polycrystalline silicon layer deposition, selective removal and the like. According to the invention, through regionalization design and accurate control of parameters such as layer thickness and doping concentration, the cell structure is optimized, and the photoelectric conversion efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a TOPCon cell structure and a preparation method thereof. Background Art

[0002] The TOPCon cell, namely the tunnel passivated contact cell, is a solar cell structure with high photoelectric conversion efficiency. Its basic structure is as follows: the front structure from the substrate to the outermost layer is a p-type doped crystalline silicon layer, an aluminum oxide layer, and an antireflection passivation layer in sequence, and the front metal electrode is directly in contact with the p-type doped crystalline silicon layer. The back structure from the substrate to the outermost layer is an oxide layer, an n-type doped polysilicon layer, and an antireflection passivation layer in sequence, and the back metal electrode is directly in contact with the n-type doped polysilicon layer. During the preparation process, first, double-sided pre-cleaning is performed on the n-type silicon substrate to remove metal particles and other impurities on the substrate surface. Then, a pyramid structure is prepared on the front with an alkaline solution, and then boron doping is carried out on the front of the substrate by boron diffusion to form a p-type doped crystalline silicon layer. After that, oxygen or nitrous oxide is introduced to generate a silicon oxide layer on the back of the substrate. Further, an intrinsic polysilicon layer is prepared on the back of the substrate by LPCVD, and it is doped by phosphorus diffusion to form n-type doped polysilicon, or an n-type doped amorphous silicon layer is prepared by PECVD and then annealed at high temperature to form n-type doped polysilicon. Finally, an antireflection passivation film is deposited and metal electrodes are printed.

[0003] The existing TOPCon cell structure and preparation method have the following problems: the front metal electrode is directly in contact with the p-type doped crystalline silicon layer, resulting in serious metal recombination and reducing the open-circuit voltage of the cell. In order to reduce the metal recombination on the front, a tunneling oxide layer and a p-type doped polysilicon layer are prepared on the front of the cell, but the polysilicon layer has a large light absorption coefficient, increasing the parasitic absorption on the front and reducing the light utilization rate, thereby reducing the short-circuit current of the cell. Some technologies reduce or remove part of the p-type doped polysilicon between the grid lines. Although the parasitic absorption of the polysilicon is reduced, the pn junction area is reduced, and the open-circuit voltage of the cell is reduced. The tunneling passivation structure on the back reduces the metal recombination on the back, but increases the parasitic absorption of the polysilicon layer, resulting in light absorption loss and reducing the cell current. Some technologies reduce or remove part of the n-type doped polysilicon layer between the grid lines. Although the parasitic absorption of the polysilicon is reduced, the electron convergence ability of the non-metallized area is reduced, thereby reducing the electron current of the cell. Therefore, the existing technology cannot balance the solution of the metal recombination and parasitic absorption problems, resulting in the inability to further improve the cell efficiency.

[0004] In view of this, there is an urgent need for a TOPCon cell structure and a preparation method thereof to solve the above problems. Summary of the Invention

[0005] The object of the present invention is to provide a TOPCon cell structure and a preparation method thereof, which have the advantages of reducing metal recombination and parasitic absorption, improving light utilization rate and cell efficiency.

[0006] To achieve the above object, in one aspect, the present invention proposes a TOPCon cell structure, including an n-type silicon substrate, metal electrodes are provided on both the front and back surfaces of the n-type silicon substrate, and the surfaces of the n-type silicon substrate facing the two metal electrodes have metallized regions and non-metallized regions; wherein: the front metallized region sequentially has a p+ crystalline silicon layer, a tunneling oxide layer, a p+ polysilicon layer, an aluminum oxide layer, and a front anti-reflection passivation layer from the n-type silicon substrate outward; the front non-metallized region sequentially has a p+ crystalline silicon layer, a tunneling oxide layer, an aluminum oxide layer, and a front anti-reflection passivation layer from the n-type silicon substrate outward; the back metallized region sequentially has an n+ crystalline silicon layer, a tunneling oxide layer, an n+ polysilicon layer, and a back anti-reflection passivation layer from the n-type silicon substrate outward; the back non-metallized region sequentially has an n+ crystalline silicon layer, a tunneling oxide layer, and a back anti-reflection passivation layer from the n-type silicon substrate outward; the doping depth of the p+ crystalline silicon layer is 0.5 μm to 2 μm, and the doping depth of the n+ crystalline silicon layer is 0.3 μm to 0.6 μm.

[0007] Further, in the front metallized region, the width of the p+ polysilicon layer is 50 μm to 300 μm and is greater than the width of the metal electrode.

[0008] Further, the thickness of the tunneling oxide layer is 1.5 nm to 2 nm, the thickness of the p+ polysilicon layer is 70 nm to 200 nm, and the thickness of the n+ polysilicon layer is 90 nm to 200 nm.

[0009] Further, the boron doping concentration of the p+ crystalline silicon layer is 3E+17 to 8E+19 atoms / cm 3 , and the phosphorus surface concentration of the n+ crystalline silicon layer ≥ 8E+20 atoms / cm 3 .

[0010] In another aspect, the present invention also proposes a preparation method of a TOPCon cell structure for preparing the above TOPCon cell structure, and the method includes the following steps:

[0011] Form a p+ crystalline silicon layer on the front surface of the n-type silicon substrate by boron diffusion;

[0012] Generate a tunneling oxide layer on the surface of the p+ crystalline silicon layer;

[0013] Deposit a p+ polysilicon layer on the tunneling oxide layer, and distinguish the metallized and non-metallized regions by laser or chemical etching;

[0014] Form an n+ crystalline silicon layer on the back surface of the silicon substrate by phosphorus diffusion;

[0015] A tunneling oxide layer is formed on the surface of the n+ crystalline silicon layer and an n+ polysilicon layer is deposited.

[0016] The polysilicon layer in the non-metallized area is removed, and the polysilicon layer in the metallized area is retained.

[0017] An alumina layer and an antireflection passivation layer are deposited on the front and back surfaces respectively.

[0018] Print metal electrodes to ensure that the electrodes only contact the polysilicon layer and do not penetrate to the substrate.

[0019] Furthermore, the p+ polysilicon layer is deposited by LPCVD or PECVD, and the boron doping concentration is ≥2E+20 atoms / cm 3 ; the n+ polysilicon layer is deposited by LPCVD or PECVD, and the phosphorus doping concentration is 2E+20 - 1E+21 atoms / cm 3 .

[0020] Furthermore, the p+ polysilicon layer and the n+ polysilicon layer in the non-metallized area are selectively removed by an alkaline solution, and the borosilicate glass or phosphosilicate glass layer in the metallized area is removed by pickling.

[0021] Furthermore, the tunneling oxide layer is formed by introducing oxygen or nitrous oxide at 800°C - 950°C, and the thickness is controlled at 1.5 nm - 2 nm.

[0022] Furthermore, the width of the p+ polysilicon layer in the metallized area is 1.5 - 5 times the width of the metal electrode, and the area differentiation is achieved by laser etching or photolithography

[0023] Compared with the prior art, the present invention discloses at least the following beneficial effects:

[0024] A TOPCon battery structure and a preparation method thereof provided by the present application, by setting a layered structure of a metallized area and a non-metallized area, and controlling the doping depth and the width of the polysilicon layer, reduce metal recombination and parasitic light absorption while reducing metal recombination, and finally effectively improve the battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0026] Figure 1 It is a schematic structural diagram of the TOPCon battery structure of the present invention;

[0027] In the figure: 1. n-type silicon substrate; 2. front metal electrode; 3. back metal electrode; 11. P+ crystalline silicon layer; 12. front tunneling oxide layer; 13. P+ polysilicon layer; 14. alumina layer; 15. front antireflection passivation layer; 21. n+ crystalline silicon layer; 22. back tunneling oxide layer; 23. n+ polysilicon layer; 24. back antireflection passivation layer. Detailed implementation manners

[0028] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0029] In the prior art, the metal electrodes of the tunneling passivated contact battery directly contact the crystalline silicon layer, resulting in significant metal recombination problems. At the same time, the polysilicon layer causes parasitic absorption in the light absorption region, reducing the light utilization rate. Existing methods attempt to thin or partially remove the polysilicon layer, but it is difficult to balance the conductive requirements and optical losses, resulting in limited improvement in battery efficiency. For example, in the manufacturing scenario of high-efficiency solar cells, it is necessary to simultaneously solve the carrier recombination in the electrode contact region and the light absorption loss in the non-contact region, while the traditional structure cannot take both aspects into account.

[0030] To solve the above problems, by analyzing the functional differences between the metallized region and the non-metallized region, it is proposed to introduce a polysilicon layer as a conductive transition layer in the contact region, and replace it with an optically transparent oxide layer in the non-contact region. Specifically, first, it is clear that the metallized region requires low-resistance contact, while the non-metallized region needs to minimize light loss; second, selective deposition and etching techniques are used to achieve the regional distribution of the polysilicon layer; finally, the passivation effect is optimized through the combination of alumina and the tunneling oxide layer. This idea decouples the conductive requirements and optical optimization, and realizes the synergistic effect through structural zoning.

[0031] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0032] Refer to Figure 1As shown in the figure, the present invention provides a TOPCon battery structure, including: an n-type silicon substrate 1, a front metal electrode 2 disposed on one side of the n-type silicon substrate 1, and a back metal electrode 3 disposed on the other side of the n-type silicon substrate 1; wherein: the front metallization region sequentially has a P+ crystalline silicon layer 11, a front tunneling oxide layer 12, a P+ polysilicon layer 13, an alumina layer 14, and a front antireflection passivation layer 15 from the n-type silicon substrate 1 outwards; the front non-metallization region sequentially has a P+ crystalline silicon layer 11, a front tunneling oxide layer 12, an alumina layer 14, and a front antireflection passivation layer 15 from the n-type silicon substrate 1 outwards; the back metallization region sequentially has an n+ crystalline silicon layer 21, a back tunneling oxide layer 22, an n+ polysilicon layer 23, and a back antireflection passivation layer 24 from the n-type silicon substrate 1 outwards; the back non-metallization region sequentially has an n+ crystalline silicon layer 21, a back tunneling oxide layer 22, and a back antireflection passivation layer 24 from the n-type silicon substrate 1 outwards; the doping depth of the P+ crystalline silicon layer 11 is greater than that of the n+ crystalline silicon layer 21.

[0033] Among them, the antireflection passivation layer refers to an optical thin film prepared by silicon nitride or alumina materials, which is used to reduce surface reflection loss and can be specifically realized by plasma-enhanced chemical vapor deposition. The alumina layer 14 refers to an alumina thin film for surface chemical passivation, which is formed by atomic layer deposition and can reduce the interface state density. The P+ polysilicon layer 13 refers to a conductive layer formed by annealing boron-doped amorphous silicon deposited in the metallization region, which is prepared by low-pressure chemical vapor deposition and is used to establish an ohmic contact between the metal electrode and the crystalline silicon. The tunneling oxide layer refers to an ultra-thin silicon oxide layer, which is generated by a high-temperature oxidation process and allows carrier tunneling transmission while suppressing recombination. The oxide layer refers to a dielectric layer formed by silicon dioxide or silicon nitride materials, which replaces the polysilicon layer in the non-metallization region to reduce light absorption. The P+ crystalline silicon layer 11 and the n+ crystalline silicon layer 21 are respectively formed by boron and phosphorus diffusion, and the doping depth difference adapts to the carrier diffusion characteristics.

[0034] Specifically, the front metallization region realizes low-resistance contact through the P+ polysilicon layer 13, avoiding metal directly penetrating into the crystalline silicon to cause recombination, and the tunneling oxide layer promotes hole selective transmission. The front non-metallization region uses an oxide layer to replace the polysilicon, retaining the passivation effect while eliminating parasitic absorption and enhancing the light absorption efficiency. The n+ polysilicon layer 23 in the back metallization region reduces the electron contact resistance, and the oxide layer in the non-metallization region reduces the back optical loss. The deeper doping depth of the P+ crystalline silicon layer 11 ensures effective hole collection, while the shallower doping of the n+ crystalline silicon layer 21 reduces surface recombination. Through the partitioned stacking design, this structure makes the polysilicon layer only exist in the electrode contact area, separating the conductive requirements and the optical optimization goals in terms of spatial distribution.

[0035] In a specific embodiment, the doping depth of the P+ crystalline silicon layer 11 is 0.5 μm to 2 μm, and the doping depth of the n+ crystalline silicon layer 21 is 0.3 μm to 0.6 μm.

[0036] Compared with the prior art, the traditional structure retains the polysilicon layer in the entire front region, resulting in parasitic absorption, and the direct contact between the electrode and the crystalline silicon layer causes recombination. This solution uses a differential layer structure in the metallization and non-metallization regions to optimize the conductivity with the polysilicon layer in the contact region, reduce the optical loss with the oxide layer in the non-contact region, and suppress recombination through the tunneling oxide layer. The prior art cannot achieve the selective distribution of the polysilicon layer, while this solution precisely controls its spatial position through the etching process, taking into account both the contact resistance and the optical performance.

[0037] Through the above technical solution, the present application effectively suppresses the direct contact recombination between the metal electrode and the crystalline silicon, and at the same time reduces the polysilicon parasitic absorption in the non-contact region. The polysilicon layer in the metallization region ensures low-resistance contact, the oxide layer in the non-metallization region improves the light utilization rate, and the tunneling oxide layer promotes the selective transport of carriers. On the basis of maintaining the passivation effect, this structure solves the contradiction between conductivity and light absorption through the regional material distribution, and improves the overall efficiency of the battery.

[0038] In a specific embodiment, the width of the P+ polysilicon layer 13 is 50 μm to 300 μm and is greater than the width of the metal electrode. Herein, the width of the P+ polysilicon layer 13 refers to the lateral extension dimension of this layer parallel to the surface of the silicon substrate, and specifically, the graphic boundary can be controlled by a laser etching or photolithography process. The width of the metal electrode refers to the coverage dimension of the metal conductor on the surface of the silicon wafer, which is formed by a screen printing or electroplating process. The limitation of the width range enables the polysilicon layer to form an extended region surrounding the electrode, which not only ensures the lateral transport path of carriers but also avoids excessive expansion of the light absorption area.

[0039] Specifically, the extension of the lateral contact region forms a gradient contact interface between the metal electrode and the P+ polysilicon layer 13, and the recombination probability decreases when carriers laterally diffuse into the electrode through the polysilicon layer. The setting of the coverage range enables the metal electrode to be completely wrapped inside the polysilicon layer, preventing the direct penetration of the electrode edge to the surface of the P+ crystalline silicon layer 11 to generate an interface state recombination center. The lower limit of the width ensures the processing margin of the laser etching process and avoids the residual polysilicon layer caused by etching deviation; the upper limit of the width controls the distribution range of the polysilicon layer in the non-electrode region, balancing the contact performance and the optical loss.

[0040] Compared with the prior art, the traditional structure has the polysilicon layer and the metal electrode set with the same width, resulting in insufficient contact area and increased contact resistance, which causes recombination losses. Some improved solutions reduce the contact resistance by expanding the width of the polysilicon layer, but this leads to an excessive increase in the light absorption area of the non-electrode region. This solution realizes an optimized balance between reducing the contact resistance and suppressing parasitic absorption by defining a width range and establishing a coverage relationship.

[0041] Through the above technical solutions, the present application effectively suppresses the interfacial recombination phenomenon caused by the contact between the edge of the metal electrode and the crystalline silicon, and at the same time avoids the light absorption loss caused by the over-wide polysilicon layer. The reasonable expansion of the contact area shortens the carrier transport path and reduces the recombination rate, while the precise control of the width range ensures the effective utilization of the incident light, ultimately achieving an improvement in the battery conversion efficiency. The complete coverage design of the metal electrode also ensures the process processing tolerance and prevents the structural failure caused by etching errors.

[0042] In a specific embodiment, the thickness of the tunneling oxide layer is controlled within the range of 1.5 nm to 2 nm, the thickness of the P+ polysilicon layer 13 is controlled within the range of 70 nm to 200 nm, and the thickness of the n+ polysilicon layer 23 is controlled within the range of 90 nm to 200 nm.

[0043] Among them, the tunneling oxide layer refers to an ultra-thin silicon oxide dielectric layer formed on the surface of the silicon substrate, which can be specifically formed by thermal oxidation by introducing oxygen or nitrous oxide under high-temperature conditions. This layer is used to achieve carrier-selective tunneling and suppress interfacial recombination. The P+ polysilicon layer 13 refers to a conductive layer formed by high-temperature crystallization of boron-doped amorphous silicon prepared by chemical vapor deposition. The thickness of this layer is limited to a specific range to balance the conductive performance and light absorption loss. The n+ polysilicon layer 23 refers to a conductive layer formed by high-temperature crystallization of phosphorus-doped amorphous silicon prepared by chemical vapor deposition. Its thickness range is set to meet the back-side electron transport requirements while avoiding excessive light absorption.

[0044] Specifically, if the thickness of the tunneling oxide layer is lower than the lower limit, it may lead to insufficient passivation effect, while exceeding the upper limit will increase the carrier tunneling barrier. By precisely controlling the thickness within the nanometer range, both efficient carrier tunneling can be maintained and interfacial recombination can be effectively suppressed. For the front-side P+ polysilicon layer 13, when the thickness is too thin, the lateral conductivity is insufficient, and when the thickness is too thick, it will cause parasitic absorption loss of the incident light. By defining its thickness range, the light absorption loss in the non-metallized region is reduced on the premise of ensuring the conductive performance of the electrode region. The back-side n+ polysilicon layer 23 adopts a thicker design than the front side, mainly considering that the back side requires stronger electron transport ability, but the light absorption is also avoided from being excessive through the upper limit control of the thickness.

[0045] Compared with the prior art, in the existing preparation methods, the thickness differences between the front and back polysilicon layers are not clearly distinguished, and the control accuracy of the tunneling oxide layer thickness is insufficient, resulting in the inability to balance parasitic absorption and passivation effects. This solution solves the photoelectric performance contradiction caused by layer thickness mismatch in traditional technologies by establishing different thickness standards for polysilicon layers in different regions and combining precise tunneling oxide layer control methods.

[0046] Through the above technical solution, this application realizes the collaborative optimization of light absorption loss and carrier transport efficiency in the battery structure. While maintaining effective passivation contacts, it significantly reduces the parasitic absorption of incident light by the polysilicon layer, thereby improving the photoelectric conversion efficiency of the battery.

[0047] In a specific embodiment, the boron doping concentration of the P+ crystalline silicon layer 11 is 3E+17 - 8E+19 atoms / cm 3 , and the phosphorus surface concentration of the n+ crystalline silicon layer 21 ≥ 8E+20 atoms / cm 3 .

[0048] Among them, the boron doping concentration of the P+ crystalline silicon layer 11 refers to the content range of boron atoms in the crystalline silicon layer, which can be specifically realized by boron diffusion or ion implantation processes. This concentration range can balance the hole transport efficiency and the recombination loss caused by lattice defects. The phosphorus surface concentration of the n+ crystalline silicon layer 21 refers to the minimum content of phosphorus atoms on the surface of the crystalline silicon, which can be specifically realized by phosphorus diffusion process. This concentration reduces the contact resistance by forming a highly conductive region and suppresses the interfacial carrier recombination at the same time.

[0049] Specifically, in the P+ crystalline silicon layer 11, the boron doping concentration is controlled within the range of 3E+17 - 8E+19 atoms / cm 3 . When the concentration is lower than the lower limit, insufficient hole concentration will lead to an increase in contact resistance; when the concentration exceeds the upper limit, aggravated lattice distortion will cause an increase in the density of recombination centers. For the n+ crystalline silicon layer 21, the phosphorus surface concentration is not less than 8E+20 atoms / cm 3 , ensuring the formation of a highly doped layer in the metal electrode contact region, reducing the contact barrier by enhancing the electron tunneling effect, and reducing the interface state density to suppress recombination at the same time. The combination of the two doping concentrations optimizes the built-in electric field distribution of the p - n junction, improving the carrier separation efficiency while reducing parasitic absorption.

[0050] Compared with the prior art, the existing TOPCon batteries do not clearly define the doping concentration ranges of the p+ and n+ crystalline silicon layers 21, and usually use a single concentration or a broad range, resulting in the inability to optimize the carrier recombination rate and the contact resistance simultaneously. For example, the existing p+ layer often uses a concentration lower than 3E+17 atoms / cm 3The concentration is too high, resulting in an excessive contact resistance; while the surface concentration of phosphorus in the n+ layer is often lower than 8E+20 atoms / cm 3 , causing interface recombination losses. This solution solves the performance contradiction caused by concentration imbalance by precisely defining the concentration range.

[0051] Through the above technical solution, the present application can reduce the hole transfer resistance between the P+ crystalline silicon layer 11 and the metal electrode, and at the same time inhibit the lattice defect recombination caused by high doping; in the n+ crystalline silicon layer 21, the ultra-high phosphorus concentration enhances the electron selective contact ability and reduces the interface recombination losses. The synergistic effect of the two enables the open circuit voltage and the short circuit current to be improved synchronously, overcoming the performance degradation problem caused by improper doping concentration in the traditional process.

[0052] The present invention also provides a preparation method for a TOPCon cell structure, including the following steps: forming a P+ crystalline silicon layer 11 on the front surface of an n-type silicon substrate 1 by boron diffusion; generating a tunneling oxide layer on the surface of the P+ crystalline silicon layer 11; depositing a P+ polysilicon layer 13 on the tunneling oxide layer, and differentiating the metallization and non-metallization regions by laser or chemical etching; forming an n+ crystalline silicon layer 21 on the back surface of the silicon substrate by phosphorus diffusion; generating a tunneling oxide layer on the surface of the n+ crystalline silicon layer 21 and depositing an n+ polysilicon layer 23; removing the polysilicon layer in the non-metallization region and retaining the polysilicon layer in the metallization region; depositing an aluminum oxide layer 14 and an antireflection passivation layer on the front and back surfaces respectively; printing metal electrodes to ensure that the electrodes only contact the polysilicon layer and do not penetrate to the substrate.

[0053] Among them, differentiating the metallization and non-metallization regions by laser or chemical etching means patterning the polysilicon layer with a laser beam or a selective etching solution with controllable energy density, such as using a pulsed laser with a wavelength of 532 nm or a hydrofluoric acid-based etching solution. This step can accurately define the interface between the conductive region and the non-conductive region. Removing the polysilicon layer in the non-metallization region means selectively removing the unprotected polysilicon thin film through a wet etching process, such as using a potassium hydroxide solution for anisotropic etching. This operation can eliminate the light absorption material in the non-conductive region. The aluminum oxide layer 14 refers to an amorphous aluminum oxide thin film formed by atomic layer deposition, such as using trimethylaluminum and water vapor as precursors and depositing at 300 °C. This layer can effectively inhibit surface carrier recombination. The metal electrodes only contact the polysilicon layer means controlling the penetration depth of the silver paste through screen printing technology, such as using a conductive paste with a viscosity of 200-400 Pa·s and sintering at a temperature below 400 °C. This process can block the direct contact between the metal and the silicon substrate.

[0054] Specifically, during the preparation process, the differential construction of the functional layer is achieved through spatial selective processing. In the front structure, the P+ polysilicon layer 13 is only retained in the metallization region, forming a localized carrier transport channel, while in the non-metallization region, only the tunneling oxide layer and the passivation layer are retained, maintaining the passivation effect and eliminating the light absorption loss. In the back structure, the selective retention of the polysilicon layer is carried out synchronously. The n+ polysilicon layer 23 in the metallization region serves as an electron transport medium, while in the non-metallization region, the parasitic absorption is reduced by removing the polysilicon layer. The combined deposition of the aluminum oxide layer 14 and the antireflection layer enhances the surface passivation and light trapping capabilities, and the defined contact mode between the metal electrode and the polysilicon layer constructs a three-dimensional carrier transport network. Through the synergistic effect of physical isolation and chemical treatment in each step, the directional transport of photo-generated carriers is achieved while maintaining the functional integrity of the pn junction.

[0055] Compared with the prior art, the existing methods use continuous polysilicon layers to cover both the front and the back, resulting in continuous light absorption losses in the non-metallization regions. In this method, the polysilicon layer is precisely defined in the electrode contact regions through patterning treatment, retaining the conductive function in the metallization regions and completely eliminating the parasitic absorption in the non-metallization regions. The recombination centers caused by the direct contact between the metal electrode and the silicon substrate in the existing processes are physically isolated by the polysilicon layer in this method, and at the same time, the retained tunneling oxide layer maintains the selective transport characteristics of the carriers.

[0056] Through the above technical solutions, this application effectively decouples the restrictive relationship between metal recombination and light absorption. In the front non-metallization region, the parasitic absorption loss is reduced by removing the P+ polysilicon layer 13, while the retained tunneling oxide layer and the passivation layer maintain the surface passivation effect; in the back non-metallization region, the light absorption loss is reduced by removing the n+ polysilicon layer 23, and the polysilicon layer retained in the metallization region ensures the effective collection of carriers. The specific contact mode between the metal electrode and the polysilicon layer blocks the recombination path, and the introduction of the aluminum oxide layer 14 further suppresses the interface recombination loss. This method realizes the multi-dimensional improvement of the photoelectric conversion efficiency through the spatial reconstruction of the functional layer.

[0057] In a specific embodiment, the P+ polysilicon layer 13 is deposited by LPCVD or PECVD, and the boron doping concentration is ≥2E+20 atoms / cm 3 ; the n+ polysilicon layer 23 is deposited by LPCVD or PECVD, and the phosphorus doping concentration is 2E+20 - 1E+21 atoms / cm 3 .

[0058] Among them, the LPCVD method refers to generating a polysilicon layer by thermally decomposing silane gas in a low-pressure environment. This method can form a polysilicon structure with high crystallinity to improve the carrier mobility. The PECVD method generates a polysilicon layer through plasma-enhanced chemical vapor deposition. Its advantage is that the deposition can be completed at a lower temperature to avoid damage to the silicon substrate passivation layer caused by high temperature. The boron doping concentration ≥ 2E+20 atoms / cm 3 The setting can ensure a sufficient hole carrier concentration to reduce the contact resistance, while avoiding the generation of recombination centers due to excessive concentration leading to lattice distortion. The phosphorus doping concentration is controlled within 2E+20 - 1E+21 atoms / cm 3 Within this range, while maintaining a high electron concentration, it can prevent the supersaturation precipitation of phosphorus atoms to form defect states.

[0059] Specifically, during the preparation of the P+ polysilicon layer 13, by selecting the deposition method of LPCVD or PECVD, the crystallization quality and thickness uniformity of the polysilicon layer can be optimized for different process conditions. The polysilicon layer generated by the LPCVD process has a higher grain size, which is beneficial to reducing the grain boundary scattering loss during the carrier transport process, while the PECVD process can reduce the damage to the substrate passivation layer structure caused by high temperature. The boron doping concentration is controlled at a level of ≥ 2E+20 atoms / cm 3 This concentration range can ensure a good ohmic contact between the polysilicon layer and the metal electrode, while avoiding an increase in lattice stress due to excessive doping concentration, which would exacerbate carrier recombination. For the n+ polysilicon layer 23, the phosphorus doping concentration is limited within the range of 2E+20 - 1E+21 atoms / cm 3 Within this interval, this range can not only meet the high electron concentration requirement to reduce the contact resistance, but also prevent the aggregation of phosphorus atoms at the grain boundaries to form recombination centers, thereby reducing the optical absorption loss while maintaining an efficient carrier transport path.

[0060] Compared with the prior art, in the prior art, the polysilicon layer usually adopts a single deposition process and the doping concentration is not optimized and controlled, resulting in a contradiction between reducing parasitic absorption and maintaining electrical conductivity in the polysilicon layer. For example, in some technologies, the thickness of the polysilicon layer is excessively thinned to reduce the optical absorption loss of the polysilicon layer, but this will lead to an increase in the contact resistance; in other technologies, too high a doping concentration is used to improve the conductivity, which instead exacerbates carrier recombination. This application realizes the balance between the optical absorption loss and the electrical conductivity of the polysilicon layer by limiting the process selection range of LPCVD and PECVD and combining the coordinated optimization of boron and phosphorus doping concentrations.

[0061] Through the above technical solution, the present application can effectively reduce the parasitic absorption of incident light by the polysilicon layer while maintaining the low contact resistance characteristic between the polysilicon layer and the metal electrode. The optimized settings of the boron doping concentration and the phosphorus doping concentration avoid the decrease in carrier transport efficiency caused by insufficient doping and prevent the lattice defects caused by excessive doping, thereby reducing the recombination loss while improving the carrier selectivity, and finally realizing the improvement of the photoelectric conversion efficiency of the solar cell.

[0062] The present application further proposes that the P+ polysilicon layer 13 and the n+ polysilicon layer 23 in the non-metallized area are selectively removed by an alkaline solution, and the borosilicate glass or phosphosilicate glass layer in the metallized area is removed by pickling.

[0063] Among them, the selective removal by the alkaline solution means using the corrosion characteristics of sodium hydroxide or potassium hydroxide solution on the polysilicon material to preferentially dissolve the conductive layer in the non-metallized area and retain the polysilicon layer in the metallized area as the electrode contact channel, thereby avoiding the optical absorption loss in the unnecessary area. Among them, the pickling removal means using hydrofluoric acid or a mixed solution of nitric acid and hydrofluoric acid to remove the silicon oxide residues formed in the high-temperature process in the metallized area, reduce the density of interface recombination centers, and ensure the low-resistance contact between the electrode and the polysilicon layer.

[0064] Specifically, in the non-metallized area, the corrosion rate of the alkaline solution on the polysilicon is much higher than that on the passivation layer, and it can accurately remove the p+ polysilicon or n+ polysilicon covering the passivation layer, and retain the complete alumina layer 14 and the tunneling oxide layer structure. This process eliminates the parasitic absorption of incident light by the polysilicon in the non-metallized area and maintains the effective area of the pn junction at the same time. In the metallized area, the acid solution preferentially dissolves the borosilicate glass or phosphosilicate glass layer and removes the silicon oxide residues generated during the high-temperature diffusion process, so that the metal electrode can directly contact the polysilicon layer with a high doping concentration, reducing the recombination loss of carriers at the interface. The combination of the two processes not only reduces the optical absorption loss but also improves the carrier transport efficiency.

[0065] Compared with the prior art, the traditional process does not distinguish the chemical treatment methods for the metallized and non-metallized areas, resulting in optical absorption loss caused by the polysilicon layer in the non-metallized area and the ineffective removal of the silicon oxide residues in the metallized area. This solution selectively treats with alkaline and acid solutions in different areas, and completely removes the non-functional layer while retaining the necessary conductive structure, avoiding optical loss and reducing the density of recombination centers at the contact interface.

[0066] Through the above technical solution, the present application effectively solves the problem of light loss caused by the parasitic absorption of the polysilicon layer in the non-metallized area, and at the same time eliminates the problem of carrier recombination caused by the residue of the passivation layer in the metallized area, realizing the synergistic improvement of the photoelectric conversion efficiency.

[0067] In a specific embodiment, the tunneling oxide layer is formed by introducing oxygen or nitrous oxide at a temperature of 800°C to 950°C, and the thickness is controlled within the range of 1.5 nm to 2 nm.

[0068] Among them, oxygen or nitrous oxide is used as the oxidation source. The composition of the oxide layer can be controlled by adjusting the gas flow ratio. Oxygen is suitable for generating silicon oxide with a stable stoichiometric ratio, and the active oxygen generated by the decomposition of nitrous oxide can improve the oxidation uniformity. This selection provides process adaptability for solving the problem of insufficient compactness of the traditional oxide layer. Among them, the temperature range is limited to 800°C to 950°C. The oxidation reaction rate is controlled by thermodynamic equilibrium, which can not only ensure the full oxidation of the silicon surface to form a continuous oxide film, but also inhibit the lateral diffusion of doping elements in the polysilicon layer. This temperature window provides the basic conditions for the thickness stability of the oxide layer. Among them, the thickness is controlled within the range of 1.5 nm to 2 nm, and atomic-level precision is achieved through the coordinated regulation of time and temperature. This thickness range enables the best balance between the carrier tunneling probability and the suppression of surface recombination. This parameter range solves the problems of passivation failure or transmission blockage caused by thickness fluctuations in the traditional process.

[0069] Specifically, during the oxidation process, by selecting oxygen or nitrous oxide as the reaction medium, a controlled oxidation reaction is promoted on the silicon surface in a high-temperature environment. The oxygen vacancy concentration of the silicon oxide generated in an oxygen environment is relatively low, which can improve the interface state passivation effect; the nitrogen element generated by the decomposition of nitrous oxide can fill the defects in the oxide layer and further reduce the interface recombination. The precise control of the temperature parameter enables the growth rate of the oxide layer to match the silicon substrate lattice, avoiding stress cracks caused by thermal expansion differences. The thickness control realizes closed-loop regulation by real-time monitoring of the ellipsometry spectrum signal, ensuring that the oxide layer can not only form an effective carrier tunneling channel but also block the direct contact between the metal electrode and the silicon substrate.

[0070] Compared with the prior art, the traditional process uses a single oxidation gas and has a wide temperature control range, resulting in pinhole defects or local over-thickness in the oxide layer. This solution realizes the dual optimization of the composition and structure of the oxide layer through the selection of a dual-gas system and the process design with a narrow temperature window. In the prior art, the thickness of the oxide layer usually fluctuates in the range of 1 to 3 nm. This solution compresses the thickness fluctuation to less than 0.5 nm through dynamic growth control, significantly improving the uniformity of interface passivation.

[0071] Through the above technical solutions, this application effectively solves the problem of the imbalance between the carrier transport efficiency and the surface passivation effect caused by the inaccurate thickness of the tunneling oxide layer. The improvement of the oxide layer density reduces the density of interface recombination centers while maintaining the barrier width required for quantum tunneling. The precise definition of process parameters enables the oxide layer to serve as both an effective carrier selective transport channel and an excellent surface passivation function, ultimately realizing the synchronous optimization of the open-circuit voltage and fill factor of the battery.

[0072] In a specific embodiment, the width of the P+ polysilicon layer 13 in the metallization region is 1.5 to 5 times the width of the metal electrode, and the area differentiation is achieved through laser etching or photolithography processes.

[0073] Among them, the ratio relationship between the width of the P+ polysilicon layer 13 in the metallization region and the width of the metal electrode refers to the multiple relationship formed by the lateral dimension of the p-type doped polysilicon layer relative to the coverage range of the metal electrode in the front-side metallization region of the battery. Specifically, the ratio control can be achieved by using a laser spot scanning or mask exposure process. By limiting this ratio range, it can not only ensure that the polysilicon layer completely covers the electrode contact area, but also avoid the parasitic absorption caused by the over-wide non-necessary area. Among them, the laser etching or photolithography process refers to selectively removing the polysilicon layer with a high-energy laser beam, or chemically etching after forming a protective layer through the pattern transfer of photosensitive materials. Specifically, a UV laser or a deep ultraviolet lithography machine can be used to achieve micron-level processing accuracy. This process can precisely control the graphic edge of the polysilicon layer, and while retaining the conductive path in the metallization region, completely remove the polysilicon material in the non-metallization region.

[0074] Specifically, when the contact area of the metal electrode is limited to a specific width, by expanding the coverage width of the P+ polysilicon layer 13 to 1.5 to 5 times the electrode width, a conductive transition region with sufficient width can be formed between the electrode and the crystalline silicon layer. This transition region design not only avoids the carrier recombination caused by the electrode directly penetrating into the crystalline silicon substrate, but also prevents the light absorption loss in the non-necessary area due to excessive extension by restricting the maximum expansion width of the polysilicon layer. During the process implementation, when using laser etching or photolithography technology to pattern the polysilicon layer, through the precise control of the energy density and scanning speed, the integrity of the alumina layer 14 can be maintained while removing the excess polysilicon material, preventing the surface passivation effect from decreasing due to processing damage.

[0075] In some specific embodiments, for a metal electrode with a width of 80 microns, the P+ polysilicon layer 13 can be set to 120 to 400 microns; for a 150-micron electrode, the width of the polysilicon layer can be adjusted to 225 to 750 microns. During the processing, when using a UV laser with a wavelength of 355 nm for etching, the pulse energy can be controlled at 0.5 to 2.0 J / cm 2 , and the scanning speed is set to 200 to 800 mm / s to achieve the selective removal of the polysilicon layer without damaging the underlying alumina layer 14.

[0076] Compared with the prior art, in the traditional method, the width of the polysilicon layer is usually the same as or only slightly larger than the width of the metal electrode, which leads to easy carrier recombination in the electrode edge region and cannot effectively suppress the parasitic absorption in the non-metallized region. By establishing the proportional relationship between the polysilicon layer and the electrode width, this solution controls the coverage range of unnecessary polysilicon materials within a reasonable interval while ensuring the carrier transport efficiency in the electrode contact area. The wet etching process used in the prior art is prone to causing damage to the interlayer interface, while the laser or photolithography process selected in this solution can achieve higher processing accuracy and edge steepness, thus maintaining the surface quality of the passivation layer.

[0077] Through the above technical solution, this application effectively balances the contradiction between the carrier transport requirements and the optical absorption loss in the metallization region, and while ensuring a reliable electrical contact is formed between the electrode and the crystalline silicon layer, it minimizes the proportion of polysilicon materials in the non-functional region. This solution not only avoids the aggravation of metal recombination caused by a too narrow polysilicon layer, but also suppresses the parasitic absorption problem caused by excessive material extension, thereby improving the short-circuit current density while maintaining the open-circuit voltage of the battery. The selection of the processing technology further ensures the accuracy and repeatability of the structure patterning, providing technical support for the yield control in large-scale production.

[0078] In a specific embodiment, the width of the P+ polysilicon layer 13 in the metallization region is 1.5 to 5 times the width of the metal electrode, and the region is distinguished by laser etching or photolithography.

[0079] Among them, the proportional relationship between the width of the P+ polysilicon layer 13 in the metallization region and the width of the metal electrode refers to the range where the polysilicon layer laterally covers the electrode contact area, which can be specifically achieved by adjusting the photolithography mask pattern or laser focusing parameters. Through this proportional range, it can not only ensure that the electrode contact area is completely covered, but also avoid unnecessary light absorption caused by an overly wide area. Among them, laser etching refers to the process of selectively removing the polysilicon layer using a high-energy laser beam, which can be specifically achieved by using an ultraviolet laser with a pulse width of 10 to 100 nanoseconds, and can accurately control the etching boundary to avoid structural deformation caused by lateral over-etching. Among them, the photolithography process refers to the process of forming a patterned mask through coating photoresist, exposure and development and then etching, which can be specifically achieved by using a contact or step-by-step exposure machine, and accurately controls the reserved area of the polysilicon layer through the mask pattern.

[0080] Specifically, during the formation of the metallization region, the width of the polysilicon layer is controlled within the range of 1.5 to 5 times the width of the electrode, such that the polysilicon layer under the electrode laterally extends beyond the edge of the electrode, thereby forming a continuous carrier transmission channel between the electrode and the crystalline silicon layer, which not only reduces the contact resistance but also avoids an excessive increase in the area of the polysilicon layer to cause parasitic absorption. During the laser etching process, by adjusting the laser power and scanning path, the polysilicon layer can be precisely removed in the non-metallization region while retaining the complete structure of the metallization region, and the etching boundary error can be controlled within ±2 micrometers. The photolithography process forms an etching barrier layer through photoresist patterning and completes the regional differentiation of the polysilicon layer using dry or wet etching, and its pattern transfer accuracy can reach the sub-micron level.

[0081] Compared with the prior art, in the existing process, the width of the polysilicon layer is only equal to the width of the electrode or no regional treatment is performed, resulting in the need to sacrifice the pn junction area when reducing parasitic absorption. However, in this solution, by defining the width ratio relationship, unnecessary light absorption is reduced while maintaining a sufficient pn junction area. In the prior art, chemical etching is mostly used for the regional differentiation of the polysilicon layer, and its lateral etching will cause rough edges. However, the laser etching or photolithography process adopted in this solution can achieve a vertical morphology of the etching boundary and reduce carrier recombination caused by surface defects.

[0082] Through the above technical solution, this application effectively balances the contradiction between the light absorption loss in the metallization region and the pn junction area, maintaining a high open-circuit voltage while reducing parasitic absorption. Through the high-precision regional differentiation process, the direct contact area between the metal electrode and the crystalline silicon layer is reduced, suppressing the recombination loss of carriers at the interface, thereby improving the conversion efficiency of the battery.

[0083] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present invention.

[0084] The embodiments described above are only descriptions of the preferred embodiments of the present invention, and do not limit the scope of the present invention. Without departing from the design spirit of the present invention, various deformations and improvements made by those of ordinary skill in the art to the technical solution of the present invention should fall within the protection scope determined by the claims of the present invention.

Claims

1. A TOPCon battery structure, characterized in that, It includes an n-type silicon substrate (1), with metal electrodes provided on both the front and back surfaces of the n-type silicon substrate (1), and the surfaces of the n-type silicon substrate (1) facing the two metal electrodes having metallized regions and non-metallized regions; wherein: The front metallized region sequentially has a P+ crystalline silicon layer (11), a tunneling oxide layer, a P+ polysilicon layer (13), an alumina layer (14), and a front antireflection passivation layer (15) from the n-type silicon substrate (1) outwards; The front non-metallized region sequentially has a P+ crystalline silicon layer (11), a tunneling oxide layer, an alumina layer (14), and a front antireflection passivation layer (15) from the n-type silicon substrate (1) outwards; The back metallized region sequentially has an n+ crystalline silicon layer (21), a tunneling oxide layer, an n+ polysilicon layer (23), and a back antireflection passivation layer (24) from the n-type silicon substrate (1) outwards; The back non-metallized region sequentially has an n+ crystalline silicon layer (21), a tunneling oxide layer, and a back antireflection passivation layer (24) from the n-type silicon substrate (1) outwards; The doping depth of the P+ crystalline silicon layer (11) is 0.5 μm to 2 μm, and the doping depth of the n+ crystalline silicon layer (21) is 0.3 μm to 0.6 μm.

2. The TOPCon battery structure according to claim 1, wherein In the front metallized region, the width of the P+ polysilicon layer (13) is 50 μm to 300 μm and is greater than the width of the metal electrode.

3. The TOPCon battery structure according to claim 1, characterized in that, The thickness of the tunneling oxide layer is 1.5 nm to 2 nm, the thickness of the P+ polysilicon layer (13) is 70 nm to 200 nm, and the thickness of the n+ polysilicon layer (23) is 90 nm to 200 nm.

4. The TOPCon cell structure according to claim 1, wherein, The boron doping concentration of the P+ crystalline silicon layer (11) is 3E+17 to 8E+19 atoms / cm 3 , and the phosphorus surface concentration of the n+ crystalline silicon layer (21) ≥ 8E+20 atoms / cm 3 .

5. A method for preparing a TOPCon cell structure, which is used to prepare the TOPCon cell structure according to any one of claims 1 to 4, characterized in that, It includes the following steps: Form a P+ crystalline silicon layer (11) on the front of the n-type silicon substrate (1) by boron diffusion; Generate a tunneling oxide layer on the surface of the P+ crystalline silicon layer (11); Deposit a P+ polysilicon layer (13) on the tunneling oxide layer and distinguish the metallized and non-metallized regions by laser or chemical etching; Form an n+ crystalline silicon layer (21) on the back of the silicon substrate by phosphorus diffusion; Generate a tunneling oxide layer on the surface of the n+ crystalline silicon layer (21) and deposit an n+ polysilicon layer (23); Remove the polysilicon layer in the non-metallized region and retain the polysilicon layer in the metallized region; Deposit an alumina layer (14) and an antireflection passivation layer on the front and back respectively; Print the metal electrode to ensure that the electrode only contacts the polysilicon layer and does not penetrate to the substrate.

6. The TOPCon cell structure according to claim 5, characterized in that, The P+ polysilicon layer (13) is deposited by LPCVD or PECVD, and the boron doping concentration is ≥ 2E+20 atoms / cm 3 ; The n+ polysilicon layer (23) is deposited by LPCVD or PECVD, and the phosphorus doping concentration is 2E+20 - 1E+21 atoms / cm 3 .

7. The TOPCon battery structure according to claim 5, wherein The P+ polysilicon layer (13) and n+ polysilicon layer (23) in the non-metallized region are selectively removed by an alkali solution, and the borosilicate glass or phosphosilicate glass layer in the metallized region is removed by pickling.

8. The TOPCon battery structure according to claim 5, wherein, The tunneling oxide layer is generated by introducing oxygen or nitrous oxide at 800 °C to 950 °C, and the thickness is controlled at 1.5 nm to 2 nm.

9. The TOPCon battery structure according to claim 5, wherein, The width of the P+ polysilicon layer (13) in the metallized region is 1.5 to 5 times the width of the metal electrode, and the region is distinguished by laser etching or photolithography.

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