Back contact solar cell

Abstract

The invention relates to a back contact solar cell, and relates to the technical field of solar cells, the back contact solar cell comprises a silicon substrate, the back surface of the silicon substrate comprises a first area, a second area and an intersection area, the first area is higher than the second area, and the intersection area comprises a step; the first region is provided with a first carrier collection layer and a first conductive layer which are sequentially laminated from the surface of the silicon substrate to the outside; a second carrier collection layer and a second conductive layer are sequentially arranged in the second region from the surface of the silicon substrate to the outside in a laminated manner, and the second conductive layer does not extend to the step surface of the step; the intersection area comprises a third intersection area which is located on the step surface and extends to the edge of the step surface, the second carrier collection layer extends from the second area to the third intersection area, the surface of the third intersection area is provided with the second carrier collection layer, and the third intersection area is not provided with the first carrier collection layer. The cell has excellent anti-creeping effect and photoelectric conversion efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and particularly to a back-contact solar cell. Background Art

[0002] In recent years, heterojunction back contact (HBC) solar cells have become a research hotspot in the photovoltaic field due to their advantages such as high open-circuit voltage, low temperature coefficient, and no front-side shading loss. The back side of an HBC cell usually adopts a design of staggered n-type regions and p-type regions, and carrier separation is achieved through localized metal contacts.

[0003] The back-contact solar cells provided by the prior art include: a silicon substrate, the back surface of the silicon substrate includes a first region, a second region, and a cross region located between the first region and the second region. The first region is provided with a first carrier collection layer and a first conductive layer, the second region is provided with a second carrier layer and a second conductive layer, the cross region is provided with a stacked first carrier collection layer and a second carrier collection layer, and both the first conductive layer and the second conductive layer extend to the cross region and are separated. However, this back-contact solar cell is prone to leakage problems. Summary of the Invention

[0004] Based on this, the present invention provides a back-contact solar cell to solve the problem of easy leakage of the existing back-contact solar cells.

[0005] A back-contact solar cell provided by the present invention includes: A silicon substrate, the back surface includes a first region, a second region, and a cross region located between the first region and the second region. The first region is higher than the second region, and the cross region includes a step; The first region is sequentially stacked with a first carrier collection layer and a first conductive layer from the surface of the silicon substrate outward; The second region is sequentially stacked with a second carrier collection layer and a second conductive layer from the surface of the silicon substrate outward, and the second conductive layer does not extend to the step surface of the step; The cross region includes a third cross region located on the step surface and extending to the edge of the step surface. The second carrier collection layer extends from the second region to the third cross region, and the surface of the third cross region is provided with the second carrier collection layer. The first carrier collection layer is not provided in the third cross region.

[0006] In one embodiment, the width of the third cross region is 0.01 - 10 μm.

[0007] In one embodiment, the cross region further includes a fourth cross region disposed between the third cross region and the second region. The fourth cross region includes the side surface of the step surface, the second carrier collection layer covers the side surface of the step surface, and an isolation groove is formed between the second conductive layer and the second carrier collection layer located on the side surface of the step surface.

[0008] In one embodiment, the width of the fourth cross region is 30 - 90 μm.

[0009] In one embodiment, the cross region further includes a second cross region connected to the third cross region and extending towards the first region; The second cross region is successively provided with a stacked first carrier collection layer and second carrier collection layer from the surface of the silicon substrate outwards.

[0010] In one embodiment, the width of the second cross region is 30 - 90 μm.

[0011] In one embodiment, the cross region further includes a first cross region disposed between the first region and the second cross region. The first cross region is successively provided with a stacked first carrier collection layer, second carrier collection layer, and first conductive layer from the surface of the silicon substrate outwards.

[0012] In one embodiment, the width of the first cross region is 50 - 150 μm.

[0013] In one embodiment, along the direction away from the silicon substrate, the second carrier collection layer includes a stacked first intrinsic hydrogenated silicon layer and second doped silicon layer, and the second doped silicon layer is connected to the second conductive layer; Along the direction away from the silicon substrate, the first carrier collection layer includes a stacked tunneling passivation layer and first doped silicon layer, and the first doped silicon layer is connected to the first conductive layer.

[0014] In one embodiment, the thickness of the first intrinsic hydrogenated silicon layer is 1 - 10 nm; And / or, the material of the second doped silicon layer includes at least one of amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide, and silicon carbide; And / or, the second doped silicon layer includes a layer of amorphous silicon layer, microcrystalline silicon layer, nanocrystalline silicon layer, silicon oxide layer, and silicon carbide layer, or a stack of at least two of them; And / or, the thickness of the second doped silicon layer is 1 - 50 nm; And / or, the thickness of the tunneling passivation layer is 0.5 nm - 3 nm; And / or, the thickness of the first doped silicon layer is 20 - 100 nm; And / or, the materials of the first conductive layer and the second conductive layer include at least one of a metal oxide containing a doping element and a metal nitride containing a doping element. Among them, the metal oxide includes at least one of indium oxide, tin oxide, zinc oxide, cadmium oxide, and titanium nitride, the metal nitride includes titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum, cadmium, zinc, cerium, and fluorine; The first conductive layer and the second conductive layer are single-layer film layers or multi-layer stacked film layers.

[0015] In one embodiment, there is a height difference between the first region and the second region, and the height difference is less than 20 μm.

[0016] In one embodiment, the back-contact solar cell further includes: a first electrode electrically connected to the first conductive layer, and a second electrode electrically connected to the second conductive layer.

[0017] In one embodiment, the back-contact solar cell further includes: a passivation layer and an antireflection layer sequentially stacked outward from the front surface of the silicon substrate.

[0018] In one embodiment, the silicon substrate is an n-type silicon substrate; The first doped silicon layer is an n-type doped silicon layer, and the second doped silicon layer is a p-type doped silicon layer.

[0019] The present invention has at least the following beneficial effects compared with the prior art: The back-contact solar cell provided by the present invention only has a second carrier collection layer disposed on the third crossover region, i.e., the stepped surface. Compared with the prior art where the first carrier collection layer and the second carrier collection layer are completely stacked in the crossover region, the stacking area of the first carrier collection layer and the second carrier collection layer is reduced, and the risk of leakage caused by electrical conduction between the first carrier collection layer and the second carrier collection layer is lowered. Since the second conductive layer does not extend to the stepped surface, this increases the horizontal spacing between the first conductive layer and the second conductive layer, forming a horizontal isolation therebetween and avoiding the problem of leakage caused by electrical conduction between the first conductive layer and the second conductive layer. Moreover, there is a height difference formed by the step between the first carrier collection layer and the first conductive layer disposed in the first region and the second carrier collection layer and the second conductive layer disposed in the second region, which forms a vertical isolation therebetween and avoids the occurrence of leakage problems. It can be seen that by reducing the stacking area between the first carrier collection layer and the second carrier collection layer and by horizontally and vertically isolating the first conductive layer and the second conductive layer, the back-contact solar cell provided by the embodiment of the present invention has an excellent anti-leakage effect, which is beneficial to improving the photoelectric conversion efficiency of the back-contact solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic structural diagram of a back-contact solar cell in an embodiment.

[0021] The reference numerals in the accompanying drawings of the specification include: 100 - silicon substrate; 110 - step; 120 - protrusion; 200 - first carrier collection layer; 210 - tunneling passivation layer; 220 - first doped silicon layer; 310 - first conductive layer; 320 - first electrode; 400 - second carrier collection layer; 410 - first intrinsic hydrogenated silicon layer; 420 - second doped silicon layer; 510 - second conductive layer; 520 - second electrode; 600 - passivation layer; 700 - antireflection layer; 800 - isolation groove; A - first region; A1 - enhanced passivation region; B - second region; C1 - first crossover region; C2 - second crossover region; C3 - third crossover region; C4 - fourth crossover region. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0023] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention.

[0024] The structures, proportions, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the conditions under which the present invention can be implemented. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effects that the present invention can produce and the objectives that can be achieved, should still fall within the scope covered by the technical content disclosed by the present invention.

[0025] The orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "middle", "longitudinal", "transverse", "horizontal", "inner", "outer", "radial", "circumferential", etc. cited in this specification is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of simplified description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0026] As described in the background art, the back-contact solar cell provided by the prior art includes: a silicon substrate, the back surface of the silicon substrate includes a first region, a second region, and an intersection region located between the first region and the second region. The first region is provided with a first carrier collection layer and a first conductive layer, the second region is provided with a second carrier collection layer and a second conductive layer, the intersection region is provided with a stacked first carrier collection layer and a second carrier collection layer, and both the first conductive layer and the second conductive layer extend to the intersection region and are separated. The conductive types of the first carrier collection layer and the second carrier collection layer are opposite. The first carrier collection layer includes a tunneling passivation layer and a first doped silicon layer provided on the surface of the tunneling passivation layer. The second carrier collection layer includes an intrinsic hydrogenated silicon layer and a second doped silicon layer provided on the surface of the intrinsic hydrogenated silicon layer. When the first carrier collection layer and the second carrier collection layer are stacked and the intrinsic hydrogenated silicon layer is located between the first doped silicon layer and the second doped silicon layer, due to the relatively thin thickness of the intrinsic hydrogenated silicon layer, the passivation effect is limited, and electrical conduction is likely to occur between the stacked first doped silicon layer and the second doped silicon layer, resulting in a leakage problem of the solar cell.

[0027] In addition, since both the first conductive layer and the second conductive layer extend to the crossover region, in practical applications, the width of the crossover region is very small, and often due to process errors or other reasons, there is conduction between the first conductive layer and the second conductive layer, resulting in a leakage problem in the back-contact solar cell.

[0028] It should be noted that when there is electrical conduction between the first doped silicon layer and the second doped silicon layer, or when there is electrical conduction between the first conductive layer and the second conductive layer, the output current of the back-contact solar cell will be reduced, that is, a leakage problem occurs.

[0029] To solve the above problems, an embodiment of the present invention provides a back-contact solar cell, which includes: A silicon substrate 100, the back surface of which includes a first region A, a second region B, and a crossover region C located between the first region A and the second region B. The first region A is higher than the second region B, and the crossover region C includes a step 110; The first region A is sequentially stacked with a first carrier collection layer 200 and a first conductive layer 310 from the surface of the silicon substrate 100 outward; The second region B is sequentially stacked with a second carrier collection layer 400 and a second conductive layer 510 from the surface of the silicon substrate 100 outward, and the second conductive layer 510 does not extend to the step surface of the step 110; The crossover region C includes a third crossover region C3 located on the step surface and extending to the edge of the step surface. The second carrier collection layer 400 extends from the second region B to the third crossover region C3, and the second carrier collection layer 400 is provided on the surface of the third crossover region C3, and the first carrier collection layer 200 is not provided in the third crossover region C3.

[0030] It should be noted that the third crossover region C3 is the region between the part of the crossover region C connected to the first region A and the side surface of the step 110.

[0031] The back-contact solar cell provided by the embodiment of the present invention only provides a second carrier collection layer 400 on the third intersection region C3, that is, on the step surface. Compared with the prior art in which the first carrier collection layer 200 and the second carrier collection layer 400 are completely stacked in the intersection region, the stacking area of the first carrier collection layer 200 and the second carrier collection layer 400 is reduced, and the risk of leakage caused by electrical conduction between the first carrier collection layer 200 and the second carrier collection layer 400 is reduced. Since the second conductive layer 510 does not extend to the step surface, this increases the horizontal distance between the first conductive layer 310 and the second conductive layer 510, forming a horizontal isolation between the two, and avoiding the problem of leakage caused by electrical conduction between the first conductive layer 310 and the second conductive layer 510. Moreover, there is a height difference between the first carrier collection layer 200 and the first conductive layer 310 provided in the first region A and the second carrier collection layer 400 and the second conductive layer 510 provided in the second region B due to the step 110, which forms a vertical isolation between the two, avoiding the problem of leakage. It can be seen that by reducing the stacking area between the first carrier collection layer 200 and the second carrier collection layer 400, and by horizontally and vertically isolating the first conductive layer 310 and the second conductive layer 510, the back-contact solar cell provided by the embodiment of the present invention has an excellent anti-leakage effect, which is beneficial to improving the photoelectric conversion efficiency of the back-contact solar cell.

[0032] In the embodiment of the present invention, the silicon substrate 100 is a doped silicon substrate. For example, the silicon substrate can be an n-type doped silicon substrate, or it can be a p-type doped silicon substrate. Among them, the n-type doping element can be phosphorus (P) or arsenic (As), etc., and the p-type doping element can be boron or gallium (Ga), etc. The silicon substrate 100 is in the shape of a silicon sheet, which includes a front surface and a back surface, and the two are distributed opposite to each other along the thickness direction of the silicon substrate 100. In this embodiment, the front surface direction and the back surface direction of the silicon substrate 100 are defined based on the light-facing surface and the light-blocking surface of the silicon substrate 100. For example, here the light-facing surface of the silicon substrate 100 is defined as the front surface, and the light-blocking surface of the silicon substrate 100 is defined as the back surface.

[0033] See Figure 1, a passivation layer 600 and an antireflection layer 700 are sequentially stacked outward from the front surface of the silicon substrate 100. Among them, the passivation layer 600 includes a second intrinsic hydrogenated silicon layer. For example, the passivation layer 600 can be a single second intrinsic hydrogenated silicon layer, or a stack of a second intrinsic hydrogenated silicon layer and an n-type doped silicon layer. Among them, the thickness of the second intrinsic hydrogenated silicon layer can be 1-15 nm, such as 1 nm, 3 nm, 5 nm, 8 nm, 10 nm, 12 nm or 15 nm, etc., and the thickness of the n-type doped silicon layer can be less than 15 nm, such as 5 nm, 8 nm, 10 nm, 12 nm or 15 nm, etc. The material of the antireflection layer 700 includes at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, indium tin oxide, zinc oxide. The thickness of the antireflection layer 700 can be 40-200 nm, such as 40 nm, 100 nm, 120 nm, 150 nm, 180 nm or 200 nm, etc. By setting the passivation layer 600 and the antireflection layer 700, the passivation effect and the antireflection effect of the back-contact solar cell are improved, which is beneficial to improving its photoelectric conversion efficiency.

[0034] See Figure 1 , in the embodiment of the present invention, the back surface of the silicon substrate 100 is divided into a first region A, a second region B and an intersection region C. Among them, this is not a strict division, but a distinction according to different types of functional layers provided. The first region A can be provided with a film layer of n-type conductive type, and the second region B can be provided with a film layer of p-type conductive type. Or, the first region A can be provided with a film layer of p-type conductive type, and the second region B can be provided with a film layer of n-type conductive type.

[0035] It should be understood that multiple groups of the first region A and the second region B are also alternately distributed on the entire back surface of the silicon substrate 100, and each group of the first region A and the second region B is separated by the intersection region C. Only the structure of one group of the first region A, the second region B and the intersection region C is described below as an example.

[0036] From the back surface of the silicon substrate 100 outward, a first carrier collection layer 200, a first conductive layer 310, and a first electrode 320 electrically connected to the first conductive layer 310 are sequentially stacked in the first region A. The first conductive layer 310 and the first electrode 320 are used to export the carriers collected by the first carrier collection layer 200. That is, the first conductive layer 310 and the first electrode 320 are electrically connected to the first carrier collection layer 200.

[0037] In some embodiments, see Figure 1, in a direction away from the silicon substrate 100, the first carrier collection layer 200 includes a stacked tunneling passivation layer 210 and a first doped silicon layer 220, and the first doped silicon layer 220 is connected to the first conductive layer 310. Among them, the specific materials, thicknesses of the tunneling passivation layer 210 and the first doped silicon layer 220, and the specific doping types and doping concentrations of the doping elements in the first doped silicon layer 220 can be set according to actual needs, as long as they can be applied to the back-contact solar cell provided by the embodiments of the present invention. For example, in some embodiments, the material of the tunneling passivation layer 210 can be silicon oxide. The thickness of the tunneling passivation layer 210 is 0.5 nm - 3 nm, for example, it can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm or 3 nm, etc. The first doped silicon layer 220 can be a doped polysilicon layer, and the thickness of the first doped silicon layer 220 can be 20 - 100 nm, for example, it can be 20 nm, 40 nm, 60 nm, 80 nm or 100 nm, etc. By setting the materials and thicknesses of the tunneling passivation layer 210 and the first doped silicon layer 220 in this way, it is beneficial to improve the passivation effect and carrier collection ability of this structure.

[0038] In some embodiments, the material of the first conductive layer 310 may include at least one of a metal oxide containing a doping element and a metal nitride containing a doping element. Among them, the metal oxide includes at least one of indium oxide, tin oxide, zinc oxide, cadmium oxide and titanium nitride. The metal nitride includes titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum, cadmium, zinc, cerium and fluorine. The first conductive layer 310 can be a single-layer film or a multi-layer stacked film. By setting it in this way, the carrier collection rate and conductivity of the first conductive layer 310 can be improved.

[0039] The first electrode 320 is a metal electrode, specifically, it can be a silver electrode, a silver alloy electrode, a copper electrode, a copper alloy electrode, a nickel / copper / silver multi-layer electrode, etc.

[0040] Continue to refer to Figure 1 , in the second region B, a second carrier collection layer 400, a second conductive layer 510, and a second electrode 520 electrically connected to the second conductive layer 510 are sequentially stacked from the back surface of the silicon substrate 100. The second conductive layer 510 and the second electrode 520 are used to export the carriers collected by the second carrier collection layer 400. That is, the second conductive layer 510 and the second electrode 520 are electrically conductive with the second carrier collection layer 400.

[0041] In some embodiments, refer to Figure 1, in a direction away from the silicon substrate 100, the second carrier collection layer 400 includes a stacked first intrinsic hydrogenated silicon-containing layer 410 and a second doped silicon layer 420, and the second doped silicon layer 420 is connected to the second conductive layer 510. Similarly, the materials, thicknesses of the first intrinsic hydrogenated silicon-containing layer 410 and the second doped silicon layer 420, the doping types and doping concentrations of the doping elements in the second doped silicon layer 420 can be set according to actual requirements, as long as they can be applied to the back-contact solar cell provided in the embodiment of the present invention. By way of example, the thickness of the first intrinsic hydrogenated silicon-containing layer 410 is 1-10 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, etc. The material of the second doped silicon layer 420 includes at least one of amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide and silicon carbide, and the second doped silicon layer 420 includes a single layer or a stack of at least two of an amorphous silicon layer, a microcrystalline silicon layer, a nanocrystalline silicon layer, a silicon oxide layer and a silicon carbide layer. The thickness of the second doped silicon layer 420 can be 1-50 nm, such as 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc. By setting the materials and thicknesses of the first intrinsic hydrogenated silicon-containing layer 410 and the second doped silicon layer 420 in this way, it is beneficial to improve the passivation performance of the first intrinsic hydrogenated silicon-containing layer 410 and the carrier collection ability of the second doped silicon layer 420.

[0042] In addition, it should be noted that in this embodiment, the doping types of the second doped silicon layer 420 and the first doped silicon layer 220 are different. For example, the second doped silicon layer 420 can be a p-type doped silicon layer doped with boron or other elements, and the first doped silicon layer 220 can be an n-type doped silicon layer doped with phosphorus or other elements. Or, the first doped silicon layer 220 can be a p-type doped silicon layer doped with boron or other elements, and the second doped silicon layer 420 can be an n-type doped silicon layer doped with phosphorus or other elements.

[0043] Among them, the second conductive layer 510 can adopt the same structure or material as the first conductive layer 310, and the second electrode 520 can adopt the same structure as the first electrode 320, which will not be elaborated here.

[0044] In this embodiment, the electrically conductive film layer between the first region A and the second region B is isolated by the cross region C. Continue to refer to Figure 1 , in the vertical direction, that is, in the thickness direction of the silicon substrate 100, there is a height difference between the first conductive layer 310 and the second conductive layer 510, so that the two are staggered from each other in the vertical direction, forming a spatial isolation, thereby avoiding the problem of leakage of the back-contact solar cell caused by the conduction between the first conductive layer 310 and the second conductive layer 510.

[0045] Exemplarily, referring to Figure 1 , a convex portion 120 is formed on the silicon substrate 100. The first region A is located on the surface of the convex portion 120, while the second region B is located on the surface of the non-convex portion of the silicon substrate 100, such that a step 110 is formed at the junction of the first region A and the second region B, and the intersection region C includes the step 110. Also, since the first conductive layer 310 is disposed on the first region A and the second conductive layer 510 is disposed on the second region B, a height difference is formed between the first conductive layer 310 and the second conductive layer 510, creating isolation in the vertical direction and avoiding the problem of leakage in the back-contact solar cell caused by conduction between the first conductive layer 310 and the second conductive layer 510.

[0046] In some embodiments, there is a height difference between the first region A and the second region B, and the height difference is less than or equal to 20 μm. For example, the height difference can be 20 μm, 18 μm, 16 μm, 14 μm, 12 μm, 10 μm, 8 μm, or 6 μm, etc. Additionally, the height can also be other values as long as it ensures that the first conductive layer 310 and the second conductive layer 510 are staggered in the vertical direction and meet the actual production requirements.

[0047] Referring to Figure 1 , in the horizontal direction, that is, in the horizontal extension direction of the back surface of the silicon substrate 100, there is a horizontal spacing between the first conductive layer 310 and the second conductive layer 510, separating the two in the horizontal direction and creating spatial isolation, thereby avoiding the problem of leakage in the back-contact solar cell caused by conduction between the first conductive layer 310 and the second conductive layer 510.

[0048] Specifically, referring to Figure 1 , the third intersection region C3 is located on the step surface and extends to the edge of the step surface, that is, the third intersection region C3 does not extend to the side surface of the step surface. Since only the second carrier collection layer 400 is provided on the surface of the third intersection region C3 and the first carrier collection layer 200 is not provided, compared with the entire intersection region where the first carrier collection layer 200 and the second carrier collection layer 400 are stacked, the area of the stacked first carrier collection layer 200 and second carrier collection layer 400 is reduced, reducing the leakage risk caused by their conduction. Also, the first conductive layer 310 is only disposed on the first region A, and the second conductive layer 510 does not extend to the step surface of the step 110. In this way, a spacing is formed between the first conductive layer 310 and the second conductive layer 510 in the horizontal direction, creating isolation in the horizontal direction, thereby avoiding the problem of leakage in the back-contact solar cell caused by conduction between the first conductive layer 310 and the second conductive layer 510.

[0049] The width of the third intersection region C3 is 0.01 - 10 μm, and for example, it can be 0.01 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, etc. With such a setting, not only can a spacing be ensured between the first carrier collection layer 200 and the side surface of the step 110, reducing the stacked area between the first carrier collection layer 200 and the second carrier collection layer 400, but also a large area of the first region A and the second region B will not be occupied, ensuring the carrier collection efficiency of the first carrier collection layer 200 and the second carrier collection layer 400.

[0050] It should be noted that the "width" involved in the present invention can be understood in combination with Figure 1 this, that is, the dimension of a certain region in the direction parallel to the surface of the silicon substrate 100.

[0051] Continuing to refer to Figure 1 , the intersection region C further includes a fourth intersection region C4 provided between the third intersection region C3 and the second region B. The fourth intersection region C4 includes the side surface of the step surface, the second carrier collection layer 400 covers the side surface of the step surface, and an isolation groove 800 is formed between the second conductive layer 510 and the second carrier collection layer 400 located on the side surface of the step surface. In this way, a horizontal spacing is ensured between the second conductive layer 510 and the side surface of the step 110, so that a larger isolation spacing can be ensured between the first conductive layer 310 and the second conductive layer 510, and the isolation effect is better. Similarly, in this embodiment, no specific limitation is made on the horizontal spacing between the first conductive layer 310 and the second conductive layer 510, as long as they can be separated in the horizontal direction.

[0052] Among them, the width of the fourth intersection region C4 is 30 - 90 μm, and for example, it can be 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm or 90 μm, etc. With such a setting, not only can a sufficient distance be ensured between the second carrier collection layer 400 and the side surface of the step 110, but also the fourth intersection region C4 will not occupy a large area of the second region B, ensuring the carrier collection efficiency of the second carrier collection layer 400.

[0053] Continuing to refer to Figure 1 , the intersection region C further includes a second intersection region C2 connected to the third intersection region C3 and extending towards the first region A. The second intersection region C2 is successively provided with a first carrier collection layer 200 and a second carrier collection layer 400 from the surface of the silicon substrate 100 outwards. That is, the area of the first conductive layer 310 is smaller than the area of the first carrier collection layer 200, avoiding the risk of electrical conduction between the large-area first conductive layer 310 and the second carrier collection layer 400.

[0054] The width of the second cross-region C2 is 30-90 μm, for example, it can be 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm or 90 μm, etc. With such a setting, it will not occupy a large area of the first region A, ensuring the carrier collection efficiency of the first carrier collection layer 200.

[0055] Continue to refer to Figure 1 , the cross-region C further includes a first cross-region C1 disposed between the first region A and the second cross-region C2. The first cross-region C1 is sequentially provided with a stacked first carrier collection layer 200, a second carrier collection layer 400, and a first conductive layer 310 from the surface of the silicon substrate 100 outward. With such a setting, the first conductive layer 310 extends and overlaps on the second carrier collection layer 400, moderately increasing the area of the first conductive layer 310, which is beneficial to the first conductive layer 310 collecting carriers, reducing the contact resistance of the film layer at the first region A, and facilitating the improvement of the conductivity.

[0056] Among them, the width of the first cross-region C1 can be 50-150 μm, for example, it can be 50 μm, 80 μm, 100 μm, 110 μm, 130 μm or 150 μm, etc. With such a setting, the area between the stacked first carrier collection layer 200 and the second carrier collection layer 400 is reduced compared with the prior art, and it is beneficial to balance the areas of the first carrier collection layer 200 and the second carrier collection layer 400, which is beneficial to the carrier collection rate.

[0057] In some embodiments, when the second carrier collection layer 400 includes a stacked first intrinsic hydrogenated silicon-containing layer 410 and a second doped silicon layer 420, the first intrinsic hydrogenated silicon-containing layer 410 directly covers the surface of the silicon substrate 100 in the fourth cross-region C4 and the third cross-region C3. In this way, compared with the tunneling passivation layer 210 of the first carrier collection layer 200 covering the silicon substrate 100, it has a better passivation effect, and further makes the back-contact solar cell have better passivation performance to improve the photoelectric conversion efficiency.

[0058] It should be noted that the first intrinsic hydrogenated silicon-containing layer 410 reduces carrier recombination through the dual effects of chemical passivation and field effect passivation. Among them, chemical passivation saturates the dangling bonds on the silicon surface with free hydrogen atoms, and field passivation realizes selective carrier transport with the help of the interface electric field. The tunneling passivation layer 210 reduces the carrier transport resistance through the tunneling effect and simultaneously suppresses the recombination caused by surface states. Research shows that the passivation effect of the first intrinsic hydrogenated silicon-containing layer 410 is better than that of the tunneling passivation layer 210.

[0059] Continue to refer to Figure 1, since the first carrier collection layer 200 is not laid in the third intersection region C3, that is, there is a spacing between the first carrier collection layer 200 and the side surface of the step 110, which forms a strengthened passivation region A1 in the third intersection region C3. At the same time, the first intrinsic hydrogenated silicon layer 410 and the second doped silicon layer 420 as a whole extend from the second region B to the first region A, and the extended part completely covers the side surface of the step 110 and completely covers the strengthened passivation region A1, that is, the third intersection region C3. With such a setting, the extended parts of the first intrinsic hydrogenated silicon layer 410 and the second doped silicon layer 420 cover and wrap the side surface of the step 110 and the edge of the surface of the step 110. And since the passivation effect of the second carrier collection layer 400 formed by the first intrinsic hydrogenated silicon layer 410 and the second doped silicon layer 420 is better than that of the first carrier collection layer 200 formed by the tunneling passivation layer 210 and the first doped silicon layer 220, the passivation effect of this boundary region can be strengthened by using the second carrier collection layer 400, improving the performance of the back-contact solar cell.

[0060] In each of the above-mentioned intersection regions, the first conductive layer 310 and the second conductive layer 510 are not provided in the second intersection region C2, the third intersection region C3, and the fourth intersection region C4, which is beneficial to the insulation isolation between the first region A and the second region B and is conducive to improving the photoelectric conversion efficiency of the back-contact battery.

[0061] On the other hand, an embodiment of the present invention further provides a photovoltaic module, which includes the back-contact solar cell of any one of the above embodiments.

[0062] Specifically, the photovoltaic module may further include a cover plate, a back plate, and an encapsulant film. A plurality of back-contact solar cells form a battery string in a series and / or parallel manner, and one or more series or parallel battery strings are encapsulated between the cover plate and the back plate through the encapsulant film.

[0063] The photovoltaic module provided by the present invention is based on a back-contact solar cell, and only the second carrier collection layer 400 is provided on the third intersection region C3, that is, the stepped surface. Compared with the prior art in which the first carrier collection layer 200 and the second carrier collection layer 400 are completely stacked in the intersection region, the stacking area of the first carrier collection layer 200 and the second carrier collection layer 400 is reduced, and the risk of leakage caused by electrical conduction between the first carrier collection layer 200 and the second carrier collection layer 400 is reduced. Since the second conductive layer 510 does not extend to the stepped surface, this increases the horizontal spacing between the first conductive layer 310 and the second conductive layer 510, forming a horizontal isolation between the two, and avoiding the problem of leakage caused by electrical conduction between the first conductive layer 310 and the second conductive layer 510. Moreover, a height difference is formed between the first carrier collection layer 200 and the first conductive layer 310 provided in the first region A and the second carrier collection layer 400 and the second conductive layer 510 provided in the second region B due to the step 110, which forms a vertical isolation between the two and avoids the occurrence of leakage problems. It can be seen that by reducing the stacking area between the first carrier collection layer 200 and the second carrier collection layer 400, and by horizontally and vertically isolating the first conductive layer 310 and the second conductive layer 510, the back-contact solar cell provided by the embodiment of the present invention has excellent anti-leakage effects, which is beneficial to improving the photoelectric conversion efficiency and further improving the photoelectric conversion efficiency and power of the photovoltaic module.

[0064] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0065] The above embodiments only represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A back-contact solar cell, characterized in that Comprising: A silicon substrate (100), the back surface of which includes a first region (A), a second region (B), and an intersection region (C) located between the first region (A) and the second region (B). The first region (A) is higher than the second region (B), and the intersection region (C) includes a step (110); On the first region (A), a first carrier collection layer (200) and a first conductive layer (310) are sequentially stacked outward from the surface of the silicon substrate (100); On the second region (B), a second carrier collection layer (400) and a second conductive layer (510) are sequentially stacked outward from the surface of the silicon substrate (100). The second conductive layer (510) does not extend to the step surface of the step (110); The intersection region (C) includes a third intersection region (C3) located on the step surface and extending to the edge of the step surface. The second carrier collection layer (400) extends from the second region (B) to the third intersection region (C3), and the second carrier collection layer (400) is provided on the surface of the third intersection region (C3). The first carrier collection layer (200) is not provided in the third intersection region (C3).

2. The back-contact solar cell according to claim 1, wherein, The width of the third intersection region (C3) is 0.01 - 10 μm.

3. The back-contact solar cell according to claim 1, characterized in that, The intersection region (C) further includes a fourth intersection region (C4) provided between the third intersection region (C3) and the second region (B). The fourth intersection region (C4) includes the side surface of the step surface. The second carrier collection layer (400) covers the side surface of the step surface, and an isolation groove (800) is formed between the second conductive layer (510) and the second carrier collection layer (400) located on the side surface of the step surface.

4. The back contact solar cell according to claim 3, characterized in that, The width of the fourth intersection region (C4) is 30 - 90 μm.

5. The back-contact solar cell according to claim 1, characterized in that, The intersection region (C) further includes a second intersection region (C2) connected to the third intersection region (C3) and extending toward the first region (A); On the second intersection region (C2), the first carrier collection layer (200) and the second carrier collection layer (400) are sequentially stacked outward from the surface of the silicon substrate (100).

6. The back contact solar cell according to claim 5, characterized in that, The width of the second intersection region (C2) is 30 - 90 μm.

7. The back contact solar cell according to claim 5, wherein, The intersection region (C) further includes a first intersection region (C1) provided between the first region (A) and the second intersection region (C2). On the first intersection region (C1), the first carrier collection layer (200), the second carrier collection layer (400), and the first conductive layer (310) are sequentially stacked outward from the surface of the silicon substrate (100).

8. The back contact solar cell according to claim 7, wherein The width of the first intersection region (C1) is 50 - 150 μm.

9. The back-contact solar cell according to claim 1, characterized in that, In the direction away from the silicon substrate (100), the second carrier collection layer (400) includes a stacked first intrinsic hydrogenated silicon layer (410) and a second doped silicon layer (420), and the second doped silicon layer (420) is connected to the second conductive layer (510); In a direction away from the silicon substrate (100), the first carrier collection layer (200) includes a stacked tunneling passivation layer (210) and a first doped silicon layer (220), and the first doped silicon layer (220) is connected to the first conductive layer (310).

10. The back-contact solar cell according to claim 9, characterized in that, The thickness of the first intrinsic hydrogenated silicon layer (410) is 1 - 10 nm; and / or, the material of the second doped silicon layer (420) includes at least one of amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide, and silicon carbide; and / or, the second doped silicon layer (420) includes a single layer or a stack of at least two of an amorphous silicon layer, a microcrystalline silicon layer, a nanocrystalline silicon layer, a silicon oxide layer, and a silicon carbide layer; and / or, the thickness of the second doped silicon layer (420) is 1 - 50 nm; and / or, the thickness of the tunneling passivation layer (210) is 0.5 nm - 3 nm; and / or, the thickness of the first doped silicon layer (220) is 20 - 100 nm; and / or, the materials of the first conductive layer (310) and the second conductive layer (510) include at least one of a metal oxide containing a doping element and a metal nitride containing a doping element, wherein the metal oxide includes at least one of indium oxide, tin oxide, zinc oxide, cadmium oxide, and titanium nitride, the metal nitride includes titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum, cadmium, zinc, cerium, and fluorine; The first conductive layer (310) and the second conductive layer (510) are single-layer film layers or multi-layer stacked film layers; and / or, the silicon substrate (100) is an n-type silicon substrate, the first doped silicon layer is an n-type doped silicon layer, and the second doped silicon layer is a p-type doped silicon layer.

11. The back-contact solar cell according to claim 1, characterized in that, There is a height difference between the first region (A) and the second region (B), and the height difference is less than or equal to 20 μm.

12. The back-contact solar cell according to claim 1, wherein, The back-contact solar cell further includes: a first electrode (320) electrically connected to the first conductive layer (310), and a second electrode (520) electrically connected to the second conductive layer (510); and / or, the back-contact solar cell further includes: a passivation layer (600) and an antireflection layer (700) sequentially stacked outward from the front surface of the silicon substrate (100).

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