Preparation method of inverted DBR-LED chip

Abstract

The invention discloses a preparation method of an inverted DBR-LED chip, and relates to the technical field of semiconductors, and the method comprises the following steps: sequentially growing an N-type GaN layer, a quantum well layer and a P-type GaN layer on a sapphire substrate; depositing along the surface of the P-type GaN layer to form a transparent ITO current expansion layer; forming an N-type conductive opening by taking the first photoresist as a mask; taking the second photoresist as a mask to form an isolation groove; performing whole-surface deposition to form a passivation reflection structure; etching in the passivation reflection structure by taking the third photoresist as a mask to form an N-type through hole and a P-type through hole; the fourth photoresist serves as a mask, an N-type metal layer and a P-type metal layer are formed on the passivation reflection structure through evaporation, the N-type metal layer is connected with the N-type GaN layer, and the P-type metal layer is connected with the transparent ITO current expansion layer. According to the invention, the process can be effectively simplified, the material consumption is reduced, and the process flow time is shortened, so that the manufacturing cost of the chip can be remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a flip-chip DBR-LED chip. Background Art

[0002] Figure 1 The structural schematic diagram of an existing flip-chip DBR-LED chip is shown. The traditional manufacturing process of a flip-chip DBR-LED chip (DBR refers to Distributed Bragg Reflector) includes: successively growing an N-type GaN layer 2', a quantum well layer 2", and a P-type GaN layer 2'" on a sapphire substrate 1 to form an epitaxial layer 2; forming a mesa structure (Mesa step) in the epitaxial layer 2 through photolithography and etching to expose the N-type GaN layer 2'; forming isolation trenches 3 in the epitaxial layer 2 through photolithography and etching to expose the sapphire substrate 1; depositing and patterning a transparent ITO current spreading layer 4; forming an N-type electrode metal layer 5' on the N-type GaN layer 2' of the mesa step through photolithography and evaporation, and forming a P-type electrode metal layer 5" on the patterned transparent ITO current spreading layer 4; depositing a passivation and reflection layer 6 over the entire surface of the structure on the sapphire substrate 1; forming an N-type through-hole and a P-type through-hole in the passivation and reflection layer 6 through photolithography and etching; forming an N-type pad metal layer 7' and a P-type pad metal layer 7" on the passivation and reflection layer 6 through photolithography and evaporation. The N-type pad metal layer 7' is connected to the N-type electrode metal layer 5' through the N-type through-hole, and the P-type pad metal layer 7" is connected to the P-type electrode metal layer 5" through the P-type through-hole.

[0003] In the traditional manufacturing process of a flip-chip DBR-LED chip, the entire process is rather cumbersome, with high material consumption and long process flow time, resulting in high manufacturing costs of the chip:

[0004] For example, the mesa step, the isolation trenches 3, and the patterning of the transparent ITO current spreading layer 4 altogether require three independent photolithography-etching processes. The number of photolithography steps is large, greatly increasing the consumption of photoresist materials and process time;

[0005] For example, this chip also requires electrode metal layers (N-type and P-type) to connect the pad metal layers (N-type and P-type), which not only adds processes such as photolithography, evaporation, and photoresist removal for the electrode metal layers (N-type and P-type), but also increases the consumption of photoresist materials and precious metal materials such as Au and Pt. Summary of the Invention

[0006] The purpose of the present invention is to overcome the deficiencies of the prior art. The present invention provides a method for manufacturing a flip-chip DBR-LED chip, which can effectively simplify the process, reduce material consumption, and shorten the process flow time, thereby significantly reducing the manufacturing cost of the chip.

[0007] The present invention provides a method for fabricating an inverted DBR-LED chip, comprising the following steps:

[0008] S1. Sequentially grow an N-type GaN layer, a quantum well layer, and a P-type GaN layer on a sapphire substrate;

[0009] S2. Deposit and form a transparent ITO current spreading layer on the surface of the P-type GaN layer;

[0010] S3. Using a first photoresist as a mask, etch downward from the surface of the transparent ITO current spreading layer to the N-type GaN layer to form an N-type conductive opening;

[0011] S4. Using a second photoresist as a mask, etch downward from the surface of the transparent ITO current spreading layer to the surface of the sapphire substrate to form isolation trenches, and the isolation trenches avoid the N-type conductive opening;

[0012] S5. Deposit and form a passivation and reflection structure on the surfaces of the isolation trenches, the transparent ITO current spreading layer, and the N-type conductive opening;

[0013] S6. Using a third photoresist as a mask, etch in the passivation and reflection structure to form an N-type through hole and a P-type through hole. The N-type through hole is located in the N-type conductive opening and exposes the N-type GaN layer, and the P-type through hole is located above the transparent ITO current spreading layer and exposes the transparent ITO current spreading layer;

[0014] S7. Using a fourth photoresist as a mask, evaporate and deposit independent N-type and P-type metal layers on the passivation and reflection structure. The N-type metal layer is connected to the N-type GaN layer through the N-type through hole, and the P-type metal layer is connected to the transparent ITO current spreading layer through the P-type through hole.

[0015] Specifically, before step S2, it further includes:

[0016] Using a fifth photoresist as a mask, etch a first pit in a preset area of the P-type GaN layer, and using the fifth photoresist as a mask, deposit and form a current blocking layer in the first pit.

[0017] Specifically, step S3 includes:

[0018] Using a first photoresist as a mask, first use an ITO etching solution to etch the transparent ITO current spreading layer, and then use plasma to etch the P-type GaN layer, the quantum well layer, and the N-type GaN layer into the interior of the N-type GaN layer to form an N-type conductive opening;

[0019] Step S4 includes:

[0020] Using the second photoresist as a mask, first use an ITO etching solution to etch the transparent ITO current spreading layer, and then etch the P-type GaN layer, the quantum well layer, and the N-type GaN layer to the surface of the sapphire substrate by plasma to form isolation trenches.

[0021] Specifically, step S3 includes:

[0022] S31. Deposit a sacrificial silicon dioxide layer on the surface of the transparent ITO current spreading layer;

[0023] S32. Using the first photoresist as a mask, first use a BOE etching solution to etch the sacrificial silicon dioxide layer, then use an ITO etching solution to etch the transparent ITO current spreading layer, and then etch the P-type GaN layer, the quantum well layer, and the N-type GaN layer into the N-type GaN layer by plasma to form an N-type conductive opening;

[0024] S33. Remove the first photoresist;

[0025] Step S4 includes:

[0026] S41. Form a second photoresist on the surface of the N-type conductive opening and the remaining sacrificial silicon dioxide layer;

[0027] S42. Using the second photoresist as a mask, first use a BOE etching solution to etch the sacrificial silicon dioxide layer, then use an ITO etching solution to etch the transparent ITO current spreading layer, and then etch the P-type GaN layer, the quantum well layer, and the N-type GaN layer to the surface of the sapphire substrate by plasma to form isolation trenches;

[0028] S43. First remove the second photoresist, and then use a BOE etching solution to etch and remove the remaining sacrificial silicon dioxide layer.

[0029] Specifically, the side wall of the N-type conductive opening is inclined and transitions into the N-type GaN layer, and the inclination angle range of the side wall of the N-type conductive opening is 40° to 60°.

[0030] Specifically, the side wall of the isolation trench is inclined and transitions to the surface of the sapphire substrate, and the inclination angle range of the side wall of the isolation trench is 40° to 60°.

[0031] Specifically, step S5 includes:

[0032] Deposit a first passivation silicon dioxide layer on the surface of the isolation trench, the surface of the transparent ITO current spreading layer, and the surface of the N-type conductive opening;

[0033] Deposit a distributed Bragg reflector on the surface of the first passivation silicon dioxide layer;

[0034] Deposit and form a second passivation silica layer along the surface of the distributed Bragg reflector;

[0035] The first passivation silica layer, the distributed Bragg reflector, and the second passivation silica layer form the passivation reflection structure; wherein, the distributed Bragg reflector is composed of paired reflective silica layers and reflective titanium dioxide layers.

[0036] Specifically, there are 3 to 20 pairs of the paired reflective silica layers and reflective titanium dioxide layers; the reflective silica layer and the reflective titanium dioxide layer are deposited by ion beam assisted deposition technology, and the deposition rate range of the reflective silica layer is The deposition rate range of the reflective titanium dioxide layer is

[0037] Specifically, step S6 further includes:

[0038] Using the third photoresist as a mask, etch the N-type GaN layer at the bottom of the N-type through hole with BCl3, and the gas flow rate of the BCl3 is 20 to 50 sccm.

[0039] Specifically, the N-type GaN layer, the quantum well layer, and the P-type GaN layer form an epitaxial layer. The length of the epitaxial layer in the horizontal direction is A, the horizontal distance from the center of the N-type through hole to the geometric center of the epitaxial layer is L1, the horizontal distance from the center of the P-type through hole to the geometric center of the epitaxial layer is L2, and the horizontal spacing between the N-type metal layer and the P-type metal layer is L3. Then:

[0040]

[0041] Compared with the prior art, the beneficial effects of the present invention are:

[0042] In the preparation method of the flip-chip DBR-LED chip of the present invention, first deposit and form a transparent ITO current spreading layer on the surface of the P-type GaN layer. When forming the N-type conductive opening (essentially a Mesa step) and the isolation trench subsequently, the transparent ITO current spreading layer can be patterned and etched by using the first photoresist and the second photoresist as masks respectively. In this way, there is no need for independent lithography-etching of the transparent ITO current spreading layer, which can effectively reduce the consumption of photoresist materials and shorten the process time;

[0043] The N-type electrode metal layer and the P-type electrode metal layer are eliminated. The N-type metal layer (essentially the N-type pad metal layer) is in direct contact with the N-type GaN layer, and the P-type metal layer (essentially the P-type pad metal layer) is in direct contact with the transparent ITO current spreading layer. This reduces the photolithography, evaporation, and photoresist stripping processes for the electrode metal layers (N-type and P-type), and also reduces the consumption of photoresist materials and precious metal materials such as Au and Pt.

[0044] In summary, the method for fabricating the flip-chip DBR-LED chip of the present invention can effectively simplify the process, reduce material consumption, and shorten the process flow time, thereby significantly reducing the manufacturing cost of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0046] Figure 1 is a schematic structural diagram of a conventional flip-chip DBR-LED chip;

[0047] Figure 2 is a schematic flow diagram of the method for fabricating the flip-chip DBR-LED chip in the embodiment of the present invention;

[0048] Figure 3 is a schematic structural diagram of a sapphire substrate and an epitaxial layer in the embodiment of the present invention;

[0049] Figure 4 is a schematic structural diagram of the structure with a transparent ITO current spreading layer formed in the embodiment of the present invention;

[0050] Figure 5 is a schematic structural diagram of the structure with a first pit formed in the embodiment of the present invention;

[0051] Figure 6 is a schematic structural diagram of the structure with a current blocking layer formed in the embodiment of the present invention;

[0052] Figure 7 is a schematic structural diagram of the transparent ITO current spreading layer and the current blocking layer in the embodiment of the present invention;

[0053] Figure 8 is a schematic structural diagram of the structure with an N-type conductive opening formed in the embodiment of the present invention;

[0054] Figure 9 is a schematic structural diagram of the structure with an isolation trench formed in the embodiment of the present invention;

[0055] Figure 10 It is a schematic flow chart of steps S3 and S4 in the embodiment of the present invention;

[0056] Figure 11 It is a schematic structural diagram of the sacrificial silicon dioxide layer formed in the embodiment of the present invention;

[0057] Figure 12 It is a first schematic structural diagram of etching the sacrificial silicon dioxide layer in the embodiment of the present invention;

[0058] Figure 13 It is a first schematic structural diagram of etching the transparent ITO current spreading layer in the embodiment of the present invention;

[0059] Figure 14 It is a first schematic structural diagram of etching the epitaxial layer in the embodiment of the present invention;

[0060] Figure 15 It is a second schematic structural diagram of etching the sacrificial silicon dioxide layer in the embodiment of the present invention;

[0061] Figure 16 It is a second schematic structural diagram of etching the transparent ITO current spreading layer in the embodiment of the present invention;

[0062] Figure 17 It is a second schematic structural diagram of etching the epitaxial layer in the embodiment of the present invention;

[0063] Figure 18 It is a schematic structural diagram of forming a passivation reflection structure in the embodiment of the present invention;

[0064] Figure 19 It is a schematic structural diagram of forming N-type vias and P-type vias in the embodiment of the present invention;

[0065] Figure 20 It is a schematic structural diagram of the P-type via and the current blocking layer in the embodiment of the present invention;

[0066] Figure 21 It is a schematic structural diagram of forming an N-type metal layer and a P-type metal layer in the embodiment of the present invention;

[0067] Figure 22 It is a schematic distribution structure diagram of the N-type vias and P-type vias in Example 1;

[0068] Figure 23 It is a schematic distribution structure diagram of the N-type vias and P-type vias in Example 2;

[0069] Figure 24 It is a schematic distribution structure diagram of the N-type vias and P-type vias in Comparative Example 1;

[0070] Figure 25It is a schematic diagram of the distribution structure of N-type vias and P-type vias in Comparative Example 2.

[0071] In the attached drawings, 10 is a sapphire substrate; 20 is an epitaxial layer; 21 is an N-type GaN layer; 22 is a quantum well layer; 23 is a P-type GaN layer; 30 is a transparent ITO current spreading layer; 31 is a sacrificial silicon dioxide layer; 40 is a passivation and reflection structure; 41 is a first passivation silicon dioxide layer; 42 is a distributed Bragg reflector; 43 is a second passivation silicon dioxide layer; 51 is an N-type metal layer; 52 is a P-type metal layer; 60 is a first pit; 61 is a current blocking layer; 71 is an N-type pit; 72 is a P-type pit; 100 is an isolation trench; 200 is an N-type conductive opening; 310 is an N-type via; 320 is a P-type via. Specific embodiments

[0072] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0073] The present invention provides a method for preparing a flip-chip DBR-LED chip, Figure 2 which shows a schematic flow chart of the method for preparing a flip-chip DBR-LED chip in an embodiment of the present invention, including the following steps:

[0074] S1. An N-type GaN layer, a quantum well layer, and a P-type GaN layer are sequentially grown on a sapphire substrate;

[0075] Figure 3 which shows a schematic diagram of the structure of a sapphire substrate and an epitaxial layer in an embodiment of the present invention.

[0076] The sapphire substrate 10 is suitable for the growth of GaN-based materials; further, the sapphire substrate 10 is a patterned substrate, which is beneficial to reducing crystal dislocations and refractive index mismatch during the subsequent growth of the epitaxial layer 20.

[0077] The N-type GaN layer 21, the quantum well layer 22, and the P-type GaN layer 23 form an epitaxial layer 20, which is the basic structure for the chip to emit light.

[0078] S2. A transparent ITO current spreading layer is deposited and formed along the surface of the P-type GaN layer;

[0079] Figure 4 which shows a schematic diagram of the structure in which a transparent ITO current spreading layer is formed in an embodiment of the present invention.

[0080] The transparent ITO current spreading layer 30 has high transparency and low sheet resistance, which is beneficial to reducing light absorption and promoting the lateral transmission of current.

[0081] In the present invention, the transparent ITO current spreading layer 30 is first deposited on the surface of the P-type GaN layer 23. When forming the N-type conductive opening 200 and the isolation trench 100 subsequently, the transparent ITO current spreading layer 30 can be patterned and etched by using the first photoresist and the second photoresist as masks respectively. In this way, independent lithography-etching of the transparent ITO current spreading layer 30 is not required, which can effectively reduce the consumption of photoresist materials and shorten the process time. This has a significant effect on simplifying the process, reducing material consumption, and shortening the process flow time, thereby significantly reducing the manufacturing cost of the chip.

[0082] In some specific embodiments, before step S2, it further includes:

[0083] Figure 5 The structural schematic diagram showing the formation of the first pit in the embodiment of the present invention is shown. Figure 6 The structural schematic diagram showing the formation of the current blocking layer in the embodiment of the present invention is shown. Figure 7 The structural schematic diagram showing the transparent ITO current spreading layer and the current blocking layer in the embodiment of the present invention is shown.

[0084] Using the fifth photoresist as a mask, a first pit 60 is etched in a preset area of the P-type GaN layer 23, and using the fifth photoresist as a mask, a current blocking layer 61 is deposited in the first pit 60. The current blocking layer 61 is located below the preset current injection point. The upper surface of the current blocking layer 61 is in direct contact with the transparent ITO current spreading layer 30. The area of the current blocking layer 61 is much smaller than the area of the transparent ITO current spreading layer 30. The current blocking layer 61 can reduce the vertical transmission of current, so that the current fully laterally transmits in the transparent ITO current spreading layer 30 and then flows into the P-type GaN layer 23, which is beneficial to improving the brightness of the chip.

[0085] The current blocking layer 61 deposited in the first pit 60 is integrally embedded in the P-type GaN layer 23, and the upper surface of the current blocking layer 61 is flush with the upper surface of the P-type GaN layer 23, so that the transparent ITO current spreading layer 30 can be smoothly laminated on the P-type GaN layer 23, which is convenient for subsequently smoothly covering the passivation and reflection structure 40 on the transparent ITO current spreading layer 30 and is beneficial to reducing the fracture risk when covering the passivation and reflection structure 40 subsequently.

[0086] Specifically, the material of the current blocking layer 61 is SiO2, which has good insulation performance and can effectively block the vertical transmission of current, relieve the current crowding effect, enable more current to laterally expand in the transparent ITO current spreading layer 30, and is beneficial to improving the brightness of the chip.

[0087] S3. Using the first photoresist as a mask, etch down from the surface of the transparent ITO current spreading layer to form an N-type conductive opening in the N-type GaN layer;

[0088] Figure 8 Fig. shows a schematic structural diagram of the N-type conductive opening formed in the embodiment of the present invention.

[0089] The N-type conductive opening 200 (essentially a Mesa step) serves as a window for exposing the N-type GaN layer 21 in the epitaxial layer 20, facilitating subsequent contact between the N-type metal layer 51 (essentially an N-type pad metal layer) and the N-type GaN layer 21 for current extraction.

[0090] Specifically, using the first photoresist as a mask, first use ITO etching solution to etch the transparent ITO current spreading layer 30, and then etch the P-type GaN layer 23, the quantum well layer 22, and the N-type GaN layer 21 to the inside of the N-type GaN layer 21 through plasma to form an N-type conductive opening 200; using the first photoresist as a mask can complete partial patterning etching of the transparent ITO current spreading layer 30 and complete the formation of the N-type conductive opening 200; moreover, this can reduce the edge spacing between the transparent ITO current spreading layer 30 and the N-type conductive opening 200, which is beneficial to retaining the area of the transparent ITO current spreading layer 30.

[0091] Further, the side wall of the N-type conductive opening 200 is inclined and transitions into the N-type GaN layer 21, and the inclination angle range of the side wall of the N-type conductive opening 200 is 40° - 60°, which is the angle range of the side wall of the N-type conductive opening 200 deviating from the vertical plane. Optionally, the inclination angle of the side wall of the N-type conductive opening 200 can be 40°, 45°, 50°, 55°, or 60°. The inclined side wall is beneficial to stably covering the passivation and reflection structure 40 later and can reduce the fracture risk when covering the passivation and reflection structure 40 later.

[0092] S4. Using the second photoresist as a mask, etch down from the surface of the transparent ITO current spreading layer to the surface of the sapphire substrate to form isolation trenches, and the isolation trenches avoid the N-type conductive opening;

[0093] Figure 9 Fig. shows a schematic structural diagram of the isolation trenches formed in the embodiment of the present invention.

[0094] The isolation trench 100 avoids the N-type conductive opening 200, enabling the N-type conductive opening 200 to be completely retained, which is beneficial to improving the current extraction efficiency.

[0095] Specifically, using the second photoresist as a mask, first use an ITO etching solution to etch the transparent ITO current spreading layer 30, and then etch the P-type GaN layer 23, the quantum well layer 22, and the N-type GaN layer 21 to the surface of the sapphire substrate 10 through plasma etching to form the isolation trench 100; using the second photoresist as a mask, the patterning etching of the remaining part of the transparent ITO current spreading layer 30 can be completed, and the formation of the isolation trench 100 can be completed; moreover, this can reduce the edge spacing between the transparent ITO current spreading layer 30 and the isolation trench 100, and is also beneficial to retaining the area of the transparent ITO current spreading layer 30.

[0096] Furthermore, the side wall of the isolation trench 100 is inclined and transitions to the surface of the sapphire substrate 10. The inclination angle range of the side wall of the isolation trench 100 is 40° to 60°. This is the angle range of the side wall of the isolation trench 100 deviating from the vertical plane. Optionally, the inclination angle of the side wall of the isolation trench 100 can be 40°, 45°, 50°, 55°, or 60°. The inclined side wall is beneficial to the subsequent stable coverage of the passivation reflection structure 40, which can not only reduce the fracture risk during the subsequent coverage of the passivation reflection structure 40, but also reduce the risk of the passivation reflection structure 40 cracking during the subsequent chip separation process.

[0097] Under the combined action of step S3 and step S4, the transparent ITO current spreading layer 30 completes the patterning etching by using the first photoresist and the second photoresist as masks respectively. In this way, independent lithography-etching of the transparent ITO current spreading layer 30 is not required, which can effectively reduce the consumption of photoresist materials and shorten the process time; moreover, this can not only reduce the edge spacing between the transparent ITO current spreading layer 30 and the N-type conductive opening 200, but also reduce the edge spacing between the transparent ITO current spreading layer 30 and the isolation trench 100, thereby effectively retaining the area of the transparent ITO current spreading layer 30, which is beneficial to expanding the current and improving the light emission efficiency of the chip.

[0098] Figure 10 The specific flow schematic diagrams of step S3 and step S4 in the embodiment of the present invention are shown. Step S3 and step S4 include:

[0099] S31. Deposit a sacrificial silicon dioxide layer on the surface of the transparent ITO current spreading layer;

[0100] Figure 11 The structural schematic diagram of the sacrificial silicon dioxide layer formed in the embodiment of the present invention is shown.

[0101] S32. Using the first photoresist as a mask, first use BOE etching solution to etch the sacrificial silicon dioxide layer, then use ITO etching solution to etch the transparent ITO current spreading layer, and then etch the P-type GaN layer, the quantum well layer, and the N-type GaN layer through plasma to the inside of the N-type GaN layer to form an N-type conductive opening;

[0102] Figure 12 FIG. 4 shows a first structural diagram of etching the sacrificial silicon dioxide layer in an embodiment of the present invention; Figure 13 FIG. 5 shows a first structural diagram of etching the transparent ITO current spreading layer in an embodiment of the present invention; Figure 14 FIG. 6 shows a first structural diagram of etching the epitaxial layer in an embodiment of the present invention.

[0103] S33. Remove the first photoresist;

[0104] S41. Form a second photoresist along the surface of the N-type conductive opening and the surface of the remaining sacrificial silicon dioxide layer;

[0105] S42. Using the second photoresist as a mask, first use BOE etching solution to etch the sacrificial silicon dioxide layer, then use ITO etching solution to etch the transparent ITO current spreading layer, and then etch the P-type GaN layer, the quantum well layer, and the N-type GaN layer through plasma to the surface of the sapphire substrate to form isolation trenches;

[0106] Figure 15 FIG. 7 shows a second structural diagram of etching the sacrificial silicon dioxide layer in an embodiment of the present invention; Figure 16 FIG. 8 shows a second structural diagram of etching the transparent ITO current spreading layer in an embodiment of the present invention; Figure 17 FIG. 9 shows a second structural diagram of etching the epitaxial layer in an embodiment of the present invention.

[0107] S43. First remove the second photoresist, and then use BOE etching solution to etch and remove the remaining sacrificial silicon dioxide layer.

[0108] Please refer to Figure 9 , after the sacrificial silicon dioxide layer 31 is removed, an N-type conductive opening 200 and isolation trenches 100 are obtained.

[0109] During the dry etching process of the N-type conductive opening 200 and the isolation trenches 100, the photoresist is easily affected by temperature and becomes hard, resulting in difficulty in subsequent complete removal; if there is photoresist residue on the surface of the transparent ITO current spreading layer 30, it is likely to affect the adhesion of the subsequent passivation reflection structure 40, and in severe cases, even interface abnormal peeling will occur.

[0110] The material of the sacrificial silicon dioxide layer 31 is SiO2, which is easily etched clean by BOE etching solution and is easy to rinse. By providing the sacrificial silicon dioxide layer 31 and attaching the photoresist mask to the surface of the sacrificial silicon dioxide layer 31, it is avoided that the photoresist mask is directly attached to the surface of the transparent ITO current spreading layer 30. In this way, even if the photoresist becomes hard and difficult to remove due to temperature influence, the residual photoresist can also be removed cleanly by removing the sacrificial silicon dioxide layer 31.

[0111] Moreover, the sacrificial silicon dioxide layer 31 can be used as a hard mask, with high stability, not easily deformed by temperature influence, and capable of accurately transferring the pattern angle of the photoresist mask to the transparent ITO current spreading layer 30 and the epitaxial layer 20, ensuring that the patterns of the N-type conductive opening 200 and the isolation trench 100 are precise and clear.

[0112] Specifically, the thickness range of the sacrificial silicon dioxide layer 31 is Preferably, the thickness range of the sacrificial silicon dioxide layer 31 is Balancing the effect and cost, with good cost performance.

[0113] S5. Deposit and form a passivation and reflection structure along the surfaces of the isolation trench, the transparent ITO current spreading layer, and the N-type conductive opening;

[0114] Figure 18 FIG. shows a schematic structural diagram of the passivation and reflection structure formed in the embodiment of the present invention.

[0115] The passivation and reflection structure 40 covers the entire surface of the structure on the sapphire substrate 10, can reflect the light emitted by the quantum well layer 22 in all directions, and can effectively passivate and protect the surface of the chip.

[0116] Specifically, step S5 includes:

[0117] Deposit and form a first passivation silicon dioxide layer 41 along the surfaces of the isolation trench 100, the transparent ITO current spreading layer 30, and the N-type conductive opening 200;

[0118] Deposit and form a distributed Bragg reflector 42 along the surface of the first passivation silicon dioxide layer 41;

[0119] Deposit and form a second passivation silicon dioxide layer 43 along the surface of the distributed Bragg reflector 42;

[0120] The first passivation silica layer 41, the distributed Bragg reflector 42, and the second passivation silica layer 43 constitute the passivation reflection structure 40; wherein, the distributed Bragg reflector 42 is composed of paired reflective silica layers and reflective titanium dioxide layers. The first passivation silica layer 41 and the second passivation silica layer 43 mainly play a passivation and protection role, and the distributed Bragg reflector 42 mainly plays a light reflection role.

[0121] Further, there are 3 to 20 pairs of the paired reflective silica layers and reflective titanium dioxide layers. The reflectivity of the distributed Bragg reflector 42 will increase with the increase in the number of film layers, and the appropriate number of film layers can be selected according to specific requirements; preferably, there are 10 to 20 pairs of the paired reflective silica layers and reflective titanium dioxide layers. The high reflection bandwidth range of the 10 - 20 pairs of film layers is 420 - 550 nm, and the reflectivity range is 85% - 99.5%, with wide applicability.

[0122] The reflective silica layer and the reflective titanium dioxide layer are deposited by an ion beam assisted deposition technique. The deposition rate range of the reflective silica layer is The deposition rate range of the reflective titanium dioxide layer is A low deposition rate can effectively improve the film layer quality and adhesion, and reduce defects (porosity < 0.3%); at this time, the current range of the ion source is controlled to be 1000 - 1500 mA, and the voltage range of the ion source is controlled to be 1000 - 1500 V.

[0123] In some specific embodiments, the second passivation silica layer 43 is deposited by a chemical vapor deposition method or an ion beam assisted deposition method; wherein, if the ion beam assisted deposition method is used for depositing the second passivation silica layer 43, its deposition rate range is The current range of the ion source is controlled to be 1200 - 1500 mA, and the voltage range of the ion source is controlled to be 1200 - 1500 V, which is beneficial to improving the denseness of the second passivation silica layer 43 and making the tensile stress of the second passivation silica layer 43 evenly distributed.

[0124] S6. Using the third photoresist as a mask, N - type through - holes and P - type through - holes are etched in the passivation reflection structure. The N - type through - holes are located in the N - type conductive openings and expose the N - type GaN layer, and the P - type through - holes are located above the transparent ITO current spreading layer and expose the transparent ITO current spreading layer;

[0125] Figure 19 The structural schematic diagram showing the formation of N - type through - holes and P - type through - holes in the embodiment of the present invention is shown.

[0126] The N-type vias 310 provide a channel for the subsequent N-type metal layer 51 to connect to the N-type GaN layer 21, and the P-type vias 320 provide a channel for the subsequent P-type metal layer 52 to connect to the transparent ITO current spreading layer 30.

[0127] Figure 20 FIG. shows a schematic structural diagram of the P-type vias and the current blocking layer in an embodiment of the present invention. Among them, the projection of the P-type vias 320 on the epitaxial layer 20 completely falls on the current blocking layer 61, which is beneficial to reducing the vertical transmission of current. It should be noted that the masks formed by the third photoresist and the fifth photoresist need to be positioned with reference to the same mark (the mark can be set on the edge or the back of the sapphire substrate 10, etc.) to ensure that the projection of the P-type vias 320 on the epitaxial layer 20 accurately falls on the current blocking layer 61.

[0128] Specifically, the side wall of the N-type via 310 is inclined and transitions to the N-type GaN layer 21. The inclination angle range of the side wall of the N-type via 310 is 20° to 50°. This is the angle range of the side wall of the N-type via 310 deviating from the vertical plane. Optionally, the inclination angle of the side wall of the N-type via 310 can be 20°, 25°, 30°, 35°, 40°, 45° or 50°, which is beneficial to improving the coverage effect of the subsequent N-type metal layer 51 at the corner and improving the thrust value of the chip. The side wall of the P-type via 320 is inclined and transitions to the surface of the transparent ITO current spreading layer 30. The inclination angle range of the side wall of the P-type via 320 is 20° to 50°. This is the angle range of the side wall of the P-type via 320 deviating from the vertical plane. Optionally, the inclination angle of the side wall of the P-type via 320 can be 20°, 25°, 30°, 35°, 40°, 45° or 50°, which is beneficial to improving the coverage effect of the subsequent P-type metal layer 52 at the corner and improving the thrust value of the chip.

[0129] Furthermore, the shape of the horizontal cross-section of the N-type via 310 is circular, square or rectangular, and the shape of the horizontal cross-section of the P-type via 320 is circular, square or rectangular, which can be selected according to specific requirements. Preferably, the shape of the horizontal cross-section of the N-type via 310 is circular, and the shape of the horizontal cross-section of the P-type via 320 is circular. Compared with other shapes, the circle has a larger area, which is convenient for the subsequent N-type metal layer 51 to connect to the N-type GaN layer 21 and is also convenient for the subsequent P-type metal layer 52 to connect to the transparent ITO current spreading layer 30.

[0130] In some specific embodiments, step S6 further includes:

[0131] Using the third photoresist as a mask, etch the N-type GaN layer 21 at the bottom of the N-type via hole 310 with BCl3, and the gas flow rate of the BCl3 is 20-50 sccm. This can effectively improve the surface flatness of the N-type GaN layer 21 at the bottom of the N-type via hole 310, thereby facilitating the reduction of the contact resistance between the subsequent N-type metal layer 51 and the N-type GaN layer 21.

[0132] Specifically, the step of etching the N-type GaN layer 21 at the bottom of the N-type via hole 310 with BCl3 includes:

[0133] In the first stage, etch with BCl3 at a rate of 180-200 nm / min;

[0134] In the second stage, etch with BCl3 at a rate of 30-50 nm / min.

[0135] The etching rate in the first stage is relatively fast, which is beneficial to shortening the process time; the etching rate in the second stage is relatively slow, which is beneficial to protecting the transparent ITO current spreading layer 30 at the bottom of the P-type via hole 320 and can reduce the damage to the transparent ITO current spreading layer 30.

[0136] S7. Using the fourth photoresist as a mask, evaporate and deposit independent N-type and P-type metal layers on the passivation and reflection structure. The N-type metal layer is connected to the N-type GaN layer through the N-type via hole, and the P-type metal layer is connected to the transparent ITO current spreading layer through the P-type via hole;

[0137] Figure 21 Fig. shows a schematic structural diagram of the N-type and P-type metal layers formed in the embodiment of the present invention.

[0138] The traditional N-type electrode metal layer and P-type electrode metal layer are cancelled. The N-type metal layer 51 (essentially an N-type pad metal layer) directly contacts the N-type GaN layer 21, and the P-type metal layer 52 (essentially a P-type pad metal layer) directly contacts the transparent ITO current spreading layer 30. This not only reduces the photolithography, evaporation, and photoresist removal processes of the electrode metal layers (N-type and P-type), but also reduces the consumption of photoresist materials and precious metal materials such as Au and Pt.

[0139] Moreover, by cancelling the traditional N-type electrode metal layer and P-type electrode metal layer, the N-type metal layer 51 passes through the passivation and reflection structure 40 to directly contact the N-type GaN layer 21, and the P-type metal layer 52 passes through the passivation and reflection structure 40 to directly contact the transparent ITO current spreading layer 30, avoiding the risk of fracture of the passivation and reflection structure 40 caused by the protrusion of the electrode metal layer.

[0140] In addition, some traditional N-type electrode metal layers and P-type electrode metal layers also extend finger structures to expand the current transmission. However, during the die bonding and testing processes of the chip, the finger structures are easily damaged by the displaced ejector pins, which can easily lead to chip leakage. By eliminating the traditional N-type electrode metal layer and P-type electrode metal layer, the existence of the finger structures is avoided, thus reducing the risk of abnormal chip leakage.

[0141] In some specific embodiments, the upper ends of the N-type metal layer 51 and the P-type metal layer 52 are flush, which is convenient for coplanar soldering during the packaging of the flip-chip DBR-LED chip.

[0142] In some specific embodiments, the length of the epitaxial layer 20 in the horizontal direction is A, the horizontal distance from the center of the N-type through hole 310 to the geometric center of the epitaxial layer 20 is L1, the horizontal distance from the center of the P-type through hole 320 to the geometric center of the epitaxial layer 20 is L2, and the horizontal spacing between the N-type metal layer 51 and the P-type metal layer 52 is L3. Then:

[0143]

[0144] Only by constraining the N-type through hole 310 and the P-type through hole 320 in appropriate positions and controlling the horizontal spacing between the N-type metal layer 51 and the P-type metal layer 52 can the voltage stability and brightness stability of the chip be ensured after eliminating the electrode metal layer. Otherwise, it is easy to cause the voltage to increase and the brightness to decrease.

[0145] Preferably, While ensuring the chip voltage and brightness, it is convenient for processing.

[0146] Specifically, the large-end radius of the N-type through hole 310 is R1, the distance from the edge of the N-type through hole 310 to the edge of the N-type metal layer 51 is C1, the large-end radius of the P-type through hole 320 is R2, and the distance from the edge of the P-type through hole 320 to the edge of the P-type metal layer 52 is C2. Then:

[0147] C1≥2R1, C2≥2R2.

[0148] This is beneficial to completely covering the N-type through hole 310 with the N-type metal layer 51 and also beneficial to completely covering the P-type through hole 320 with the P-type metal layer 52.

[0149] In addition, the projection of the N-type metal layer 51 on the epitaxial layer 20 completely covers the N-type conductive opening 200, which can ensure the current extraction efficiency. Both the N-type metal layer 51 and the P-type metal layer 52 extend to cover in the isolation trench 100, which not only has a larger heat dissipation area but also plays a certain protective role for the passivation reflection structure 40.

[0150] Further, one of the N-type vias 310 and one of the P-type vias 320 form a set of conductive vias, and the number of sets of the conductive vias is 1 to 4 sets.

[0151] In some specific embodiments, the N-type metal layer 51 includes, from bottom to top, a first Cr layer, a first AlTi stack, a first Ni layer, and a first Au layer stacked in sequence, and the P-type metal layer 52 includes, from bottom to top, a second Cr layer, a second AlTi stack, a second Ni layer, and a second Au layer stacked in sequence. The Cr layer can enhance the adhesion ability, the AlTi stack can improve the structural stability, the Ni layer can effectively protect the underlying AlTi stack, and the Au layer can improve the soldering contact effect.

[0152] Specifically, the number of pairs of the first AlTi stack is 3 to 5 pairs, and the number of pairs of the second AlTi stack is 3 to 5 pairs, which can effectively improve the denseness of the film layer and release the internal stress.

[0153] In some specific embodiments, please refer to Figure 21 , the N-type metal layer 51 has an N-type pit 71, and the N-type pit 71 is directly above the N-type via 310; the P-type metal layer 52 has a P-type pit 72, and the P-type pit 72 is directly above the P-type via 320; during soldering, the N-type pit 71 and the P-type pit 72 can provide a larger contact area, which is beneficial to enhancing the soldering contact effect.

[0154] Further, the N-type pit 71 is provided with a first solder layer, and the P-type pit 72 is provided with a second solder layer. By pre-setting the solder, the efficiency of subsequent eutectic soldering can be improved.

[0155] The preparation method of the flip-chip DBR-LED chip of the present invention can effectively simplify the process, reduce material consumption, and shorten the process flow time, thereby significantly reducing the manufacturing cost of the chip.

[0156] In the present invention, a transparent ITO current spreading layer 30 is first deposited on the surface of the P-type GaN layer 23. When forming the N-type conductive opening 200 and the isolation trench 100 subsequently, the transparent ITO current spreading layer 30 can be patterned and etched by using the first photoresist and the second photoresist as masks respectively. In this way, independent lithography-etching for the transparent ITO current spreading layer 30 is not required, which can effectively reduce the consumption of photoresist materials and shorten the process time. Moreover, in this way, the edge distance between the transparent ITO current spreading layer 30 and the N-type conductive opening 200 can be reduced, and the edge distance between the transparent ITO current spreading layer 30 and the isolation trench 100 can be reduced, so that the area of the transparent ITO current spreading layer 30 can be effectively retained, which is beneficial to current spreading and improving the light-emitting efficiency of the chip.

[0157] In the present invention, the N-type electrode metal layer and the P-type electrode metal layer are cancelled. The N-type metal layer 51 (essentially an N-type pad metal layer) directly contacts the N-type GaN layer 21, and the P-type metal layer 52 (essentially a P-type pad metal layer) directly contacts the transparent ITO current spreading layer 30, reducing the processes such as lithography, evaporation plating, and photoresist removal of the electrode metal layers (N-type and P-type), and also reducing the consumption of photoresist materials and precious metal materials such as Au and Pt.

[0158] Moreover, since the traditional electrode metal layer is cancelled in the present invention, the risk of fracture of the passivation reflection structure 40 caused by the protrusion of the electrode metal layer can be avoided. At the same time, the finger structure extending from the traditional electrode metal layer is also avoided, so that the chip is not easily damaged by the thimble at the finger structure during die bonding, testing and other processes, causing leakage. And in the present invention, by obliquely arranging the side wall of the N-type conductive opening 200 and the side wall of the isolation trench 100, the vertical walls can be reduced, and the passivation reflection structure 40 is more likely to stably adhere to the inclined walls, which can also effectively reduce the risk of fracture of the passivation reflection structure 40. By embedding the current blocking layer 61 in the P-type GaN layer 23, the upper surface of the P-type GaN layer 23 is kept flat, so that the transparent ITO current spreading layer 30 can be flatly laminated on the P-type GaN layer 23, and thus the passivation reflection structure 40 can be flatly covered on the transparent ITO current spreading layer 30, which is beneficial to reducing the fracture risk when covering the passivation reflection structure 40.

[0159] During the formation process of the N-type conductive opening 200 and the isolation trench 100, a sacrificial silicon dioxide layer 31 is provided, and a photoresist mask is attached to the surface of the sacrificial silicon dioxide layer 31, preventing the photoresist mask from directly attaching to the surface of the transparent ITO current spreading layer 30. In this way, even if the photoresist becomes hard and difficult to remove due to temperature effects, the residual photoresist can be removed by removing the sacrificial silicon dioxide layer 31. Moreover, the sacrificial silicon dioxide layer 31 can serve as a hard mask, with high stability and not easily deformed by temperature, and can accurately transfer the pattern angle of the photoresist mask to the transparent ITO current spreading layer 30 and the epitaxial layer 20, ensuring the accuracy and clarity of the patterns of the N-type conductive opening 200 and the isolation trench 100.

[0160] In addition, the side walls of the N-type through holes 310 and P-type through holes 320 of the present invention are both inclined, which is beneficial to improving the coverage effect of the N-type metal layer 51 and the P-type metal layer 52 at the corners and increasing the pushing force value of the chip; the present invention flattens and repairs the N-type GaN layer 21 at the bottom of the N-type through hole 310 by using BCl3 etching, which is beneficial to reducing the contact resistance between the N-type metal layer 51 and the N-type GaN layer 21; the N-type metal layer 51 and the P-type metal layer 52 both extend and cover in the isolation trench 100, which not only has a larger heat dissipation area but also plays a certain protective role for the passivation reflection structure 40.

[0161] Example 1

[0162] Figure 22 Shows a schematic distribution structure diagram of the N-type through holes and P-type through holes in Example 1, and the horizontal distance between the N-type metal layer and the P-type metal layer satisfies Set a group of conductive through holes: one N-type through hole and one P-type through hole,

[0163] Satisfy

[0164] Example 2

[0165] Figure 23 Shows a schematic distribution structure diagram of the N-type through holes and P-type through holes in Example 2, and the horizontal distance between the N-type metal layer and the P-type metal layer satisfies Set two groups of conductive through holes: two N-type through holes and two P-type through holes,

[0166] Satisfy

[0167] Comparative Example 1

[0168] Figure 24 Shows a schematic distribution structure diagram of the N-type through holes and P-type through holes in Comparative Example 1, and the horizontal distance between the N-type metal layer and the P-type metal layer satisfies Set two groups of conductive vias: two N-type vias and two P-type vias,

[0169] Meet

[0170] Comparative Example 2

[0171] Figure 25 Fig. shows the distribution structure schematic diagram of the N-type vias and P-type vias in Comparative Example 2. The horizontal distance between the N-type metal layer and the P-type metal layer meets Set four groups of conductive vias: four N-type vias and four P-type vias,

[0172] Among them, two groups of conductive vias meet

[0173] The other two groups of conductive vias meet

[0174] Result comparison of voltage and brightness

[0175]

[0176] (1) Compared with the traditional chip, the brightness of the chips in Embodiments 1 and 2 is effectively improved, and the increase in the chip voltage is slight. This shows that by constraining the N-type vias and P-type vias in specific positions and controlling the horizontal distance between the N-type metal layer and the P-type metal layer, that is, meeting

[0177]

[0178] The chip brightness can be effectively improved. Although the chip voltage increases slightly, the advantage of the chip brightness improvement is obvious.

[0179] (2) Compared with Embodiment 1, the chip voltage in Embodiment 2 decreases slightly, while the chip brightness decreases more. This shows that under the same conditions of L1, L2, and L3, as the number of groups of conductive vias increases, the chip brightness is likely to decrease and the decrease is more, and the change in the chip voltage is not obvious.

[0180] (3) Compared with Embodiment 2, the chip voltage in Comparative Example 1 increases significantly, and at the same time the chip brightness decreases slightly. This shows that the proximity of the N-type vias and P-type vias is beneficial to reducing the chip voltage.

[0181] (4) Compared with Embodiment 2, the chip voltage in Comparative Example 2 increases slightly, and the chip brightness decreases significantly. This shows that increasing the conductive vias, the chip brightness is likely to decrease and the decrease is more, and the change in the chip voltage is not obvious.

[0182] The above has introduced in detail a method for preparing an inverted DBR-LED chip provided by an embodiment of the present invention. In this article, specific examples have been used to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A preparation method of an inverted DBR-LED chip, characterized in that It includes the following steps: S1. Sequentially grow an N-type GaN layer, a quantum well layer, and a P-type GaN layer on a sapphire substrate; S2. Deposit and form a transparent ITO current spreading layer on the surface of the P-type GaN layer; S3. Using a first photoresist as a mask, etch downward from the surface of the transparent ITO current spreading layer into the N-type GaN layer to form an N-type conductive opening; S4. Using a second photoresist as a mask, etch downward from the surface of the transparent ITO current spreading layer to the surface of the sapphire substrate to form isolation trenches, and the isolation trenches avoid the N-type conductive opening; S5. Deposit and form a passivation and reflection structure on the surfaces of the isolation trenches, the transparent ITO current spreading layer, and the N-type conductive opening; S6. Using a third photoresist as a mask, etch to form an N-type through hole and a P-type through hole in the passivation and reflection structure. The N-type through hole is located in the N-type conductive opening and exposes the N-type GaN layer, and the P-type through hole is located above the transparent ITO current spreading layer and exposes the transparent ITO current spreading layer; S7. Using a fourth photoresist as a mask, evaporate and deposit independent N-type and P-type metal layers on the passivation and reflection structure. The N-type metal layer is connected to the N-type GaN layer through the N-type through hole, and the P-type metal layer is connected to the transparent ITO current spreading layer through the P-type through hole.

2. The manufacturing method of the flip-chip DBR-LED chip according to claim 1, characterized in that, Before step S2, it further includes: Using a fifth photoresist as a mask, etch to form a first pit in a preset area of the P-type GaN layer, and using the fifth photoresist as a mask, deposit and form a current blocking layer in the first pit.

3. The manufacturing method of the flip-chip DBR-LED chip according to claim 1, characterized in that Step S3 includes: Using a first photoresist as a mask, first use an ITO etching solution to corrode the transparent ITO current spreading layer, and then use plasma to etch the P-type GaN layer, the quantum well layer, and the N-type GaN layer into the interior of the N-type GaN layer to form an N-type conductive opening; Step S4 includes: Using a second photoresist as a mask, first use an ITO etching solution to corrode the transparent ITO current spreading layer, and then use plasma to etch the P-type GaN layer, the quantum well layer, and the N-type GaN layer to the surface of the sapphire substrate to form isolation trenches.

4. The manufacturing method of the flip-chip DBR-LED chip according to claim 3, characterized in that, Step S3 includes: S31. Deposit and form a sacrificial silicon dioxide layer on the surface of the transparent ITO current spreading layer; S32. Using a first photoresist as a mask, first use a BOE etching solution to corrode the sacrificial silicon dioxide layer, then use an ITO etching solution to corrode the transparent ITO current spreading layer, and then use plasma to etch the P-type GaN layer, the quantum well layer, and the N-type GaN layer into the interior of the N-type GaN layer to form an N-type conductive opening; S33. Remove the first photoresist; Step S4 includes: S41. Form a second photoresist on the surface of the N-type conductive opening and the remaining sacrificial silicon dioxide layer; S42. Using the second photoresist as a mask, first use BOE etching solution to etch the sacrificial silicon dioxide layer, then use ITO etching solution to etch the transparent ITO current spreading layer, and then etch the P-type GaN layer, the quantum well layer and the N-type GaN layer to the surface of the sapphire substrate through plasma to form isolation trenches; S43. First remove the second photoresist, and then use BOE etching solution to etch and remove the remaining sacrificial silicon dioxide layer.

5. The manufacturing method of the flip-chip DBR-LED chip according to claim 1, 3 or 4, characterized in that, The side wall of the N-type conductive opening is inclined and transitions into the N-type GaN layer, and the inclination angle range of the side wall of the N-type conductive opening is 40° to 60°.

6. The manufacturing method of the flip-chip DBR-LED chip according to claim 1, 3 or 4, characterized in that The side wall of the isolation trench is inclined and transitions to the surface of the sapphire substrate, and the inclination angle range of the side wall of the isolation trench is 40° to 60°.

7. The manufacturing method of the flip - type DBR - LED chip according to claim 1, characterized in that, Step S5 includes: Deposit and form a first passivation silicon dioxide layer along the surfaces of the isolation trench, the transparent ITO current spreading layer and the N-type conductive opening; Deposit and form a distributed Bragg reflector along the surface of the first passivation silicon dioxide layer; Deposit and form a second passivation silicon dioxide layer along the surface of the distributed Bragg reflector; The first passivation silicon dioxide layer, the distributed Bragg reflector and the second passivation silicon dioxide layer form the passivation reflection structure; wherein, the distributed Bragg reflector is composed of paired reflection silicon dioxide layers and reflection titanium dioxide layers.

8. The manufacturing method of the flip-chip DBR-LED chip according to claim 7, characterized in that The paired reflective silica layers and reflective titanium dioxide layers are 3 to 20 pairs; the reflective silica layers and the reflective titanium dioxide layers are deposited by an ion beam assisted deposition technique, and the deposition rate range of the reflective silica layers is The deposition rate range of the reflective titanium dioxide layers is 9. The manufacturing method of the flip-chip DBR-LED chip according to claim 1, characterized in that, Step S6 further includes: Using the third photoresist as a mask, use BCl3 to etch the N-type GaN layer at the bottom of the N-type through hole, and the gas flow rate of BCl3 is 20 to 50 sccm.

10. The manufacturing method of the flip-chip DBR-LED chip according to claim 1, characterized in that, The N-type GaN layer, the quantum well layer and the P-type GaN layer form an epitaxial layer. The length of the epitaxial layer in the horizontal direction is A, the horizontal distance from the center of the N-type through hole to the geometric center of the epitaxial layer is L1, the horizontal distance from the center of the P-type through hole to the geometric center of the epitaxial layer is L2, and the horizontal spacing between the N-type metal layer and the P-type metal layer is L3. Then:

Images