Multi-die package with shaped brightness

Abstract

The present specification discloses a light emitting device having a pad with improved performance. A pad is disposed under the die to prevent the occurrence of hot spots, particularly under the peak luminance region of the shaped luminance die. The pad may have an n-region and a p-region that are asymmetric, with a larger region disposed below the peak brightness region, while a gap between the n-region and the p-region does not overlap the peak brightness region. The pads of different dies are bridged by horizontal or diagonal connections between the dies.

Description

[0001] Cross - reference to related applications This application claims the benefit of the priority of U.S. Provisional Application No. 63 / 433,279, filed on Dec. 16, 2022, which is hereby incorporated by reference in its entirety into this application. Technical field

[0002] The present invention generally relates to LEDs, pcLEDs, LED arrays, and pcLED arrays, light sources including LEDs, pcLEDs, LED arrays, or pcLED arrays, multi - die packages including LED arrays or pcLED arrays, and motor vehicle headlights including such multi - die packages. Background art

[0003] Semiconductor light - emitting diodes and laser diodes (collectively referred to herein as "LEDs") are among the most efficient light sources currently available. The emission spectrum of an LED typically exhibits a single narrow peak at a wavelength determined by the structure of the device and the composition of the semiconductor material of which it is made. By appropriately selecting the device structure and material system, an LED can be designed to operate at ultraviolet, visible, or infrared wavelengths.

[0004] An LED can be combined with one or more wavelength - converting materials (generally referred to herein as "phosphors") that absorb the light emitted by the LED and in response emit light of a longer wavelength. For such phosphor - converted LEDs ("pcLEDs"), the fraction of the light emitted by the LED that is absorbed by the phosphor depends on the amount of phosphor material on the optical path of the light emitted by the LED, e.g., on the concentration of the phosphor material in a phosphor layer disposed on or around the LED and the thickness of the layer. A phosphor - converted LED can be designed such that all of the light emitted by the LED is absorbed by one or more phosphors, in which case the emission from the pcLED comes entirely from the phosphors. In such a case, for example, the phosphors can be selected to emit light in a narrow spectral region that is not directly and efficiently generated by the LED. Alternatively, a pcLED can be designed such that only a portion of the light emitted by the LED is absorbed by the phosphor, in which case the emission from the pcLED is a mixture of the light emitted by the LED and the light emitted by the phosphor. By appropriately selecting the LED, the phosphor, and the phosphor composition, such a pcLED can be designed to emit, for example, white light having a desired color temperature and desired color - rendering properties.

[0005] Inorganic LEDs and pcLEDs have been widely used in manufacturing different types of displays, matrices, and light engines, including: motor vehicle adaptive headlights, augmented reality (AR) displays, virtual reality (VR) displays, mixed reality (MR) displays (AR, VR, and MR systems are referred to as visualization systems herein), smart glasses, and displays for mobile phones, smart watches, monitors, and televisions, as well as flash lighting for cameras in mobile phones. Depending on the size of the matrix or display and its pixel-per-inch requirements, each LED or pcLED in these architectures can have an area ranging from several square millimeters down to several square micrometers (e.g., microLEDs).

[0006] Such LEDs and pcLEDs can be arranged in arrays for use, for example, in motor vehicles and for general lighting, including indoor and outdoor. Specifically, some of these LEDs and pcLEDs can be shaped to have a specific brightness distribution with a brightness gradient and / or regions with peak brightness. In particular, these multi-die packages with these LEDs and pcLEDs can be used for high-beam and low-beam applications in motor vehicle headlights. These devices are often subject to physical constraints to meet optical and thermal requirements, such that they emit light effectively while having good heat dissipation. The optical requirements may suggest that the dies in the multi-die package be spaced as closely as possible. At the same time, manufacturing tolerances for connecting the dies to avoid short circuits and solder overflow may suggest spacing the dies farther apart. A die design that meets all these requirements is needed. Summary of the Invention

[0007] This specification discloses a way of connecting dies to each other that provides better heat dissipation, prevents short circuits during manufacturing, and / or improves the optical efficiency of the brightness dies for shaping. These advantages can be obtained by horizontally orienting the pads such that the gap between the opposite-polarity electrical pads under the die does not overlap with the peak brightness region of the die. Additional advantages can be obtained by reversing the electrical pad polarity between adjacent dies or diagonally connecting the opposite-polarity electrical pads between adjacent dies.

[0008] The present invention can be used in any motor vehicle headlight where a multi-die package is needed. It is preferably used in a multi-die package where the surface brightness distribution of each die is intentionally non-uniform and where large electrical pads must completely cover the region where peak current is generated to reduce thermal resistance.

[0009] Other embodiments, features, and advantages of the present invention will become more apparent to those skilled in the art when reference is made to the following more detailed description of the invention in conjunction with the accompanying drawings, which are briefly described first. Brief Description of the Drawings

[0010] Figure 1 Shows a schematic cross-sectional view of an exemplary pcLED.

[0011] Figure 2A and Figure 2B Show a schematic cross-sectional view and a top view of a pcLED array, respectively. Figure 2C Shows a schematic top view of an LED die from which an LED array such as Figure 2A and Figure 2B The LED arrays shown in can be formed.

[0012] Figure 3A Shows a schematic top view of an electronic board on which an LED or pcLED array can be mounted, and Figure 3B Similarly shows a pcLED array mounted on the Figure 3A Electronic board.

[0013] Figure 4A Shows a schematic cross-sectional view of a pcLED array arranged relative to a waveguide and a projection lens. Figure 4B Shows an arrangement similar to that of Figure 4A In the absence of a waveguide.

[0014] Figure 5 Schematically shows an exemplary camera flash system.

[0015] Figure 6 Shows a top view of a multi-die package with a die having a shaped brightness.

[0016] Figure 7 Shows a top view of a die and vertically oriented solder pads under the die.

[0017] Figure 8 Shows a top view of a die and horizontally oriented solder pads under the die such that the gap between the n-region and the p-region does not overlap the peak brightness region of the die.

[0018] Figure 9a Shows a top view of a multi-die package having a die with a shaped brightness and solder pads horizontally aligned with the pads of adjacent dies of the same polarity. Figure 9b Shows the same view such that the diagonal connection of the top metallization layer of the tile of the solder pads and the metallization layer connecting the solder pads is visible.

[0019] Figure 10 Shows a cross-section of a multi-die package viewed from the lower edge of the package.

[0020] Figure 11 Shows a cross-section of a multi-die package viewed from the side edge of the package.

[0021] Figure 12 Shows a metallization layer with diagonally connected solder pads.

[0022] Figure 13 Shows a top view of a multi-die package having dies with shaped brightness and solder pads horizontally aligned with pads of adjacent dies of opposite polarity, with visible top metallization layers of the tiles bridged by horizontal connections.

[0023] Figure 14 Shows a metallization layer with horizontally connected solder pads.

[0024] Figure 15 Shows a cross-section of a multi-die package viewed from the lower edge of the package.

[0025] Figure 16 Shows a die and a metallization layer with horizontally connected solder pads in a 1×5 array.

[0026] Figure 17 Shows a metallization layer with horizontally connected solder pads in a 1×5 array.

[0027] Figure 18 Shows a cross-section of the under-bump metallization of the solder pad and the layer forming its electrical connection to the die. DETAILED DESCRIPTION

[0028] The following detailed description should be read with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout the different figures. The drawings, which are not necessarily to scale, depict alternative embodiments and are not intended to limit the scope of the invention. The detailed description illustrates the principles of the invention by way of example and not by way of limitation.

[0029] Figure 1 Shows an example of a single pcLED 100, which includes a light-emitting semiconductor diode (LED) structure 102 disposed on a substrate 104, and a phosphor layer 106 (which may also be referred to herein as a wavelength conversion structure) disposed on the LED. The light-emitting semiconductor diode structure 102 generally includes an active region disposed between an n-type layer and a p-type layer. Applying a suitable forward bias across the diode structure causes light to be emitted from the active region. The wavelength of the emitted light is determined by the composition and structure of the active region.

[0030] For example, the LED can be a Group III nitride LED that emits ultraviolet, blue, green, or red light. LEDs formed from any other suitable material system and emitting light of any other suitable wavelength can also be used. Other suitable material systems can include, for example, Group III phosphide materials, Group III arsenide materials, and II-IV group materials.

[0031] Any suitable phosphor material can be used, depending on the desired optical output and color specifications from the pcLED. The phosphor layer can, for example, include phosphor particles dispersed in a binder material or bonded to each other with a binder material, or can be or include a sintered ceramic phosphor plate.

[0032] Figures 2A - 2B A cross-sectional view and a top view of an array 200 of pcLEDs 100 including a phosphor layer 106 disposed on a substrate 202 are shown, respectively. Such an array can include any suitable number of pcLEDs arranged in any suitable manner. In the illustrated example, the array is depicted as being formed monolithically on a shared substrate, but alternatively, an array of LEDs or pcLEDs can be formed from individually mechanically separated LEDs or pcLEDs. The substrate 202 can optionally include CMOS circuitry for driving the LEDs and can be formed from any suitable material.

[0033] Although Figures 2A - 2B a three-by-three array of nine pcLEDs is shown, such an array can include, for example, dozens, hundreds, or thousands of LEDs or pcLEDs. The width (e.g., side length) of each LED or pcLED in the array plane can be, for example, less than or equal to 1 millimeter (mm), less than or equal to 500 micrometers, less than or equal to 100 micrometers, less than or equal to 50 micrometers, or less than or equal to 10 micrometers. The LEDs in such an array can be spaced apart from each other by streets or lanes having a width, for example, of hundreds of micrometers, less than or equal to 100 micrometers, less than or equal to 50 micrometers, less than or equal to 10 micrometers, or less than or equal to 5 micrometers in the array plane. Although the illustrated example shows rectangular LEDs or pcLEDs arranged in a symmetric matrix, the LEDs or pcLEDs and the array can have any suitable shape or arrangement and do not all need to have the same shape or size. For example, the LEDs or pcLEDs located in the central portion of the array may be larger than the LEDs or pcLEDs located in the peripheral portion of the array. Alternatively, the LEDs or pcLEDs located in the central portion of the array can be smaller than the LEDs or pcLEDs located in the peripheral portion of the array.

[0034] Figure 2C A schematic top view of a portion of an LED wafer 210 is shown from which an LED array such as Figure 2A and Figure 2B the LED arrays shown in Figure 2CAn enlarged 3×3 portion of the wafer is also shown. In an exemplary wafer, individual LEDs or pcLEDs 111 having a side length (e.g., width) of W1 are arranged in a square matrix, with the center-to-center distance between adjacent LEDs or pcLEDs being D1 and separated by channels 113 having a width of W2. W1 can be, for example, less than or equal to 1 millimeter (mm), less than or equal to 500 micrometers, less than or equal to 100 micrometers, less than or equal to 50 micrometers, or less than or equal to 10 micrometers. W2 can be, for example, several hundred micrometers, less than or equal to 100 micrometers, less than or equal to 50 micrometers, less than or equal to 10 micrometers, or less than or equal to 5 micrometers. D1 = W1 + W2.

[0035] For example, an array can be formed by cutting the wafer 210 into individual LEDs or pcLEDs and arranging the dies on a substrate. Alternatively, the array can be formed from the entire wafer 210 or by dividing the wafer 210 into smaller LED or pcLED arrays.

[0036] LEDs or pcLEDs having dimensions (e.g., side length) in the array plane less than or equal to about 50 micrometers are generally referred to as microLEDs, and an array of such microLEDs can be referred to as a microLED array.

[0037] In a pcLED array, all pcLEDs can be configured to emit light of substantially the same spectrum. Alternatively, the pcLED array can be a multicolor array, where different pcLEDs in the array can be configured to emit light of different spectra (colors) by employing different phosphor compositions. Similarly, in an array of direct-emitting LEDs (i.e., without wavelength conversion by a phosphor), all LEDs in the array can be configured to emit light of substantially the same spectrum, or the array can be a multicolor array that includes LEDs configured to emit light of different colors.

[0038] Individual LEDs or pcLEDs in the array can be individually operable (addressable) and / or can be operable as part of a group or subset of LEDs or pcLEDs in the array (e.g., adjacent).

[0039] An array of LEDs or pcLEDs, or portions of such an array, may be formed as a segmented monolithic structure, where individual LEDs or pcLEDs are electrically isolated or partially electrically isolated from each other by trenches and / or insulating materials, but the electrically isolated or partially electrically isolated segments remain physically connected to each other through other parts of the semiconductor structure. For example, in such a monolithic structure, the active region and the first semiconductor layer of the first conductivity type (n or p) on one side of the active region may be segmented, and the second unsegmented semiconductor layer of the opposite conductivity type (p or n) is located on the side of the active region opposite to the first semiconductor layer. Then, the second semiconductor layer may physically and electrically connect the segmented structures to each other on one side of the active region, where the segmented structures are otherwise electrically isolated from each other and can thus operate individually as separate LEDs.

[0040] Thus, an array of LEDs or pcLEDs can be or include a monolithic multicolor matrix of individually operable LED or pcLED light emitters. The LEDs or pcLEDs in the monolithic array can be, for example, microLEDs as described above.

[0041] A single individually operable LED or pcLED or a group of adjacent such LEDs or pcLEDs can correspond to a single pixel (picture element) in a display. For example, a group of three adjacent individually operable LEDs or pcLEDs including a red emitter, a blue emitter, and a green emitter can correspond to a single color-tunable pixel in a display.

[0042] As Figures 3A - 3B shown, an array 200 of LEDs or pcLEDs can be mounted, for example, on an electronic board 300 that includes a power and control module 302, a sensor module 304, and an attachment area 306. The power and control module 302 can receive power and control signals from an external source and signals from the sensor module 304, and the power and control module 302 controls the operation of the LEDs / pcLEDs based on these signals. The sensor module 304 can receive signals from any suitable sensor (such as from a temperature or light sensor). Alternatively, the array 200 can be mounted on a separate board (not shown) from the power and control module and the sensor module.

[0043] Each LED or pcLED can optionally be combined or arranged in combination with a phosphor layer positioned adjacent to the LED or pcLED or a lens or other optical element disposed on the phosphor layer of the LED or pcLED. Such optical elements not shown in the figures can be referred to as "primary optical elements". In addition, as Figures 4A - 4B shown, the array 200 (e.g., mounted on the electronic board 300) can be arranged in combination with secondary optical elements (such as waveguides, lenses, or both) for use in the intended application. In Figure 4AIn [the example], the light emitted by the pcLED 100 is collected by the waveguide 402 and directed to the projection lens 404. For example, the projection lens 404 can be a Fresnel lens. Such an arrangement can be suitable for use, for example, in vehicle headlights. In Figure 4B In [another example], the light emitted by the pcLED 100 is collected directly by the projection lens 404 without using an intervening waveguide. This arrangement can be particularly suitable when the LEDs or pcLEDs can be spaced close enough to each other, and can also be used in vehicle headlights and camera flash applications. For example, micro-LED display applications can use an optical arrangement similar to Figures 4A - 4B the optical arrangement depicted in [the example].

[0044] In another example arrangement, a central block of LEDs or pcLEDs in an array can be associated with a single common (shared) optical device, and the edge LEDs or pcLEDs in the array located at the periphery of the central block are each associated with a corresponding individual optical device.

[0045] Generally speaking, depending on the desired application, any suitable optical element arrangement can be used in combination with the LED and pcLED arrays described herein.

[0046] The LED and pcLED arrays as described herein can be used in applications that require or benefit from fine-grained intensity, spatial, and temporal control of light distribution. These applications can include, but are not limited to, precise special patterning of the emitted light from individual LEDs or pcLEDs or from groups (e.g., blocks) of LEDs or pcLEDs. Depending on the application, the emitted light can be spectrally distinct, time-adaptive, and / or environment-responsive. Such an array can provide a pre-programmed light distribution in various intensity, spatial, or temporal patterns. The emitted light can be at least partially based on received sensor data and can be used for optical wireless communication. The associated electronics and optics can be distinct at the individual LED / pcLED, group, or device level.

[0047] An array of individually operable LEDs or pcLEDs can be used in combination with a lens, a lens system, or other optical device or optical system (e.g., as described above) to provide illumination suitable for a particular purpose. For example, in operation, such an adaptive lighting system can provide illumination that changes color and / or intensity across an illuminated scene or object and / or is aimed in a desired direction. Focusing or steering of the light beam emitted by the LED or pcLED array can be performed electronically by activating the LEDs or pcLEDs in groups of different sizes or activating the LEDs or pcLEDs sequentially to allow dynamic adjustment of the beam shape and / or direction without moving the optical device or changing the focus of the lens in the lighting device. The controller can be configured to receive data indicating the position and color characteristics of an object or person in the scene and control the LEDs or pcLEDs in the array based on this information to provide illumination suitable for the scene. Such data can be provided by, for example, an image sensor, an optical (e.g., laser scanning) sensor, or a non-optical (e.g., millimeter wave radar) sensor. Such adaptive lighting is becoming increasingly important for motor vehicles (e.g., adaptive headlights), mobile device cameras (e.g., adaptive flash), and AR, VR, and MR applications (such as the applications described below).

[0048] Figure 5 FIG. schematically illustrates an example camera flash system 500 that includes an LED or pcLED array and an optical (e.g., lens) system 502, which can be or include the adaptive lighting system described above, in which the LEDs or pcLEDs in the array can be individually operable or group operable. In operation of the camera flash system, the illumination from some or all of the LEDs or pcLEDs in the array and the optical system 502 can be adjusted (deactivated, operated at full intensity, or operated at an intermediate intensity). As described above, the array can be a monolithic array or include one or more monolithic arrays. As described above, the array can be a micro-LED array.

[0049] The flash system 500 also includes an LED driver 506 controlled by a controller 504 (such as a microprocessor). The controller 504 can also be coupled to a camera 507 and a sensor 508 and operates according to instructions and profiles stored in a memory 510. The camera 507 and the LED or pcLED array and the lens system 502 can be controlled by the controller 504 to, for example, match the illumination provided by the system 502 (i.e., the field of view of the lighting system) to the field of view of the camera 507 or to otherwise adapt the illumination provided by the system 502 to the scene observed by the camera as described above. The sensor 508 can include, for example, a position sensor (e.g., a gyroscope and / or an accelerometer) and / or other sensors that can be used to determine the position and orientation of the system 500.

[0050] Analysis of certain motor vehicle system optics shows that shaped surface brightness with a peak at the center or a gradient from one side to the other has the best system optical efficiency, which is indicated by the system optical figure of merit (FOM). For a high beam optical system with a total internal reflection (TIR) lens and a low beam reflector optical system, there may be different optimal spatial brightnesses. Regardless of whether the beam is high beam or low beam, both systems can employ a multi-chip package.

[0051] A multi-chip package can provide shaped brightness. To achieve this, several dies each having its own shaped brightness can be attached to a tile. These dies may not necessarily be segmented, but can provide smooth brightness with no strong discontinuities between different regions. A die with shaped brightness has regions of peak brightness and regions of less than peak brightness. For example, each die can have its own brightness gradient. In a multi-chip package, the peak brightnesses of the dies can be aligned, for example, on the same side of the tile to provide a gradient of the overall brightness of the package. If possible, the peak brightnesses are aligned on the side of the package with less material: OSC, tile, electrical contact pads, etc. This configuration can provide the highest contrast and maximize the FOM gain.

[0052] Figure 6 A multi-chip package with dies having a shaped brightness distribution is shown. For example, the package can have a 1×3 die array, that is, it is arranged in a single row with three columns. Various other arrangements are possible, such as an X by Y array, where X is a number from 1 to 10 and Y is the same or a different number from 1 to 10.

[0053] Package 600 includes a plurality of dies 610 and at least one tile contact pad 629. In an embodiment of the present invention, package 600 includes three or more dies 610 and two tile contact pads 629. Dies 610 can be arranged adjacent to each other with as low a gap as possible between the dies to maximize brightness. Similarly, for better contrast, the distance D0 of the dies from the tile edge can be as small as possible. The two tile contact pads 629 can be electrically connected to the dies through Cu vias in the case of a ceramic tile and can be electrically connected to the dies through a lead frame in the case of an FR4 tile. Since the dies are connected in series, one tile contact pad 629 is connected to the anode of the first die and the other is connected to the cathode of the last die. In Figure 6In [the figure], two die contact pads 629 are shown on top of a die 640 (e.g., substrate 640). However, the die contact pads 629 can be on the bottom of the die 640, and their area in the plan view can overlap with the die 610 (from the opposite side of the die 640 on which the die 610 is disposed). In this case, there can be a through-via in the dielectric material of the die 640 that bridges the die contact pads 629 and the die 610.

[0054] The dies 610 can each individually have a shaped luminance. A die with a shaped luminance distribution is defined as a die in which the luminance averaged over an area equal to at least 10% of the entire light-emitting area deviates from the average luminance averaged over the entire light-emitting area by 20% or more. This area can be the peak luminance area. For example, each die can have a luminance gradient, having a peak luminance area and a lower luminance area. The gradient can be of various types. One type of gradient is arranged such that the lowest luminance is at the four edges of the die, gradually increasing to the center where there is a peak luminance. Another type of gradient is arranged from the first edge of the die to the opposite edge of the die such that the luminance at the first edge is the peak luminance and the luminance at the opposite edge is the lowest luminance in the die, where the luminance continuously decreases from the first edge to the opposite edge. The peak luminance area can have a length or width extending in a horizontal direction parallel to the upper edge of the die 610 (the horizontal direction can extend along the length (the longest dimension) of the package 600, and the horizontal direction is perpendicular to the vertical direction). These peak luminance areas can include the upper edge of the die 610 (which is closest to Figure 6 the top of the page). In this arrangement, the dies can be disposed on the die such that their peak luminance edges are all horizontally aligned with each other and extend in the same direction, which means that their lowest luminance edges on the opposite sides of the die 610 are also aligned with each other. This provides a package 600 with a shaped luminance that is brighter towards one edge than the other. In another arrangement, the dies align their lowest luminance edges and are adjacent to the upper edge of the package 600. However, these arrangements are not necessary, and the dies can have their peak luminance edges not aligned and facing different directions from each other. For ease of understanding, unless otherwise stated, the following description will assume the case where the dies 610 align their peak luminance on Figure 6 the upper edges of the dies 610 with each other.

[0055] The die 610 on the tile can be electrically connected in series with each other. The bonding pads 620 can be used to connect the dies. These bonding pads 620 can include multiple layers, some of which are in direct contact with the die and some of which are not in direct contact with the die. In an embodiment of the present invention, the bonding pad 620 can include an under bump metallization (UBM) having negative ("n") or positive ("p") polarity regions (nUBM and pUBM respectively) that are both in direct contact with the die 610, a top metalization layer of the tile in direct contact with the tile, and a solder layer that connects the nUBM / pUBM to the top metalization layer of the tile. The nUBM and pUBM coverage areas on the die may have different areas, such that one is larger than the other. The nUBM / pUBM can be square, rectangular, or other shapes. It may have sharp corners, beveled corners, or curved corners.

[0056] The asymmetric regions of the nUBM and pUBM may be because in the case of a die with non-uniform surface brightness during shaping, a large bonding pad is required under the peak current region (e.g., peak brightness region) to maximize heat dissipation of the tile and reduce the thermal resistance (Rth).

[0057] In Figure 7 A possible arrangement of the nUBM 624 and pUBM 626 coverage areas on the die is shown. For example, the peak brightness of the die has a length that extends parallel to the upper edge of the die 610 (the edge closer to Figure 7 the upper edge of the page). P1 represents a possible peak brightness region, which can be smaller or larger depending on specific brightness requirements. The peak brightness region can be a rectangular shape having a length that extends in the horizontal direction. This arrangement can be referred to as a vertical arrangement because the lengths of the nUBM and pUBM are perpendicular to the length of the peak brightness that extends along the upper edge of the die, perpendicular to the length of the tile 610, and / or perpendicular to the direction along which the die 610 is arranged on the tile.

[0058] The nUBM 624 and pUBM 626 on a specific die 610 have a gap 613 between them such that they are not in direct physical contact with each other. This gap can be filled with silicone resin or air. In the vertical arrangement, the peak brightness that extends along or near the upper edge passes through the gap between the nUBM / pUBM. A hot spot 616 may appear in this gap below the peak brightness / current region because heat dissipation at this gap is not optimal.

[0059] To prevent this hot spot, the nUBM 624 and pUBM 626 can be arranged in a horizontal arrangement. In Figure 8Embodiments of the present invention for preventing hot spots are shown. The length of the nUBM / pUBM is parallel to the peak brightness extending along the upper edge or the direction of the upper edge, perpendicular to the length of the tile 610, and / or perpendicular to the direction along which the die 610 is arranged on the tile. Here, the nUBM 624 is shown as the larger of the two pads, but alternatively, in Figure 8 the larger pad shown may be the pUBM, and instead the smaller pad may be the nUBM. In other words, the pUBM 626 and the nUBM 624 may be interchanged with each other in any description of any embodiment of the present invention, as described in the following drawings or text (while maintaining the same area / dimensions of the depicted elements).

[0060] The peak brightness region P1 does not overlap with the smaller pad (in this case, the pUBM 626), and only overlaps with the larger of the pads (in this case, the nUBM 624). (Overlap may mean that when observing the surface of the plane of the package 600, some parts of the regions of the respective elements intersect; non - overlap means that no parts of their regions intersect). For example, the nUBM may overlap with 80 - 100% (such as from 80 - 95%) of the peak brightness region P1; this overlap by the nUBM may be over a continuous, unbroken region. Similarly, the peak brightness region does not overlap with the gap 613 between the nUBM and the pUBM, thus preventing hot spots. The gap 613 also does not overlap with the peak brightness region P1. Advantageously, there is now uniform or more uniform heat dissipation under the peak brightness region of the die.

[0061] If the electrical pads 620 are arranged on the tile as Figure 7 shown, the n - region and the p - region of the electrical pads of one die will be adjacent to the regions of the electrical pads of opposite polarities of an adjacent die. In the embodiments of the present invention for preventing hot spots as shown in Figure 8 and Figure 9a not only the thermal requirements are considered, but also the optical requirement of desiring to align the peak brightness on the same side of the package is considered. The regions of the electrical pads 620 with the same polarity are now aligned along the horizontal direction (see Figure 9a the n - region and the p - region it has). In order to connect the dies 610 in series, it is necessary to electrically connect these pads of opposite polarities.

[0062] Figure 10Shows a cross-section of FIG. 9 when viewed from the lower edge of the package 600 in FIG. 9 (the edge closest to the bottom of the page in FIG. 9). From this view, the larger pad nUBM 624 is not visible, and only the smaller pad pUBM 626 is visible. The die 610 is disposed on the pUBM 626 (and nUBM 624), and the pUBM / nUBM is disposed on the solder 628. The solder 628 is disposed between and in direct physical contact with: the pUBM / nUBM and the n die top metallization layer 630 (not visible) and the p die top metallization layer 631. The n / p die top metallization layers 630 / 631 are in direct contact with the die 640 and may share polarity with the corresponding nUBM / pUBM under which they are disposed. The die 640 may be a printed circuit board (PCB) or any other suitable substrate. The die 640 is disposed on the thermal interface and / or electrode layer 643, which is disposed on the heat sink 646.

[0063] The dies 610 are electrically connected to each other through the nUBM 624 / pUBM 626, the solder 628, the n / p die top metallization layers 630 / 631, and the connection 632 between the die top metallization layers 630. These connections can be made in various ways, including by soldering the connection from the die top metallization layer 630 under one die to the die top metallization layer 630 under an adjacent die. Due to the horizontal arrangement of the nUBM / pUBM and the corresponding die top metallization layers, the connection 632 may not be straight horizontal from one die top metallization layer to another, but rather a diagonal metallization from the upper nUBM624 of an adjacent die to the lower pUBM 626 (shown in Figure 9b ). The connection 632 can be diagonal in the sense that there are both non-zero horizontal and vertical components in its extending direction. For example, it can form an angle of 10 - 80 degrees, such as 30 - 60 degrees, such as 45 degrees, with respect to the upper edge of the die from which it extends. The gap 613 between the nUBM 624 and the pUBM 626 can extend in a first horizontal direction. In this case, the diagonal connection 632 can extend vertically to intersect the first horizontal direction.

[0064] The connection 632 between the n / p die top metallization layers 630 / 631 is shown in Figure 12 and Figure 9b is shown. Figure 12Also shown is a top view or plan view of the tile top metallization layers 630 under each die. Similar to the nUBM 624 / pUBM 626 layers, there are two tile top metallization layers 630 / 631 of different polarities disposed under each die 610 (i.e., partially or fully overlapping each die 610), as indicated by the "n" and "p" symbols. One or both of the tile top metallization layers 630 / 631 may extend beyond the die, as Figure 9b shown in (for ease of understanding, Figure 9b the die 610 is shown as transparent). The n tile top metallization layer 630 of one die is electrically and physically connected to the p tile top metallization layer 631 of another die. The connection 632 therebetween may be a diagonal metallization as described above, i.e., from one tile top metallization layer to a tile top metallization layer of opposite polarity in an adjacent die. One way to define the diagonal aspect is that when the n tile top metallization layer 630 and the p tile top metallization layer 631 of one die are horizontally aligned with the n tile top metallization layer 630 and the p tile top metallization layer 631 of another die respectively, the connection extends from the upper n tile top metallization layer 630 of one die to the lower p tile top metallization layer 631 of another die. Horizontal alignment may mean that the upper edges of the tile top metallization layers are on the same horizontal line with each other, and / or their lower edges are on the same horizontal line with each other, or simply that a horizontal line drawn through any part (such as an edge) of them intersects any area of both of them. The connection 632 may be disposed on the surface of the tile 640, or it may be embedded in the tile 640, so that it is partially or fully under the tile top metallization layer. Figure 10 The previous embodiment is shown.

[0065] Figure 9b and Figure 12 shown that the n / p tile top metallization layers 630 / 631 of one die are spaced apart from each other and do not directly contact. For each outer die (the die on the outer edge of the array), at least one of the n / p tile top metallization layers 630 / 631 is not physically connected to any metallization connection, while the other is physically connected to any metallization connection. For each inner die (the die having two adjacent dies), both of the n / p tile top metallization layers 630 / 631 are physically connected to the connection 632. Figure 11 Shown is another cross-section similar to Figure 10 except viewed from the side of the side edge (the edge connecting the lower edge and the upper edge of the package 600) of the package 600 in FIG. 9. Here, it is clear that the n / p tile metallization layers 630 / 631 of one die are electrically connected to each other through the solder 628, the nUBM 624 / pUBM 626, and the die 610.

[0066] The advantages of the above embodiments of the present invention are that they can prevent hot spots from forming under the area of the die with peak brightness, because the gap 613 between the nUBM 624 and the pUBM 626 is not provided under this peak brightness area. As a result, there is uniform heat dissipation under this area. However, since the dies 610 need to be close to each other for brightness purposes, with this configuration, when the welding diagonal connection is made, there may be a risk of solder paste overflow and short circuit generation. Considering the manufacturing tolerance, it may be necessary to increase the gap between the dies. However, increasing the spacing may reduce the brightness of the entire multi-die area and thus reduce the system optical FOM.

[0067] Embodiments of the present invention connect several dies to the horizontal metal pads without increasing the gap between the dies or using solder with an irregular shape after reflow soldering. This method uses the reversed pad polarity between adjacent pads to alternately place two die designs on the tile.

[0068] By alternately placing two different die designs, an electrical series connection of the dies is obtained. These two die designs (die #1 and die #2) have the same orientation of pads with asymmetric sizes, and pads of the same size have different polarities. For example, die #1 has the largest pad for the n contact, and die #2 has the largest pad for the p contact. Figure 13 Views of these two die designs are shown. In fact, the reversal of the metal pad polarity is obtained by modifying the opening of the dielectric layer, which includes the insulation 665 described further below. Advantageously, the change in the layout mask is minimal because it only involves the dielectric layer. Die #1 has a large horizontal n pad (under the peak current area) and a small horizontal p pad. On the other hand, die #2 has a large horizontal p pad (under the peak current area) and a small horizontal n pad. Then, die #1 and die #2 can be serially connected on the tile by alternately arranging die #1 and die #2 without the risk of short circuit. With this specific arrangement, each pad of a given die is aligned with a pad of a different polarity, thus allowing for easy serial connection on the tile.

[0069] Figure 13 and Figure 14Shows an alternating polarity design (for informational purposes, die 610 is shown transparent so that the top die metallization layer 630 is visible). The n top die metallization layer 630 of one die is electrically and physically connected to the p top die metallization layer 631 of another die. This connection 634 connects the n top die metallization layer and the p top die metallization layers 630 and 631 of the two dies. The connection 634 can have the same width (measured in the vertical direction) as the n top die metallization layer and the p top die metallization layer 630 to which it is connected. The n top die metallization layer, the p top die metallization layer 630 and 631, and the connection 634 can all be continuous monolithic pieces, and / or can be welded together. The areas considered to be the n top die metallization or the p top die metallization monolithic pieces can be the areas overlapping with die 610, and / or the areas not horizontally between adjacent dies 610 (but extending across the die without overlapping the die). In contrast, the area considered to be the connection 634 can be the area horizontally between adjacent dies 610. The connected n top die metallization layer and p top die metallization layers 630 and 631 can form a rectangle or a square together with the connection 634. In other words, the connection 634 is not diagonal, and it has a completely horizontal upper edge and lower edge that do not form any angle with respect to the upper or lower edge of die 610.

[0070] In Figure 13 the embodiment of the present invention shown, the outer dies in the die array of the package 600 have at least two in the top die metallization layer 630 that are not connected to the top die metallization layer 630 of the opposite polarity through the connection 634. This is because these top die metallization layers are the starting and ending points of the series connection for powering die 610, so they themselves do not need to be connected to the top die metallization layer of another die. Instead, they can be connected to two die contact pads 629, which in turn are connected to the drive circuit for driving the die. For example, for these outer dies, there may be only one connection 634 bridging their top die metallization layers, such that one of the n top die metallization layer 630 and the p top die metallization layer 631 has the connection 634, and the other does not have the connection 634, and instead is spaced apart from the connected n / p top die metallization layers 630 / 631 of the same die, and is spaced apart from both the n top die metallization layer 630 and the p top die metallization layer 631 of the adjacent die. At least two top die metallization layers without the connection 634 in the die array can have opposite polarities, and they can be arranged on opposite sides of the arrangement of die 610. For example, as Figure 13 and Figure 14As shown, the n - tile top metallization layer 630 without connection 634 is on the upper - left of the die array, and the p - tile top metallization layer 631 without connection 634 is on the lower - left.

[0071] Figure 15 A cross - section of the package 600 depicted in Figure 13 is shown looking down from the lower edge of the package. The connection 634 on the left side (which is demarcated by a dashed line) is closer to the observer than the connection 634 on the right side (which is depicted by a solid line indicating the edge of the closer tile top metallization layer). Figure 11 The package 600 can also be depicted looking down from a side edge connecting the upper and lower edges of the package 600, except that the diagonal connection 632 depicted by a dashed line does not exist in this embodiment.

[0072] Although Figures 13 - 15 the package 600 with a 1×3 die array is shown, the concept of an alternating die design can be generalized to larger or smaller 1×N arrays, where N ranges from 2 to 12, such as from 4 to 8. Figure 16 and Figure 17 illustrate such a generalization (in this case a 1×5 die array) with depictions of die 610 and n / p - tile top metallization layers 630 / 631 respectively.

[0073] Figure 18 A cross - section of die 610 with connections of nUBM 624 and pUBM 626 is shown in more detail. Die 610 includes an epitaxial layer having an nGaN layer 670, quantum wells 675, and a pGaN layer 673. The nUBM624 is electrically connected to the nGaN layer 670 through an n - bonding layer 660, and the n - bonding layer 660 forms an n - via passing through the pGaN layer 673, and this n - via is physically spaced from the pGaN layer 673 by an insulator 665. The insulator 665 can be a dielectric material. The pUBM 626 is electrically connected to the pGaN layer through a p - bonding layer 663. The p - bonding layer 663 is in direct contact with both: the pUBM 626; and the pGaN layer 673 or a mirror layer 680 (e.g., made of silver) that is in electrical contact and / or direct physical contact with the pGaN layer 673. The p - bonding layer 663 is physically spaced from the n - bonding layer 660 by the insulator 665 such that they are not in direct physical contact. Figure 15 It is shown that the pUBM 626 has a larger area than the nUBM 624, but as described above, this size relationship can be reversed as desired as long as the larger pad covers the peak brightness region. Thus, the nUBM and the n - tile top metallization layer are electrically connected to the nGaN layer and the pUBM and the p - tile top metallization layer are electrically connected to the pGaN layer, and vice versa.

[0074] Disposed on the die 610 may be a substrate 658 (e.g., a sapphire wafer or an undoped semiconductor material) that is bonded to the phosphor layer 655 through an adhesive layer 650. The die having an adjustable light-emitting area may be a VTF (Vertical Thin Film or Embedded Contact Vertical Thin Film), a CSP (Sapphire Still on Epitaxy), or a TFFC (Thin Film Flip Chip). The die according to the present invention may be constructed using standard processes. The specific steps consist of a paired die design that obtains pads with opposite polarities. The inversion of the pad polarity can be simply obtained by changing the layout of the dielectric layer including the insulation 655. All other layers may remain the same.

[0075] This disclosure is illustrative and not restrictive. Given this disclosure, further modifications will be apparent to those skilled in the art and are intended to fall within the scope of the appended claims.

Claims

1. A light-emitting diode array, comprising: a substrate; a plurality of die disposed on the substrate, each die including a light-emitting surface and configured to emit light having an average luminance greater than an average luminance of the light-emitting surface in a peak luminance region of the light-emitting surface, the die including a first die and a second die adjacent to each other; and a plurality of solder pads disposed under respective ones of the die, each solder pad including: a first under-bump metallization (fUBM) having a first area and overlapping the peak luminance region of the respective die in the die; a second under-bump metallization (sUBM) having a second area smaller than the first area, and a gap spacing the fUBM and the sUBM, which does not overlap the peak luminance region of the light-emitting surface.

2. The light-emitting diode array according to claim 1, wherein each solder pad further includes: a first metallization layer disposed under the fUBM and arranged to have the same polarity as the fUBM; a second metallization layer disposed under the sUBM, the second metallization layer being spaced apart from the first metallization layer and arranged to have a polarity opposite to that of the first metallization layer; and a connection connecting either the first metallization layer or the second metallization layer of the first die to any one of the first metallization layer or the second metallization layer of the second die having an opposite polarity, the second die being adjacent to the first die.

3. The light-emitting diode array according to claim 2, wherein the first metallization layer and the second metallization layer are in direct contact with the substrate.

4. The light-emitting diode array according to claim 1, wherein the die are at least arranged in a row extending in a horizontal direction perpendicular to a vertical direction, and the fUBMs of adjacent die in the die are horizontally aligned with each other and have opposite polarities to each other, and the sUBMs of adjacent die in the die are horizontally aligned with each other and have opposite polarities to each other.

5. The light-emitting diode array according to claim 4, wherein each solder pad further includes: a first metallization layer disposed under the fUBM and arranged to have the same polarity as the fUBM; a second metallization layer disposed under the sUBM, the second metallization layer being spaced apart from the first metallization layer and arranged to have a polarity opposite to that of the first metallization layer; and a connection connecting the second metallization layer of the first die to the second metallization layer of the second die, the second die being adjacent to the first die; and wherein the first metallization layers of adjacent die in the die are horizontally aligned with each other and have opposite polarities to each other, and the second metallization layers of adjacent die in the die are horizontally aligned with each other and have opposite polarities to each other.

6. The light-emitting diode array according to claim 2, wherein each solder pad further includes solder disposed between the fUBM and the first metallization layer.

7. The light-emitting diode array according to claim 2, wherein at least one of the first metallization layer and the second metallization layer extends beyond the die under which it is disposed.

8. The light-emitting diode array according to claim 2, wherein the connection is disposed between the first die and the second die without overlapping the first die or the second die.

9. The light-emitting diode array according to claim 5, wherein the width of the connection in the vertical direction is the same as the corresponding width of the second metallization layer to which the connection is connected in the vertical direction.

10. The light-emitting diode array according to claim 4, wherein the first die is only directly adjacent to the second die, and the first metallization layer of the first die is spaced apart from the first metallization layer of the second die, with a second gap therebetween the first die and the second die.

11. The light-emitting diode array according to claim 1, wherein the peak brightness region of the die does not overlap with the sUBM.

12. The light-emitting diode array according to claim 1, wherein the dies are arranged in a 1×X array, where X ranges from 3 to 5.

13. The light-emitting diode array according to claim 1, wherein the size of the peak brightness region is equal to at least 10% of the light-emitting surface, and the average brightness of the larger peak brightness region deviates from the average brightness of the light-emitting surface by 20% or more.

14. The light-emitting diode array according to claim 1, wherein the peak brightness regions of the dies are horizontally aligned with each other.

15. The light-emitting diode array according to claim 1, wherein the fUBM of the first die is arranged to have a negative polarity, and the sUBM of the first die is arranged to have a positive polarity.

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