Peak to average ratio (PAR)-based analog pre-distortion (APD) in front-end modules

Abstract

Analog pre-distortion (APD) based on peak to average ratio (PAR) in a front end module (FEM) is disclosed. In one aspect, an FEM acquires PAR measurements and adjusts operating parameters (i.e., APDs) within the FEM to produce a normalized distortion distribution that can simplify digital pre-distortion in a baseband processor (BBP). The PAR measurement may be triggered by various events, such as on a per symbol, per slot, or per frame basis, and may be associated with a change in supply voltage level or a command to change the supply voltage. Providing this APD can improve the operating efficiency of the FEM. Also, providing a normalized distortion distribution can simplify the design requirements of the BBP.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 482,093, filed on Jan. 30, 2023, entitled "PEAK - TO - AVERAGE RATIO (PAR) - BASED ANALOG PREDISTORTION (APD) IN A FRONT - END MODULE", the content of which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology of the present disclosure generally relates to front - end modules, and more particularly to ways of normalizing the distortion distribution of front - end modules in transceivers. Background Art

[0004] In modern society, computing devices are ubiquitous, and more particularly, mobile communication devices are becoming increasingly common. The popularity of these mobile communication devices is driven in part by the many functions currently enabled on such devices. The increase in processing power in such devices means that mobile communication devices have evolved from pure communication tools to complex mobile entertainment centers, thus enhancing the user experience. With the emergence of the various functions available on such devices, the pressure to find ways to increase the bandwidth of data transmission has increased. This pressure has led to evolving wireless standards. Each new wireless standard poses new requirements on the circuitry of wireless transmitters. Such requirements provide room for innovation. Summary of the Invention

[0005] Aspects disclosed in the detailed description include peak - to - average ratio (PAR) - based analog predistortion (APD) in a front - end module (FEM). Specifically, exemplary aspects of the present disclosure contemplate obtaining PAR measurements in the FEM and adjusting operating parameters (i.e., APD) within the FEM to produce a normalized distortion distribution that simplifies digital predistortion (DPD) in a baseband processor (BBP). The PAR measurements can be triggered by various events, such as on a per - symbol, per - time - slot, or per - frame basis, and can be associated with a change in the power supply voltage level or a command to change the power supply voltage. Providing this APD can improve the operating efficiency of the FEM. Similarly, providing a normalized distortion distribution can simplify the design requirements of the BBP.

[0006] In this regard, in one aspect, a method of normalizing the distortion distribution of an FEM is disclosed. The method includes measuring the PAR in the FEM. The method further includes adjusting operating parameters to change the distortion distribution of the FEM.

[0007] In another aspect, a FEM is disclosed. The FEM includes a power amplifier chain having PAR characteristics. The FEM further includes a PAR detector coupled to the power amplifier chain to measure the PAR characteristics. The FEM further includes a control circuit coupled to the PAR detector. The control circuit is configured to adjust the operating parameters of the FEM based on the measurements from the PAR detector.

[0008] In another aspect, a wireless communication device is disclosed. The wireless communication device includes a transmission chain including a FEM. The FEM includes a power amplifier chain having PAR characteristics and a PAR detector coupled to the power amplifier chain to measure the PAR characteristics. The FEM further includes a control circuit coupled to the PAR detector and configured to adjust the operating parameters of the FEM based on the measurements from the PAR detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Block diagram of a conventional front-end module (FEM) coupled to a baseband processor (BBP) via a radio frequency front-end (RFFE) bus as part of a transmission chain;

[0010] Figure 2 Signal diagram showing the power supply voltage change with time relative to time slots and symbols for various types of power control circuits, and power supply voltage change commands that may appear on the RFFE bus;

[0011] Figure 3 Block diagram of a FEM coupled to a BBP according to an exemplary aspect of the present disclosure, the FEM using information from the RFFE bus to assist in triggering peak-to-average ratio (PAR) measurements in the FEM;

[0012] Figure 4 Block diagram of a FEM having a PAR detector according to an exemplary aspect of the present disclosure, the PAR detector measuring the PAR within the FEM to adjust the operating parameters of the FEM;

[0013] Figure 5 Block diagram of a BBP-FEM pair having a PAR detector according to an exemplary aspect of the present disclosure, the PAR detector measuring the PAR within the FEM to adjust the operating parameters of the FEM;

[0014] Figure 6 Block diagram of a hybrid complementary metal oxide semiconductor (CMOS) bipolar FEM that can implement portions of the present disclosure in different technologies;

[0015] Figure 7 Similar to Figure 6 But with different distributions of aspects of the present disclosure between different technologies;

[0016] Figure 8 Block diagram of a hybrid CMOS bipolar FEM with an integrated PAR detector;

[0017] Figure 9 Block diagram of the PAR detector of the present disclosure in the receiving part of the FEM; and

[0018] Figure 10 For a mobile terminal of an FEM that may include according to the present disclosure Figures 3 to 9 Block diagram. Detailed implementation manners

[0019] The embodiments described below represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will understand the applications of these concepts that are not specifically described herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0020] It will be understood that although terms such as first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish different elements. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] It should be understood that when an element such as a layer, region, or substrate is referred to as "on another element" or "extending onto another element", it may be directly on another element or directly extend onto another element, or there may also be intermediate elements. In contrast, when an element is referred to as "directly on another element" or "directly extending onto another element", there are no intermediate elements. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as "above another element" or "extending above another element", it may be directly above another element or directly extend above another element, or there may also be intermediate elements. In contrast, when an element is referred to as "directly above another element" or "directly extending above another element", there are no intermediate elements. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to another element, or there may be intermediate elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0022] Relative terms such as "below", "above", "upper", "lower", "horizontal", or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientations depicted in the figures.

[0023] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. Additionally, it should be understood that the term "comprising", when used herein, specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0025] Aspects disclosed in the detailed description include analog pre-distortion (APD) based on peak-to-average ratio (PAR) in a front-end module (FEM). Specifically, exemplary aspects of the present disclosure contemplate obtaining PAR measurements in the FEM and adjusting operating parameters (i.e., APD) within the FEM to produce a normalized distortion profile that simplifies digital pre-distortion (DPD) in a baseband processor (BBP). The PAR measurements can be triggered by various events, such as on a per-symbol, per-slot, or per-frame basis, and can be associated with a change in the power supply voltage level or a command to change the power supply voltage. Providing this APD can improve the operating efficiency of the FEM. Similarly, providing the normalized distortion profile can simplify the design requirements of the BBP.

[0026] Prior to addressing the exemplary aspects of the present disclosure, reference Figure 1 is made to a brief overview of a conventional FEM coupled to a BBP, and reference Figure 2 is made to the timing diagrams of existing signals that can be transmitted therebetween on a radio frequency front-end (RFFE) bus to control voltage signals. The exemplary aspects of the present disclosure are discussed below with reference to Figure 3 beginning.

[0027] In this regard, Figure 1Block diagram of transmission chain 100. Transmission chain 100 may include BBP 102 and FEM 104. BBP 102 communicates with FEM 104 via RFFE bus 106. Thus, BBP 102 has a bus interface 108, which may be a digital RFFE interface. FEM 104 may include a bus interface 110 coupled to digital control circuit 112. Digital control circuit 112 may control aspects of power amplifier chain 114. Power amplifier chain 114 may include a bias circuit 116, which may provide a static bias to power amplifier stage 118 within power amplifier chain 114.

[0028] More generally, FEM 104 may include a power management integrated circuit (PMIC) that receives power management signals such as envelope tracking (ET) or average power tracking (APT), and the power management signals set the bias level in such a way as to maintain efficiency by holding the supply voltage at a level suitable for the desired level of the signal to be transmitted.

[0029] A new generation of cellular communications such as fifth-generation - new radio (5G-NR) has introduced more aggressive timing requirements for signal transmission. Consider carrier spacings of 15 to 240 kilohertz (kHz) and symbols as short as 4.46 microseconds (μs). The allocation between transmitted symbols (uplink symbols) and received signals (downlink symbols) may vary and may be changed on a symbol-by-symbol basis, thus forcing rapid stabilization within the system. Also, the uplink modulation may vary from quadrature phase shift keying (QPSK) to 256 quadrature amplitude modulation (QAM).

[0030] Although ET or APT information may be passed from BBP 102 to FEM 104, there is currently no information transfer related to the modulation type between BBP 102 and FEM 104. It should be understood that the PAR of a signal may vary significantly depending on the modulation scheme used. PAR has a fundamental impact on the linearity of the behavior of power amplifier chain 114. Since PAR may affect the compression of power amplifier stage 118, the absence of this communication affects the operation of BBP 102. Specifically, there may be more distortion in power amplifier chain 114, and BBP 102 may have to have more DPD to counteract this non-linear behavior in power amplifier chain 114.

[0031] In Figure 2 The timing diagram 200 better shows what is transmitted between BBP 102 and FEM 104. Specifically, Figure 2Shows power supply voltage (also known as Vcc) change commands for various types of APT systems. In line 202 corresponding to traditional slow APT, there can be two power supply voltage change commands 204A, 204B per frame 206 on the RFFE bus 106. Similarly, in the time slot tracking fast APT line 208, there can be multiple power supply voltage change commands 210(1) to 210(M) per frame 212. This can cause changes in the power supply voltage and power level, as seen by line 214. It should be understood that line 214 is only an example, and the actual changes can vary according to the needs of the wireless system. Whenever the power supply voltage changes, there is a corresponding command 216 on the RFFE bus 106.

[0032] In addition, it should be understood that currently there is no provision to transfer modulation scheme information from the BBP 102 to the FEM 104. Similarly, there is no expectation of PAR information being transmitted from the BBP 102 to the FEM 104.

[0033] Exemplary aspects of the present disclosure contemplate adding a PAR detector in the FEM to detect the PAR characteristics of the power amplifier chain and using the information derived therefrom to change the operating parameters within the FEM to help obtain a normalized distortion distribution of the FEM over multiple frequencies and various modulation types. This normalized distortion distribution allows the BBP to use a smaller set of DPD coefficients, thereby making the overall operation of the BBP simpler (and saving memory space, etc.). The PAR detector can be located at various positions and various adjustments can be made. These variations are explored in the following diagrams.

[0034] In this regard, Figure 3 Is a block diagram of a transmission chain 300 including a BBP 302 and an FEM 304 coupled via an RFFE bus 306. The BBP 302 can include a bus interface 308, a control circuit 310, and a digital signal processor (DSP) 312. Although not shown, the BBP 302 can also include a memory.

[0035] Continuing to refer to Figure 3 , the FEM 304 can include a bus interface 314 coupled to the RFFE bus 306, a power amplifier chain 316, and a PAR detector 318. The bus interface 314 extracts trigger events from the RFFE bus 306, as better explained below, and causes the trigger sensing circuit 320 to enable the PAR detector 318 to measure the PAR in the power amplifier chain 316.

[0036] The RFFE bus 306 is also coupled to a Power Management Integrated Circuit (PMIC) 322. The PMIC 322 may include a bus interface 324 and receive a power supply voltage change command to adjust the power supply voltage provided to the power amplifier chain 316. These power supply voltage change commands may be sent from the BBP 302 to the PMIC 322 via the RFFE bus 306 and may be detected by the bus interface 314 and used as a trigger event to trigger the sensing circuit 320. There is no obvious indication of a signal modulation scheme or an expected PAR value on the RFFE bus 306.

[0037] Figure 4 Provide more details about the FEM 304. Specifically, the FEM 304 may include a trigger extraction circuit 400 coupled to the bus interface 314. The trigger extraction circuit 400 may send commands to the PAR detector 318. Also, the trigger extraction circuit 400 may provide this information to the decoding circuit 402, which may calculate the value of the power supply voltage written to the PMIC 322. The output of the PAR detector 318 may be provided to a comparator 404, which compares the measured value with the calculated power supply voltage. The comparator 404 may be coupled to an APD control circuit 406, which may adjust the operating parameters of the power amplifier chain 316. Additionally, information from the PAR detector 318 may be provided back to the bus interface 314 and sent back via the RFFE bus 306 to an external point (such as the BBP 302) for use as needed or desired.

[0038] Figure 5 Provide more details about the transmission chain 300. The BBP 302 may include a DPD circuit 500 associated with a memory 502 that stores the coefficients of the DPD to be applied. Exemplary aspects of the present disclosure normalize the distortion distribution such that fewer sets of coefficients are needed in the BBP 302. This reduction in the set of DPD coefficients allows for a reduction in the memory size, which may also have the benefit of reducing power consumption.

[0039] Continuing to refer Figure 5 , by way of example, the APD control circuit 406 may adjust a bias circuit 504 that biases one or more power amplifiers in the power amplifier chain 316. Additionally or alternatively, the APD control circuit 406 may tune a load line 506.

[0040] As described above, the PAR detector 318 may be located at various positions within the FEM 304. Figure 6Shows three possible locations. Specifically, the power amplifier chain 316 may include a driver amplifier stage 600 and an output stage 602, with an inter-stage node 604 therebetween. Although not shown, there may be an intermediate amplifier stage located at the inter-stage node 604. The PAR detector 318 may be located at the input node 606 in front of the driver amplifier stage 600, at the inter-stage node 604, or at the output node 608 after the output stage 602. Although not shown, there may be a bias circuit 504 that can control the driver amplifier stage 600 or the output stage 602 or both. If the PAR detector 318 is located at the input node 606, the lower signal level in the power amplifier chain 316 at this time may require a more complex detector circuitry. If the PAR detector 318 is located at the inter-stage node 604, a suitable compromise between signal level and ease of detection can be achieved. If the PAR detector 318 is located at the output node 608, the signal is easy to detect, but there may be compression of the signal, which may adversely affect the PAR estimation. There may be other trade-offs in biasing the driver amplifier stage 600 or the output stage 602.

[0041] Figure 7 Shows a possible implementation in a hybrid complementary metal oxide semiconductor (CMOS) bipolar technology system 700. Specifically, the output stage 602 may be made of bipolar technology such as gallium arsenide (GaAs). The driver amplifier stage 600 and the bias circuits 504A, 504B are located within the CMOS die 702. The PAR detector 318 may also be located in the CMOS die 702. The load line 506 tuning can be bipolar or on a silicon-on-insulator (SoI) die 704.

[0042] Figure 8 More details about the PAR detector 318 are provided, where the PAR detector 318 may include a peak power detector 800 and an average power detector 802. The digital controller 804 may subtract or calculate the PAR based on signals from the peak power detector 800 and the average power detector 802. It should also be noted that the tuning of the load line 506 can be accomplished by switched capacitors.

[0043] It should be noted that although the above discussion has focused on the transmit chain, it should be understood that aspects of the present disclosure may also be applied to a receive chain as Figure 9 shown, where the receive chain 900 may include a low noise amplifier (LNA) 902 with a bias circuit 904. The PAR detector 906 may provide a PAR measurement for setting the bias of the bias circuit 904.

[0044] Refer to Figure 10, the concepts described above can be implemented in various types of user elements 1000, which are such as mobile terminals, smart watches, tablet computers, computers, navigation devices, access points, and similar wireless communication devices that support wireless communications (such as cellular, wireless local area network (WLAN), Bluetooth, and near field communication). The user element 1000 will generally include a control system 1002, a BBP 1004, a transmission circuit system 1006, a receiving circuit system 1008, an antenna switching circuit system 1010, a plurality of antennas 1012, and a user interface circuit system 1014. In a non-limiting example, by way of example, the control system 1002 can be a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). In this regard, the control system 1002 can at least include a microprocessor, an embedded memory circuit, and a communication bus interface. The receiving circuit 1008 receives radio frequency signals from one or more base stations via the antenna 1012 and through the antenna switching circuit 1010. The LNA and filter of the receiving circuit system 1008 cooperate to amplify and remove broadband interference from the received signals for processing. Then, a downconversion and digitization circuit system (not shown) downconverts the filtered received signals to an intermediate or baseband frequency signal, and then digitizes the signals into one or more digital streams using an analog-to-digital converter (ADC).

[0045] The BBP 1004 processes the digitized received signals to extract the information or data bits transmitted in the received signals. This processing generally includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The BBP 1004 is typically implemented in one or more DSPs and ASICs.

[0046] For transmission, the BBP 1004 receives digitized data from the control system 1002 that can represent voice, data, or control information, and the BBP encodes the digitized data for transmission. The encoded data is output to the transmission circuit system 1006, where one or more digital-to-analog converters (DACs) convert the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at one or more desired transmission frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission, and transfers the modulated carrier signal from the antenna switching circuit system 1010 to the antenna 1012. The plurality of antennas 1012 and the repeated transmit circuit 1006 and receive circuit 1008 can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0047] It should also be noted that the operation steps described in any of the exemplary aspects herein are provided for purposes of illustration and discussion. The described operations may be performed in a number of different orders other than the order shown. In addition, the operations described in a single operation step may actually be performed in many different steps. Additionally, one or more operation steps discussed in the exemplary aspects may be combined. It should be understood that it will be readily apparent to those skilled in the art that the operation steps illustrated in the flowcharts are subject to various different modifications. Those skilled in the art will also understand that any of a variety of different technologies and techniques may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0048] A prior description of the present disclosure is provided so that any person skilled in the art can make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the present disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for normalizing the distortion distribution of a front-end module (FEM), comprising: Measuring a peak-to-average ratio (PAR) in the FEM; And Adjusting operating parameters to change the distortion distribution of the FEM.

2. The method according to claim 1, wherein adjusting the operating parameters includes changing the bias of a power amplifier.

3. The method according to claim 1, wherein adjusting the operating parameters includes changing the bias of a plurality of power amplifiers.

4. The method according to claim 1, wherein adjusting the operating parameters includes adjusting load line tuning.

5. The method according to claim 4, wherein adjusting the load line tuning includes using a switched capacitor to adjust the load line tuning.

6. The method according to claim 1, wherein measuring the PAR includes measuring the PAR with a PAR detector positioned between two amplifiers in the FEM.

7. The method according to claim 1, further comprising detecting a trigger event on an external bus coupled to the FEM.

8. The method according to claim 7, wherein detecting the trigger event includes snooping on a radio frequency front-end (RFFE) bus coupled to the FEM.

9. The method according to claim 7, wherein detecting the trigger event includes detecting a power supply voltage change command.

10. The method according to claim 1, further comprising sending PAR information from the FEM to a baseband processor (BBP).

11. A front-end module (FEM), comprising: A power amplifier chain having peak-to-average (PAR) characteristics; A PAR detector coupled to the power amplifier chain to measure the PAR characteristics; And A control circuit coupled to the PAR detector and configured to: Adjust the operating parameters of the FEM based on measurements from the PAR detector.

12. The FEM according to claim 11, wherein the power amplifier chain includes at least two power amplifiers having inter-stage nodes, and the PAR detector is coupled to the inter-stage nodes.

13. The FEM according to claim 11, wherein the power amplifier chain includes a transmit power amplifier chain.

14. The FEM according to claim 11, wherein the power amplifier chain includes a low-noise amplifier (LNA) receive amplifier.

15. The FEM according to claim 11, further comprising a bus interface configured to be coupled to a communication bus, and wherein the control circuit is further configured to snoop on the communication bus through the bus interface.

16. The FEM according to claim 15, wherein the control circuit is further configured to detect a trigger event that triggers detection with the PAR detector by snooping on the communication bus.

17. The FEM according to claim 11, wherein the power amplifier chain includes a bias circuit.

18. The FEM according to claim 17, wherein the control circuit is configured to adjust the operating parameters by adjusting the bias circuit.

19. The FEM according to claim 11, wherein the control circuit is configured to adjust an operating parameter by tuning a load line.

20. A wireless communication device, comprising: a transmission chain including a front-end module (FEM), the front-end module including: a power amplifier chain having peak-to-average ratio (PAR) characteristics; a PAR detector coupled to the power amplifier chain to measure the PAR characteristics; and a control circuit coupled to the PAR detector and configured to: adjust an operating parameter of the FEM based on a measurement from the PAR detector.

Images