Power supply voltage preprocessing circuit

Abstract

The invention discloses a power supply voltage preprocessing circuit which comprises a power supply voltage VDDH, the power supply voltage VDDH is sequentially connected with Zener diodes D1 and D2 and a resistor R0 in series, the source electrode of an NMOS tube MN0 is connected with the Zener diode D0 in series and then grounded, the drain electrode of the NMOS tube MN0 is divided into three paths, one path is connected with the grid electrode of the NMOS tube MN0, the other path is connected with the drain electrode of a PMOS tube MP0, and the other path is connected with the grid electrode of an NMOS tube MN1 and the grid electrode of an NMOS tube MN2; the grid electrode of the PMOS tube MP0 is respectively connected with the grid electrode and the drain electrode of the PMOS tube MP1; the source electrode of the PMOS tube MP1 is connected with a power supply voltage VDDH, and the drain electrode of the PMOS tube MP1 is also connected with the drain electrode of the NMOS tube MN1. According to the circuit, the chip area can be reduced; the chip is low in circuit current consumption in a low-power-consumption mode; the transient response is good, and the output voltage is stable.

Description

Technical Field

[0001] The present invention belongs to the technical field of power supply voltage circuits, and particularly relates to a power supply voltage preprocessing circuit. Background Art

[0002] In the design of some automotive-grade chips, there are often switches between different operating modes of the automotive-grade chips. For example, in the low-power mode and the normal operating mode, in the low-power mode, it is expected that the current consumed by the chip is as small as possible; in the normal operating mode, the operating current of the chip is more than that in the low-power mode. Automotive-grade chips generally operate at 12V or 24V, and the voltage operating range is relatively wide. For chip design, the selection of high-voltage devices often brings a large area consumption. Therefore, automotive-grade chips are more expected to use more low-voltage devices in the internal circuit design under high-voltage power supply to reduce the area consumption of the integrated circuit.

[0003] Chinese Patent 2023108305967 discloses a power supply preprocessing circuit and device, which can make the output voltage range smaller. However, under the low-power requirement, the internal resistance value of this circuit is very large, reaching the megaohm level, which will increase the chip area consumption.

[0004] The low-dropout linear regulator (LDO) is one of the most common structures in the power management circuit. Its main function is to convert the input high voltage into a stable low-voltage power supply and provide good PSR ability and good transient response ability. The traditional LDO design usually includes a bandgap reference circuit, an error amplifier, and a power MOS transistor. The bandgap reference circuit provides a reference voltage that is stable against temperature and power supply changes. The error amplifier compares the output voltage with the reference voltage and adjusts the gate voltage of the power MOS transistor to maintain the stability of the output voltage. However, this design has certain limitations in a high-voltage power supply environment.

[0005] First, the traditional LDO needs to use high-voltage devices to withstand the input voltage of 12V or 24V. The areas of these high-voltage devices are usually large, resulting in a significant increase in the chip area. Second, the bandgap reference circuit and the error amplifier of the LDO need to consume static current, especially in the low-power mode, and it is difficult to significantly reduce this part of the current consumption, which affects the power supply efficiency. Finally, the output voltage of the traditional LDO responds slowly to the transient changes of the load current, which makes the output voltage unstable when the load current fluctuates greatly, affecting the reliability of the system. Summary of the Invention

[0006] The purpose of the present invention is to provide a power supply voltage preprocessing circuit, which can reduce the chip area, the circuit current consumption of the chip is small in the low-power mode; the transient response is good, and the output voltage is stable.

[0007] To achieve the above object, a power supply voltage preprocessing circuit of the present invention includes a power supply voltage VDDH. The power supply voltage VDDH is sequentially connected in series with a Zener diode D1, a Zener diode D2, and a resistor R0. The other end of the resistor R0 is connected to the gate of an NMOS transistor MN0. The source of the NMOS transistor MN0 is connected in series with a Zener diode D0 and then grounded. The drain of the NMOS transistor MN0 is divided into three paths. One path is connected to the gate of the NMOS transistor MN0, one path is connected to the drain of a PMOS transistor MP0, and one path is respectively connected to the gates of an NMOS transistor MN1 and an NMOS transistor MN2. The source of the PMOS transistor MP0 is connected to the power supply voltage VDDH. The gate of the PMOS transistor MP0 is respectively connected to the gate and the drain of a PMOS transistor MP1. The source of the PMOS transistor MP1 is connected to the power supply voltage VDDH. The drain of the PMOS transistor MP1 is also connected to the drain of the NMOS transistor MN1. The source of the NMOS transistor MN1 is divided into two paths. One path is connected to the source of the NMOS transistor MN2, and the other path is further divided into two paths. One path is connected to an output voltage Vout, and the other path is grounded after passing through a low-voltage circuit, where the output voltage Vout is the voltage used by the low-voltage circuit. The drain of the NMOS transistor MN2 is connected to the power supply voltage VDDH.

[0008] As a further scheme of the present invention: A capacitor C0 is connected in parallel at the drain-source terminals of the NMOS transistor MN1. A Zener diode D4 is also connected in series at the gate of the NMOS transistor MN1. The cathode of the Zener diode D4 is respectively connected to the source of the NMOS transistor MN1, one end of a resistor RL, and the cathode of a Zener diode D3. The other end of the resistor RL is grounded. The anode of the Zener diode D3 is grounded. The cathode of the Zener diode D3 is also connected to one end of a capacitor CL. One end of the capacitor CL is also connected to the output voltage Vout. The other end of the capacitor CL is grounded.

[0009] As a further scheme of the present invention: The PMOS transistors MP0 and MP1 form a 1:N current mirror.

[0010] As a further scheme of the present invention: The NMOS transistors MN0, MN1 and the PMOS transistors MP1, MP0 form a positive feedback circuit, and the loop gain of the positive feedback loop is less than 1 in the full frequency band.

[0011] As a further scheme of the present invention: The NMOS transistors MN0, MN1, and MN2 are of the same type of high-voltage LDMOS, that is, the threshold voltages Vth are all the same.

[0012] As a further scheme of the present invention: During normal operation, the output voltage Vout is approximately equal to the breakdown voltage V of the Zener diode D0 BV.ZENER 。

[0013] Compared with the prior art, the output voltage Vout of the present invention is approximately equal to the breakdown voltage V of the Zener diode D0BV.ZENER , it can generate a low - voltage output voltage Vout for on - chip use. The on - chip designed circuit can operate at low voltage, thereby avoiding the large - area use of high - voltage devices across the entire chip, and thus reducing the chip area. In the low - power mode, the power - consumption current of the power - supply voltage pre - processing circuit is in the nA level, and the current consumption is very small. It mainly relies on the loop of PMOS transistors MP0 and MP1. Without many circuit links, it can respond quickly and has good transient response. By utilizing the breakdown characteristic of the Zener diode to provide a stable reference voltage and adjusting the gate voltage of the power MOS transistor through a current - mirror structure, a stable output voltage is achieved. Brief Description of the Drawings

[0014] Figure 1 is the circuit diagram of the power - supply voltage pre - processing circuit of the present invention.

[0015] Figure 2 is the circuit diagram of the power - supply voltage pre - processing circuit of the present invention with a capacitor C0 connected in parallel at the drain - source terminal of NMOS transistor MN1. Detailed Embodiments

[0016] The present invention will be further described below with reference to the accompanying drawings.

[0017] As Figure 1 shown, the power - supply voltage pre - processing circuit includes a power - supply voltage VDDH. The power - supply voltage VDDH is sequentially connected in series with a Zener diode D1, D2, and a resistor R0. The other end of the resistor R0 is connected to the gate of NMOS transistor MN0. The source of NMOS transistor MN0 is connected in series with a Zener diode D0 and then grounded. The drain of NMOS transistor MN0 is divided into three paths. One path is connected to the gate of NMOS transistor MN0, one path is connected to the drain of PMOS transistor MP0, and one path is respectively connected to the gates of NMOS transistor MN1 and NMOS transistor MN2; the source of PMOS transistor MP0 is connected to the power - supply voltage VDDH, and the gate of PMOS transistor MP0 is respectively connected to the gates and the drain of PMOS transistor MP1; the source of PMOS transistor MP1 is connected to the power - supply voltage VDDH, and the drain of PMOS transistor MP1 is also connected to the drain of NMOS transistor MN1; the source of NMOS transistor MN1 is divided into two paths. One path is connected to the source of NMOS transistor MN2, and the other path is further divided into two paths. One path is connected to the output voltage Vout, and the other path is grounded after passing through a low - voltage circuit, where the output voltage Vout is the voltage used by the low - voltage circuit; the drain of NMOS transistor MN2 is connected to the power - supply voltage VDDH.

[0018] As Figure 2As shown, in order to reduce the transconductance current of NMOS transistor MN1 flowing to PMOS transistor MP0 at high frequencies, a capacitor C0 is connected in parallel at the drain and source terminals of NMOS transistor MN1. To facilitate different loads, the addition of this capacitor C0 can reduce the loop gain at high frequencies to ensure that the loop gain is less than 1 across the entire frequency band. A Zener diode D4 is also connected in series at the gate of NMOS transistor MN1. The cathode of Zener diode D4 is connected to the source of NMOS transistor MN1, one end of resistor RL, and the cathode of Zener diode D3. The other end of resistor RL is grounded, the anode of Zener diode D3 is grounded, and the cathode of Zener diode D3 is also connected to one end of capacitor CL. One end of capacitor CL is also connected to output voltage Vout, and the other end of capacitor CL is grounded.

[0019] PMOS transistors MP0 and MP1 form a 1:N current mirror.

[0020] NMOS transistors MN0, MN1 and PMOS transistors MP1, MP0 form a positive feedback circuit, and the loop gain of the positive feedback loop is less than 1 across the entire frequency band.

[0021] NMOS transistors MN0, MN1, and MN2 are of the same type of high-voltage LDMOS, that is, they have the same threshold voltage Vth.

[0022] When operating normally, the gate voltage V of NMOS transistor MN1 G.MN1 is:

[0023] V G.MN1 = V GS.MN0 + V BV.ZENER

[0024] V GS.MN0 is the gate-source voltage of NMOS transistor MN0, and V BV.ZENER is the breakdown voltage of Zener diode D0; the output voltage Vout is:

[0025] V out = V G.MN1 - V GS.MN1

[0026] where V GS.MN1 is the gate-source voltage of NMOS transistor MN1;

[0027] Also, since V GS = V TH + V dsat , where V dsat is the saturation drain-source voltage,

[0028] then:

[0029] V out = V BV.ZENER + V TH.MN0 + V dsat.MN0–(V TH.MN1 +V dsat.MN1 )

[0030] V out =V BV.ZENER +V dsat.MN0 –V dsat.MN1

[0031] Through reasonable circuit design, the value of Vdsat can be reduced as much as possible. Then the output voltage V out is:

[0032] V out ≈V BV.ZENER

[0033] As can be seen from the above formula, the output voltage is relatively stable and will not deviate greatly.

[0034] Next, taking the power supply voltage VDDH = 12V and V GS.MN0 = 0.5V as an example, the performance of the circuit of the present invention will be analyzed.

[0035] I. Power consumption analysis

[0036] (a) The power supply voltage VDDH supplies current to the gate of the NMOS transistor MN1 through the Zener diodes D1, D2 and the resistor R0. The PMOS transistor MP0 current mirror transistor mirrors the current of the PMOS transistor MP1 and supplies current to the gate of the NMOS transistor MN1 at the same time.

[0037] In the low-power mode, the low-voltage circuit consumes very little current. When this part of the power consumption current is controlled by other circuit modules, the PMOS transistors MP0 and MP1 will mirror a part of the current and inject it into the NMOS transistor MN0 and the Zener diode D0. In the low-power mode, the low-voltage circuit is basically in the off state, and the power consumption current is the leakage current, generally nA, that is, the currents of the PMOS transistors MP1 and MP0 will mirror a part of this small current to the NMOS transistor MN0 and the Zener diode D0. The nA-level current can be ignored.

[0038] (b) Another path of current comes from the Zener diodes D1, D2 and the resistor R0. If V BV.ZENER = 5V, then when working at 12V high voltage, the gate voltage of the NMOS transistor MN1 is: V BV.ZENER +V GS.MN0 . The difference between the power supply voltage VDDH and the gate voltage of the NMOS transistor MN1 is 12V (VDDH) - 5V (V BV.ZENER ) - 0.5V (V GS.MN0 ) = 6.5V. This voltage is not enough to break down the Zener diodes D1 and D2, and it can be considered that the Zener diodes D1 and D2 are resistors with extremely large impedance at this time.

[0039] The resistance R0 can be reduced to the KΩ level to suppress the current in the Zener diode D1 and D2 paths under all PVT conditions. This is much less than the megaohm-level resistance in the structure of the background technology patent 2023108305967 and can save a part of the area. Theoretically, the area overhead of the Zener diode is much smaller than that of the megaohm-level resistance. If it is necessary to save another part of the resistance area, a Zener diode is connected in series based on the Zener diode D0, and the consumed resistance will be further reduced.

[0040] Therefore, in the low-power mode, the current in the circuit of the present invention can be ignored, meeting the low-power requirement.

[0041] II. Transient analysis

[0042] (a) In the low-power mode, the PMOS transistors MP0 and MP1 mirror a very small part of the current and inject it into the NMOS transistors MN0 and the Zener diode D0. In the normal operating mode, since the low-voltage circuit uses more current, the current injected into the NMOS transistor MN0 and the Zener diode D1 is also more. Even if the voltage at the output voltage Vout terminal drops rapidly, causing the gate voltage of the NMOS transistor MN1 to drop, there will still be more μA-level current to supplement the current to the gate compared to the nA-level circuit, thereby stabilizing the gate voltage of the NMOS transistor MN1.

[0043] (b) Further analysis shows that if the load is very heavy and a large current that changes rapidly is required. Then, the PMOS transistors MP0 and MP1 mirror a part of the current and inject it into the NMOS transistor MN0 and the Zener diode D0, further raising the gate voltage of the NMOS transistor MN1. That is to say, for different current loads, the circuit can provide a very stable voltage for use.

[0044] (c) When the output voltage Vout instantaneously drops by a large current, the source voltages of the NMOS transistors MN1 and MN2 are pulled down, and the gate voltages are also pulled down by crosstalk, but to a lesser extent. Consequently, the gate-source voltage V of the NMOS transistors MN1 and MN2 GS increases, the current flowing through the PMOS transistor MP1 increases, and the PMOS transistor MP0 mirrors more current and injects it into the NMOS transistor MN0 and the Zener diode D0, further raising the gate voltage of the NMOS transistor MN1 to offset the voltage drop caused by the large instantaneous pull-down current noise at the output voltage Vout terminal.

[0045] (d) The improvement of the transient response mainly relies on the PMOS transistors MP0 and MP1. This loop is not complex and does not have many circuit links, so it can respond quickly.

[0046] Therefore, in both the low-power mode and the normal operating mode, the circuit of the present invention can achieve good transient response.

[0047] III. Circuit startup analysis

[0048] (a) The PMOS transistors MP0 and MP1 and the NMOS transistor MN1 form a positive feedback loop. When the circuit starts up, when the gate voltage of the NMOS transistor MN1 exceeds the threshold voltage V th , the positive feedback of the PMOS transistors MP0 and MP1 starts, and the circuit can quickly raise the gate voltages of the NMOS transistors MN1 and MN2. It should be emphasized that when designing the circuit, it is necessary to ensure that the loop gain of this positive feedback loop is less than 1 in the full frequency band.

[0049] (b) When the power supply voltage VDDH is rising, if it is a fast power-on, the Zener diode D0 is quickly broken down, then the gate voltages of the NMOS transistors MN1 and MN2 reach the expected voltages, and the circuit startup is completed.

[0050] When the power supply voltage VDDH rises slowly, before the Zener diode D0 is broken down, the Zener diodes D1 and D2 are equivalent to two very large resistors, which divide the power supply voltage VDDH. The gate voltages of the NMOS transistors MN1 and MN0 also have voltages, which does not affect the slow startup.

Claims

1. A power supply voltage preprocessing circuit, characterized in that, It includes a power supply voltage VDDH, where the power supply voltage VDDH is successively connected in series with a Zener diode D1, a Zener diode D2, and a resistor R0. The other end of the resistor R0 is connected to the gate of an NMOS transistor MN0. The source of the NMOS transistor MN0 is connected in series with a Zener diode D0 and then grounded. The drain of the NMOS transistor MN0 is divided into three paths. One path is connected to the gate of the NMOS transistor MN0, one path is connected to the drain of a PMOS transistor MP0, and one path is respectively connected to the gates of an NMOS transistor MN1 and an NMOS transistor MN2. The source of the PMOS transistor MP0 is connected to the power supply voltage VDDH, and the gate of the PMOS transistor MP0 is respectively connected to the gate and the drain of a PMOS transistor MP1. The source of the PMOS transistor MP1 is connected to the power supply voltage VDDH, and the drain of the PMOS transistor MP1 is also connected to the drain of the NMOS transistor MN1. The source of the NMOS transistor MN1 is divided into two paths. One path is connected to the source of the NMOS transistor MN2, and the other path is further divided into two paths. One path is connected to an output voltage Vout, and the other path is grounded after passing through a low-voltage circuit, where the output voltage Vout is the voltage used by the low-voltage circuit. The drain of the NMOS transistor MN2 is connected to the power supply voltage VDDH.

2. The power supply voltage preprocessing circuit according to claim 1, characterized in that A capacitor C0 is connected in parallel at the drain-source terminals of the NMOS transistor MN1. The gate of the NMOS transistor MN1 is also connected in series with a Zener diode D4. The cathode of the Zener diode D4 is respectively connected to the source of the NMOS transistor MN1, one end of a resistor RL, and the cathode of a Zener diode D3. The other end of the resistor RL is grounded. The anode of the Zener diode D3 is grounded. The cathode of the Zener diode D3 is also connected to one end of a capacitor CL. One end of the capacitor CL is also connected to the output voltage Vout, and the other end of the capacitor CL is grounded.

3. The power supply voltage preprocessing circuit according to claim 1 or 2, characterized in that, The PMOS transistors MP0 and MP1 form a 1:N current mirror.

4. A power supply voltage preprocessing circuit according to claim 1 or 2, characterized in that The NMOS transistors MN0, MN1 and the PMOS transistors MP1, MP0 form a positive feedback circuit, and the loop gain of the positive feedback loop is less than 1 in the full frequency band.

5. A power supply voltage preprocessing circuit according to claim 1, characterized in that, The NMOS transistors MN0, MN1, and MN2 are of the same type of high-voltage LDMOS, that is, the threshold voltages Vth are all the same.

6. The power supply voltage preprocessing circuit according to claim 1, wherein When working normally, the output voltage Vout is approximately equal to the breakdown voltage V of the Zener diode D0 BV.ZENER .

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