Storage system, controller, host, and operating method

Abstract

The embodiment of the invention discloses a storage system, a controller, a host and an operation method, and belongs to the technical field of storage. In the storage system, a first interface is configured on a host, a second interface is configured on a controller, and the controller exchanges temporary verification data with the host through the second interface and the first interface when writing data into a memory. Compared with temporary verification data exchange between the controller and the memory, on one hand, the overhead of the memory can be reduced, so that the OP of the memory is improved; on the other hand, the IO bandwidth between the controller and the memory can be saved, so that the performance of the controller and the memory is improved; on the other hand, the requirement of the controller for cache spaces such as the SRAM can be reduced, and the cost of the SRAM on the controller is correspondingly reduced; and on the other hand, RAID protection can be carried out on the write-in data in the host write-in scene, and RAID protection can also be carried out on the write-in data in the garbage collection scene.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of storage technology, and particularly to a storage system, a controller, a host, and an operation method. Background Art

[0002] When a controller writes data to a memory such as 3D NAND (NAND gate), it also generates check data for the data, so that when an error occurs in reading the data subsequently, the data can be recovered based on the check data. Summary of the Invention

[0003] Embodiments of the present application provide a storage system, a controller, a host, and an operation method, which can improve the performance of the memory. The technical solutions are as follows:

[0004] In a first aspect, a storage system is provided. The storage system includes a host, a controller, and a memory. The host includes a first interface, the controller includes a second interface, the memory includes a plurality of storage planes, and each storage plane in the plurality of storage planes includes a plurality of word lines numbered according to the same rule. Each word line in the plurality of word lines is coupled to a plurality of memory strings.

[0005] The controller is configured to:

[0006] Obtain target write data, where the target write data includes write data corresponding to a plurality of selected word lines respectively, and the plurality of selected word lines include word lines with a target word line number in the plurality of storage planes.

[0007] During the process of storing the target write data to the memory strings respectively coupled to the plurality of selected word lines, exchange temporary check data with the host through the second interface and the first interface to determine the target check data of the target write data, where the temporary check data is check data generated during the process of determining the target check data.

[0008] Optionally, the host further includes a first cache, the controller further includes a second cache. The first cache is used to store the temporary check data received by the host through the first interface, the second cache is used to store the temporary check data received by the controller through the second interface and the currently generated temporary check data, and the capacity of the first cache is greater than the capacity of the second cache.

[0009] Optionally, the plurality of selected word lines include N selected word line groups, each selected word line group includes n selected word lines, n is greater than or equal to 1, and N is greater than 1.

[0010] The controller is configured to: sequentially store the write data corresponding to each of the N selected word line groups; after the write data corresponding to the i-th selected word line group is stored, where i is greater than or equal to 1, send the temporary verification data of the write data corresponding to the i-th selected word line group through the second interface;

[0011] The host is configured to: receive the temporary verification data of the write data corresponding to the i-th selected word line group through the first interface and store the temporary verification data of the write data corresponding to the i-th selected word line group;

[0012] The controller is further configured to: determine the temporary verification data of the write data corresponding to the N-th selected sub-word line group as the target verification data.

[0013] Optionally, i is greater than 1;

[0014] The controller is configured to: obtain the temporary verification data of the write data corresponding to the (i - 1)-th selected word line group backed up on the host through the second interface, and determine the temporary verification data of the write data corresponding to the i-th selected word line group based on the obtained temporary verification data.

[0015] Optionally, the write data corresponding to each selected word line group includes multiple page data numbered according to the same rule;

[0016] The controller is configured to: sequentially store each page data among the multiple page data corresponding to the i-th selected sub-word line group, and after the j-th page data corresponding to the i-th selected word line group is stored, where j is greater than or equal to 1, send the temporary verification data of the j-th page data corresponding to the i-th selected word line group through the second interface;

[0017] The host is configured to: receive the temporary verification data of the j-th page data corresponding to the i-th selected word line group through the first interface and store the temporary verification data of the j-th page data corresponding to the i-th selected word line group.

[0018] Optionally, i is greater than 1;

[0019] The controller is further configured to: obtain the temporary verification data of the j-th page data corresponding to the (i - 1)-th selected sub-word line group through the second interface and determine the temporary verification data of the j-th page data in the i-th selected word line group based on the obtained temporary verification data.

[0020] Optionally, the memory includes at least one memory chip, and each memory chip in the at least one memory chip includes the multiple memory planes;

[0021] The host further includes a first cache, the first cache includes at least one first area, the at least one first area corresponds to a storage chip respectively, and each first area includes a plurality of first sub-areas, and the plurality of first sub-areas correspond to a page number respectively.

[0022] Optionally, the host is configured to:

[0023] When receiving the temporary check data of the j-th page data corresponding to the i-th selected word line group through the first interface, select a first sub-area from the first area corresponding to the target storage chip based on the page number corresponding to the j-th page data, where the target storage chip is the storage chip to store the target write data;

[0024] Store the received temporary check data in the selected first sub-area in a way of overwrite writing.

[0025] Optionally, the memory includes at least one storage chip, and each storage chip in the at least one storage chip includes the plurality of storage planes;

[0026] The controller further includes a second cache, the second cache includes at least one second area, the at least one second area corresponds to a storage chip respectively, each second area includes a plurality of second sub-areas, and the total number of second sub-areas in each second area is less than the total number of page data corresponding to a selected word line group.

[0027] Optionally, the controller is further configured to:

[0028] Before storing the j-th page data corresponding to the i-th selected word line group, in the case that there is no free second sub-area in the second area corresponding to the target storage chip, select a second sub-area with an encoding completed state from the second area corresponding to the target storage chip, and send the temporary check data in the selected second sub-area through the second interface, where the target storage chip is the storage chip to store the target write data;

[0029] Obtain the temporary check data of the j-th page data corresponding to the (i - 1)-th selected sub-line group from the host through the second interface, store the obtained temporary check data in the selected second sub-area in a way of overwrite writing, and update the state of the selected second sub-area to a waiting for encoding state;

[0030] During the process of storing the j-th page data, store the temporary check data of the j-th page data in the selected second sub-area in a way of overwrite writing;

[0031] After the j-th page data is stored, update the state of the selected second sub-area to an encoding completed state.

[0032] Optionally, the controller is further configured to: obtain configuration information of the memory; determine first cache configuration information based on the configuration information of the memory, and send the first cache configuration information to the host through the second interface;

[0033] The host is configured to: receive the first cache configuration information through the first interface, and configure a first cache based on the first cache configuration information, where the first cache is used to store temporary verification data received through the first interface.

[0034] Optionally, the controller is further configured to:

[0035] Obtain configuration information of the memory;

[0036] Determine second cache configuration information based on the configuration information of the memory;

[0037] Configure a second cache based on the second cache configuration information, where the second cache is used to store temporary verification data received by the controller through the second interface and temporary verification data currently generated by the controller.

[0038] In a second aspect, a controller is provided. The controller is respectively coupled to a host and a memory. The controller includes a second interface. The memory includes a plurality of storage planes. Each storage plane in the plurality of storage planes includes a plurality of word lines numbered according to the same rule. Each word line in the plurality of word lines is coupled to a plurality of memory strings;

[0039] The controller is configured to:

[0040] Obtain target write data, where the target write data includes write data respectively corresponding to a plurality of selected word lines, and the plurality of selected word lines include word lines with a target word line number in the plurality of storage planes;

[0041] During the process of storing the target write data into the memory strings respectively coupled to the plurality of selected word lines, send temporary verification data to the host through the second interface and receive temporary verification data sent by the host through the second interface to determine target verification data of the target write data, where the temporary verification data is verification data generated during the process of determining the target verification data.

[0042] Optionally, the plurality of selected word lines include N selected word line groups, each selected word line group includes n selected word lines, n is greater than or equal to 1, and N is greater than 1;

[0043] The controller is configured to:

[0044] Store the write data corresponding to each selected word line group among the N selected word line groups in sequence;

[0045] After the write data corresponding to the i-th selected word line group is stored, where i is greater than or equal to 1, send the temporary verification data of the write data corresponding to the i-th selected word line group through the second interface;

[0046] Determine the temporary verification data of the write data corresponding to the N-th selected sub-line group as the target verification data.

[0047] Optionally, i is greater than 1;

[0048] The controller is configured to: obtain the temporary verification data of the write data corresponding to the (i - 1)-th selected word line group backed up on the host through the second interface, and determine the temporary verification data of the write data corresponding to the i-th selected word line group based on the obtained temporary verification data;

[0049] Optionally, the memory includes at least one memory chip, and each memory chip in the at least one memory chip includes the multiple memory planes;

[0050] The write data corresponding to each selected word line group includes multiple page data numbered according to the same rule;

[0051] The controller further includes a second cache, the second cache includes at least one second area, the at least one second area corresponds to a memory chip respectively, each second area includes multiple second sub-areas, and the total number of second sub-areas in each second area is less than the total number of page data corresponding to a selected word line group, and each second sub-area is used to store the temporary verification data of a page of data.

[0052] Optionally, the controller is further configured to:

[0053] Obtain the configuration information of the memory;

[0054] Determine the second cache configuration information based on the configuration information of the memory;

[0055] Configure the second cache based on the second cache configuration information;

[0056] Wherein, the second cache is used to store the temporary verification data received by the controller through the second interface and the currently generated temporary verification data.

[0057] Optionally, the controller is further configured to:

[0058] Obtain the configuration information of the memory;

[0059] Determine first cache configuration information based on the configuration information of the memory; send the first cache configuration information to the host through the second interface.

[0060] In a third aspect, a host is provided. The host is coupled to a controller, and the controller is coupled to a memory. The host includes a first interface, and the memory includes a plurality of memory planes. Each memory plane in the plurality of memory planes includes a plurality of word lines numbered according to the same rule. Each word line in the plurality of word lines is coupled to a plurality of memory strings;

[0061] The host is configured to: receive, through the first interface, temporary verification data sent by the controller, store the received temporary verification data, and send the stored temporary verification data to the controller through the first interface;

[0062] Wherein, the temporary verification data is verification data generated during the process of the controller determining the target verification data of the target write data. The target write data includes write data respectively corresponding to a plurality of selected word lines. The plurality of selected word lines include word lines with a target word line number in the plurality of memory planes.

[0063] Optionally, the plurality of selected word lines include N selected word line groups, each selected word line group includes n selected word lines, n is greater than or equal to 1, and N is greater than 1;

[0064] The host is configured to: receive, through the first interface, the temporary verification data of the write data corresponding to the i-th selected word line group, i is greater than or equal to 1, and store the temporary verification data of the write data corresponding to the i-th selected word line group.

[0065] Optionally, the memory includes at least one memory chip, and each memory chip in the at least one memory chip includes the plurality of memory planes;

[0066] The write data corresponding to each selected word line group includes a plurality of page data numbered according to the same rule;

[0067] The host further includes a first cache. The first cache includes at least one first area. The at least one first area corresponds to a memory chip respectively, and each first area includes a plurality of first sub-areas. The plurality of first sub-areas correspond to a page number respectively.

[0068] Optionally, the host is configured to:

[0069] When receiving the temporary verification data of the j-th page data corresponding to the i-th selected word line group through the first interface, a first sub-region is selected from a first region corresponding to the target storage chip based on the page number corresponding to the j-th page data, where the target storage chip is the storage chip for storing the target write data;

[0070] The received temporary verification data is stored in the selected first sub-region in a way of overwrite writing.

[0071] Optionally, the host is configured to:

[0072] Receive first cache configuration information through the first interface;

[0073] Configure a first cache based on the first cache configuration information, where the first cache is used to store the received temporary verification data.

[0074] In a fourth aspect, an operation method based on a storage system is provided. The storage system includes a host, a controller, and a memory. The host includes a first interface, the controller includes a second interface, and the memory includes a plurality of storage planes. Each storage plane in the plurality of storage planes includes a plurality of word lines numbered according to the same rule, and each word line in the plurality of word lines is coupled to a plurality of memory strings. The method includes:

[0075] The controller obtains target write data, where the target write data includes write data respectively corresponding to a plurality of selected word lines. The plurality of selected word lines include word lines with a target word line number in the plurality of storage planes, and the target storage chip is one of the plurality of storage chips;

[0076] During the process of storing the target write data into the memory strings respectively coupled to the plurality of selected word lines, the controller exchanges temporary verification data with the host through the second interface and the first interface to determine the target verification data of the target write data, where the temporary verification data is verification data generated during the process of determining the target verification data.

[0077] In the embodiments of the present application, a first interface is configured on the host and a second interface is configured on the controller. When the controller writes data into the memory, the controller exchanges temporary verification data with the host through the second interface and the first interface. Compared with the scheme of exchanging temporary verification data between the controller and the memory, the scheme of exchanging temporary verification data between the controller and the host provided by the embodiments of the present application can at least achieve the following technical effects:

[0078] (1) Since there is no need to cache temporary verification data in the memory, the overhead of the memory can be reduced, thereby improving the OP (over proportion) of the memory;

[0079] (2) Since there is no need to exchange temporary verification data between the memory and the controller, the IO (input / output) bandwidth between the controller and the memory occupied by the exchange of temporary verification data can be avoided, thereby improving the performance of the controller and the memory;

[0080] (3) Since it is the controller that exchanges temporary verification data with the host, considering that the cache space for storing temporary verification data on the host is relatively large, most of the temporary verification data can be backed up to the host, and a small amount of temporary verification data is stored at the controller, thereby reducing the controller's requirement for cache space such as SRAM (static random access memory), and correspondingly reducing the cost of SRAM on the controller;

[0081] (4) In the solution of exchanging temporary verification data between the controller and the memory, in order to avoid excessive occupation of the memory storage space by the temporary verification data, only the write data in the host write scenario is generated with verification data for RAID (redundant array of independent disks) protection, and the write data in the garbage collection scenario is not subject to RAID protection. In the solution of exchanging temporary verification data between the controller and the host provided in the embodiments of the present application, considering that the cache space for storing temporary verification data on the host is relatively large, not only can the write data in the host write scenario be subject to RAID protection, but also the write data in the garbage collection scenario can be subject to RAID protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0083] Figure 1 is a schematic diagram of a storage system 10 provided by an embodiment of the present application;

[0084] Figure 2 is a schematic diagram of a storage device provided by an embodiment of the present application;

[0085] Figure 3 is a schematic diagram of another storage device provided by an embodiment of the present application;

[0086] Figure 4It is a schematic diagram of a memory 100 provided by an embodiment of the present application;

[0087] Figure 5 It is a cross-sectional schematic diagram of a memory array 110 including a memory string 111 provided by an embodiment of the present application;

[0088] Figure 6 It is a schematic diagram of a peripheral circuit provided by an embodiment of the present application;

[0089] Figure 7 It is a schematic diagram of a memory chip provided by an embodiment of the present application;

[0090] Figure 8 It is a schematic diagram of a controller exchanging temporary verification data with a memory provided by an embodiment of the present application;

[0091] Figure 9 It is a schematic diagram of the architecture of a storage system provided by an embodiment of the present application;

[0092] Figure 10 It is a flowchart of an operation method of a controller provided by an embodiment of the present application;

[0093] Figure 11 It is a flowchart of an operation method of a host provided by an embodiment of the present application;

[0094] Figure 12 It is a flowchart of an operation method of a storage system provided by an embodiment of the present application;

[0095] Figure 13 It is a schematic diagram of a first cache and a second cache provided by an embodiment of the present application;

[0096] Figure 14 It is a schematic flowchart of a controller storing temporary verification data provided by an embodiment of the present application;

[0097] Figure 15 It is a schematic diagram of the framework of an HBR technology provided by an embodiment of the present application;

[0098] Figure 16 It is a schematic flowchart of backing up temporary verification data from a controller to a host provided by an embodiment of the present application;

[0099] Figure 17 It is a schematic flowchart of restoring temporary verification data from a host to a controller provided by an embodiment of the present application;

[0100] Figure 18 It is a schematic diagram of the architecture of another storage system provided by an embodiment of the present application. Detailed implementation manners

[0101] To make the objectives, technical solutions, and advantages of this application clearer, the following will further describe the embodiments of this application in detail with reference to the accompanying drawings.

[0102] Figure 1 It is a schematic diagram of a storage system 10 provided by an embodiment of this application. As Figure 1 shown, the storage system 10 includes: one or more memories 100, and a controller 200 coupled to the memories 100 and configured to control the memories 100.

[0103] The controller 200 can be configured to control the operations performed by the memories 100. Such as read, erase, and program operations. The controller 200 can also be configured to manage various functions regarding data stored in or to be stored in the memories 100, including but not limited to bad block management, garbage collection, logical address to physical address conversion, wear leveling, etc. Optionally, the controller 200 can also be configured to process error correcting codes (ECC) for data read from or written to the memories 100. The controller 200 can also perform any other suitable functions. For example, formatting the memories 100.

[0104] The controller 200 can also communicate with external devices according to a specific communication protocol. Exemplarily, the controller 200 can communicate with external devices through at least one of various interface protocols. The interface protocol can be a Universal Serial Bus (USB) protocol, a Multi-Media card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Development Environment (IDE) protocol, a Fire wire protocol, etc.

[0105] In some embodiments, the controller 200 and one or more memories 100 may be integrated into various types of electronic devices. The electronic device may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. In such a scenario, as Figure 1 shown, the storage system 10 further includes a host 300. The controller 200 is coupled to the host 300. The controller 200 may manage the data stored in the memory 100 and communicate with the host 300 to implement the functions of the aforementioned electronic devices.

[0106] In other embodiments, the controller 200 and one or more memories 100 may be integrated into various types of storage devices.

[0107] As an example, as Figure 2 shown, the controller 200 and a single memory 100 may be integrated into a memory card 400. The memory card 400 may include a Personal Computer Memory Card International Association (PCMCIA, PC) card, a CompactFlash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multi-Media Card (MMC), a Reduced-Size MMC (RS-MMC), a micro-MMC, a Secure Digital (SD) card, a Universal Flash Storage (UFS), etc. As Figure 2 shown, the memory card 400 may further include a connector 410 for coupling the memory card 400 to the host.

[0108] As another example, as Figure 3 shown, the controller 200 and multiple memories 100 may be integrated into a Solid State Disk (SSD) 500. The solid state drive 500 may further include a connector 510 for coupling the solid state drive 500 to the host. Among them, the storage capacity and / or operating speed of the solid state drive 500 is greater than that of the memory card 400.

[0109] In addition, Figures 1 to 3 the memory 100 in

[0110] Figure 4 It is a schematic diagram of a memory 100 provided by an embodiment of the present application. As Figure 4 shown, the memory 100 includes:

[0111] A storage array 110, the storage array 110 includes a plurality of storage unit rows;

[0112] A plurality of word lines 120, the plurality of word lines 120 are respectively coupled to the plurality of storage unit rows;

[0113] A peripheral circuit 130, the peripheral circuit 130 is coupled to the plurality of word lines 120 and is configured to perform operations such as programming (i.e., writing data) or reading data on a selected storage unit row among the plurality of storage unit rows. The selected storage unit row is the storage unit row coupled to the selected word line. Wherein, in order to perform operations such as programming or reading data, the peripheral circuit 130 is configured to execute the operation method of the memory provided by the embodiment of the present application.

[0114] The storage array 110 may be a NAND flash storage array. As Figure 1 shown, the NAND flash storage array includes a plurality of memory strings 111, the memory strings 111 are arranged in an array form on the substrate, and each memory string 111 extends vertically above the substrate (not shown). In some embodiments, each memory string 111 includes a plurality of memory cells 112 coupled in series and vertically stacked.

[0115] As Figure 4 shown, each memory string 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also referred to as a lower select transistor, a bottom select gate (BSG), or a source select transistor, and the drain select gate is also referred to as an upper select transistor, a top select gate (TSG), or a drain select transistor. The source select gate 113 and the drain select gate 114 may be configured to activate the selected memory string 111 during read and program operations.

[0116] In some embodiments, the drain select gate 114 of each memory string 111 is coupled to a corresponding bit line 115, and data can be read or written from the bit line 115 via an output bus (not shown).

[0117] In some embodiments, each memory string 111 is configured to apply a select voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 114 via one or more DSG lines 116. And / or, in some embodiments, each memory string 111 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 113) or a deselect voltage (e.g., 0V) to the corresponding source select gate 113 via one or more SSG lines 117.

[0118] As Figure 4 shown, the memory strings 111 may be organized into a plurality of blocks 140. For any one of the plurality of blocks 140, the block 140 may have a source line (SL) 118, and the sources of all the memory strings 111 in the block 140 are coupled through the source line 118, which is also referred to as a common source line or an array common source (ACS).

[0119] Among them, the source line 118 can be used for grounding to ground the sources of the respective memory cells of the memory strings in the block 140 in some subsequent operations. Optionally, in some other operations, a high voltage can also be applied to the sources of the respective memory cells of the memory strings in the block 140 through the source line 118.

[0120] Among them, each block 140 is a basic data unit for the erase operation, that is, all the memory cells 112 on the same block 140 are erased simultaneously. To erase the memory cells 112 in the selected block, the source line coupled to the selected block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (20V or higher)).

[0121] It should be understood that in some other embodiments, the erase operation can be performed at the half-block level, at the quarter-block level, or at any appropriate number of blocks or any appropriate fractional level of blocks.

[0122] As Figure 4 shown, the same-layer memory cells 112 of adjacent memory strings 111 in the same block 140 can be coupled through a word line 120, and the word line 120 is used to select which layer of memory cells 112 in the block 140 is affected by the read and program operations.

[0123] In some embodiments, each word line 120 is coupled to a page 150 to which the storage unit 112 belongs, and the page 150 is the basic data unit for programming operations. Among them, the size of the page 150 can be related to the number of memory strings 111 coupled by the word line 120 in a block 140. Each word line 120 can be coupled to the control gate (i.e., the gate electrode) of each storage unit 112 in the corresponding page 150. It can be understood that a row of storage units is multiple storage units 112 located on the same page 150.

[0124] It should be noted that the same layer of storage units in a block 140 corresponds to the same word line, but the storage units in the same layer can be divided into one or more pages. That is, a word line can be coupled to one or more pages. For example, for SLC, a word line is coupled to one page, and for MLC, a word line is coupled to two pages.

[0125] Figure 5 It is a cross-sectional schematic diagram of a storage array 110 including memory strings 111 provided by an embodiment of the present application. As Figure 5 shown, the memory string 111 can vertically extend above the substrate 101 and pass through the stacked layer 102. The substrate 101 can include silicon (for example, single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0126] The stacked layer 102 can include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104. The paired number of the gate conductive layer 103 and the gate-to-gate dielectric layer 104 in the stacked layer 102 can determine the number of storage units 112 in the storage array 110.

[0127] The gate conductive layer 103 can include a conductive material, and the conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 103 includes a metal layer, for example, a tungsten layer. In other embodiments, each gate conductive layer 103 includes a doped polysilicon layer. In addition, each gate conductive layer 103 can include a control gate surrounding the storage unit 112, and can laterally extend at the top of the stacked layer 102 as the DSG line 116, laterally extend at the bottom of the stacked layer 102 as the SSG line 117, or laterally extend between the DSG line 116 and the SSG line 117 as the word line 120.

[0128] As Figure 5As shown, the storage string 111 includes a channel structure 105 that extends vertically through the stacked layer 102. In some embodiments, the channel structure 105 includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a storage film). The semiconductor channel includes silicon, such as polysilicon. The storage film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a blocking layer.

[0129] In some embodiments, the channel structure 105 has a cylindrical shape (e.g., a column shape). The layers in the semiconductor channel and the storage film are radially arranged in this order from the center of the cylinder toward the outer surface of the cylinder.

[0130] It should be understood that although not shown in Figure 5 , the storage array 110 may also include other additional components, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0131] Returning to Figure 4 , the peripheral circuit 130 can be coupled to the storage array 110 through the bit line 115, the word line 120, the source line 118, the SSG line 117, and the DSG line 116. The peripheral circuit 130 can include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the storage array 110 by applying voltage signals and / or current signals to the storage cells 112 and sensing voltage signals and / or current signals from the storage cells 112 via the bit line 115, the word line 120, the source line 118, the SSG line 117, and the DSG line 116.

[0132] The peripheral circuit 130 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 some exemplary peripheral circuits 130 are shown, and the peripheral circuit 130 includes a page buffer / sense amplifier 131, a column decoder / bit line (BL) driver 132, a row decoder / word line (WL) driver 133, a voltage generator 134, a control logic unit 135, a register 136, an interface 137, and a data bus 138. It should be understood that in some examples, additional peripheral circuits not shown in Figure 6 may also be included.

[0133] The page buffer / sense amplifier 131 can be configured to read data from the memory array 110 and program (write) data to the memory array 110 according to control signals from the control logic unit 135. For example, the page buffer / sense amplifier 131 can store a page of programming data (write data) to be programmed into a page 130 of the memory array 110. The page buffer / sense amplifier 131 can also perform a verification operation to ensure that the data has been correctly programmed into the memory cells 112 coupled to the selected word line 120. The page buffer / sense amplifier 131 can also sense a low-power signal from the bit line 115, which represents a data bit stored in the memory cell 112, and amplify a small voltage swing to a recognizable logic level during a read operation.

[0134] The column decoder / bit line driver 132 can be configured to be controlled by the control logic unit 135 and select one or more memory strings 111 by applying a bit line voltage generated from the voltage generator 134.

[0135] The row decoder / word line driver 133 can be configured to be controlled by the control logic unit 135, and select / deselect the blocks 140 of the memory array 110, and select / deselect the word lines 120 of the blocks 140. The row decoder / word line driver 133 can also be configured to drive the word lines 120 with a word line voltage (VWL) generated from the voltage generator 134. In some embodiments, the row decoder / word line driver 133 can also select / deselect and drive the SSG line 117 and the DSG line 116. As described in detail below, the row decoder / word line driver 133 is configured to perform an erase operation on the memory cells 112 coupled to the (one or more) selected word lines 120.

[0136] The voltage generator 134 can be configured to be controlled by the control logic unit 135 and generate word line voltages (such as read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 110.

[0137] The control logic unit 135 can be coupled to each of the peripheral circuits described above and is configured to control the operations of each circuit.

[0138] The register 136 can be coupled to the control logic unit 135. The register can include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operations of each circuit in the peripheral circuit.

[0139] The interface (I / F) 137 can be coupled to the control logic unit 135 and act as a control buffer to buffer the control commands received from a host (not shown) and relay them to the control logic unit 135, and buffer the status information received from the control logic unit 135 and relay it to the host. The interface 137 can also be coupled to the column decoder / bit line driver 132 via the data bus 138 and act as a data I / O interface and a data buffer to buffer data and relay it to or from the storage array 110.

[0140] The above description of the memory-related hardware embodiments has beneficial effects similar to those of the following method embodiments. For the technical details not disclosed in the memory-related hardware embodiments, please refer to the description of the method embodiments of this application for understanding.

[0141] In addition, in order to improve the operation efficiency of the memory, Figures 1 to 4 the memory shown may include one memory chip (chip) or may include multiple memory chips. In other words, the memory provided by the embodiments of this application includes at least one memory chip. Among them, each memory chip in the at least one memory chip includes multiple memory planes, and each memory plane in the multiple memory planes includes multiple word lines numbered according to the same rule, and each word line in the multiple word lines is coupled to multiple memory strings.

[0142] Figure 7 is a schematic diagram of a memory chip provided by the embodiments of this application. As Figure 7 shown, the memory chip includes four memory planes, respectively labeled as memory plane 0, memory plane 1, memory plane 2, and memory plane 3. Each memory plane includes multiple word lines numbered according to the same rule. For example, each memory plane includes multiple word lines such as WL1, WL2, WL3, WL4... Figure 7 The schematic diagrams of the respective memory planes along the direction of the WLk word line are given as examples in

[0143] As Figure 7 shown, in each memory plane, the WLk word line is coupled to 6 memory strings. Figure 7 Each square grid in Figure 7 represents a memory string. It should be noted that Figure 4 a memory string in Figure 7 is a different concept from a memory string 111 in

[0144] In addition, Figure 7Each square in the stored string represents a logical page, and the number of logical pages included in each stored string is related to the type of storage unit in the memory. Exemplarily, when the storage unit in the memory is TLC (Triple-Level Cell), each stored string includes 3 logical pages. Figure 7 Taking TLC as an example for illustration. Again exemplarily, when the storage unit in the memory is MLC (Multi-Level Cell), each stored string includes 2 logical pages.

[0145] In a scenario where the memory includes at least one memory chip, when the controller operates on the memory, it can operate on different memory chips in parallel. For example, when the controller writes data to a certain memory chip, it can simultaneously perform garbage collection on the data in another memory chip, thereby improving the operation efficiency of the memory.

[0146] Moreover, when operating on a certain memory chip, since the interference between the stored strings coupled to the word lines with the same word line number in different memory planes is relatively small, the controller can operate on the stored strings coupled to the word lines with the same word line number in different memory planes together, further improving the operation efficiency.

[0147] For example, when the controller writes data to a certain memory chip, according to the word line number, the controller sequentially performs programming operations on the stored strings coupled to the word lines with the same word line number in different memory planes. For example, for Figure 7 the shown memory chip, when the controller writes data to this memory chip, it first writes data to the stored strings coupled to WL1 in the four memory planes, then writes data to the stored strings coupled to WL2 in the four memory planes…, and so on.

[0148] Furthermore, for each word line number, the controller generates the same parity data based on the data in the stored strings coupled to the word lines with the same word line number in different memory planes. In other words, the data in the stored strings coupled to the word lines with the same word line number in different memory planes corresponds to the same parity data. For example, for Figure 7 the shown memory chip, the data in the stored strings coupled to WLk in the four memory planes corresponds to the same parity data.

[0149] In addition, the data in the stored strings coupled to the word lines with the same word line number in different memory planes is stored sequentially according to a certain rule. Therefore, during the process of the controller storing this data, it can generate a temporary parity data when storing the current data, and when storing other data subsequently, regenerate a new temporary parity data based on the temporary parity data generated before the current time until all this data is stored and the final parity data is obtained.

[0150] It can be seen from this that a large amount of temporary parity data is generated during the process of the controller obtaining the parity data, and the currently generated temporary parity data will also be used in the subsequent process of generating the parity data. However, the memory space of the controller is limited. Therefore, during the process of generating the parity data, the controller needs to back up this temporary parity data to other devices and restore this temporary parity data from other devices in the subsequent process. In other words, the controller needs to exchange temporary parity data with other devices during the process of generating the parity data.

[0151] In some technologies, the controller can exchange temporary parity data with a memory. Figure 8 FIG. is a schematic diagram of a controller exchanging temporary parity data with a memory provided by an embodiment of the present application. As Figure 8 shown, a UFS (Universal Flash Storage) includes a controller and a NAND. The controller includes a CPU (Central Processing Unit), a parity data cache, and a controller-NAND interaction interface.

[0152] Among them, when the CPU of the controller writes data to the NAND, it caches the currently generated temporary parity data in the parity data cache, and backs up the temporary parity data in the parity data cache to the NAND through the controller-NAND interaction interface. When the temporary parity data is needed subsequently, the temporary parity data backed up on the NAND is restored to the parity data cache through the controller-NAND interaction interface.

[0153] In Figure 8 the shown solution, since the temporary parity data needs to be backed up to the NAND, the space on the NAND for storing the written data is reduced, thereby affecting the performance of the NAND. Moreover, during the process of the controller exchanging temporary parity data with the NAND, it is necessary to occupy the IO (Input / Output) bandwidth between the controller and the NAND, thereby affecting the performance of the UFS.

[0154] In some scenarios, the following two technologies can be adopted to reduce Figure 8 the impact on the NAND performance caused by the shown solution.

[0155] Technology 1: Increase the space of the SRAM on the controller to increase the capacity of the parity data cache, thereby reducing the amount of temporary parity data that needs to be backed up to the NAND. However, this technology causes the size of the SRAM of the controller to increase, and further causes the manufacturing cost of the SRAM of the controller to rise.

[0156] Technology 2: Only generate parity data for some of the written data for RAID protection. For example, only perform RAID (Redundant Array of Independent Disks) protection on the written data in the host write scenario, and abandon the RAID protection for the written data in the garbage collection scenario, thereby reducing the amount of temporary parity data that needs to be backed up to NAND. However, this solution requires the cost of verification or re-performing garbage collection to ensure the security of the written data in the garbage collection scenario.

[0157] Among them, the host write scenario can be understood as the user writing data to the memory through the host. The garbage collection scenario can be understood as integrating the scattered data originally stored in the memory strings coupled by multiple word lines into the memory string coupled by the specified word line.

[0158] Based on this, the embodiments of the present application provide a storage system, a controller, a host, and an operation method. In the embodiments of the present application, a first interface is configured on the host, and a second interface is configured on the controller. When the controller writes data to the memory, the controller exchanges temporary parity data with the host through the second interface and the first interface. Compared with the scheme of exchanging temporary parity data between the controller and the memory, the scheme of exchanging temporary parity data between the controller and the host provided by the embodiments of the present application can at least achieve the following technical effects:

[0159] (1) Since there is no need to cache temporary parity data in the memory, the overhead of the memory can be reduced, thereby improving the OP (Over Proportion) of the memory; where OP can be understood as the ratio of the size of the written data stored in the memory to the entire storage space of the memory.

[0160] (2) Since there is no need to exchange temporary parity data between the memory and the controller, the IO bandwidth occupied by the exchange of temporary parity data can be avoided, thereby improving the performance of the controller and the memory.

[0161] (3) Since it is the controller that exchanges temporary parity data with the host, considering that the cache space for storing temporary parity data on the host is relatively large, most of the temporary parity data can be backed up to the host, and a small amount of temporary parity data can be stored at the controller, thereby reducing the controller's demand for cache space such as SRAM (Static Random Access Memory), and correspondingly reducing the cost of SRAM on the controller.

[0162] (4) In the solution of exchanging temporary check data between the controller and the memory, in order to avoid excessive occupation of the memory storage space by the temporary check data, check data is only generated for the written data in the host write scenario for RAID protection, and the written data in the garbage collection scenario is not subject to RAID protection. In the solution of exchanging temporary check data between the controller and the host provided in the embodiments of the present application, considering that the cache space for storing temporary check data on the host is relatively large, not only can the written data in the host write scenario be subject to RAID protection, but also the written data in the garbage collection scenario can be subject to RAID protection.

[0163] The storage system, controller, host, operation method, etc. provided in the embodiments of the present application will be explained below.

[0164] Figure 9 is a schematic architecture diagram of a storage system provided in the embodiments of the present application. As Figure 9 shown, the storage system includes a host, a controller, and a memory. The controller and the memory exemplarily form a UFS. Among them, the memory can be a memory of types such as NAND, and the embodiments of the present application do not limit the type of the memory.

[0165] As Figure 9 shown, the host includes a first CPU, a first cache, and a first interface. The controller includes a second CPU, a second cache, a second interface, and a controller-memory interaction interface.

[0166] Among them, the first CPU and the second CPU include FW (firmware), and the FW is used to implement the method provided in the embodiments of the present application. That is, the FW includes instructions for implementing the method provided in the embodiments of the present application, and the first CPU and the second CPU implement the method provided in the embodiments of the present application by executing these instructions.

[0167] Specifically, in the process of the second CPU storing the written data in the memory through the controller-memory interaction interface, the currently generated temporary check data is cached in the second cache. The second CPU backs up the temporary check data in the second cache to the first cache through the second interface and the first interface according to certain rules. When the second CPU needs to back up the subsequent temporary check data, it restores the required temporary check data from the first cache through the second interface and the first interface. The detailed implementation method will be explained in the subsequent method embodiments and will not be elaborated here first.

[0168] That is, the first cache is used to store the temporary check data received by the host through the first interface. The second cache is used to store the temporary check data received by the controller through the second interface and the currently generated temporary check data.

[0169] Among them, the temporary verification data currently generated by the controller can be understood as the temporary verification data generated by the controller within a period of time before the current time and closest to the current time. The larger the capacity of the second cache, the more temporary verification data generated by the controller within the recent period of time can be cached. Regarding how to back up the temporary verification data in the second cache to the first cache, it will be described in detail in the subsequent method embodiments and will not be elaborated here for now.

[0170] Since the temporary verification data received by the controller through the second interface is the temporary verification data to be used within the recent period of time after the current time, the temporary verification data received by the controller through the second interface and the currently generated temporary verification data can also be collectively referred to as the recently used temporary verification data, that is, the second cache is used to store the recently used temporary verification data of the controller.

[0171] In addition, the first cache can be a part of the cache space allocated in the memory of the host, and the second cache can be a part of the cache space allocated in the memory of the controller. For the convenience of subsequent description, the memory of the host is referred to as the first memory, and the memory of the controller is referred to as the second memory.

[0172] Among them, the first memory and the second memory can be storage devices such as SRAM, and the embodiments of the present application do not limit the types of the memories of the host and the controller.

[0173] In some embodiments, in order to avoid the excessive size of the second memory of the controller resulting in a high manufacturing cost, the capacity of the first cache is greater than the capacity of the second cache. That is, a relatively small amount of temporary verification data is stored in the second cache, and most of the temporary verification data is backed up to the first cache.

[0174] Figure 10 is a flowchart of an operation method of a controller provided by an embodiment of the present application. This method is applied to Figure 9 the controller shown in Figure 10 as shown, and this method includes the following steps.

[0175] Step 1001: The controller obtains target write data, where the target write data includes write data corresponding to multiple selected word lines respectively, and the multiple selected word lines include the word lines with the target word line numbers in multiple memory planes.

[0176] Step 1002: When the controller stores the target write data into the memory strings respectively coupled to the multiple selected word lines, it sends temporary verification data to the host through the second interface and receives the temporary verification data sent by the host through the second interface to determine the target verification data of the target write data, where the temporary verification data is the verification data generated during the process of determining the target verification data.

[0177] ThroughFigure 10 The steps shown can enable the controller to exchange temporary verification data with the host to achieve the aforementioned technical effects.

[0178] Figure 11 It is a flowchart of an operation method of a host provided by an embodiment of the present application. This method is applied to Figure 9 the host shown, such as Figure 11 shown, and this method includes the following steps.

[0179] Step 1101: The host receives the temporary verification data sent by the controller through the first interface, stores the received temporary verification data, and sends the stored temporary verification data to the controller through the first interface.

[0180] Among them, the temporary verification data is the verification data generated during the process of the controller determining the target verification data of the target write data. The target write data includes the write data corresponding to multiple selected word lines respectively, and the multiple selected word lines include the word lines with the target word line number in multiple memory planes.

[0181] Through Figure 11 the steps shown, the host and the controller can exchange temporary verification data to achieve the aforementioned technical effects.

[0182] Figure 12 It is a flowchart of an operation method of a storage system provided by an embodiment of the present application. This method is applied to Figure 9 the storage system shown, such as Figure 12 shown, and this method includes the following steps.

[0183] Step 1201: The controller obtains the target write data. The target write data includes the write data corresponding to multiple selected word lines respectively, and the multiple selected word lines include the word lines with the target word line number in multiple memory planes.

[0184] Among them, when the memory includes one memory chip, the multiple memory planes in step 1201 can be understood as all the memory planes in this memory. When the memory includes multiple memory chips, the multiple memory planes in step 1201 can be understood as multiple memory planes in a certain memory chip, that is, currently storing the target write data to this memory chip. The memory chip that stores the target write data later is called the target memory chip.

[0185] The multiple selected word lines including the word lines with the target word line number in multiple memory planes can be understood as: the multiple selected word lines are the word lines with the word line numbers all being the target word line number in multiple memory planes. For example, for Figure 7For the storage chip shown, if the target word line number is WLk, then the multiple selected word lines include the word line WLk in storage plane 0, the word line WLk in storage plane 1, the word line WLk in storage plane 2, and the word line WLk in storage plane 3.

[0186] In addition, the method provided by the embodiments of the present application can be used to perform RAID protection on the write data in the host write scenario. In this scenario, the implementation manner for the controller to obtain the target write data can be: the controller receives the target write data from the host, and the target write data is the data to be written by the user.

[0187] Optionally, the method provided by the embodiments of the present application can also perform RAID protection on the write data in the garbage collection scenario. In this scenario, the implementation manner for the controller to obtain the target write data can be: the controller reads data from the memory strings coupled to the word lines corresponding to the multiple word line numbers in each storage plane respectively, and integrates the read data to obtain the target write data.

[0188] Step 1202: During the process of storing the target write data into the memory strings respectively coupled to the multiple selected word lines, the controller exchanges temporary check data with the host through the second interface and the first interface to determine the target check data of the target write data, and the temporary check data is the check data generated during the process of determining the target check data.

[0189] Since the target write data includes the write data corresponding to the multiple selected word lines respectively, and the multiple selected word lines are the word lines with the target word line numbers in multiple storage planes respectively, therefore, the process of storing the target write data into the memory strings respectively coupled to the multiple selected word lines can be understood as: the controller starts from storing the write data corresponding to the word line with the target word line number in the first storage plane, and ends after storing the write data corresponding to the word line with the target word line number in the last storage plane.

[0190] For example, for Figure 7 the storage chip shown, the process of storing the target write data into the memory strings respectively coupled to the multiple selected word lines can be understood as: starting from storing the write data corresponding to WLk in the first storage plane (i.e., storage plane 0), and ending after storing the write data corresponding to WLk in the last storage plane (i.e., storage plane 3).

[0191] In addition, there is a corresponding protection mode for performing RAID protection on the write data, and the protection mode is usually recorded as the nWLRAID protection mode. When n = 1, the protection mode is called the 1WL RAID protection mode. When n = 2, the protection mode is called the 2WLRAID protection mode.

[0192] The so-called nWL RAID protection mode means that when generating parity data, multiple selected word lines are grouped according to the quantity n to obtain multiple selected word line groups. The parity data corresponding to the written data of the selected word lines in the same selected word line group are independent of each other, while there is an association between the parity data corresponding to the written data of the selected word lines in different selected word line groups.

[0193] Based on this, in some embodiments, multiple selected word lines include N selected word line groups, each selected word line group includes n selected word lines, n is greater than or equal to 1, and N is greater than 1. In other words, multiple selected word lines are divided into N selected word line groups, and each selected word line group includes n selected word lines.

[0194] For example, for Figure 7 the storage chip shown, when n = 1, each selected word line group includes 1 selected word line. Among them, WLk in storage plane 0 forms a selected word line group, WLk in storage plane 1 forms another selected word line group, WLk in storage plane 2 forms another selected word line group, and WLk in storage plane 3 forms another selected word line group. When n = 2, each selected word line group includes 2 selected word lines. Among them, WLk in storage plane 0 and WLk in storage plane 1 form a selected word line group, and WLk in storage plane 2 and WLk in storage plane 3 form another selected word line group.

[0195] In the case where multiple selected word lines include N selected word line groups, step 1202 is exemplarily implemented through the following several steps.

[0196] Step 1: The controller sequentially stores the written data corresponding to each selected word line group among the N selected word line groups; after the written data corresponding to the i-th selected word line group is stored, i is greater than or equal to 1, and the temporary parity data of the written data corresponding to the i-th selected word line group is sent through the second interface.

[0197] Step 2: The host receives the temporary parity data of the written data corresponding to the i-th selected word line group through the first interface and stores the temporary parity data of the written data corresponding to the i-th selected word line group.

[0198] Among them, when the controller sequentially stores the written data corresponding to each selected word line group among the N selected word line groups, it sequentially generates the temporary parity data of the written data corresponding to each selected word line group, and then backs up the temporary parity data of the written data corresponding to each selected word line group to the host through the above step 1 and step 2 in sequence.

[0199] Exemplarily, when i equals 1, the controller generates temporary check data for the write data corresponding to the first selected word line group according to a certain strategy. When i is greater than 1, the controller obtains the temporary check data for the write data corresponding to the (i - 1)-th selected word line group backed up on the host through the second interface, and determines the temporary check data for the write data corresponding to the i-th selected word line group based on the obtained temporary check data.

[0200] In the embodiments of the present application, the temporary check data for the write data can be generated by means of parity check. Based on this, when i = 1, the write data corresponding to the first selected word line group can be directly used as the temporary check data for the write data corresponding to the first selected word line group. When i is greater than 1, an exclusive OR operation is performed between the write data corresponding to the i-th selected word line group and the temporary check data for the write data corresponding to the previous (i.e., the (i - 1)-th) selected word line group to obtain the temporary check data for the write data corresponding to the i-th selected word line group.

[0201] Optionally, in the embodiments of the present application, the check data can also be generated by other means, which will not be exemplified one by one here. The subsequent embodiments will be explained by taking parity check as an example.

[0202] In addition, when i is greater than 1, the controller determines the temporary check data for the write data corresponding to the i-th selected word line group based on the temporary check data for the write data corresponding to the (i - 1)-th selected word line group. Optionally, the temporary check data for the write data corresponding to the i-th selected word line group can also be determined based on the temporary check data for the write data corresponding to the (i - 1)-th and (i - 2)-th selected word line groups. Optionally, the temporary check data for the write data corresponding to the i-th selected word line group can also be determined based on all the temporary check data generated before the current time. This will not be exemplified one by one here.

[0203] Step three: The controller is further configured to: determine the temporary check data for the write data corresponding to the N-th selected sub-line group as the target check data.

[0204] After the controller sequentially stores the write data corresponding to each of the N selected word line groups, since a new temporary check data is generated each time the write data corresponding to a selected word line group is stored, based on the temporary check data of the write data corresponding to the selected word line groups stored before the current time. Therefore, when the write data corresponding to the Nth selected word line group (i.e., the last selected word line group) is stored, the last obtained temporary check data is related to the write data corresponding to these N selected word line groups. That is, the last obtained temporary check data can indicate the association between the write data corresponding to these N selected word line groups. Therefore, the last obtained temporary check data can be used as the target check data for the write data corresponding to these N selected word line groups (i.e., the target write data).

[0205] After the controller obtains the target check data of the target write data, it can store the target check data in the memory. For example, for Figure 9 the storage system shown, during the process of the controller storing the target write data in the memory, it exchanges the temporary check data with the host and stores the finally generated target check data in the memory for verifying the target write data when the target write data is read subsequently.

[0206] Optionally, after the controller obtains the target check data of the target write data, it can also store the target check data in other storage devices, which will not be exemplified one by one here.

[0207] In addition, when the controller stores data in the memory, it stores data in units of pages. Based on this, the write data corresponding to each selected word line group includes multiple page data numbered according to the same rule.

[0208] For example, for Figure 7 the storage chip shown, each word line is coupled to 6 memory strings, and each memory string includes 3 pages. Assuming the current is 2WL RAID protection mode, that is, n = 2, then the write data corresponding to each selected word line group includes 2 * 6 * 3 = 36 page data, and the page numbers corresponding to the 36 page data corresponding to each selected word line group are page0 to page35 respectively.

[0209] In this scenario, in step one, the controller sequentially stores each page data among the multiple page data corresponding to the ith selected sub-word line group. After the jth page data corresponding to the ith selected word line group is stored, where j is greater than or equal to 1, the temporary check data of the jth page data corresponding to the ith selected word line group is sent through the second interface.

[0210] Accordingly, in step two, the host receives the temporary check data of the j-th page data corresponding to the i-th selected word line group through the first interface, and stores the temporary check data of the j-th page data corresponding to the i-th selected word line group.

[0211] Among them, when i equals 1, the controller generates the temporary check data of each page data corresponding to the first selected word line group according to a certain strategy. When i is greater than 1, the controller obtains the temporary check data of the j-th page data corresponding to the (i - 1)-th selected sub-line group through the second interface, and determines the temporary check data of the j-th page data in the i-th selected word line group based on the obtained temporary check data. That is, when i is greater than 1, the temporary check data of a certain page data in the current selected word line group is updated based on the temporary check data of the page data with the same number in the previous selected word line group.

[0212] Exemplarily, in the scenario of generating check data by parity check, when i = 1, when storing each page data corresponding to the first selected word line group, each page data corresponding to the first selected word line group is used as the temporary check data of the corresponding page number. When i is greater than 1, when storing the j-th page data corresponding to the i-th selected word line group, an exclusive OR operation is performed on the j-th page data corresponding to the i-th selected word line group and the temporary check data of the j-th page data corresponding to the (i - 1)-th selected sub-line group to obtain the temporary check data of the j-th page data corresponding to the i-th selected sub-line group.

[0213] In addition, based on the foregoing introduction to the memory, the memory includes at least one memory chip, and each memory chip in the at least one memory chip includes multiple memory planes.

[0214] In this scenario, the first cache on the host can include at least one first area, and at least one first area corresponds to a memory chip respectively, so as to store the temporary check data related to the corresponding memory chip in different first areas. Among them, the temporary check data related to the corresponding memory chip can be understood as: the temporary check data generated when writing data to the memory chip.

[0215] Further, in the scenario where the written data corresponding to each selected word line group includes multiple page data numbered according to the same rule, in order to facilitate storing the temporary check data of different page data, each first area includes multiple first sub-areas, and multiple first sub-areas correspond to a page number respectively.

[0216] Figure 10 It is a schematic diagram of the configuration of the first cache on the host provided by an embodiment of the present application. Figure 10 The first cache includes M first areas such as the first area 0 to the first area M - 1, and each first area includes L first sub-areas such as the first sub-area 0 to the first sub-area L - 1.

[0217] For example, for Figure 7 the storage chip shown, assuming the current is the 2WL RAID protection mode, that is, n = 2, then the write data corresponding to each selected word line group includes 2 * 6 * 3 = 36 page data. The 36 page data corresponding to each selected word line group can be sequentially labeled as page0 to page35. Correspondingly, each first region includes 36 first sub-regions, that is, L = 36. The page numbers corresponding to these 36 first sub-regions are page0 to page35 respectively, where the first sub-region 0 corresponds to page0, the first sub-region 1 corresponds to page1, … the second sub-region L - 1 corresponds to page35. The total capacity of the first region = 36 * 16kKB = 576KB.

[0218] Based on this, the implementation method for the host to store the temporary check data of the jth page data corresponding to the ith selected word line group can be: when receiving the temporary check data of the jth page data corresponding to the ith selected word line group through the first interface, select the first sub-region from the first region corresponding to the target storage chip based on the page number corresponding to the jth page data, and the target storage chip is the storage chip to store the target write data; store the received temporary check data into the selected first sub-region in a way of overwrite writing.

[0219] Among them, overwrite writing means that when there is data stored in the selected first sub-region, delete (or empty) the data and store the received temporary check data.

[0220] In addition, in the scenario where the memory includes at least one storage chip, in order to facilitate the controller to cache the temporary check data, the second cache on the controller includes at least one second region, and at least one second region corresponds to a storage chip respectively, so as to store the temporary check data related to the corresponding storage chip in different second regions. Among them, the temporary check data related to the corresponding storage chip can be understood as: the temporary check data generated when storing write data to this storage chip.

[0221] Furthermore, since the temporary check data can be backed up to the first cache of the host later, each second region includes multiple second sub-regions, each second sub-region is used to store the temporary check data of one page data, and the total number of second sub-regions in each second region is less than the total number of page data corresponding to a selected word line group. This can reduce the amount of temporary check data stored on the controller, thereby improving the performance of the controller.

[0222] Such as Figure 13As shown, assuming that the memory includes M memory chips, the second cache includes M second regions such as the second region 0, each second region includes 9 second sub-regions, and each second sub-region is used to cache the temporary verification data of one page of data. The temporary verification data of one page of data can be called a parity entry. The total capacity of the second region = 9 * 16k KB = 144 KB.

[0223] Since the total number of second sub-regions in the second region is less than the total number of page data corresponding to a selected word line group, when the controller stores the temporary verification data of the page data corresponding to a selected word line group, there is a need to back up the temporary verification data in the second region to the host before all the page data corresponding to the selected word line group is stored.

[0224] In some embodiments, the implementation manner of the controller backing up the temporary verification data in the second region to the host can be: before storing the j-th page data corresponding to the i-th selected word line group, when there is no second sub-region in the second region corresponding to the target memory chip in an idle state, select a second sub-region in the second region corresponding to the target memory chip with the state of encoding completed, send the temporary verification data in the selected second sub-region through the second interface, and the target memory chip is the memory chip to store the target write data; obtain the temporary verification data of the j-th page data corresponding to the (i - 1)-th selected sub-line group from the host through the second interface, store the obtained temporary verification data in the selected second sub-region in a overwrite write manner, and update the state of the selected second sub-region to the waiting encoding state; during the process of storing the j-th page data, store the temporary verification data of the j-th page data in the selected second sub-region in a overwrite write manner; after the j-th page data is stored, update the state of the selected second sub-region to the encoding completed state.

[0225] Among them, that there is no second sub-region in the second region corresponding to the target memory chip in an idle state can be understood as: each second sub-region in the second region stores temporary verification data.

[0226] In the embodiments of the present application, when there is no second sub-region in the second region corresponding to the target memory chip in an idle state, it is possible to select which second sub-regions' temporary verification data to back up to the host according to whether the states of the second sub-regions in the second region are in the encoding completed state.

[0227] Correspondingly, when there is a second sub-region in the second region corresponding to the target memory chip in an idle state, it indicates that it is in the early stage of storing the write data corresponding to the first selected word line group. At this time, select the second sub-region in the idle state to store the currently generated temporary verification data.

[0228] In addition, the states of the second sub-regions may include an encoding-in-progress state in addition to the above-mentioned encoded-completion state and waiting-for-encoding state. In such a scenario, after the controller obtains the temporary verification data of the j-th page data corresponding to the (i-1)-th selected sub-word line group from the host through the second interface and stores the obtained temporary verification data in the selected second sub-region in an overwrite-write manner, the controller updates the state of the selected second sub-region to the waiting-for-encoding state. When starting to store the j-th page data corresponding to the i-th selected word line group, the controller updates the state of the selected second sub-region to the encoding-in-progress state. After the storage of the j-th page data is completed, the controller updates the state of the selected second sub-region to the encoded-completion state.

[0229] In the scenario where the second sub-regions correspond to the waiting-for-encoding state, the encoding-in-progress state, and the encoded-completion state, when the storage cells in the memory are TLC, considering that the controller writes 3 page data in parallel each time, each second region may include 3 * 3 = 9 second sub-regions. Therefore Figure 10 Take the storage cells in the memory being TLC as an example.

[0230] As Figure 10 shown, during the process of the controller storing the target write data in the memory, among the 9 second sub-regions in the second region, three second sub-regions are in the encoded-completion state, Figure 10 respectively marked as encoded-completion state PB0, encoded-completion state PB1, and encoded-completion state PB2; three second sub-regions are in the waiting-for-encoding state, Figure 10 respectively marked as waiting-for-encoding state PB0, waiting-for-encoding state PB1, and waiting-for-encoding state PB2; three second sub-regions are in the encoding-in-progress state, Figure 10 respectively marked as encoding-in-progress state PB0, encoding-in-progress state PB1, and encoding-in-progress state PB2.

[0231] Optionally, when the storage cells in the memory are MLC, each second sub-region may include 2 * 3 = 6 second sub-regions. When the storage cells in the memory are QLC (quad-level cells), each second sub-region may include 4 * 3 = 12 second sub-regions.

[0232] Optionally, each second region may include a larger number of second sub-regions, and the embodiments of the present application do not limit this.

[0233] As Figure 13As shown in the figure, assume that the second area corresponding to the target storage chip is the second area 0. Before the controller stores a certain page of data in the target storage chip, it first selects a second sub-area with the status of encoding completed in the second area 0, backs up the temporary verification data in the selected second sub-area to the host, and deletes the temporary verification data in the selected second sub-area at the same time. Then, it restores the temporary verification data in the first sub-area in the first area 0 with the same page number as the page number of the page data to the selected second sub-area, and updates the status of the selected second sub-area to the waiting for encoding status.

[0234] Figure 14 It is a schematic flow chart of a controller storing temporary verification data provided by an embodiment of the present application. As Figure 14 shown, after the controller updates the status of the selected second sub-area to the waiting for encoding status, it waits for the controller to store the page data in the memory, that is, waits for programming, and determines whether programming starts. When programming starts, it updates the status of the selected second sub-area to the encoding status, and then determines whether programming ends. When programming ends, it updates the status of the selected second sub-area to the encoding completed status.

[0235] After that, when the controller determines that it is necessary to exchange temporary verification data, for example, when it is necessary to store the next page number, at this time, it exchanges the temporary verification data in the way Figure 13 shown. Specifically, it first exchanges the temporary verification data in the currently selected second sub-area from the controller to the host, and after the exchange is completed, clears the data in the selected second sub-area (that is, resets the PB). Then, when it is determined that it is necessary to exchange temporary verification data from the host to the controller, it exchanges the temporary verification data from the host to the controller.

[0236] In addition, in the embodiment of the present application, the first cache in the host and the second cache in the controller can be pre-configured.

[0237] In some embodiments, the implementation method of configuring the first cache in the host can be: the controller obtains the configuration information of the memory; determines the first cache configuration information based on the configuration information of the memory, and sends the first cache configuration information to the host through the second interface; the host receives the first cache configuration information through the first interface and configures the first cache based on the first cache configuration information. The first cache is used to store the temporary verification data received through the first interface.

[0238] Among them, the configuration information of the memory obtained when configuring the first cache in the host exemplarily includes information about the storage chips in the memory, the number of memory strings coupled to each word line in each storage chip, the type of storage unit in the memory, the RAID protection mode of the memory, etc.

[0239] Exemplarily, the number of first regions in the first cache is configured according to the number of memory chips in the memory, and each first region corresponds to one memory chip. The number of first sub-regions in each first region is configured according to the number of memory strings coupled to each word line, the type of memory cells in the memory, and the RAID protection mode of the memory.

[0240] Among them, the detailed implementation manner of determining the first cache configuration information based on the configuration information of the memory can refer to Figure 13 the relevant content, which will not be elaborated here.

[0241] In some embodiments, the implementation manner of configuring the second cache in the configuration controller may be: obtaining the configuration information of the memory; determining the second cache configuration information based on the configuration information of the memory; and configuring the second cache based on the second cache configuration information. The second cache is used to store the temporary verification data received by the controller through the second interface and the temporary verification data currently generated by the controller.

[0242] Among them, the configuration information of the memory obtained when configuring the second cache in the configuration controller exemplarily includes information about memory chips in the memory, the type of memory cells in the memory, etc.

[0243] Exemplarily, the number of second regions in the second cache is configured according to the number of memory chips in the memory, and each second region corresponds to one memory chip. The number of second sub-regions in each second region is configured according to the type of memory cells in the memory.

[0244] Among them, the detailed implementation manner of determining the first cache configuration information based on the configuration information of the memory can refer to Figure 13 the relevant content, which will not be elaborated here.

[0245] In addition, the solution for the controller and the host to interact with temporary verification data provided in the embodiments of the present application can be referred to as HBR (host boost RAID) technology. Figure 15 It is a schematic framework diagram of an HBR technology provided in the embodiments of the present application. As Figure 15 shown, the HBR technology includes two parts, namely HBR initialization and HBR cache management.

[0246] Among them, HBR initialization is used to configure the first cache on the host and the second cache on the controller. Exemplarily, the controller in the UFS obtains the configuration information of the memory, configures the second cache on the controller based on the configuration information of the memory, and configures the first cache on the host based on the configuration information of the memory.

[0247] The HBR cache management is used to exchange temporary verification data between the host and the controller. For example, backing up the temporary verification data from the controller to the host, and restoring the temporary verification data from the host to the controller.

[0248] Figure 16 It is a schematic flow diagram for backing up temporary verification data from the controller to the host provided by an embodiment of the present application. As shown in FIG. 16, when the controller in the UFS determines that it is necessary to back up the temporary verification data corresponding to a certain page number from the controller to the host, the controller sends a notification message to the host. This notification message is used to notify that the temporary verification data corresponding to this page number is backed up from the controller to the host, and this notification message can be marked as "RESPONSE UPIU notify "Read ParityRegion"". The host receives this notification message and returns a request message to the controller based on this notification message. This request message is used to request the temporary verification data corresponding to this page number to be backed up from the controller to the host, and this request message can be marked as "READBUFFER command request to "Read Parity Region"". After receiving this request message, the controller reads the temporary verification data corresponding to this page number from the second cache and sends this temporary verification data to the host, where the sent temporary verification data can be marked as "DATA IN UPIU HBR Regions delivery". The host receives this temporary verification data and stores this temporary verification data in the first sub-region corresponding to this page number, that is, stores it in the first cache.

[0249] Figure 17It is a schematic flowchart of a process for restoring temporary verification data from a host to a controller provided by an embodiment of the present application. As shown in Figure 17, when the controller in the UFS determines that it is necessary to restore the temporary verification data corresponding to a certain page number from the host to the controller, the controller sends a notification message to the host. This notification message is used to notify the restoration of the temporary verification data corresponding to this page number from the host to the controller, and this notification message can be marked as "RESPONSE UPIU notify “Write ParityRegion”". The host receives this notification message and returns a request message to the controller based on this notification message. This request message is used to request the restoration of the temporary verification data corresponding to this page number from the host to the controller, and this request message can be marked as "WRITEBUFFER command request to “Write Parity Region”". After receiving this request message, the controller returns a ready-to-transfer message to the host. This ready-to-transfer response message can be marked as "READY TO TRANSFER UPIU". The host receives this ready-to-transfer message, reads the temporary verification data corresponding to this page number from the first buffer, and sends this temporary verification data to the controller. The sent temporary verification data can be marked as "DATAOUT UPIU HBR Regionsdelivery". The controller receives this temporary verification data and stores this temporary verification data in the second buffer.

[0250] It should be noted that Figure 16 and Figure 17 are schematic diagrams of examples of the interaction between the host and the controller in the embodiments of the present application, and do not constitute a limitation on the embodiments of the present application. In the embodiments of the present application, when the host and the controller interact with temporary verification data, other means can also be used to exchange the temporary verification data, which will not be exemplified one by one here.

[0251] In addition, it should be noted that in the solution for the host and the controller to interact with temporary verification data provided by the embodiments of the present application, the bandwidth between the host and the controller needs to meet the requirements for the host and the controller to interact with temporary verification data. In the host write scenario, since the rate of transmitting write data between the host and the controller is relatively low, there is more redundant bandwidth for interacting with temporary verification data. In the garbage collection scenario, there is no write data transmitted between the host and the controller, so there is sufficient bandwidth for interacting with temporary verification data.

[0252] In summary, in the embodiments of the present application, a first interface is configured on the host, and a second interface is configured on the controller. When the controller writes data into the memory, the controller exchanges temporary verification data with the host through the second interface and the first interface. Compared with the exchange of temporary verification data between the controller and the memory, on the one hand, the overhead of the memory can be reduced, thereby improving the OP of the memory; on the other hand, the IO bandwidth between the controller and the memory can be saved, thereby improving the performance of the controller and the memory; on the other hand, the demand of the controller for cache spaces such as SRAM can be reduced, and correspondingly, the cost of SRAM on the controller can be reduced; on the other hand, not only can the written data in the host write scenario be protected by RAID, but also the written data in the garbage collection scenario can be protected by RAID.

[0253] Based on Figure 12 the operation method of the storage system shown, the embodiments of the present application further provide a storage system. Figure 18 FIG. is a schematic architecture diagram of another storage system provided by the embodiments of the present application. As Figure 18 shown, the storage system 1800 includes a host 1801, a controller 1802, and a memory 1803. The host includes a first interface, the controller includes a second interface, the memory includes a plurality of storage planes, and each storage plane in the plurality of storage planes includes a plurality of word lines numbered according to the same rule. Each word line in the plurality of word lines is coupled to a plurality of memory strings;

[0254] The controller is configured to:

[0255] Obtain target write data, where the target write data includes write data respectively corresponding to a plurality of selected word lines, and the plurality of selected word lines include word lines with a target word line number in a plurality of storage planes;

[0256] During the process of storing the target write data into the memory strings respectively coupled to the plurality of selected word lines, exchange temporary verification data with the host through the second interface and the first interface to determine the target verification data of the target write data, where the temporary verification data is the verification data generated during the process of determining the target verification data.

[0257] Optionally, the host further includes a first cache, the controller further includes a second cache. The first cache is used to store the temporary verification data received by the host through the first interface, the second cache is used to store the temporary verification data received by the controller through the second interface and the currently generated temporary verification data, and the capacity of the first cache is greater than the capacity of the second cache.

[0258] Optionally, the plurality of selected word lines include N selected word line groups, each selected word line group includes n selected word lines, n is greater than or equal to 1, and N is greater than 1;

[0259] The controller is configured to: sequentially store the write data corresponding to each of the N selected word line groups; after the write data corresponding to the i-th selected word line group is stored, where i is greater than or equal to 1, send the temporary verification data of the write data corresponding to the i-th selected word line group through a second interface;

[0260] The host is configured to: receive the temporary verification data of the write data corresponding to the i-th selected word line group through a first interface, and store the temporary verification data of the write data corresponding to the i-th selected word line group;

[0261] The controller is further configured to: determine the temporary verification data of the write data corresponding to the N-th selected sub-word line group as the target verification data.

[0262] Optionally, i is greater than 1;

[0263] The controller is configured to: obtain the temporary verification data of the write data corresponding to the (i - 1)-th selected word line group backed up on the host through a second interface, and determine the temporary verification data of the write data corresponding to the i-th selected word line group based on the obtained temporary verification data.

[0264] Optionally, the write data corresponding to each selected word line group includes multiple page data numbered according to the same rule;

[0265] The controller is configured to: sequentially store each page data among the multiple page data corresponding to the i-th selected sub-word line group, and after the j-th page data corresponding to the i-th selected word line group is stored, where j is greater than or equal to 1, send the temporary verification data of the j-th page data corresponding to the i-th selected word line group through a second interface;

[0266] The host is configured to: receive the temporary verification data of the j-th page data corresponding to the i-th selected word line group through a first interface, and store the temporary verification data of the j-th page data corresponding to the i-th selected word line group.

[0267] Optionally, i is greater than 1;

[0268] The controller is further configured to: obtain the temporary verification data of the j-th page data corresponding to the (i - 1)-th selected sub-word line group through a second interface, and determine the temporary verification data of the j-th page data in the i-th selected word line group based on the obtained temporary verification data.

[0269] Optionally, the memory includes at least one memory chip, and each memory chip in the at least one memory chip includes multiple memory planes;

[0270] The host further includes a first cache, the first cache includes at least one first area, at least one first area corresponds to a memory chip respectively, and each first area includes multiple first sub-areas, and the multiple first sub-areas correspond to a page number respectively.

[0271] Optionally, the host is configured to:

[0272] When receiving the temporary check data of the j-th page data corresponding to the i-th selected word line group through the first interface, select a first sub-region from the first region corresponding to the target storage chip based on the page number corresponding to the j-th page data, where the target storage chip is the storage chip for storing the target write data;

[0273] Store the received temporary check data in the selected first sub-region in an overwrite write manner.

[0274] Optionally, the memory includes at least one storage chip, and each storage chip in the at least one storage chip includes a plurality of storage planes;

[0275] The controller further includes a second cache, the second cache includes at least one second region, each of the at least one second region corresponds to a storage chip, each second region includes a plurality of second sub-regions, and the total number of second sub-regions in each second region is less than the total number of page data corresponding to a selected word line group.

[0276] Optionally, the controller is further configured to:

[0277] Before storing the j-th page data corresponding to the i-th selected word line group, in the case where there is no free second sub-region in the second region corresponding to the target storage chip, select a second sub-region with an encoding completed state from the second region corresponding to the target storage chip, and send the temporary check data in the selected second sub-region through the second interface, where the target storage chip is the storage chip for storing the target write data;

[0278] Obtain the temporary check data of the j-th page data corresponding to the i-1-th selected sub-line group from the host through the second interface, store the obtained temporary check data in the selected second sub-region in an overwrite write manner, and update the state of the selected second sub-region to the waiting for encoding state;

[0279] During the process of storing the j-th page data, store the temporary check data of the j-th page data in the selected second sub-region in an overwrite write manner;

[0280] After the j-th page data is stored, update the state of the selected second sub-region to the encoding completed state.

[0281] Optionally, the controller is further configured to: obtain the configuration information of the memory; determine the first cache configuration information based on the configuration information of the memory, and send the first cache configuration information to the host through the second interface;

[0282] The host is configured to: receive first cache configuration information through a first interface, configure a first cache based on the first cache configuration information, and the first cache is used to store temporary verification data received through the first interface.

[0283] Optionally, the controller is further configured to:

[0284] Obtain the configuration information of the memory;

[0285] Determine second cache configuration information based on the configuration information of the memory;

[0286] Configure a second cache based on the second cache configuration information, and the second cache is used to store temporary verification data received by the controller through a second interface and temporary verification data currently generated by the controller.

[0287] Figure 18 The technical effects of the storage system shown can be referred to Figure 12 the embodiments shown, which will not be elaborated here.

[0288] In addition, an embodiment of the present application further provides a controller, the controller is respectively coupled to the host and the memory, the controller includes a second interface, the memory includes a plurality of storage planes, and each storage plane in the plurality of storage planes includes a plurality of word lines numbered according to the same rule, and each word line in the plurality of word lines is coupled to a plurality of memory strings;

[0289] The controller is configured to:

[0290] Obtain target write data, the target write data includes write data respectively corresponding to a plurality of selected word lines, and the plurality of selected word lines include word lines with a target word line number in a plurality of storage planes;

[0291] During the process of storing the target write data into the memory strings respectively coupled to the plurality of selected word lines, send temporary verification data to the host through the second interface and receive temporary verification data sent by the host through the second interface to determine the target verification data of the target write data, and the temporary verification data is verification data generated during the process of determining the target verification data.

[0292] Optionally, the plurality of selected word lines include N selected word line groups, each selected word line group includes n selected word lines, n is greater than or equal to 1, and N is greater than 1;

[0293] The controller is configured to:

[0294] Store the write data corresponding to each selected word line group in the N selected word line groups in order;

[0295] After the write data corresponding to the i-th selected word line group is stored, i is greater than or equal to 1, send the temporary verification data of the write data corresponding to the i-th selected word line group through the second interface;

[0296] Determine the temporary verification data of the write data corresponding to the Nth selected sub-word line group as the target verification data.

[0297] Optionally, i is greater than 1;

[0298] The controller is configured to: obtain, through a second interface, the temporary verification data of the write data corresponding to the (i - 1)th selected word line group backed up on the host, and determine the temporary verification data of the write data corresponding to the ith selected word line group based on the obtained temporary verification data;

[0299] Optionally, the memory includes at least one memory chip, and each memory chip in the at least one memory chip includes a plurality of memory planes;

[0300] The write data corresponding to each selected word line group includes a plurality of page data numbered according to the same rule;

[0301] The controller further includes a second cache, the second cache includes at least one second area, at least one second area corresponds to a memory chip respectively, each second area includes a plurality of second sub-areas, and the total number of second sub-areas in each second area is less than the total number of page data corresponding to a selected word line group, and each second sub-area is used to store the temporary verification data of a page data.

[0302] Optionally, the controller is further configured to:

[0303] Obtain the configuration information of the memory;

[0304] Determine the second cache configuration information based on the configuration information of the memory;

[0305] Configure the second cache based on the second cache configuration information;

[0306] Wherein, the second cache is used to store the temporary verification data received by the controller through the second interface and the currently generated temporary verification data.

[0307] Optionally, the controller is further configured to:

[0308] Obtain the configuration information of the memory;

[0309] Determine the first cache configuration information based on the configuration information of the memory; send the first cache configuration information to the host through the second interface.

[0310] The technical effects of the above controller can be referred to Figure 12 the embodiments shown, and will not be elaborated here.

[0311] In addition, an embodiment of the present application further provides a host. The host is coupled to a controller, and the controller is coupled to a memory. The host includes a first interface, and the memory includes a plurality of storage planes. Each storage plane in the plurality of storage planes includes a plurality of word lines numbered according to the same rule. Each word line in the plurality of word lines is coupled to a plurality of memory strings;

[0312] The host is configured to: receive, through the first interface, temporary verification data sent by the controller, store the received temporary verification data, and send the stored temporary verification data to the controller through the first interface;

[0313] Wherein, the temporary verification data is verification data generated during the process of the controller determining the target verification data of the target write data. The target write data includes write data respectively corresponding to a plurality of selected word lines, and the plurality of selected word lines include word lines with the target word line numbers in a plurality of storage planes.

[0314] Optionally, the plurality of selected word lines include N selected word line groups, each selected word line group includes n selected word lines, n is greater than or equal to 1, and N is greater than 1;

[0315] The host is configured to: receive, through the first interface, the temporary verification data of the write data corresponding to the i-th selected word line group, i is greater than or equal to 1, and store the temporary verification data of the write data corresponding to the i-th selected word line group.

[0316] Optionally, the memory includes at least one memory chip, and each memory chip in the at least one memory chip includes a plurality of storage planes;

[0317] The write data corresponding to each selected word line group includes a plurality of page data numbered according to the same rule;

[0318] The host further includes a first cache. The first cache includes at least one first area. Each of the at least one first areas corresponds to a memory chip, and each first area includes a plurality of first sub-areas. The plurality of first sub-areas respectively correspond to a page number.

[0319] Optionally, the host is configured to:

[0320] When receiving the temporary verification data of the j-th page data corresponding to the i-th selected word line group through the first interface, select a first sub-area from the first area corresponding to the target memory chip based on the page number corresponding to the j-th page data. The target memory chip is the memory chip to store the target write data;

[0321] Store the received temporary verification data into the selected first sub-area in a way of overwrite writing.

[0322] Optionally, the host is configured to:

[0323] Receive first cache configuration information through a first interface;

[0324] Configure a first cache based on the first cache configuration information, where the first cache is used to store received temporary verification data.

[0325] The technical effects of the above host can be referred to Figure 12 the embodiments shown and will not be elaborated here.

[0326] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk, an optical disc, etc.

[0327] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A storage system, characterized in that, The storage system includes a host, a controller, and a memory. The host includes a first interface, the controller includes a second interface, the memory includes a plurality of storage planes, and each storage plane in the plurality of storage planes includes a plurality of word lines numbered according to the same rule. Each word line in the plurality of word lines is coupled to a plurality of memory strings; The controller is configured to: Obtain target write data, where the target write data includes write data respectively corresponding to a plurality of selected word lines, and the plurality of selected word lines include word lines with a target word line number in the plurality of storage planes; During the process of storing the target write data into the memory strings respectively coupled to the plurality of selected word lines, exchange temporary verification data with the host through the second interface and the first interface to determine the target verification data of the target write data, and the temporary verification data is verification data generated during the process of determining the target verification data.

2. The storage system according to claim 1, characterized in that, The host further includes a first cache, and the controller further includes a second cache. The first cache is used to store the temporary verification data received by the host through the first interface, and the second cache is used to store the temporary verification data received by the controller through the second interface and the currently generated temporary verification data, and the capacity of the first cache is greater than the capacity of the second cache.

3. The storage system according to claim 1, wherein The plurality of selected word lines include N selected word line groups, each selected word line group includes n selected word lines, n is greater than or equal to 1, and N is greater than 1; The controller is configured to: sequentially store the write data corresponding to each selected word line group in the N selected word line groups; After the write data corresponding to the i-th selected word line group is stored, i is greater than or equal to 1, send the temporary verification data of the write data corresponding to the i-th selected word line group through the second interface; The host is configured to: receive the temporary verification data of the write data corresponding to the i-th selected word line group through the first interface and store the temporary verification data of the write data corresponding to the i-th selected word line group; The controller is further configured to: determine the temporary verification data of the write data corresponding to the N-th selected word line group as the target verification data.

4. The storage system according to claim 3, wherein i is greater than 1; The controller is configured to: obtain the temporary verification data of the write data corresponding to the (i - 1)-th selected word line group backed up on the host through the second interface, and based on the obtained temporary verification data, determine the temporary verification data of the write data corresponding to the i-th selected word line group.

5. The storage system according to claim 3, wherein The write data corresponding to each selected word line group includes a plurality of page data numbered according to the same rule; The controller is configured to: sequentially store each page data in the plurality of page data corresponding to the i-th selected word line group. After the j-th page data corresponding to the i-th selected word line group is stored, j is greater than or equal to 1, send the temporary verification data of the j-th page data corresponding to the i-th selected word line group through the second interface; The host is configured to: receive the temporary check data of the j-th page data corresponding to the i-th selected word line group through the first interface, and store the temporary check data of the j-th page data corresponding to the i-th selected word line group.

6. The storage system according to claim 5, wherein wherein i is greater than 1; The controller is further configured to: obtain the temporary check data of the j-th page data corresponding to the (i - 1)-th selected sub-word line group through the second interface, and determine the temporary check data of the j-th page data in the i-th selected word line group based on the obtained temporary check data.

7. The storage system according to claim 5, wherein The memory includes at least one memory chip, and each memory chip in the at least one memory chip includes the plurality of memory planes; The host further includes a first cache, and the first cache includes at least one first area. Each of the at least one first area corresponds to a memory chip, and each first area includes a plurality of first sub-areas, and the plurality of first sub-areas respectively correspond to a page number.

8. The storage system according to claim 7, wherein The host is configured to: when receiving the temporary check data of the j-th page data corresponding to the i-th selected word line group through the first interface, select a first sub-area from the first area corresponding to the target memory chip based on the page number corresponding to the j-th page data, where the target memory chip is the memory chip to store the target write data; store the received temporary check data in the selected first sub-area in a way of overwrite writing.

9. The storage system according to claim 5, wherein The memory includes at least one memory chip, and each memory chip in the at least one memory chip includes the plurality of memory planes; The controller further includes a second cache, and the second cache includes at least one second area. Each of the at least one second area corresponds to a memory chip, each second area includes a plurality of second sub-areas, and the total number of second sub-areas in each second area is less than the total number of page data corresponding to a selected word line group.

10. The storage system according to claim 9, characterized in that, The controller is further configured to: before storing the j-th page data corresponding to the i-th selected word line group, in the case that there is no free second sub-area in the second area corresponding to the target memory chip, select a second sub-area with an encoding completed state from the second area corresponding to the target memory chip, and send the temporary check data in the selected second sub-area through the second interface, where the target memory chip is the memory chip to store the target write data; obtain the temporary check data of the j-th page data corresponding to the (i - 1)-th selected sub-word line group from the host through the second interface, store the obtained temporary check data in the selected second sub-area in a way of overwrite writing, and update the state of the selected second sub-area to a waiting for encoding state; during the process of storing the j-th page data, store the temporary check data of the j-th page data in the selected second sub-area in a way of overwrite writing; after the j-th page data is stored, update the state of the selected second sub-area to an encoding completed state.

11. The storage system according to claim 1, wherein The controller is further configured to: obtain configuration information of the memory; determine first cache configuration information based on the configuration information of the memory, and send the first cache configuration information to the host through the second interface; The host is configured to: receive the first cache configuration information through the first interface, and configure a first cache based on the first cache configuration information, where the first cache is used to store temporary verification data received through the first interface.

12. The storage system according to claim 1, wherein The controller is further configured to: obtain configuration information of the memory; determine second cache configuration information based on the configuration information of the memory; configure a second cache based on the second cache configuration information, where the second cache is used to store temporary verification data received by the controller through the second interface and temporary verification data currently generated by the controller.

13. A controller, characterized in that, The controller is respectively coupled to the host and the memory. The controller includes a second interface. The memory includes a plurality of storage planes. Each storage plane in the plurality of storage planes includes a plurality of word lines numbered according to the same rule, and each word line in the plurality of word lines is coupled to a plurality of memory strings; The controller is configured to: obtain target write data, where the target write data includes write data respectively corresponding to a plurality of selected word lines, and the plurality of selected word lines include word lines with a target word line number in the plurality of storage planes; During the process of storing the target write data into the memory strings respectively coupled to the plurality of selected word lines, send temporary verification data to the host through the second interface and receive temporary verification data sent by the host through the second interface to determine target verification data of the target write data, where the temporary verification data is verification data generated during the process of determining the target verification data.

14. The controller according to claim 13, wherein The plurality of selected word lines include N selected word line groups, each selected word line group includes n selected word lines, where n is greater than or equal to 1 and N is greater than 1; The controller is configured to: store the write data corresponding to each selected word line group in the N selected word line groups in sequence; after the write data corresponding to the i-th selected word line group is stored, where i is greater than or equal to 1, send the temporary verification data of the write data corresponding to the i-th selected word line group through the second interface; determine the temporary verification data of the write data corresponding to the N-th selected word line group as the target verification data.

15. The controller according to claim 14, wherein i is greater than 1; The controller is configured to: obtain, through the second interface, the temporary verification data of the write data corresponding to the (i - 1)-th selected word line group backed up on the host, and determine the temporary verification data of the write data corresponding to the i-th selected word line group based on the obtained temporary verification data.

16. The controller according to claim 14, wherein The memory includes at least one memory chip, and each memory chip in the at least one memory chip includes the plurality of storage planes; The write data corresponding to each selected word line group includes a plurality of page data numbered according to the same rule; The controller further includes a second cache, the second cache including at least one second region, each of the at least one second region corresponding to a storage chip, each second region including a plurality of second sub-regions, and the total number of second sub-regions in each second region being less than the total number of page data corresponding to a selected word line group, each second sub-region being configured to store temporary verification data of a page data.

17. The controller according to claim 13, characterized in that, The controller is further configured to: Obtain configuration information of the memory; Determine second cache configuration information based on the configuration information of the memory; Configure the second cache based on the second cache configuration information; Wherein, the second cache is configured to store the temporary verification data received by the controller through the second interface and the currently generated temporary verification data.

18. The controller according to claim 13, wherein The controller is further configured to: Obtain configuration information of the memory; Determine first cache configuration information based on the configuration information of the memory; and send the first cache configuration information to the host through the second interface.

19. A host, characterized in that, The host is coupled to the controller, the controller is coupled to the memory, the host includes a first interface, the memory includes a plurality of memory planes, each memory plane in the plurality of memory planes including a plurality of word lines numbered according to the same rule, and each word line in the plurality of word lines being coupled to a plurality of memory strings; The host is configured to: receive, through the first interface, the temporary verification data sent by the controller, store the received temporary verification data, and send the stored temporary verification data to the controller through the first interface; Wherein, the temporary verification data is verification data generated during the process of the controller determining the target verification data of the target write data, the target write data including write data respectively corresponding to a plurality of selected word lines, and the plurality of selected word lines including word lines with target word line numbers in the plurality of memory planes.

20. The host according to claim 19, characterized in that, The plurality of selected word lines includes N selected word line groups, each selected word line group including n selected word lines, where n is greater than or equal to 1 and N is greater than 1; The host is configured to: receive, through the first interface, the temporary verification data of the write data corresponding to the i-th selected word line group, where i is greater than or equal to 1, and store the temporary verification data of the write data corresponding to the i-th selected word line group.

21. The host according to claim 20, wherein The memory includes at least one storage chip, and each storage chip in the at least one storage chip includes the plurality of memory planes; The write data corresponding to each selected word line group includes a plurality of page data numbered according to the same rule; The host further includes a first cache, the first cache including at least one first region, each of the at least one first region corresponding to a storage chip, and each first region including a plurality of first sub-regions, the plurality of first sub-regions respectively corresponding to a page number.

22. The host according to claim 21, wherein The host is configured to: When receiving the temporary verification data of the j-th page data corresponding to the i-th selected word line group through the first interface, select a first sub-region from the first region corresponding to the target storage chip based on the page number corresponding to the j-th page data, where the target storage chip is the storage chip to store the target write data; Store the received temporary verification data in the selected first sub-region in a way of overwrite writing.

23. The host according to claim 19, characterized in that, The host is configured to: Receive first cache configuration information through the first interface; Configure a first cache based on the first cache configuration information, where the first cache is used to store the received temporary verification data.

24. An operation method based on a storage system, characterized in that, The storage system includes a host, a controller, and a memory. The host includes a first interface, the controller includes a second interface, the memory includes multiple storage planes, each storage plane in the multiple storage planes includes multiple word lines numbered according to the same rule, and each word line in the multiple word lines is coupled to multiple memory strings; the method includes: The controller obtains target write data, where the target write data includes write data respectively corresponding to multiple selected word lines, the multiple selected word lines include word lines with a target word line number in the multiple storage planes, and the target storage chip is one of the multiple storage chips; During the process of storing the target write data in the memory strings respectively coupled to the multiple selected word lines, the controller exchanges temporary verification data with the host through the second interface and the first interface to determine the target verification data of the target write data, where the temporary verification data is the verification data generated during the process of determining the target verification data.

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