Error correction deactivation by memory system

Abstract

The invention relates to error correction deactivation by a memory system. A method may include a memory system reading data from one or more memory cells of a memory device at a first time, and deactivating a first error correction capability based on the data including one or more errors of a first type. Further, the method may include the memory system reading the data at a second time, and transmitting the data to a host device based on the data not including the one or more errors of the first type.

Description

[0001] Cross-reference

[0002] This patent application claims the priority of U.S. Patent Application No. 18 / 776,867, titled "ERROR CORRECTION DISABLEMENT BY A MEMORY SYSTEM", filed by Sforzin et al. on July 18, 2024, and claims the benefit and priority of U.S. Patent Application No. 63 / 623,653, titled "ERROR CORRECTION DISABLEMENT BY A MEMORY SYSTEM", filed by Sforzin et al. on January 22, 2024. Each of the patent applications is assigned to the assignee hereof, and each of the patent applications is hereby incorporated by reference in its entirety.

[0003] The technical field relates to error correction disablement by a memory system. Background Art

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically denoted by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, and any of the states can be stored by the memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to the memory cell. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. Summary of the Invention

[0005] A method is described. The method can include: reading data from one or more memory cells of a memory device at a first time; disabling a first error correction capability of the memory system based on determining that the data read from the one or more memory cells of the memory system includes one or more errors of a first type; reading data from the one or more memory cells of the memory device at a second time; and transmitting the data to a host device based on determining that the data does not include one or more errors of the first type based on reading the data from the one or more memory cells of the memory system at the second time.

[0006] Describe a non - transitory computer - readable medium storing code. The non - transitory computer - readable medium storing code may include instructions executable by one or more processors to perform the following operations: read data from one or more memory cells of a memory device at a first time; deactivate a first error - correction capability of the memory system based on determining that the data read from one or more memory cells of the memory system includes one or more errors of a first type; read data from one or more memory cells of the memory device at a second time; and transmit the data to a host device based on reading the data from one or more memory cells of the memory system at the second time and based on determining that the data does not include one or more errors of the first type.

[0007] Describe a memory system. The memory system may include: one or more memory devices; and processing circuitry coupled to the one or more memory devices and configured to cause the memory system to perform the following operations: read data from one or more memory cells of the memory device at a first time; deactivate a first error - correction capability of the memory system based on determining that the data read from one or more memory cells of the memory system includes one or more errors of a first type; read data from one or more memory cells of the memory device at a second time; and transmit the data to a host device based on reading the data from one or more memory cells of the memory system at the second time and based on determining that the data does not include one or more errors of the first type. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Show examples of systems supporting error - correction deactivation performed by a memory system according to examples disclosed herein.

[0009] Figure 2 Show examples of flowcharts supporting error - correction deactivation performed by a memory system according to examples disclosed herein.

[0010] Figure 3 Show a block diagram of a memory system supporting error - correction deactivation performed by a memory system according to examples disclosed herein.

[0011] Figure 4 and 5 Show flowcharts depicting one or more methods supporting error - correction deactivation performed by a memory system according to examples disclosed herein. DETAILED DESCRIPTION

[0012] A memory system can be configured with a first error correction capability. In some instances, the first error correction capability can include on-die error correction code (ECC). The memory system can perform on-die ECC to detect and potentially correct errors at the memory array of the memory system. For example, a memory device can receive a read command to access data at the memory array of the memory device. Based on or in response to the read command, the memory device can read data from the memory array and perform on-die ECC on the data before sending the data to the host system to detect and potentially correct errors in the data. During on-die ECC, the memory device can determine whether the data is error-free, contains one or more errors of a first type (e.g., uncorrectable errors), or contains one or more errors of a second type (e.g., correctable errors).

[0013] In addition to the first error correction capability, the memory system can also be configured with a second error correction capability. Examples of the second error correction capability can include Reed-Solomon (RS) error correction. In some instances, the memory system can implement RS error correction in combination with on-die ECC. For example, one or more memory devices can receive a read command to read data from their respective memory arrays. In response to the read command, each memory device among the one or more memory devices can retrieve data from its respective memory array and perform on-die ECC. When performing on-die ECC, the one or more memory devices can transmit the data to the memory controller of the memory system for RS error correction. During RS error correction, the memory controller can determine whether the data is error-free, contains one or more errors of a first type (e.g., uncorrectable errors), or contains one or more errors of a second type (e.g., correctable errors).

[0014] However, in some instances, the first error correction capability and the second error correction capability may not work effectively together. For example, when performing the first error correction capability (e.g., on-die ECC), the memory device may inadvertently introduce additional errors into the data and send the data with the additional errors to the memory controller for RS error decoding. The memory controller may not be able to correct the errors in the data as well as the additional errors introduced by the ECC using RS error decoding, which may result in uncorrectable errors in the data. Alternatively, if the first error correction capability does not introduce additional errors, then the memory controller may have the ability to correct the data using RS error decoding. Therefore, a memory system configured to disable on-die ECC to prevent or otherwise mitigate errors from being introduced into the data (e.g., due to ECC) may be needed.

[0015] As described herein, a memory system may be configured to disable error correction capabilities. In some instances, at a first time, the memory system may read data from one or more memory cells of a memory device and determine that the data includes one or more errors of a first type (e.g., uncorrectable errors). For example, the system may fail to correct one or more errors using a first error correction capability (on-die ECC) or a second error correction capability (RS error decoding), and may determine that the data includes uncorrectable errors. When determining that the data includes one or more errors of the first type, the memory system may disable the first error correction capability.

[0016] At a second time, and when the first error correction capability is disabled, the memory system may read (or re-read) data from one or more memory cells of the memory device and may determine that the data does not include one or more errors of a second type, but instead includes one or more errors of a second type (e.g., correctable errors). For example, with the first error correction capability disabled, the memory system may perform the second error correction capability (or RS error decoding) on the data alone. Using the second error correction capability, the memory system may determine that the data includes one or more errors of the second type (e.g., correctable errors), and may correct one or more errors in the data before transmitting the data to a host system. The methods described herein may allow the memory system to selectively disable a first error correction capability of the memory system, which may reduce uncorrectable errors in the data in some cases. Reducing or otherwise mitigating the occurrence of such uncorrectable errors in the data may improve the system's ability to identify and correct errors, which may improve the overall performance of the memory system.

[0017] In addition to its applicability in memory systems as described herein, techniques for error correction disabling by a memory system may also generally be implemented to support increased connectivity of an electronic system. As the use of systems of interconnected electronic devices increases, the connectivity of these electronic devices becomes an increasingly relevant factor in system operation. For example, as critical systems become more reliant on connectivity, as the system uses a greater number of interconnected devices, or if the number and complexity of signals communicated between devices increases, the latency associated with signals communicated between devices may become increasingly relevant. Implementing the techniques described herein may support techniques for improving connectivity in an electronic system by improving data transfer between devices, among other benefits.

[0018] The features of the present disclosure are illustrated and described in the context of systems and architectures. The features of the present disclosure are further illustrated and described in the context of one or more flowcharts.

[0019] Figure 1FIG. 0 illustrates an example of a system 100 that supports error correction disablement by a memory system as disclosed herein. System 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, a smartphone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or other stationary or portable electronic systems, and other examples. System 100 includes a host system 105, a memory system 110, and one or more channels 115 that couple the host system 105 to the memory system 110 (e.g., to support communication coupling). System 100 may include any number of one or more memory systems 110 coupled to the host system 105.

[0020] The host system 105 may include one or more components (e.g., circuitry, processing circuitry, one or more processing components) that execute programs using the memory, and any one or more of the one or more components may be referred to as or included in a processor 125. The processor 125 may include at least one of one or more processing elements that may be co-located or distributed, including a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a controller, discrete gates or transistor logic, one or more discrete hardware components, or a combination thereof. The processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or an SoC or a component thereof, and other examples.

[0021] The host system 105 may also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement the functionality of an external memory controller (e.g., a host system memory controller), which may be referred to as or included in a host system controller 120. For example, the host system controller 120 may issue commands or other signaling for operating the memory system 110, such as write commands, read commands, configuration signaling, or other operation signaling. In some examples, the host system controller 120 or the associated functionality described herein may be implemented by or be part of the processor 125. For example, the host system controller 120 may be hardware, instructions (e.g., software, firmware), or some combination thereof implemented by the processor 125 or other components of the host system 105. In various examples, the host system 105 or the host system controller 120 may be referred to as the host.

[0022] Memory system 110 provides physical memory locations (e.g., addresses) that can be used or referenced by system 100. Memory system 110 may include a memory system controller 140 operable to store data and one or more memory devices 145 (e.g., memory packages, memory dies, memory chips). Memory system 110 may be configured for operation with different types of host systems 105 and may respond to commands from host system 105 (e.g., from host system controller 120). For example, memory system 110 (e.g., memory system controller 140) may receive a write command indicating that memory system 110 is to store data received from host system 105, or a read command indicating that memory system 110 is to provide data stored in memory device 145 to host system 105, or a refresh command indicating that memory system 110 is to refresh data stored in memory device 145, as well as other types of commands and operations.

[0023] Memory system controller 140 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of memory system 110. Memory system controller 140 may include hardware or instructions that support memory system 110 in performing various operations and may be operable to receive, transmit, or respond to commands, data, or control information related to the operation of memory system 110. Memory system controller 140 may be operable to communicate with one or more of host system controller 120, one or more memory devices 145, or processor 125. In some instances, memory system controller 140 may cooperate with host system controller 120, local controller 150 of memory device 145, or any combination thereof to control the operation of memory system 110. Although an example of memory system controller 140 is depicted as a separate component of memory system 110, in some instances, aspects of the functionality of memory system 110 may be implemented by at least one of processor 125, host system controller 120, one or more local controllers 150, or any combination thereof.

[0024] Each memory device 145 may include a local controller 150 and one or more memory arrays 155. The memory arrays 155 may be a collection of memory cells (e.g., two-dimensional arrays, three-dimensional arrays), where each memory cell may be operable to store data (e.g., as one or more stored bits). Each memory array 155 may include memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase change memory (PCM) cells, chalcogenide memory cells, NOR memory cells, and NAND memory cells, or any combination thereof.

[0025] The local controller 150 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory device 145. In some instances, the local controller 150 may be operable to communicate with the memory system controller 140 (e.g., receive or transmit data or commands or both). In some instances, the memory system 110 may not include the memory system controller 140, and the local controller 150 or the host system controller 120 may perform the functions of the memory system controller 140 described herein. In some instances, the local controller 150 or the memory system controller 140 or both may include decoding components operable to access the addresses of the memory cells of the memory array 155, sensing components for sensing the states of the memory cells of the memory array 155, writing components for writing the states to the memory cells of the memory array 155, or various other components operable to support the described operations of the memory system 110.

[0026] The host system 105 (e.g., host system controller 120) and the memory system 110 (e.g., memory system controller 140) may use one or more channels 115 to communicate information (e.g., data, commands, control information, configuration information). Each channel 115 may be an instance of a transmission medium for carrying information, and each channel 115 may include one or more signal paths (e.g., transmission medium, electrical conductor, conductive path) between terminals (e.g., nodes, pins, contacts) associated with components of the system 100. The terminals may be instances of conductive input or output points of devices of the system 100, and the terminals may be operable as part of the channel 115. To support communication through the channel 115, the host system 105 (e.g., host system controller 120) and the memory system 110 (e.g., memory system controller 140) may include a receiver (e.g., latch) for receiving signals, a transmitter (e.g., driver) for transmitting signals, a decoder for decoding or demodulating received signals, or an encoder for encoding or modulating signals to be transmitted, and other components to support signal conduction through the channel 115, which may be included in corresponding interface portions of the respective systems.

[0027] The channel 115 is dedicated to communicating one or more types of information, and the channel 115 may include unidirectional channels, bidirectional channels, or both. For example, the channel 115 may include one or more command / address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some instances, the channel 115 may be configured to supply power from one system to another system (e.g., from the host system 105 to the memory system 110 according to a regulated voltage). In some instances, at least a subset of the channel 115 may be configured according to a protocol (e.g., logic protocol, communication protocol, operation protocol, industry standard), which may support the configured operation of the host system 105 and the memory system 110 and the interaction between the host system 105 and the memory system 110.

[0028] The command / address channel (e.g., CA channel) may be operable to communicate commands between the host system 105 and the memory system 110, including control information associated with the commands (e.g., address information, configuration information). The commands carried by the command / address channel may include a write command having an address of data to be written to the memory system 110, or a read command having an address of data to be read from the memory system 110.

[0029] The clock signal channel can be operable to communicate one or more clock signals between the host system 105 and the memory system 110. The clock signal can oscillate between a high state and a low state and can support coordination (e.g., in time) between the operations of the host system 105 and the memory system 110. In some instances, the clock signal can provide a timing reference for the operation of the memory system 110. The clock signal can be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal can be generated by a system clock, which can include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors).

[0030] The data channel (e.g., the DQ channel) can be operable to communicate information (e.g., data, control information) between the host system 105 and the memory system 110 (e.g., bidirectionally). For example, the data channel can convey information from the host system 105 to be written to the memory system 110 or information read from the memory system 110 to the host system 105. In some instances, the channel 115 can include one or more error detection code (EDC) channels. The EDC channel can be operable to communicate error detection signals, such as checksums or parity bits, which can accompany the information transmitted through the data channel.

[0031] In some instances, each memory device 145 of the memory system 110 can include an ECC circuit 160. Using the ECC circuit 160, the memory device 145 can perform on-die ECC. On-die ECC can allow the memory device 145 to detect and correct errors present in the memory array 155 of the memory device 145. During a write operation, the ECC circuit 160 can generate a first set of parity bits corresponding to the written data and can store the first set of parity bits together with the written data in the memory array 155. During a read operation, the memory device 145 can read data from the memory array 155, and the ECC circuit 160 can check for errors in the read data using the first set of parity bits. For example, the ECC circuit 160 can generate a second set of parity bits based on the read data and can compare the second set of parity bits with the first set of parity bits. If the second set of parity bits matches the first set of parity bits, then the ECC circuit 160 can detect zero errors in the read data (e.g., the data may not contain any errors), and the memory system 110 can send the read data to the host system 105.

[0032] Alternatively, if the first set of parity bits and the second set of parity bits do not match, then the ECC circuit 160 can detect one or more errors in the read data. If only one error is detected (e.g., a single-bit error (SBE)), then the ECC circuit 160 can implement a single error correction (SEC) code (e.g., a Hamming code) to correct the error, and the memory device 145 can send the corrected read data to the host system 105. However, if the ECC circuit 160 detects more than one error in the data (e.g., a multi-bit error (MBE)), then the ECC circuit 160 may not be able to correct the error in the read data, and in some cases, a message indicating that the memory device 145 is unable to correct the error in the read data can be sent to the host system 105. Errors that the ECC circuit 160 can correct can be referred to as correctable errors, and errors that the ECC circuit 160 cannot correct can be referred to as uncorrectable errors.

[0033] In addition to on-die ECC, the memory system 110 can also implement an RS code to perform error correction using the RS circuit 130. The RS code can be a block-based error correction code. In some instances, to increase speed, the memory system 110 can read data from multiple memory devices 145 in parallel. For example, the memory system 110 can read a first portion of data from a first memory array 155 of a first memory device 145 and a second portion of data from a second memory array 155 of a second memory device 145 in parallel. After performing on-die ECC on the respective portions of the data, the memory device 145 can send the data to the memory system controller 140. At the memory system controller 140, the RS circuit 130 can detect and potentially correct errors in the data using the RS code.

[0034] However, in some instances, the ECC circuit 160 may not be able to correct one or more errors in the data stored at the memory array 155. For example, the ECC circuit 160 may detect an SBE but fail to correct the SBE. In addition to failing to correct the SBE, the ECC circuit 160 may potentially introduce additional errors into the data, resulting in uncorrectable errors (e.g., MBE). Thus, the RS circuit 130 may receive data with additional errors introduced by the ECC circuit 160. In some instances, the additional errors may corrupt one or more symbols of the RS codeword (e.g., data or parity symbols), and the RS circuit 130 may not be able to correct the errors present in the read data. Further, even if only one ECC circuit 160 of the memory device 145 introduces one or more additional errors into a portion of the read data, the entire data may be affected because the RS circuit 130 collectively analyzes data read from all of the memory devices 145 involved in a parallel read operation. In the absence of on-die ECC, the read data may not contain additional errors (e.g., errors introduced by one or more ECC circuits 160) that would allow the RS circuit 130 to correct the original errors in the read data.

[0035] Accordingly, in some scenarios (e.g., when using the RS circuit 130 or when the memory system 110 is in a test mode), dynamically disabling on-die ECC may be beneficial to the memory system 110 or the host system 105. As Figure 1 shown, the memory system controller 140 may include a mode register 135 (e.g., MR50 or another mode register) configured to store a set of bits indicative of one or more operating states of the memory system 110. In some instances, one or more bits in the set of bits may be related to the on-die ECC operation of the memory system 110. For example, the first bit stored in the mode register 135 may indicate whether the memory system 110 supports the disabling of on-die ECC. As an example, a bit value of 1 in the first position of the mode register 135 may indicate support for the disabling of on-die ECC (or DiSEC), while a bit value of 0 may indicate no support for the disabling of on-die ECC. In some instances, the bit value of the first bit (e.g., in the first position) may be programmed during the manufacturing phase of the memory system 110.

[0036] Additionally or alternatively, a second bit stored in a second location of the mode register 135 may indicate whether to enable the deactivation of on-die ECC for the memory system 110. As an example, a bit value of 1 may indicate enabling the deactivation of on-die ECC (or deactivation of single error correction (DiSEC or DS)), while a bit value of 0 may indicate not enabling the deactivation of on-die ECC. In some instances, the bit value of the second bit may be programmatically set dynamically using a mode register write (MRW) command. Additionally, in some instances, the second bit may be protected by a key (e.g., a secret key or a guard key). For example, the host system 110 may issue a specific command sequence (e.g., a guard key) that enables the memory system 110 to change or update the second bit in the mode register 135. If the specific command sequence is not issued by the host system 105, then the second bit is maintained.

[0037] Tables 1 and 2 show examples of a set of bits stored in the mode register 135. In the examples of Tables 1 and 2, the mode register 135 may store 8 bits represented by OP0, OP1, OP2, OP3, OP4, OP5, OP6, and OP7 in Tables 1 and 2. OP1 to OP5 may be related to cyclic redundancy check (CRC) operations at the memory system 110, and OP6 and OP7 are related to on-die ECC operations. Specifically, OP[6] may be an example of the first bit in the first location (e.g., the DiSEC support bit), and OP[7] may be an example of the second bit in the second location (e.g., the DiSEC enable bit). If the bit value of the first bit (e.g., OP[6]) indicates support for the deactivation of on-die ECC (e.g., set to 1), and the bit value of the second bit (e.g., OP[7]) indicates enabling the deactivation of on-die ECC (e.g., set to 1), then on-die ECC may be deactivated at the memory system 110. The content of Tables 1 and 2 is only exemplary, and it should be understood that the bits stored in the mode register 135 (e.g., OP1 to OP5) may represent other features (e.g., features different from those related to CRC operations). Additionally, the order of the bits in the mode register 135 may be different from the order represented in Tables 1 and 2.

[0038]

[0039] Table 1

[0040] Function Type OP Description / Data Read CRC Enable R / W OP[0] 0 = Disabled (default), 1 = Enabled Write CRC Enable Lower Half Byte R / W OP[1] 0 = Disabled (default), 1 = Enabled Write CRC Enable Upper Half Byte R / W OP[2] 0 = Disabled (default), 1 = Enabled Write CRC Error Status R / W OP[3] 0 = Disabled (default), 1 = Enabled Write CRC Auto Disable Enable R / W OP[4] 0 = Disabled (default), 1 = Enabled Write CRC Auto Disable Status R / W OP[5] 0 = Disabled (default), 1 = Enabled DiSEC Support R OP[6] 0 = Not supported, 1 = Supported DiSEC Enable R / W OP[7] 0 = Disabled (default), 1 = Enabled

[0041] Table 2

[0042] In some instances, the memory system 110 may deactivate on-die ECC in response to a trigger. An example of a trigger may be a command received from the host system 105 (e.g., a write command, a write auto-precharge command, a read command, or a read auto-precharge command). As an example, the host system 105 may transmit a command to access data from the memory array 155 of the memory device 145. In addition to indicating the location of the data to be accessed, the command may also indicate whether the memory device 145 will perform the access operation without on-die ECC.

[0043] If the command indicates deactivation of on-die ECC, then the memory device 145 may perform the access operation without implementing the ECC circuit 160 (or without on-die ECC). Further, in response to the command and / or prior to performing the access operation with on-die ECC deactivated, the memory system 110 may perform a mode register read (MRR) on the mode register 135 to ensure that the memory system 110 is enabled or supports deactivation of on-die ECC. If the memory system 110 is not enabled or does not support on-die ECC (e.g., as indicated in the mode register 135), then the memory system 110 may perform the access operation with on-die ECC enabled, even if the command otherwise indicates. In another example, the command may indicate activation of on-die ECC. In such cases, the memory device 145 may perform the access operation with the ECC circuit 160 (or with on-die ECC).

[0044] In some instances, upon receiving a command to deactivate on-die ECC, the memory system 110 may deactivate on-die ECC for the duration of the operation (e.g., a read operation or a write operation) indicated by the command. After the duration, the memory system 110 may reactivate on-die ECC, and on-die ECC may remain active until otherwise indicated (e.g., via another command or trigger to deactivate). Alternatively, after the duration, on-die ECC may remain deactivated until otherwise indicated (e.g., via another command or trigger to activate).

[0045] Table 3 illustrates how an indication can be incorporated into a command (e.g., a read command). To signal a command to the memory system 110, the host system 105 can apply corresponding voltages to each pin in a set of pins (e.g., connecting the host system 105 and the memory system 110). The set of pins can include a chip select (CS) pin and a plurality of CA pins (e.g., CA0 to CA13). At least one pin in the set of pins can correspond to Die ECC Disable (DiSEC or DS) on the die. For example, as shown in Table 3, CA9 can correspond to Die ECC Disable (DiSEC or DS) on the die. To indicate disabling Die ECC for a read operation specified by a read command, the host system 105 can set the CA9 pin to high (e.g., the voltage output of the pin is higher than a threshold). Alternatively, to indicate enabling Die ECC for a read operation specified by a read command, the host system 105 can set the CA9 pin to low (e.g., the voltage output of the pin is lower than a threshold). The content of Table 3 is merely exemplary, and it should be understood that Die ECC Disable can correspond to a pin different from those illustrated in Table 3 (e.g., different from CA9).

[0046]

[0047] Table 3. Command truth table.

[0048] As described herein, the memory system 110 can dynamically disable Die ECC. In many cases, disabling Die ECC can be beneficial. For example, the memory system 110 can disable Die ECC when performing read operations on multiple memory devices 145 in parallel to avoid uncorrectable errors at the RS circuit 130. Additionally, the memory system 110 can disable Die ECC when the memory system 110 is operating in a test mode so that the memory system 110 can evaluate aspects of a faulty bit (e.g., its location within the memory array 155).

[0049] Figure 2 An example of a flowchart 200 that supports error correction disable by a memory system according to an example disclosed herein is shown. In some examples, the flowchart 200 can be implemented by aspects of the memory system 110 as described Figure 1 herein. For example, the flowchart 200 can be implemented by one or more of the memory system controller 140, the RS circuit 130, the memory device 145, the local controller 150, or the ECC circuit 160.

[0050] At 205, the memory system may perform a first read operation. During the first read operation, one or more memory devices (or local controllers) of the memory system may retrieve the read data stored at one or more memory arrays. When retrieving the read data from the one or more memory arrays, one or more ECC circuits may perform on-die ECC (or first error correction capability) on the read data. In some instances, each memory device of the one or more memory devices may include an ECC circuit. In such instances, the ECC circuit of each corresponding memory device may perform on-die ECC on a corresponding portion of the data. Alternatively, the memory system may include a single ECC circuit corresponding to multiple memory devices. In such instances, the single ECC circuit may perform on-die ECC on the data. Performing on-die ECC may include applying an SEC code to the read data to detect (and potentially correct) single-bit errors in the read data. After performing on-die ECC, the one or more memory devices may transfer the read data to the RS circuit of the memory system controller of the memory system and proceed to 210.

[0051] At 210, the memory system controller of the memory system may perform RS error decoding (e.g., second error correction capability) on the read data using the RS circuit and determine whether there is an error in the read data. In some instances, the RS circuit may detect zero errors in the read data and may proceed to 240.

[0052] At 240, the memory system may transfer the read data to the host system.

[0053] Alternatively, at 210, the RS circuit may detect a correctable error (or second type of error) in the read data and may proceed to 215. A correctable error may include an error that the RS circuit can correct. At 215, the RS circuit may correct the correctable error in the read data and may proceed to 240.

[0054] Alternatively, at 210, the RS circuit may detect an uncorrectable error (or first type of error) in the read data and may proceed to 220. An uncorrectable error may include an error that the RS circuit cannot correct. An uncorrectable error may occur if the ECC circuit is unable to correct an error in the read data. In some instances, the ECC circuit may attempt to correct the uncorrectable error and fail, resulting in additional errors in the read data.

[0055] At 220, one or more memory devices may perform a second read operation to read (or reread) the read data from one or more memory arrays. In some instances, prior to performing the second read operation, the memory system may receive an indication to disable on-die ECC. For example, the memory system may receive a command (e.g., a read command or a write command for the second read operation) that includes an indication to disable on-die ECC. In response to the indication, the memory system may perform the second read operation without performing on-die ECC. That is, one or more memory devices may retrieve the read data from one or more memory arrays and may send the read data directly to the memory system controller at 225 for RS error decoding, thereby bypassing the ECC circuitry of the one or more memory devices.

[0056] At 225, the memory system controller of the memory system may perform RS error decoding on the read data using the RS circuitry and determine whether an error exists in the data. In some instances, the RS circuitry may detect zero errors in the read data and may proceed to 240.

[0057] Alternatively, at 225, the RS circuitry may detect a correctable error in the read data and may proceed to 235. A correctable error may include an error that the RS circuitry can correct, such as a single-bit error. At 235, the RS circuitry may correct the correctable error in the read data and may proceed to 240.

[0058] Alternatively, at 225, the RS circuitry may detect an uncorrectable error in the read data and proceed to 220. An uncorrectable error may include an error that the RS circuitry cannot correct, such as a multi-bit error. When an uncorrectable error is detected, the memory system may proceed to 230.

[0059] At 230, the memory system may transmit a message indicating that the memory system encountered an uncorrectable error during the second read operation to the host system. Using the method described herein may allow the memory system to dynamically disable on-die ECC, which may reduce the number of uncorrectable errors in the data, thereby allowing other circuitry of the memory system (e.g., the RS circuitry) to correct the errors.

[0060] Figure 3 FIG. 300 is a block diagram showing a memory system 320 that supports error correction disabling by a memory system according to an example as disclosed herein. The memory system 320 may be as described with reference to Figure 1 to 2Examples of aspects of the described memory system. Memory system 320 or its various components can be examples of components for performing various aspects of error correction deactivation by the memory system as described herein. For example, memory system 320 can include access component 325, ECC enabling component 330, communication component 335, error correction component 340, MRR component 345, MRW component 350, or any combination thereof. Each of these components or sub-components of the components (e.g., one or more processors, one or more memories) can communicate with each other directly or indirectly (e.g., via one or more buses).

[0061] Access component 325 can be configured to or otherwise support components for reading data from one or more memory cells of a memory device at a first time. ECC enabling component 330 can be configured to or otherwise support components for deactivating a first error correction capability of the memory system based on determining that data read from one or more memory cells of the memory system includes one or more errors of a first type. In some instances, access component 325 can be configured to or otherwise support components for reading data from one or more memory cells of a memory device at a second time. Communication component 335 can be configured to or otherwise support components for transmitting data to a host device based on reading data from one or more memory cells of the memory system at the second time and determining that the data does not include one or more errors of the first type.

[0062] In some instances, to support determining that data read from one or more memory cells of the memory system includes one or more errors of a first type, error correction component 340 can be configured to or otherwise support components for failing to correct at least one error in the data using a second error correction capability of the memory system. In some instances, the second error correction capability of the memory system includes a Reed - Solomon (RS) error correction code.

[0063] In some instances, access component 325 can be configured to or otherwise support components for reading second data from one or more second memory cells of the memory system at a third time. In some instances, error correction component 340 can be configured to or otherwise support components for correcting one or more errors in the second data using a second error correction capability of the memory system based on determining that the second data includes one or more errors of a second type. In some instances, communication component 335 can be configured to or otherwise support components for transmitting the second data to a host device based on correcting one or more errors in the second data using a second error correction capability of the memory system.

[0064] In some instances, one or more errors of the first type include uncorrectable errors (UEs). In some instances, one or more errors of the second type include correctable errors (CEs).

[0065] In some instances, the access component 325 may be configured to or otherwise support a component for reading third data from one or more third memory cells of the memory system. In some instances, the error correction component 340 may be configured to or otherwise support a component for determining that the third data includes zero errors based on reading the third data from one or more third memory cells of the memory system. In some instances, the communication component 335 may be configured to or otherwise support a component for transmitting the third data to the host device based on determining that the third data includes zero errors.

[0066] In some instances, the error correction component 340 may be configured to or otherwise support a component for determining that the data includes one or more errors of the second type based on determining that the data does not include one or more errors of the first type. In some instances, the error correction component 340 may be configured to or otherwise support a component for correcting one or more errors of the second type using a second error correction capability of the memory system based on determining that the data includes one or more errors of the second type, wherein transmitting the data to the host device is based on correcting one or more errors of the second type.

[0067] In some instances, to support determining that the data does not include one or more errors of the first type, the error correction component 340 may be configured to or otherwise support a component for determining that the data includes zero errors, wherein transmitting the data to the host device is based on determining that the data includes zero errors.

[0068] In some instances, the MRR component 345 may be configured to or otherwise support a component for reading a first bit value from a mode register of the memory system, wherein the first bit value indicates that a first error correction capability of the memory system is configured to be deactivated, and wherein deactivating the first error correction capability of the memory system is based on reading the first bit value from the mode register of the memory system.

[0069] In some instances, the MRW component 350 may be configured to or otherwise support a component for receiving, from the host device, a command including an indication to write a second bit value to a mode register of the memory system based on determining that data read from one or more memory cells of the memory system includes one or more errors of the first type. In some instances, the MRW component 350 may be configured to or otherwise support a component for writing the second bit value to the mode register of the memory system based on receiving the command, wherein deactivating the first error correction capability of the memory system is based on writing the second bit value to the mode register.

[0070] In some instances, the MRR component 345 may be configured or otherwise support components for receiving a secret key from a host device, where writing a second bit value to a mode register of the memory system is based on the secret key.

[0071] In some instances, the ECC enable component 330 may be configured or otherwise support components for receiving, from a host device and based on determining that data includes one or more errors of a first type, a command to reread data from one or more memory cells of the memory system, where the command includes an indication to disable a first error correction capability of the memory system.

[0072] In some instances, the command includes a write command, a write auto precharge command, a read command, or a read auto precharge command.

[0073] In some instances, the ECC enable component 330 may be configured or otherwise support components for enabling a first error correction capability of the memory system based on transferring data to a host device. In some instances, the first error correction capability includes on-die ECC.

[0074] In some instances, the error correction component 340 may be configured or otherwise support components for determining that data read from one or more memory cells of the memory system at a first time includes one or more errors of a first type. In some instances, the error correction component 340 may be configured or otherwise support components for determining that data read from one or more memory cells of the memory system at a second time does not include one or more errors of a first type.

[0075] In some instances, the access component 325 may be configured or otherwise support components for reading third data from one or more third memory cells of the memory device at a fourth time. In some instances, the access component 325 may be configured or otherwise support components for rereading third data from one or more third memory cells of the memory device at a fifth time. In some instances, the error correction component 340 may be configured or otherwise support components for transmitting an indication to a host device based on rereading third data from one or more third memory cells of the memory system and based on determining that the third data includes one or more errors of a first type.

[0076] In some instances, the described functionality of the memory system 320 or its various components may be supported by or may involve at least a portion of at least one processor, where the at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some instances, the described functionality of the memory system 320 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) executable by the at least one processor.

[0077] Figure 4 FIG. 4 is a flow diagram illustrating a method 400 that supports error correction disablement by a memory system according to an example as disclosed herein. Operations of method 400 may be implemented by a memory system or its components as described herein. For example, operations of method 400 may be performed by a memory system as described with reference to Figure 1 to 3 the memory system described. In some instances, the memory system may execute a set of instructions to control functional elements of a device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0078] At 405, the method may include reading data from one or more memory cells of a memory device at a first time. The operation of 405 may be performed according to an example as disclosed herein. For example, the memory system may include an access component 325 that reads data from one or more memory cells of a memory device (e.g., Figure 1 memory device 145) at the first time.

[0079] At 410, the method may include disabling a first error correction capability of the memory system based on determining that data read from one or more memory cells of the memory system includes one or more errors of a first type. The operation of 410 may be performed according to an example as disclosed herein. For example, the memory system may include an ECC enable component 330 that disables a first error correction capability of the memory system (e.g., Figure 1 ECC circuit 160) based on determining that data read from one or more memory cells of the memory system includes one or more errors of a first type.

[0080] At 415, the method may include reading data from one or more memory cells of a memory device at a second time. The operation of 415 may be performed according to an example as disclosed herein. For example, the memory system may include an access component 325 that reads data from one or more memory cells of a memory device (e.g., Figure 1 memory device 145) at the second time.

[0081] At 420, the method may include reading data from one or more memory cells of a memory system within a second time and transmitting the data to a host device based on determining that the data does not include one or more errors of a first type. The operations of 420 may be performed according to the examples disclosed herein. For example, the memory system may include a communication component 335 that transmits the data to the host device (e.g., Figure 1 host system 105) based on determining that the data does not include one or more errors of a first type and based on reading the data from one or more memory cells of the memory system within the second time.

[0082] In some examples, a device as described herein may perform one or more methods, such as method 400. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure or any combination thereof:

[0083] Aspect 1: A method, device, or non-transitory computer-readable medium that includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: reading data from one or more memory cells of a memory device at a first time; disabling a first error correction capability of the memory system based on determining that data read from one or more memory cells of the memory system includes one or more errors of a first type; reading data from one or more memory cells of the memory device at a second time; and transmitting the data to a host device based on reading the data from one or more memory cells of the memory system within the second time and based on determining that the data does not include one or more errors of a first type.

[0084] Aspect 2: The method, device, or non-transitory computer-readable medium according to aspect 1, wherein determining that data read from one or more memory cells of the memory system includes one or more errors of a first type includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for failing to correct at least one error in the data using a second error correction capability of the memory system.

[0085] Aspect 3: The method, device, or non-transitory computer-readable medium according to aspect 2, wherein the second error correction capability of the memory system includes a RS error correction code.

[0086] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: reading second data from one or more second memory cells of a memory system at a third time; correcting one or more errors in the second data using a second error correction capability of the memory system based on determining that the second data includes one or more errors of a second type; and transmitting the second data to a host device based on correcting one or more errors in the second data using the second error correction capability of the memory system.

[0087] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to Aspect 4, wherein the one or more errors of the first type include uncorrectable errors (UEs), and the one or more errors of the second type include correctable errors (CEs).

[0088] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 5, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: reading third data from one or more third memory cells of a memory system; determining that the third data includes zero errors based on reading the third data from the one or more third memory cells of the memory system; and transmitting the third data to a host device based on determining that the third data includes zero errors.

[0089] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: determining that the data includes one or more errors of a second type based on determining that the data does not include one or more errors of the first type; and correcting the one or more errors of the second type using the second error correction capability of the memory system based on determining that the data includes one or more errors of the second type, wherein transmitting the data to the host device is based on correcting the one or more errors of the second type.

[0090] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, wherein determining that the data does not include one or more errors of the first type includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: determining that the data includes zero errors, wherein transmitting the data to the host device is based on determining that the data includes zero errors.

[0091] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 8, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: reading a first bit value from a mode register of a memory system, wherein the first bit value indicates that a first error correction capability of the memory system is configured to be disabled, and wherein disabling the first error correction capability of the memory system is based on reading the first bit value from the mode register of the memory system.

[0092] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 9, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving, from a host device, a command comprising an indication to write a second bit value to a mode register of the memory system based on determining that data read from one or more memory cells of the memory system includes one or more errors of a first type; and writing the second bit value to the mode register of the memory system based on receiving the command, wherein disabling the first error correction capability of the memory system is based on writing the second bit value to the mode register.

[0093] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to aspect 10, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a secret key from a host device, wherein writing the second bit value to the mode register of the memory system is based on the secret key.

[0094] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 11, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving, from a host device and based on determining that the data includes one or more errors of a first type, a command to reread data from one or more memory cells of the memory system, wherein the command includes an indication to disable the first error correction capability of the memory system.

[0095] Aspect 13: The method, apparatus, or non-transitory computer-readable medium according to aspect 12, wherein the command includes a write command, a write auto-precharge command, a read command, or a read auto-precharge command.

[0096] Aspect 14: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 13, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: enabling the first error correction capability of the memory system based on transferring data to a host device.

[0097] Aspect 15: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 14, wherein the first error correction capability includes on-die ECC.

[0098] Aspect 16: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 15, further comprising operations, features, circuitry, logic, components, or instructions or any combination thereof for: determining that data read from one or more memory cells of a memory system at a first time includes one or more errors of a first type; and determining that data read from one or more memory cells of the memory system at a second time does not include one or more errors of the first type.

[0099] Aspect 17: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 16, further comprising operations, features, circuitry, logic, components, or instructions or any combination thereof for: reading third data from one or more third memory cells of a memory device at a fourth time; rereading the third data from one or more third memory cells of the memory device at a fifth time; and transmitting an indication to a host device based on rereading the third data from one or more third memory cells of the memory system and determining that the third data includes one or more errors of the first type.

[0100] Figure 5 FIG. 500 is a flow diagram showing a method 500 for supporting error correction deactivation by a memory system according to an example as disclosed herein. The operations of method 500 may be implemented by a memory system or its components as described herein. For example, the operations of method 500 may be performed by a memory system as described with reference to Figure 1 to 3 described memory system. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0101] At 505, the method may include reading data from one or more memory cells of a memory device at a first time. The operation of 505 may be performed according to an example as disclosed herein. For example, the memory system may include an access component 325 that reads data from one or more memory cells of a memory device (e.g., Figure 1 memory device 145) at a first time.

[0102] At 510, the method may include failing to correct at least one error in the data using a second error correction capability of the memory system. The operation of 510 may be performed in accordance with the examples disclosed herein. For example, the memory system may include an error correction component 340 that fails to correct at least one error in the data using the second error correction capability of the memory system (e.g., the RS circuit 130).

[0103] At 515, the method may include disabling a first error correction capability of the memory system based on failing to correct at least one error in the data using the second error correction capability of the memory system. The operation of 515 may be performed in accordance with the examples disclosed herein. For example, the memory system may include an ECC enabling component 330 that disables the first error correction capability of the memory system (e.g., Figure 1 the ECC circuit 160) based on failing to correct at least one error in the data using the second error correction capability of the memory system.

[0104] At 520, the method may include reading data from one or more memory cells of a memory device at a second time. The operation of 520 may be performed in accordance with the examples disclosed herein. For example, the memory system may include an access component 325 that reads data from one or more memory cells of a memory device (e.g., Figure 1 the memory device 145) at the second time.

[0105] At 525, the method may include transmitting the data to a host device based on reading the data from one or more memory cells of the memory system at the second time and based on determining that the data does not include one or more errors of a first type. The operation of 525 may be performed in accordance with the examples disclosed herein. For example, the memory system may include a communication component 335 that transmits the data to a host device (e.g., Figure 1 the host system 105) based on determining that the data does not include one or more errors of a first type and based on reading the data from one or more memory cells of the memory system at the second time.

[0106] Note that the aspects described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0107] Any of a variety of different arts and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, or symbols of the signaling that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have various bit widths.

[0108] Switching components (e.g., transistors) discussed herein may be field effect transistors (FETs) and may include a source (e.g., source terminal), a drain (e.g., drain terminal), a channel between the source and the drain, and a gate (e.g., gate terminal). The conductivity of the channel may be controlled (e.g., modulated) by applying a voltage to the gate, which may cause the channel to become conductive in some instances. Examples of switching components may be n-type FETs or p-type FETs.

[0109] The description presented herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or that are within the scope of the claims. The detailed description includes specific details that provide an understanding of the described techniques. However, the techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0110] In the accompanying drawings, like components or features may have the same reference numerals. Like components may be distinguished by following the reference numeral with one or more dashes and an additional numeral that differentiates among the like components. If only the first reference numeral is used in the specification, the description applies to any of the like components having the same first reference numeral regardless of the additional reference numerals.

[0111] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software, hardware, firmware, hardwiring, or any combination of these. The features implementing the functions may be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations.

[0112] The illustrative blocks and modules described herein can be implemented or performed by one or more processors, such as DSPs, ASICs, FPGAs, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof that are designed to perform the functions described herein. The processor can be an example of a microprocessor, a controller, a microcontroller, a state machine, or other types of processors. The processor can also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0113] As used herein, including in the claims, the "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed to refer to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" can be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0114] As used herein, including in the claims, the article "a" before a noun is open-ended and is understood to refer to "at least one of" those nouns or "one or more of" those nouns. Thus, the terms "a", "at least one", "one or more", "at least one of one or more..." can be interchangeable. For example, if a claim recites a "component" that performs one or more functions, each of the individual functions can be performed by a single component or by any combination of multiple components. Thus, the term "component" having a characteristic or performing a function can refer to "at least one of one or more components" having a specific characteristic or performing a specific function. A subsequent reference to a component introduced with the article "a" using the term "the" or "said" can refer to any or all of the one or more said components. For example, a component introduced with the article "a" can be understood to mean "one or more components", and a subsequent reference to "the component" in the claims can be understood to be equivalent to a reference to "at least one of the one or more components". Similarly, a subsequent reference to a component introduced as "one or more components" using the term "the" or "said" can refer to any or all of the one or more said components. For example, a subsequent reference to "the one or more components" in the claims can be understood to be equivalent to a reference to "at least one of the one or more components".

[0115] A computer-readable medium includes both a non-transitory computer storage medium and a communication medium, where the communication medium includes any medium that facilitates transfer of a computer program from one place to another. The non-transitory storage medium can be any available medium that is accessible by a computer, or a combination of multiple media. By way of example and not limitation, the non-transitory computer-readable medium can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage, or other magnetic storage devices, or any other non-transitory medium or combination of media that can be used to carry or store the desired program code components in the form of instructions or data structures and that is accessible by a computer or a processor.

[0116] Descriptions and schematics are provided so that those skilled in the art can make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the techniques disclosed herein can be applied to other variations without departing from the scope of the present disclosure. Accordingly, the present disclosure is not limited to the examples and designs described herein, but is accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method performed by a memory system, comprising: Reading data from one or more memory cells of a memory device at a first time; Deactivating a first error correction capability of the memory system based on determining that data read from the one or more memory cells of the memory system includes one or more errors of a first type; Reading the data from the one or more memory cells of the memory device at a second time; And Transmitting the data to a host device based on reading the data from the one or more memory cells of the memory system at the second time and based on determining that the data does not include the one or more errors of the first type.

2. The method according to claim 1, wherein determining that the data read from the one or more memory cells of the memory system includes the one or more errors of the first type includes: Failing to correct at least one error in the data using a second error correction capability of the memory system.

3. The method according to claim 2, wherein the second error correction capability of the memory system includes a Reed - Solomon error correction code.

4. The method according to claim 1, further comprising: Reading second data from one or more second memory cells of the memory system at a third time; Correcting the one or more errors in the second data using the second error correction capability of the memory system based on determining that the second data includes one or more errors of a second type; And Transmitting the second data to the host device based on correcting the one or more errors in the second data using the second error correction capability of the memory system.

5. The method according to claim 4, wherein: The one or more errors of the first type include uncorrectable errors UE; and The one or more errors of the second type include correctable errors CE.

6. The method according to claim 1, further comprising: Reading third data from one or more third memory cells of the memory system at a third time; Determining that the third data includes zero errors based on reading the third data from the one or more third memory cells of the memory system; And Transmitting the third data to the host device based on determining that the third data includes zero errors.

7. The method according to claim 1, further comprising: Determining that the data includes one or more errors of a second type based on determining that the data does not include the one or more errors of the first type; And Correcting the one or more errors of the second type using the second error correction capability of the memory system based on determining that the data includes the one or more errors of the second type, wherein transmitting the data to the host device is based on correcting the one or more errors of the second type.

8. The method according to claim 1, wherein determining that the data does not include the one or more errors of the first type includes: Determine that the data includes zero errors, wherein transmitting the data to the host device is based on determining that the data includes zero errors.

9. The method according to claim 1, further comprising: Reading a first bit value from a mode register of the memory system, wherein the first bit value indicates that the first error correction capability of the memory system is configured to be disabled, and wherein disabling the first error correction capability of the memory system is based on reading the first bit value from the mode register of the memory system.

10. The method according to claim 1, further comprising: Receiving, from the host device, a command including an indication to write a second bit value to a mode register of the memory system based on determining that the data read from the one or more memory cells of the memory system includes the one or more errors of the first type; And Writing the second bit value to the mode register of the memory system based on receiving the command, wherein disabling the first error correction capability of the memory system is based on writing the second bit value to the mode register.

11. The method according to claim 10, further comprising: Receiving a secret key from the host device, wherein writing the second bit value to the mode register of the memory system is based on the secret key.

12. The method according to claim 1, further comprising: Receiving, from the host device and based on determining that the data includes the one or more errors of the first type, a command to reread the data from the one or more memory cells of the memory system, wherein the command includes an indication to disable the first error correction capability of the memory system.

13. The method according to claim 12, wherein the command includes a write command, a write auto precharge command, a read command, or a read auto precharge command.

14. The method according to claim 1, further comprising: Enabling the first error correction capability of the memory system based on transmitting the data to the host device.

15. The method according to claim 1, wherein the first error correction capability includes an on-die error correction code.

16. The method according to claim 1, further comprising: Determining that the data read from the one or more memory cells of the memory system at the first time includes the one or more errors of the first type; And Determining that the data read from the one or more memory cells of the memory system at the second time does not include the one or more errors of the first type.

17. The method according to claim 1, further comprising: Reading third data from one or more third memory cells of the memory device at a fourth time; Rereading the third data from the one or more third memory cells of the memory device at a fifth time; And Based on rereading the third data from the one or more third memory cells of the memory system, transmitting an indication to the host device based on determining that the third data includes one or more errors of the first type.

18. A non-transitory computer-readable medium storing code, the code including instructions executable by one or more processors to perform the following operations: Read data from one or more memory cells of a memory device at a first time; Disable a first error correction capability of the memory system based on determining that the data read from the one or more memory cells of the memory system includes one or more errors of a first type; Read the data from the one or more memory cells of the memory device at a second time; and Transmit the data to a host device based on reading the data from the one or more memory cells of the memory system at the second time and based on determining that the data does not include the one or more errors of the first type.

19. The non-transitory computer-readable medium of claim 18, wherein the instructions for determining that the data read from the one or more memory cells of the memory system includes one or more errors of the first type are executable by the one or more processors to perform the following operations: Fail to correct at least one error in the data using a second error correction capability of the memory system.

20. The non-transitory computer-readable medium of claim 18, wherein the instructions can further be executed by the one or more processors to perform the following operations: Read second data from one or more second memory cells of the memory system at a third time; Correct the one or more errors in the second data using a second error correction capability of the memory system based on determining that the second data includes one or more errors of a second type; and Transmit the second data to the host device based on correcting the one or more errors in the second data using the second error correction capability of the memory system.

21. The non-transitory computer-readable medium of claim 18, wherein the instructions can further be executed by the one or more processors to perform the following operations: Read third data from one or more third memory cells of the memory system at a third time; Determine that the third data includes zero errors based on reading the third data from the one or more third memory cells of the memory system; and Transmit the third data to the host device based on determining that the third data includes zero errors.

22. The non-transitory computer-readable medium of claim 18, wherein the instructions can further be executed by the one or more processors to perform the following operations: Determine that the data includes one or more errors of a second type based on determining that the data does not include the one or more errors of the first type; and Using a second error correction capability of the memory system to correct the one or more errors of the second type based on determining that the data includes the one or more errors of the second type, wherein transmitting the data to the host device is based on correcting the one or more errors of the second type.

23. The non-transitory computer-readable medium of claim 18, wherein the instructions for determining that the data does not include the one or more errors of the first type are executable by the one or more processors to: Determine that the data includes zero errors, wherein transmitting the data to the host device is based on determining that the data includes zero errors.

24. The non-transitory computer-readable medium of claim 18, wherein the instructions are further executable by the one or more processors to: Read a first bit value from a mode register of the memory system, wherein the first bit value indicates that the first error correction capability of the memory system is configured to be disabled, and wherein disabling the first error correction capability of the memory system is based on reading the first bit value from the mode register of the memory system.

25. A memory system, comprising: One or more memory devices; And Processing circuitry coupled to the one or more memory devices and configured to cause the memory system to: Read data from one or more memory cells of a memory device at a first time; Disable a first error correction capability of the memory system based on determining that data read from the one or more memory cells of the memory system includes one or more errors of a first type; Read the data from the one or more memory cells of the memory device at a second time; And Transmit the data to a host device based on reading the data from the one or more memory cells of the memory system at the second time and based on determining that the data does not include the one or more errors of the first type.

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