Test method and test system for double BIOSs (Basic Input Output System)

Abstract

The invention discloses a double BIOS testing method and system, and relates to the technical field of BIOS fault testing, and the method comprises the steps: controlling double BIOS simulation target faults of a tested device through a control machine, i.e., one of BIOS link short circuit, BIOS firmware faults and SETUP interface jamming, enabling the double BIOS to fail to start due to the target faults, obtaining logs of the double BIOS failing to start due to the target faults, and sending the logs to the tested device; whether the tested device passes the fault test of the target fault is determined according to whether the log accords with the expectation, and the partition of the double BIOS does not need to be damaged, so that the fault test can be realized through the double BIOS fault, that is, various fault tests can be performed without damaging the double BIOS, the stability of the tested device after the test is ensured, and the test efficiency is improved. The problem that double BIOSs of the storage device are damaged by a test method in the prior art is solved.

Description

Technical Field

[0001] This application relates to the technical field of BIOS fault testing, and particularly to dual-BIOS fault testing. Background Art

[0002] The dual-BIOS technology improves the reliability of storage devices through redundant design. The main BIOS is responsible for daily startup, and the backup BIOS is responsible for taking over the system when the main BIOS fails, thereby enhancing the fault tolerance of the system. However, most of the existing testing methods have deficiencies. For example, traditional methods rely on damaging the BIOS partition, cannot simulate real hardware link failures, have a single test scenario, high test risks (easy to cause system crashes due to physical damage, etc.), and low efficiency of manual testing.

[0003] The existing technologies mainly have the following technical problems:

[0004] (1) Most of the currently disclosed methods are development and design schemes for dual-BIOS, and there are few methods related to dual-BIOS testing;

[0005] (2) The existing technologies only support a single scenario when the BIOS firmware is damaged and cannot simulate faults such as link interruption and SETUP interface freeze;

[0006] (3) Some methods need to modify the BIOS partition information or physically damage the chip, affecting the subsequent stability of the system;

[0007] (4) It is impossible to achieve full automation testing, and manual operation has high risks and low test efficiency and coverage. Summary of the Invention

[0008] This application provides a testing method and a testing system for dual-BIOS to at least solve the problem that the testing method in the related technologies damages the dual-BIOS of the storage device.

[0009] This application provides a testing method for dual-BIOS. The testing method is applied to a testing system for dual-BIOS. The testing system for dual-BIOS includes a control machine, and the control machine is communicatively connected to the device under test. The method includes: the control machine controls the dual-BIOS of the device under test to simulate a target fault, so that the dual-BIOS fails to start due to the target fault, and the target fault includes at least one of BIOS link short circuit, BIOS firmware fault, and SETUP interface freeze; the control machine receives the log of the dual-BIOS failing to start due to the target fault; the control machine determines whether the device under test passes the fault test of the target fault according to the log.

[0010] The present application also provides a dual-BIOS test system. The dual-BIOS test system includes a control machine, which is communicatively connected to the device under test. The control machine includes: a control unit for controlling the dual BIOS of the device under test to simulate a target fault, such that the dual BIOS fails to start due to the target fault, where the target fault includes at least one of a BIOS link short circuit, a BIOS firmware fault, and a SETUP interface freeze; a receiving unit for receiving the log of the dual BIOS failing to start due to the target fault; and a first determination unit for determining whether the device under test passes the fault test of the target fault according to the log.

[0011] Through the present application, the control machine controls the dual BIOS of the device under test to simulate a target fault, that is, at least one of a BIOS link short circuit, a BIOS firmware fault, and a SETUP interface freeze, such that the dual BIOS fails to start due to the target fault, and obtains the log of the dual BIOS failing to start due to the target fault. It is determined whether the device under test passes the fault test of the target fault according to whether the log meets the expectation. There is no need to damage the partition of the dual BIOS to cause a dual-BIOS fault to implement the fault test, that is, various fault tests can be performed without damaging the dual BIOS, ensuring the stability of the device under test after the test, and solving the problem that the test method in the prior art damages the dual BIOS of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 It is a flowchart of a method for testing a dual BIOS provided by an embodiment of the present application;

[0014] Figure 2 It is a flowchart of another method for testing a dual BIOS provided by an embodiment of the present application;

[0015] Figure 3 It is a connection diagram of a dual-BIOS test system provided by an embodiment of the present application;

[0016] Figure 4 It is a structural block diagram of a control machine provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0018] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0019] In order to enable those skilled in the art of the present technology to better understand the solutions of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0020] In combination with the specific application environment architecture or specific hardware architecture on which the execution of the test method of dual BIOS depends, the specific application environment architecture or specific hardware architecture is described herein.

[0021] The term explanations are as follows:

[0022] BIOS: Basic Input Output System, a firmware program that runs when the storage device starts up, responsible for hardware initialization and system boot;

[0023] Dual BIOS: including a main BIOS and a backup BIOS, a technology that automatically switches to the backup BIOS when the main BIOS is abnormal;

[0024] POST hardware self-test (Power-On Self-Test): the first stage of BIOS startup;

[0025] SETUP interface: the BIOS setup menu, used to configure hardware parameters and startup order;

[0026] Short circuit: forcibly conduct the circuit through a physical connection to simulate a hardware link failure;

[0027] Interface freeze: refers to the situation where the user interface of a computer software or system stops responding to the user's input operations and cannot update the display content normally, being in a frozen state.

[0028] Embodiments of the present application provide a method for testing a dual BIOS. The method is described in detail in combination with the execution process of the method for testing the dual BIOS.

[0029] This test method is applied to a dual BIOS test system. The dual BIOS test system includes a control machine, which is communicatively connected to the device under test, as Figure 1 shown. This test method includes:

[0030] Step S101, the control machine controls the dual BIOS of the device under test to simulate a target fault, so that the dual BIOS fails to start due to the target fault. The target fault includes at least one of a BIOS link short circuit, a BIOS firmware fault, and a SETUP interface freeze.

[0031] Specifically, there are various target faults that need to be tested for faults, including hardware faults and software faults. The hardware faults include a BIOS link short circuit, and the software faults include a BIOS firmware fault and a SETUP interface freeze. The control machine controls the dual BIOS of the device under test to simulate these target faults, so that the dual BIOS fails to start due to the target fault, and the fault test of the target fault is realized.

[0032] Step S102, the control machine receives the log of the dual BIOS failing to start due to the target fault.

[0033] Specifically, when the dual BIOS fails to start due to the target fault, corresponding logs will be output. The control machine reads these logs through the serial port during the test.

[0034] Step S103, the control machine determines whether the device under test passes the fault test of the target fault according to the log.

[0035] Specifically, the control machine analyzes the fields in the log to determine whether there are fields that meet the expectations. For example, when the dual BIOS fails to start due to the target fault, the output log will include fields indicating the startup failure.

[0036] In the above test method, by controlling the dual BIOS of the device under test by the control machine to simulate a target fault, that is, at least one of a BIOS link short circuit, a BIOS firmware fault, and a SETUP interface freeze, the dual BIOS fails to start due to the target fault, and the log of the dual BIOS failing to start due to the target fault is obtained. Whether the device under test passes the fault test of the target fault is determined according to whether the log meets the expectations. It is not necessary to damage the partition of the dual BIOS to cause a dual BIOS fault to implement the fault test, that is, various fault tests can be performed without damaging the dual BIOS, ensuring the stability of the device under test after the test, and solving the problem that the existing test method damages the dual BIOS of the storage device.

[0037] In order to achieve comprehensive testing of faults, in an alternative implementation, the dual BIOS includes a main BIOS chip and a backup BIOS chip, and the above step S101 includes:

[0038] Step S1011, the control machine controls the main BIOS chip of the device under test to simulate a target fault, so that the main BIOS chip fails to start due to the target fault;

[0039] Step S1012, after the main BIOS chip fails to start due to the target fault, when the device under test switches to start with the backup BIOS chip, the control machine controls the backup BIOS chip of the device under test to simulate the target fault, so that the backup BIOS chip fails to start due to the target fault.

[0040] In the above implementation, the dual BIOS includes a main BIOS chip and a backup BIOS chip. Both the main BIOS chip and the backup BIOS chip need to be tested for faults. Since the device under test boots by default through the main BIOS chip when powered on, first, the control machine controls the main BIOS chip of the device under test to simulate a target fault, so that the main BIOS chip fails to start due to the target fault, achieving the fault test of the target fault of the main BIOS chip. After the main BIOS chip fails to start due to the target fault, the device under test will automatically switch to start with the backup BIOS chip. Then, the control machine controls the backup BIOS chip of the device under test to simulate the target fault, so that the backup BIOS chip fails to start due to the target fault, achieving the fault test of the target fault of the backup BIOS chip.

[0041] In order to achieve the fault test of BIOS link short - circuit and BIOS firmware fault, in an alternative implementation, the test system of the dual BIOS further includes a first switch and a second switch. Both the first switch and the second switch are communicatively connected to the control machine. The main BIOS chip includes a first SPI line and a first main - board GND ground wire, and the backup BIOS chip includes a second SPI line and a second main - board GND ground wire. The first switch is located on the connection line between the first SPI line and the first main - board GND ground wire, and the second switch is located on the connection line between the second SPI line and the second main - board GND ground wire. The above step S1011 includes:

[0042] Step S10111, the control machine controls the device under test to shut down;

[0043] Step S10112, the control machine controls the first switch to conduct and the second switch to disconnect, so that the first SPI line and the first main - board GND ground wire of the main BIOS chip are short - circuited to simulate a first BIOS link short - circuit, or the control machine flashes faulty firmware to the main BIOS chip, so that the main BIOS chip simulates a BIOS firmware fault. The first BIOS link short - circuit is one type of BIOS link short - circuit;

[0044] Step S10113, the control machine controls the device under test to power on, causing the main BIOS chip to fail to start due to a short circuit in the BIOS link or a BIOS firmware failure.

[0045] In the above embodiment, when the device under test is powered on, a short circuit in the BIOS link or a BIOS firmware failure of the main BIOS chip may pose a security risk or damage the device under test. Therefore, first control the device under test to power off, and then control the main BIOS chip of the device under test to simulate a short circuit in the BIOS link or a BIOS firmware failure. Among them, the first switch and the second switch can be relays, and the control machine can issue instructions to control the on / off of the first switch and the second switch. The short circuit of the BIOS link includes the short circuit of the first BIOS link of the main BIOS chip. Since the first switch is located on the connection line between the first SPI line and the first main board GND ground wire, when the control machine controls the first switch to conduct, the first SPI line of the main BIOS chip and the first main board GND ground wire can be shorted to simulate the short circuit of the first BIOS link, that is, the communication failure of the main BIOS chip. The first BIOS link is the link for the main BIOS chip to communicate through the first SPI line. When the second switch is off, the second BIOS link is not shorted, and the backup BIOS chip has no communication failure. Or, when the main BIOS chip has no failure, the faulty firmware is flashed to the main BIOS chip, which can make the main BIOS chip simulate a BIOS firmware failure. Finally, control the device under test to power on, causing the main BIOS chip to fail to start due to a short circuit in the BIOS link or a BIOS firmware failure during the startup process, realizing the fault test of the short circuit of the BIOS link or the BIOS firmware failure of the main BIOS chip.

[0046] It should be noted that the device under test can be powered on normally by default without failure of the main BIOS chip. Of course, it can be detected before the test to ensure that the main BIOS chip has no failure before performing the fault test to avoid startup failure caused by other failures.

[0047] In order to implement the fault test of the short circuit of the BIOS link and the BIOS firmware failure, in an optional embodiment, the dual-BIOS test system further includes a first switch and a second switch. Both the first switch and the second switch are communicatively connected to the control machine. The main BIOS chip includes a first SPI line and a first main board GND ground wire, and the backup BIOS chip includes a second SPI line and a second main board GND ground wire. The first switch is located on the connection line between the first SPI line and the first main board GND ground wire, and the second switch is located on the connection line between the second SPI line and the second main board GND ground wire. The above step S1012 includes:

[0048] Step S10121: After the main BIOS chip fails to start due to a target fault, when the device under test switches to the backup BIOS chip for startup and the backup BIOS chip starts successfully, the control machine controls the device under test to shut down.

[0049] Step S10122: The control machine controls the first switch to disconnect and the second switch to conduct, so that the second SPI line of the backup BIOS chip is shorted to the second main board GND ground wire to simulate a short circuit of the second BIOS link. Alternatively, the control machine flashes the faulty firmware to the backup BIOS chip, so that the backup BIOS chip simulates a BIOS firmware fault. The short circuit of the second BIOS link is another type of short circuit of the BIOS link.

[0050] Step S10123: The control machine controls the device under test to power on, so that the backup BIOS chip fails to start due to a short circuit of the BIOS link or a BIOS firmware fault.

[0051] In the above embodiment, when the main BIOS chip fails to start due to a target fault, the device under test will automatically switch to the backup BIOS chip for startup. If the backup BIOS chip starts successfully, it indicates that the backup BIOS chip has no current fault, avoiding startup failure caused by other faults. Then, the control machine controls the device under test to shut down, and then controls the backup BIOS chip of the device under test to simulate a short circuit of the BIOS link or a BIOS firmware fault. Among them, the first switch and the second switch can be relays, and the control machine can issue instructions to control the on and off of the first switch and the second switch. The short circuit of the BIOS link also includes the short circuit of the second BIOS link of the backup BIOS chip. Since the second switch is located on the connection line between the second SPI line and the second main board GND ground wire, the control machine controls the second switch to conduct, and the second SPI line of the backup BIOS chip can be shorted to the second main board GND ground wire to simulate a short circuit of the second BIOS link, that is, a communication fault of the backup BIOS chip. The second BIOS link is the link for the main BIOS chip to communicate through the second SPI line. When the first switch is disconnected, the first BIOS link is not shorted, and the main BIOS chip has no communication fault. Or, when the backup BIOS chip has no fault, flashing the faulty firmware to the backup BIOS chip can make the backup BIOS chip simulate a BIOS firmware fault. Finally, the control machine controls the device under test to power on, so that the backup BIOS chip fails to start during startup due to a short circuit of the BIOS link or a BIOS firmware fault, realizing the fault test of the short circuit of the BIOS link or the BIOS firmware fault of the backup BIOS chip.

[0052] In order to implement the fault test for the SETUP interface getting stuck, in an optional embodiment, the above step S1011 includes:

[0053] Step S10114, the control machine controls the device under test to power on;

[0054] Step S10115, during the startup process of the main BIOS chip of the device under test, the control machine controls the device under test to enter the SETUP interface, and controls the device under test to keep the SETUP interface unchanged for more than a predetermined duration or controls the device under test to continuously switch between sub-interfaces of the SETUP interface, so as to simulate that the startup fails due to the SETUP interface getting stuck during the startup of the main BIOS chip.

[0055] In the above embodiment, when the main BIOS chip is fault-free, the control machine controls the device under test to power on. The device under test defaults to start through the main BIOS chip. During the startup process, the control machine controls the device under test to enter the SETUP interface, and controls the device under test to keep the SETUP interface unchanged for more than a predetermined duration or controls the device under test to continuously switch between sub-interfaces of the SETUP interface. Both of these conform to the manifestations of the SETUP interface getting stuck, thus simulating that the startup fails due to the SETUP interface getting stuck during the startup of the main BIOS chip, and realizing the fault test of the SETUP interface getting stuck during the startup of the main BIOS chip. It should be noted that the user operating the device under test can achieve controlling the device under test to keep the SETUP interface unchanged for more than a predetermined duration or controlling the device under test to continuously switch between sub-interfaces of the SETUP interface. However, the test method of this application is to control the device under test to keep the SETUP interface unchanged for more than a predetermined duration or control the device under test to continuously switch between sub-interfaces of the SETUP interface by the control machine issuing instructions, ensuring that the test is fully automated.

[0056] To implement the fault test of the SETUP interface getting stuck, in an optional embodiment, the above step S1012 includes:

[0057] Step S10124, after the main BIOS chip fails to start due to a target fault and the device under test switches to start with the backup BIOS chip and the backup BIOS chip starts successfully, the control machine controls the device under test to power off;

[0058] Step S10125, the control machine controls the device under test to power on;

[0059] Step S10126, during the startup process of the backup BIOS chip of the device under test, the control machine controls the device under test to enter the SETUP interface, and controls the device under test to keep the SETUP interface unchanged for more than a predetermined duration or controls the device under test to continuously switch between sub-interfaces of the SETUP interface, so as to simulate that the startup fails due to the SETUP interface getting stuck during the startup of the backup BIOS chip.

[0060] In the above embodiments, after the main BIOS chip fails to start due to a target fault, the device under test switches to the backup BIOS chip for startup and the backup BIOS chip starts successfully, indicating that the backup BIOS chip has no current fault. Then, the device under test is controlled to shut down and restart. Since the main BIOS chip failed to start and the backup BIOS chip started successfully before, the device under test will directly use the backup BIOS chip to start when restarted. During the startup process of the backup BIOS chip of the device under test, the device under test is controlled to enter the SETUP interface, and the device under test is controlled to keep the SETUP interface unchanged for more than a predetermined duration or the device under test is controlled to continuously switch between the sub-interfaces of the SETUP interface. For example, the startup order is repeatedly switched. Both of these conform to the performance of the SETUP interface being stuck, so as to simulate the startup failure caused by the SETUP interface being stuck when the backup BIOS chip starts, and realize the fault test of the SETUP interface being stuck when the backup BIOS chip starts.

[0061] In order to verify whether the fault test is passed, in an optional embodiment, the above step S103 includes:

[0062] Step S1031, the control machine reads the first log, and the first log is the log of the main BIOS chip failing to start due to a target fault;

[0063] Step S1032, the control machine reads the second log, and the second log is the log of the backup BIOS chip failing to start due to a target fault;

[0064] Step S1033, when it is satisfied that there is a failure in the main BIOS chip startup and a switch to the backup BIOS chip in the first log, the switching duration is less than the automatic switching timeout duration, there is a failure in the backup BIOS chip startup in the second log, and the downtime duration is less than the timeout downtime duration, it is determined that the device under test passes the fault test of the target fault. The switching duration is the interval duration between the moment when the main BIOS chip has a target fault and the moment of switching to the backup BIOS chip, and the downtime duration is the interval duration between the moment when the backup BIOS chip has a target fault and the moment when the device under test shuts down.

[0065] In the above embodiments, the logs of the main BIOS chip failing to start due to target faults (BIOS link short circuit, BIOS firmware failure, and SETUP interface freeze) and the logs of the backup BIOS chip failing to start due to target faults are obtained, namely the first log and the second log. The existence of the main BIOS chip failing to start and switching to the backup BIOS chip in the first log indicates that when the main BIOS chip fails to start due to target faults (BIOS link short circuit, BIOS firmware failure, and SETUP interface freeze), it can automatically switch to the backup BIOS chip for startup, and the switching duration is less than the automatic switching timeout duration, indicating that the switching speed also meets the requirements. The existence of the backup BIOS chip failing to start in the second log indicates that when the backup BIOS chip fails to start due to target faults (BIOS link short circuit, BIOS firmware failure, and SETUP interface freeze), it can automatically trigger a shutdown, and the shutdown duration is less than the timeout shutdown duration, indicating that the speed of triggering the shutdown also meets the requirements. If all these conditions are met, it indicates that when the main BIOS chip and the backup BIOS chip encounter faults such as BIOS link short circuit, BIOS firmware failure, and SETUP interface freeze, they can be automatically processed in a timely manner to avoid damaging the device under test, and then the device under test passes the fault test of the target faults (BIOS link short circuit, BIOS firmware failure, and SETUP interface freeze).

[0066] In an alternative embodiment, in order to verify whether the device under test is damaged by the test, before the dual BIOS of the device under test is controlled by the control machine to simulate target faults and cause the dual BIOS to fail to start due to target faults, the test method further includes:

[0067] Step S201, the control machine writes different specific data files in different directories of the device under test;

[0068] After the control machine determines whether the device under test passes the fault test of the target faults according to the logs, the test method further includes:

[0069] Step S202, when the device under test passes the fault test of the target faults and all the specific data files remain unchanged, the control machine determines that the device under test is not damaged by the test.

[0070] In the above embodiments, before the test starts, different specific data files are written in different directories of the device under test respectively. After the test is completed, check whether all the specific data files remain unchanged. If they remain unchanged, it indicates that the device under test is not damaged by the test, otherwise the device under test has been damaged by the test, and thus it can be verified that the test method of the present application does not damage the device under test.

[0071] In an alternative embodiment, in order to verify whether the device under test is damaged by the test, the above step S201 includes:

[0072] Step S2011, the control machine logs in to the operating system of the device under test;

[0073] Step S2012, the control machine writes different specific data files in different directories of the operating system of the device under test;

[0074] The above-mentioned step S202 includes:

[0075] Step S2021, when the device under test passes the fault test of the target fault, the control machine sends a restart command to the device under test to control the device under test to perform a cold restart after power-off;

[0076] Step S2022, when the main BIOS chip of the device under test passes the self-check and the operating system is successfully started, the control machine logs in to the operating system of the device under test;

[0077] Step S2023, the control machine reads the specific data files stored in the device under test, and determines that the device under test is not damaged by the test when all the specific data files are not lost and the md5 values of all the specific data files remain unchanged.

[0078] In the above-mentioned embodiment, the control machine reads the configuration file, logs in to the OS environment of the device under test through the SSH method, writes different data files in different directories, and records their md5 values. After the test is completed, the device under test crashes. The control machine uses the ipmitool tool to send a command to power off and cold restart the device under test; the controller checks through the log. After the device under test is cold restarted, it should start from the main BIOS again, pass the self-check successfully in the POST stage, and successfully start the operating system; and log in to the operating system of the device under test through the SSH method to read and check whether the previously written data is not lost, and whether the md5 value of the file is the same as the previously recorded md5 value. If so, it is determined that the device under test is not damaged by the test.

[0079] It should be noted that the above test method for each type of fault needs to be tested multiple times, and only when all the multiple tests pass can it be determined that the fault test is passed.

[0080] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0081] In order to enable those skilled in the art to understand the technical solution of the present application more clearly, the implementation process of the dual-BIOS test method of the present application will be described in detail below with specific embodiments.

[0082] This embodiment relates to a specific dual - BIOS testing method, as Figure 2 shown, and includes the following steps:

[0083] (1) The test system composition is as Figure 3 shown:

[0084] Device under test: A storage device supporting dual - BIOS, equipped with a main BIOS chip, a short - circuitable SPI line interface (such as CLK) for the backup BIOS chip, and a motherboard GND ground wire interface;

[0085] Link short - circuit control module: Connects the SPI line of the main BIOS chip and the motherboard GND ground wire, and the SPI line of the backup BIOS chip and the motherboard GND ground wire, with a total of 2 short - circuit links. Controls the switch through a relay and connects the relay to the control machine;

[0086] Serial serial line: Connects the serial port of the storage device under test and the USB port of the control machine;

[0087] Control machine: The control machine and the device under test are in the same network environment. It can transmit firmware and commands to the device under test through the network, can control the link communication between the main BIOS and the backup BIOS by opening and closing the relay, and can also obtain the log information output during the test of the device under test through the serial port.

[0088] (2) Initialize the test configuration:

[0089] A. Write the IP address, BMC address, SSH login account name / password, and the addresses of the main BIOS and the backup BIOS of the storage device under test into the configuration file;

[0090] B. Store the BIOS faulty firmware and normal firmware in a specific directory of the control machine;

[0091] C. Create a directory and files for storing logs in the control machine environment.

[0092] (3) The control machine reads the configuration file, logs in to the OS environment of the device under test through SSH, writes different data files in different directories, and records their md5 values;

[0093] (4) Use the short - circuit BIOS link communication method for testing:

[0094] A. The control machine uses the ipmitool tool through BMC to issue a shutdown command to the device under test;

[0095] B. After the shutdown is completed, the control machine controls the relay to short - circuit the SPI line of the main BIOS chip and the motherboard GND ground wire, making the link communication of the main BIOS chip abnormal;

[0096] C. The control machine uses the ipmitool tool through the BMC to send a power-on startup command to the device under test;

[0097] D. During the startup process of the device under test, the control machine reads the log information to view the current startup process. The main BIOS failure should be detected during the POST self-check stage, and relevant similar information such as "Start BIOS 0 Failed" and "Switch to BIOS1 Boot" should be present in the log to verify whether the dual-BIOS mechanism of the storage device under test can automatically trigger a boot from the backup BIOS after the main BIOS startup fails; and record the time from detecting the main BIOS failure in the POST stage to switching to the backup BIOS to verify whether it meets the automatic switching timeout duration designed by the dual-BIOS mechanism;

[0098] E. After the operating system is successfully booted from the backup BIOS in step D, the control machine uses the ipmitool tool through the BMC to send a shutdown command to the device under test;

[0099] F. After the shutdown is completed, the control machine controls the relay to short-circuit the SPI line of the backup BIOS chip and the motherboard GND ground wire to make the backup BIOS chip link communication abnormal;

[0100] G. The control machine uses the ipmitool tool through the BMC to send a power-on startup command to the device under test;

[0101] H. During the startup process of the device under test, the control machine reads the log information to view the current startup process. The storage device under test should directly boot from the backup BIOS. After the backup BIOS failure is detected during the POST self-check stage, it should directly enter the down state, and relevant similar information such as "Start BIOS1 Failed" should be present in the log to verify whether the dual-BIOS mechanism of the storage device can automatically trigger a shutdown after the backup BIOS startup fails; and record the time from detecting the backup BIOS failure in the POST stage to the shutdown to verify whether it meets the timeout shutdown duration designed by the dual-BIOS mechanism;

[0102] I. After the device under test shuts down, the control machine closes the short-circuit links between the main BIOS and the GND ground wire, and between the backup BIOS and the GND ground wire through the control module relay to restore the communication links of both the main BIOS and the backup BIOS to normal;

[0103] J. The control machine uses the ipmitool tool to send a command to power off the device under test and restart it cold;

[0104] K. Through log viewing on the controller, after the device under test is restarted from a cold start, it should restart from the main BIOS, pass the self-check during the POST stage successfully, and start the operating system successfully; then log in to the operating system of the device under test via SSH, and check whether the data written in step (3) is not lost and whether the md5 value of the file is the same as the previously recorded md5 value.

[0105] L. Repeat steps A - K for multiple rounds; if the results of each step meet the set expectations, it can be determined that the dual BIOS is verified to pass through the short-circuit BIOS link communication method.

[0106] (5) Conduct tests using the method of flashing the faulty BIOS firmware:

[0107] A. The controller transfers the BIOS faulty firmware to the device under test via a network path such as SCP, and uses the firmware flashing command to flash the faulty firmware into the main BIOS.

[0108] B. The controller issues a shutdown command to the device under test through the BMC using the ipmitool tool.

[0109] C. The controller issues a startup command to the device under test through the BMC using the ipmitool tool.

[0110] D. During the startup process of the device under test, the controller reads the log information to view the current startup process. The main BIOS failure should be detected during the POST self-check stage, and relevant similar information such as "Start BIOS 0Failed" and "Switchto BIOS1 Boot" should be present in the log to verify whether the dual BIOS mechanism of the storage device can automatically trigger a startup from the backup BIOS after the main BIOS startup fails; and record the time from detecting the main BIOS failure during the POST stage to switching to the backup BIOS to verify whether it meets the automatic switching timeout duration designed by the dual BIOS mechanism.

[0111] E. After the operating system is successfully started from the backup BIOS in step D, the controller transfers the normal BIOS firmware and the faulty firmware to the device under test via a network path such as SCP, and uses the firmware flashing command to flash the normal firmware into the main BIOS and the faulty firmware into the backup BIOS.

[0112] F. Issue a shutdown command to the device under test through the BMC using the ipmitool tool.

[0113] G. The controller issues a startup command to the device under test through the BMC using the ipmitool tool.

[0114] H. During the startup process of the device under test, the control machine reads the log information to view the current startup process. The storage device under test should directly boot from the backup BIOS. If a failure occurs in the backup BIOS, it should directly crash after being detected during the POST self-check phase, and relevant similar information such as "Start BIOS1Failed" should be present in the log to verify whether the dual-BIOS mechanism of the storage device can automatically trigger a crash after the backup BIOS fails to boot; and record the time from detecting the backup BIOS failure in the POST phase to the crash to verify whether it meets the timeout crash duration designed by the dual-BIOS mechanism;

[0115] I. After the device under test crashes, the control machine uses the ipmitool tool to send a command to power off and then cold start the device under test;

[0116] J. Through log viewing by the controller, after the device under test is cold started again, it should restart from the main BIOS, pass the self-check successfully in the POST phase, and successfully start the operating system; and log in to the operating system of the device under test via SSH to check whether the data written in step (3) is not lost and whether the md5 value of the file is the same as the previously recorded md5 value;

[0117] K. After successfully starting the operating system from the main BIOS in step J, the control machine transfers the normal BIOS firmware to the device under test via a network method such as SCP and writes the normal firmware to the backup BIOS through a firmware flashing command;

[0118] L. Repeat steps A - K multiple rounds. If the results of each step meet the set expectations, it can be determined that the dual-BIOS is verified by flashing the faulty BIOS firmware.

[0119] (6) Conduct tests using the method of the SETUP interface getting stuck:

[0120] A. The control machine uses the ipmitool tool through the BMC to send a shutdown command to the device under test;

[0121] B. The control machine uses the ipmitool tool through the BMC to send a startup command to the device under test;

[0122] C. During the startup process of the device under test, after the self-check in the POST phase passes, when the control machine boots in the BIOS phase, it sends the DELETE key through the serial port to make the device under test enter the SETUP interface and perform loop operations such as repeatedly switching the startup order to simulate the SETUP interface getting stuck;

[0123] D. The control machine reads the log information to view the current startup process. After staying at the SETUP interface for a certain period of time, the dual-BIOS mechanism should determine that the main BIOS startup has timed out, and relevant similar information such as "Switch to BIOS1 Boot" should be present in the log to verify whether the dual-BIOS mechanism of the storage device automatically triggers a boot from the backup BIOS after the main BIOS fails to start. Also, record the time from when it is detected to enter the SETUP interface to when it switches to the backup BIOS to verify whether it meets the automatic switch timeout duration designed by the dual-BIOS mechanism.

[0124] E. After the operating system is successfully booted from the backup BIOS in step D, the control machine uses the ipmitool tool through the BMC to issue a shutdown command to the device under test.

[0125] F. The control machine uses the ipmitool tool through the BMC to issue a power-on startup command to the device under test.

[0126] G. During the startup process of the device under test, after the POST stage self-check passes, when the control machine boots at the BIOS stage, it issues the DELETE key through the serial port to make the device under test enter the SETUP interface and perform loop operations such as repeatedly switching the startup order to simulate the SETUP interface getting stuck.

[0127] H. During the startup process of the device under test, the control machine reads the log information to view the current startup process. After staying at the SETUP interface for a certain period of time, the dual-BIOS mechanism should determine that the backup BIOS startup has timed out and enters the crashed state to verify whether the dual-BIOS mechanism of the storage device automatically triggers a crash after the backup BIOS fails to start. Also, record the time from when it is detected to enter the SETUP interface to when it switches to the crashed state to verify whether it meets the timeout crash duration designed by the dual-BIOS mechanism.

[0128] I. After the device under test crashes, the control machine uses the ipmitool tool to issue a command to power off the device and perform a cold restart.

[0129] J. Through log viewing by the controller, the device under test should start from the main BIOS again after a cold restart, and can successfully pass the self-check in the POST stage and the BIOS stage, and successfully start the operating system. Also, log in to the operating system of the device under test through SSH to read whether the data written in step (3) is not lost and whether the md5 value of the file is the same as the previously recorded md5 value.

[0130] K. Repeat steps A - J multiple rounds. If the results of each step meet the set expectations, it can be determined that the dual-BIOS is verified to pass by using the method of simulating the SETUP interface getting stuck.

[0131] (7) If the actual results of steps (4), (5), and (6) all meet the set expectations, it can be determined that the dual-BIOS test verification passes; if there is any inconsistent phenomenon, the dual-BIOS test verification fails.

[0132] The above test method has the following effects: (1) Support storage devices for master-slave BIOS switching; (2) Control modules: control machine, link short-circuit control module (relay), serial port, used to simulate link interruption, flash the normal firmware of the faulty machine, and simulate the SETUP interface freeze failure; (3) Automated testing, through BMC, operating system network, serial port device, control module, to achieve automatic fault triggering and result analysis; (4) More comprehensive detection items: detect startup logs, master-slave BIOS switching timeout duration, downtime timeout duration, pre-written data and MD5 values, etc.

[0133] An embodiment of the present application also provides a dual-BIOS test system. The dual-BIOS test system includes a control machine, and the control machine is communicatively connected to the device under test, as Figure 4 shown, the control machine includes:

[0134] A control unit 10, configured to control the dual-BIOS of the device under test to simulate target faults, so that the dual-BIOS fails to start due to the target faults, and the target faults include at least one of BIOS link short-circuit, BIOS firmware fault, and SETUP interface freeze;

[0135] Specifically, there are various target faults that need to be tested for faults, including hardware faults and software faults. The hardware faults include BIOS link short-circuit, and the software faults include BIOS firmware fault and SETUP interface freeze. The control machine controls the dual-BIOS of the device under test to simulate these target faults, so that the dual-BIOS fails to start due to the target faults, and the fault test of the target faults is realized.

[0136] A receiving unit 20, configured to receive the log of the dual-BIOS failing to start due to the target faults;

[0137] Specifically, when the dual-BIOS fails to start due to the target faults, corresponding logs will be output, and the control machine reads these logs through the serial port during the test.

[0138] A first determination unit 30, configured to determine whether the device under test passes the fault test of the target faults according to the log.

[0139] Specifically, the control machine analyzes the fields in the log to determine whether there are fields that meet the expectations. For example, when the dual-BIOS fails to start due to the target faults, the output log will include fields indicating startup failure.

[0140] In the above test method for dual BIOS, the control module controls the dual BIOS of the device under test to simulate target faults, namely, at least one of BIOS link short circuit, BIOS firmware failure, and SETUP interface freeze, so that the dual BIOS fails to start due to the target fault. The receiving module obtains the log of the dual BIOS failure to start due to the target fault, and the determination module determines whether the device under test passes the fault test of the target fault according to whether the log meets the expectation. It is not necessary to damage the partition of the dual BIOS to achieve the fault test by causing the dual BIOS fault, that is, various fault tests can be carried out without damaging the dual BIOS, ensuring the stability of the device under test after the test, and solving the problem that the existing test method damages the dual BIOS of the storage device.

[0141] In order to achieve a comprehensive test of faults, in an optional implementation, the dual BIOS includes a main BIOS chip and a backup BIOS chip, and the control unit includes:

[0142] The first control subunit is used to control the main BIOS chip of the device under test to simulate the target fault, so that the main BIOS chip fails to start due to the target fault;

[0143] The second control subunit is used to control the backup BIOS chip of the device under test to simulate the target fault when the device under test switches to start with the backup BIOS chip after the main BIOS chip fails to start due to the target fault, so that the backup BIOS chip fails to start due to the target fault.

[0144] In order to implement the fault tests of BIOS link short circuit and BIOS firmware failure, in an optional implementation, the test system for dual BIOS further includes a first switch and a second switch. Both the first switch and the second switch are communicatively connected to the control machine. The main BIOS chip includes a first SPI line and a first motherboard GND ground wire, and the backup BIOS chip includes a second SPI line and a second motherboard GND ground wire. The first switch is located on the connection line between the first SPI line and the first motherboard GND ground wire, and the second switch is located on the connection line between the second SPI line and the second motherboard GND ground wire. The first control subunit includes:

[0145] The first control module is used to control the device under test to shut down;

[0146] The second control module is used to control the control machine to turn on the first switch and turn off the second switch, so that the first SPI line and the first motherboard GND ground wire of the main BIOS chip are shorted to simulate the first BIOS link short circuit, or the control machine flashes the faulty firmware to the main BIOS chip, so that the main BIOS chip simulates the BIOS firmware failure. The first BIOS link short circuit is a kind of BIOS link short circuit;

[0147] A third control module is used to control the device under test to power on, so that the main BIOS chip fails to start due to a short circuit in the BIOS link or a BIOS firmware failure.

[0148] To implement the fault tests for BIOS link short circuit and BIOS firmware failure, in an optional implementation, the dual-BIOS test system further includes a first switch and a second switch. Both the first switch and the second switch are communicatively connected to the control machine. The main BIOS chip includes a first SPI line and a first main board GND ground wire, and the backup BIOS chip includes a second SPI line and a second main board GND ground wire. The first switch is located on the connection line between the first SPI line and the first main board GND ground wire, and the second switch is located on the connection line between the second SPI line and the second main board GND ground wire. The second control subunit includes:

[0149] A fourth control module is used to control the device under test to power off when the device under test switches to the backup BIOS chip to start and the backup BIOS chip starts successfully after the main BIOS chip fails to start due to a target fault.

[0150] A fifth control module is used for the control machine to control the first switch to disconnect and the second switch to conduct, so that the second SPI line and the second main board GND ground wire of the backup BIOS chip are shorted to simulate a second BIOS link short circuit, or the control machine flashes a faulty firmware to the backup BIOS chip, so that the backup BIOS chip simulates a BIOS firmware failure. The second BIOS link short circuit is another type of BIOS link short circuit.

[0151] A sixth control module is used to control the device under test to power on, so that the backup BIOS chip fails to start due to a BIOS link short circuit or a BIOS firmware failure.

[0152] To implement the fault test for the SETUP interface freeze, in an optional implementation, the first control subunit includes:

[0153] A seventh control module is used to control the device under test to power on;

[0154] An eighth control module is used to control the device under test to enter the SETUP interface during the startup process of the main BIOS chip of the device under test, and control the device under test to keep the SETUP interface unchanged for more than a predetermined duration or control the device under test to continuously switch between sub-interfaces of the SETUP interface, so as to simulate the startup failure caused by the SETUP interface freeze during the startup of the main BIOS chip.

[0155] To implement the fault test for the SETUP interface freeze, in an optional implementation, the second control subunit includes:

[0156] The ninth control module is used to control the device under test to shut down when the main BIOS chip fails to start due to a target fault and the device under test switches to the backup BIOS chip for startup and the backup BIOS chip starts successfully.

[0157] The tenth control module is used to control the device under test to power on.

[0158] The eleventh control module is used to control the device under test to enter the SETUP interface during the startup process of the backup BIOS chip of the device under test, and control the device under test to keep the SETUP interface unchanged for more than a predetermined duration or control the device under test to continuously switch between sub-interfaces of the SETUP interface, so as to simulate that the startup fails due to the SETUP interface getting stuck during the startup of the backup BIOS chip.

[0159] In order to verify whether the fault test is passed, in an optional implementation manner, the first determination unit includes:

[0160] The first reading subunit is used to read the first log, and the first log is the log of the main BIOS chip failing to start due to a target fault.

[0161] The second reading subunit is used to read the second log, and the second log is the log of the backup BIOS chip failing to start due to a target fault.

[0162] The determination subunit is used to determine that the device under test passes the fault test of the target fault when it is satisfied that there is a failure in starting the main BIOS chip and switching to the backup BIOS chip in the first log, the switching duration is less than the automatic switching timeout duration, there is a failure in starting the backup BIOS chip in the second log, and the downtime duration is less than the timeout downtime duration. The switching duration is the interval duration between the moment when the target fault occurs in the main BIOS chip and the moment of switching to the backup BIOS chip, and the downtime duration is the interval duration between the moment when the target fault occurs in the backup BIOS chip and the moment when the device under test shuts down.

[0163] In order to verify whether the device under test is damaged by the test, in an optional implementation manner, the control machine further includes:

[0164] The writing unit is used to write different specific data files in different directories of the device under test before the control machine controls the dual BIOS of the device under test to simulate a target fault and causes the dual BIOS to fail to start due to the target fault.

[0165] The control machine further includes:

[0166] A second determination unit, configured to determine that the device under test is not damaged by the test when the control machine determines whether the device under test passes the fault test of the target fault according to the log, and when the device under test passes the fault test of the target fault and all specific data files remain unchanged.

[0167] In order to verify whether the device under test is damaged by the test, in an alternative embodiment, the above-mentioned writing unit includes:

[0168] A first login subunit, configured to log in to the operating system of the device under test;

[0169] A writing subunit, configured to write different specific data files in different directories of the operating system of the device under test;

[0170] The second determination unit includes:

[0171] A sending subunit, configured to send a restart instruction to the device under test to control the device under test to perform a cold restart after power-off when the device under test passes the fault test of the target fault;

[0172] A second login subunit, configured to log in to the operating system of the device under test when the main BIOS chip self-check of the device under test passes and the operating system is successfully started;

[0173] A reading subunit, configured to read the specific data files stored in the device under test, and determine that the device under test is not damaged by the test when all specific data files are not lost and the md5 values of all specific data files remain unchanged.

[0174] For the description of the features in the corresponding embodiment of the dual-BIOS test system, reference can be made to the relevant description in the corresponding embodiment of the dual-BIOS test method, which will not be elaborated here one by one.

[0175] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any one of the above-mentioned embodiments of the dual-BIOS test method when running.

[0176] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs, etc., various media that can store computer programs.

[0177] An embodiment of the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above-described embodiments of the dual-BIOS test method are implemented.

[0178] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-described embodiments of the dual-BIOS test method are implemented.

[0179] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0180] The above has introduced in detail a dual-BIOS test method and a test system provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A testing method for dual BIOS, characterized in that, The described test method is applied to a dual-BIOS test system. The dual-BIOS test system includes a control machine, and the control machine is communicatively connected to the device under test. The method includes: The control machine controls the dual BIOS of the device under test to simulate a target fault, so that the dual BIOS fails to start due to the target fault. The target fault includes at least one of BIOS link short circuit, BIOS firmware fault, and SETUP interface freeze. The control machine receives the log of the dual BIOS failing to start due to the target fault. The control machine determines whether the device under test passes the fault test of the target fault according to the log.

2. The dual-BIOS test method according to claim 1, wherein: The dual BIOS includes a main BIOS chip and a backup BIOS chip. The control machine controls the dual BIOS of the device under test to simulate a target fault, so that the dual BIOS fails to start due to the target fault, including: The control machine controls the main BIOS chip of the device under test to simulate the target fault, so that the main BIOS chip fails to start due to the target fault. After the main BIOS chip fails to start due to the target fault, when the device under test switches to start with the backup BIOS chip, the control machine controls the backup BIOS chip of the device under test to simulate the target fault, so that the backup BIOS chip fails to start due to the target fault.

3. The test method for dual BIOS according to claim 2, wherein The dual-BIOS test system further includes a first switch and a second switch. Both the first switch and the second switch are communicatively connected to the control machine. The main BIOS chip includes a first SPI line and a first motherboard GND ground wire. The backup BIOS chip includes a second SPI line and a second motherboard GND ground wire. The first switch is located on the connection line between the first SPI line and the first motherboard GND ground wire. The second switch is located on the connection line between the second SPI line and the second motherboard GND ground wire. The control machine controls the main BIOS chip of the device under test to simulate the target fault, so that the main BIOS chip fails to start due to the target fault, including: The control machine controls the device under test to shut down. The control machine controls the first switch to conduct and the second switch to disconnect, so that the first SPI line and the first motherboard GND ground wire of the main BIOS chip are short-circuited to simulate a first BIOS link short circuit. Alternatively, the control machine flashes a faulty firmware to the main BIOS chip, so that the main BIOS chip simulates the BIOS firmware fault. The first BIOS link short circuit is one kind of the BIOS link short circuit. The control machine controls the device under test to power on, so that the main BIOS chip fails to start due to the BIOS link short circuit or the BIOS firmware fault.

4. The test method for dual BIOS according to claim 2, wherein The dual-BIOS test system further includes a first switch and a second switch. Both the first switch and the second switch are communicatively connected to the control machine. The main BIOS chip includes a first SPI line and a first motherboard GND ground wire, and the backup BIOS chip includes a second SPI line and a second motherboard GND ground wire. The first switch is located on the connection line between the first SPI line and the first motherboard GND ground wire, and the second switch is located on the connection line between the second SPI line and the second motherboard GND ground wire. After the main BIOS chip fails to start due to the target fault, when the device under test switches to start from the backup BIOS chip, the control machine controls the backup BIOS chip of the device under test to simulate the target fault, so that the backup BIOS chip fails to start due to the target fault, including: After the main BIOS chip fails to start due to the target fault, when the device under test switches to start from the backup BIOS chip and the backup BIOS chip starts successfully, the control machine controls the device under test to shut down. The control machine controls the first switch to disconnect and the second switch to conduct, so that the second SPI line and the second motherboard GND ground wire of the backup BIOS chip are short-circuited to simulate a second BIOS link short circuit. Alternatively, the control machine flashes a faulty firmware to the backup BIOS chip, so that the backup BIOS chip simulates a BIOS firmware fault. The second BIOS link short circuit is another type of the BIOS link short circuit. The control machine controls the device under test to power on, so that the backup BIOS chip fails to start due to the BIOS link short circuit or the BIOS firmware fault.

5. The dual-BIOS test method according to claim 2, wherein The control machine controls the main BIOS chip of the device under test to simulate the target fault, so that the main BIOS chip fails to start due to the target fault, including: The control machine controls the device under test to power on. During the startup process of the main BIOS chip of the device under test, the control machine controls the device under test to enter the SETUP interface, and controls the device under test to keep the SETUP interface unchanged for more than a predetermined duration or controls the device under test to continuously switch between sub-interfaces of the SETUP interface, so as to simulate that the startup fails due to the SETUP interface getting stuck during the startup of the main BIOS chip.

6. The dual-BIOS test method according to claim 2, wherein After the main BIOS chip fails to start due to the target fault, when the device under test switches to start from the backup BIOS chip, the control machine controls the backup BIOS chip of the device under test to simulate the target fault, so that the backup BIOS chip fails to start due to the target fault, including: After the main BIOS chip fails to start due to the target failure, when the device under test switches to the backup BIOS chip for startup and the backup BIOS chip starts successfully, the control machine controls the device under test to shut down. The control machine controls the device under test to power on. During the startup process of the backup BIOS chip of the device under test, the control machine controls the device under test to enter the SETUP interface, and controls the device under test to keep the SETUP interface unchanged for more than a predetermined duration or controls the device under test to continuously switch between sub-interfaces of the SETUP interface to simulate a startup failure caused by the SETUP interface getting stuck during the startup of the backup BIOS chip.

7. The test method for dual BIOS according to claim 2, characterized in that, The control machine determines whether the device under test passes the fault test for the target failure according to the log, including: The control machine reads the first log, and the first log is the log of the main BIOS chip failing to start due to the target failure. The control machine reads the second log, and the second log is the log of the backup BIOS chip failing to start due to the target failure. When it is satisfied that there is a failure in starting the main BIOS chip and switching to the backup BIOS chip in the first log, the switching duration is less than the automatic switching timeout duration, there is a failure in starting the backup BIOS chip in the second log, and the downtime duration is less than the timeout downtime duration, it is determined that the device under test passes the fault test for the target failure. The switching duration is the interval duration between the moment when the target failure occurs in the main BIOS chip and the moment of switching to the backup BIOS chip, and the downtime duration is the interval duration between the moment when the target failure occurs in the backup BIOS chip and the moment when the device under test shuts down.

8. The test method for dual BIOS according to any one of claims 1 to 7, characterized in that Before the control machine controls the dual BIOS of the device under test to simulate the target failure, causing the dual BIOS to fail to start due to the target failure, the method further includes: The control machine writes different specific data files in different directories of the device under test. After the control machine determines whether the device under test passes the fault test for the target failure according to the log, the method further includes: When the device under test passes the fault test for the target failure and all the specific data files remain unchanged, the control machine determines that the device under test is not damaged by the test.

9. The test method for dual BIOS according to claim 8, characterized in that The control machine writing different specific data files in different directories of the device under test includes: The control machine logs in to the operating system of the device under test. The control machine writes different specific data files in different directories of the operating system of the device under test. When the device under test passes the fault test of the target fault and all the specific data files remain unchanged, the control machine determines that the device under test is not damaged by the test, including: When the device under test passes the fault test of the target fault, the control machine issues a restart instruction to the device under test to control the device under test to perform a cold restart after power-off; When the main BIOS chip self-check of the device under test passes and the operating system is successfully started, the control machine logs in to the operating system of the device under test; The control machine reads the specific data files stored in the device under test, and determines that the device under test is not damaged by the test when all the specific data files are not lost and the md5 values of all the specific data files remain unchanged.

10. A dual-BIOS test system, characterized in that The test system of the dual BIOS includes a control machine, which is communicatively connected to the device under test. The control machine includes: A control unit, configured to control the dual BIOS of the device under test to simulate a target fault, so that the dual BIOS fails to start due to the target fault, and the target fault includes at least one of a BIOS link short circuit, a BIOS firmware fault, and a SETUP interface freeze; A receiving unit, configured to receive the log of the dual BIOS failing to start due to the target fault; A first determination unit, configured to determine whether the device under test passes the fault test of the target fault according to the log.

Images