PCIe overspeed mode implementation method based on equalization technology and data transmission method and system

Abstract

The invention discloses a PCIe (Peripheral Component Interconnect Express) overspeed mode implementation method and a data transmission method and system based on an equalization technology, and the PCIe overspeed mode implementation method comprises the steps: judging whether a current link state supports a PCIe overspeed mode or not according to a link state requirement of a PCIe link corresponding to a preset PCIe overspeed mode; judging whether the current hardware information supports the PCIe overspeed mode or not according to a hardware information requirement of a PCIe link corresponding to a preset PCIe overspeed mode; if both the link state and the hardware information support the PCIe overspeed mode, starting the PCIe overspeed mode by the following steps: acquiring a pre-stored maximum overspeed rate; and increasing the current rate of the PCIe link according to a preset first step length, and executing balancing operation every time / after the current rate is increased, so that the rate of the PCIe link reaches the maximum overspeed rate. According to the invention, the data transmission speed and stability can be improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a PCIe overspeed mode implementation method based on equalization technology, a data transmission method and a system. Background Art

[0002] In modern computer systems, high-speed data transmission technology has become an indispensable core component. Especially with the rapid development of big data, cloud computing, artificial intelligence and other fields, higher requirements are placed on the speed and efficiency of data transmission. PCI Express (PCIe) bus is a widely used high-speed serial computer expansion bus standard that can provide efficient data transmission and flexible expansion capabilities. With the continuous evolution of technology, the PCIe standard has developed from the initial version 2.0 to the latest version 6.0. Among them, the data transmission rate of PCIe2.0 is 5GT / s (about 500MB per second after conversion), while the data transmission rate of PCIe6.0 is as high as 64GT / s.

[0003] In the scenario of high-speed data transmission, the quality and stability of the signal undoubtedly play a decisive role. Due to the existence of many factors such as electromagnetic interference, signal reflection and cable loss, high-speed signals are very likely to be distorted or attenuated during transmission, which in turn causes transmission errors. In view of this, equalization technology is applied to high-speed data transmission. PCIe is a high-speed bus. The propagation of high-speed signals will cause huge interference and will also be easily distorted. Equalization technology ensures the stability of high-speed transmission by pre-processing and post-processing the signal at the sending and receiving ends. Therefore, if you want to achieve higher transmission rates, you need to achieve effective transmission equalization. Equalization technology uses the method of pre-processing and correcting the signal to ensure that the signal can still be transmitted stably under the conditions of long-distance transmission or high-speed transmission, thereby ensuring the accuracy and reliability of data transmission.

[0004] Since PCIe design often uses a larger deserializer (SerDes), SerDes is integrated into the PCIe hardware to serialize and deserialize data. Since the SerDes rate multiple does not match the PCIe rate multiple, in order to meet the PCIe rate requirements, designers consider a larger SerDes. For example, the sixth-generation PCIe standard has a maximum rate of 64GT / s, while the corresponding SerDes is as high as 112GT / s, which is far from fully utilizing the standard maximum rate of SerDes. Summary of the invention

[0005] The purpose of the present invention is to provide a PCIe overspeed mode implementation method, a data transmission method and a system based on equalization technology to improve the speed and stability of data transmission.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows: A method for implementing a PCIe over-speed mode based on an equalization technique, comprising the following steps: According to the link state requirements of the PCIe link corresponding to the preset PCIe over-speed mode, determine whether the link state of the current PCIe link supports the PCIe over-speed mode; According to the hardware information requirements of the PCIe link corresponding to the preset PCIe over-speed mode, determine whether the hardware information of the current PCIe link supports the PCIe over-speed mode; If both the link state and the hardware information support the PCIe over-speed mode, then start the PCIe over-speed mode in the following manner: Obtain the maximum over-speed rate stored in advance; Increase the current rate of the PCIe link in accordance with a preset first step length, and perform an equalization operation each time / after increasing the current rate, so that the rate of the PCIe link reaches the maximum over-speed rate.

[0007] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, when starting the PCIe over-speed mode, it further includes: Obtain the maximum over-speed rate stored in advance, and determine whether there is a historical failure rate stored in advance; If there is no such historical failure rate, then increase the current rate of the PCIe link in accordance with a preset first step length, and perform an equalization operation each time / after increasing the current rate, so that the rate of the PCIe link reaches the maximum over-speed rate.

[0008] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, when starting the PCIe over-speed mode, it further includes: If there is a historical failure rate stored in advance, and the historical failure rate is not greater than the maximum over-speed rate, then determine the first over-speed rate: First over-speed rate = historical failure rate - first step length; Increase the current rate of the PCIe link in accordance with a preset first step length, and perform an equalization operation to make the rate of the PCIe link reach the first over-speed rate; If the PCIe link operates stably at the first over-speed rate, then increase the current rate of the PCIe link using a second step length, and perform an equalization operation each time / after increasing the current rate, so that the rate of the PCIe link reaches the maximum over-speed rate, and the second step length is less than the first step length.

[0009] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, when starting the PCIe over-speed mode, it further includes: If there is a pre-stored historical failure rate and the historical failure rate is greater than the maximum over-speed rate, determine a second over-speed rate: the second over-speed rate = historical failure rate - the third step length, where the third step length is less than the first step length; Then increase the current rate of the PCIe link by the preset first step length, and perform an equalization operation each time after increasing the current rate, so that the rate of the PCIe link reaches the maximum over-speed rate; If the PCIe link operates stably at the maximum over-speed rate, increase the current rate of the PCIe link by the third step length, and perform an equalization operation each time after increasing the current rate, so that the rate of the PCIe link reaches the second over-speed rate.

[0010] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, when starting the PCIe over-speed mode, it further includes: Perform an equalization operation each time the current rate of the PCIe link is updated by the preset first step length. If the equalization fails, reduce the current rate of the PCIe link by the preset first step length and perform an equalization operation until the equalization is successful.

[0011] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the first step length is a fixed value or a variable value. If the first step length is a variable value, during the process of starting the PCIe over-speed mode, the closer the rate of the PCIe link is to the maximum over-speed rate, the smaller the first step length.

[0012] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, it further includes: reduce the current rate of the PCIe link by the preset first step length and perform an equalization operation until the equalization is successful, then determine the current rate corresponding to the successful equalization as the maximum over-speed rate and store the maximum over-speed rate.

[0013] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, after an equalization failure occurs, reduce the current rate of the PCIe link by the preset first step length and perform an equalization operation until the equalization is successful; Determine the rate corresponding to the first equalization failure during the process of starting the PCIe over-speed mode this time as the historical failure rate, or determine the rate corresponding to the last equalization failure during the process of starting the PCIe over-speed mode this time as the historical failure rate.

[0014] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, after starting the PCIe over-speed mode, if the PCIe link operates stably at the maximum over-speed rate, perform the following steps: Then, the current rate of the PCIe link is increased according to a preset fourth step length, and the fourth step length is smaller than the first step length; And an equalization operation is performed each time the current rate is increased until equalization fails or the current rate of the PCIe link reaches a preset over-speed rate threshold, and the over-speed rate threshold is greater than the maximum over-speed rate.

[0015] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the maximum over-speed rate is the upper limit rate at which the PCIe link operates stably in the previous PCIe over-speed mode; or, The maximum over-speed rate is the upper limit rate at which the PCIe link operates stably in the over-speed mode predicted based on the software and hardware of the PCIe link; or, The maximum over-speed rate is determined according to the following calculation formula: V Turbo = (1 + α)V1, where V Turbo represents the maximum over-speed rate, V1 represents the standard maximum rate corresponding to the highest generation of PCIe supported by the PCIe link, and 0 < α < 1.

[0016] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the first step length corresponds to the maximum over-speed rate, and the greater the maximum over-speed rate, the greater the first step length; or, The difference between the maximum over-speed rate and the standard maximum rate corresponding to the highest generation of PCIe supported by the PCIe link is determined, and the first step length corresponds to the difference, and the greater the difference, the greater the first step length.

[0017] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the following method is used to determine whether the link state of the PCIe link supports the PCIe over-speed mode: Determine how many generations of PCIe the PCIe link supports at most. Assume that the PCIe link supports the Kth generation of PCIe at most, and K takes 2 or 3 or 4 or 5 or 6; If the current rate of the PCIe link is the standard maximum rate corresponding to the Kth generation of PCIe and the bit error rate is lower than a preset bit error rate threshold, it is determined that the link state of the PCIe link supports the PCIe over-speed mode.

[0018] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, if the PCIe link supports at least the 5th generation of PCIe at most and the current rate of the PCIe link does not reach the standard maximum rate corresponding to the 5th generation of PCIe, it is determined whether the PCIe link supports cross-level equalization; If the PCIe link supports cross-level equalization, increase the current rate of the PCIe link to the standard maximum rate corresponding to the 5th generation PCIe, and perform the equalization operation; If the PCIe link does not support cross-level equalization, increase the current rate of the PCIe link generation by generation to the standard maximum rate corresponding to the 5th generation PCIe, and perform the equalization operation each time the rate of the PCIe link is increased / after the rate is increased.

[0019] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, if the PCIe link supports at least the 5th generation PCIe at the highest level, and the current rate of the PCIe link reaches the standard maximum rate corresponding to the 5th generation PCIe, increase the current rate of the PCIe link to the standard maximum rate corresponding to the 6th generation PCIe, and perform the equalization operation; If the equalization is successful, determine whether the PCIe link supports the PCIe over-speed mode. If it supports, enable the PCIe over-speed mode; otherwise, the PCIe link maintains its current operating state; If the equalization fails, reduce the current rate of the PCIe link so that the PCIe link stably operates at the standard maximum rate corresponding to the 5th generation PCIe, and determine whether the PCIe link supports at least the 5th generation PCIe at the highest level. If so, determine whether the PCIe link supports the PCIe over-speed mode. If it supports, enable the PCIe over-speed mode; otherwise, the PCIe link maintains its current operating state.

[0020] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, determine whether the hardware information of the PCIe link supports the PCIe over-speed mode in the following manner: If the hardware supports the PCIe over-speed mode, and the operating state of the hardware also supports the PCIe over-speed mode, determine that the hardware information of the PCIe link supports the PCIe over-speed mode; Among them, the operating state of the hardware also supporting the PCIe over-speed mode includes: the power of the hardware is lower than a preset power threshold, and the temperature of the hardware is lower than a preset temperature threshold.

[0021] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, after implementing the PCIe over-speed mode, the following steps are further included to maintain the PCIe over-speed mode: Monitor the link state of the PCIe link, evaluate the current data transmission quality according to the link state, and the link state also includes the signal jitter situation; If the data transmission quality does not meet the preset first-level requirement but meets the preset second-level requirement, the current rate of the PCIe link is reduced by a preset fifth step size and an equalization operation is performed, where the fifth step size is smaller than the fourth step size; If the data transmission quality does not meet the preset second-level requirement but meets the preset third-level requirement, the current rate of the PCIe link is reduced to the rate corresponding to the last stable operation and an equalization operation is performed; If the data transmission quality does not meet the preset third-level requirement, the PCIe over-speed mode is turned off and an equalization operation is performed; The first-level requirement, the second-level requirement, and the third-level requirement for data transmission quality decrease in sequence.

[0022] According to another aspect of the present invention, a data transmission method is provided, and data transmission is performed based on the method for implementing the PCIe over-speed mode based on the equalization technology according to any one of the above technical solutions or a combination of multiple technical solutions.

[0023] According to another aspect of the present invention, a data transmission system is provided, and the data transmission system performs data transmission based on the method for implementing the PCIe over-speed mode based on the equalization technology according to any one of the above technical solutions or a combination of multiple technical solutions.

[0024] The beneficial effects brought by the technical solution provided by the present invention are as follows: a. The present invention provides a method for implementing the PCIe over-speed mode based on the equalization technology. By combining various speed-up strategies with the equalization operation, corresponding step sizes are adopted for different situations to increase the data transmission rate of the PCIe link. Combining the corresponding data of the historical PCIe over-speed mode, including the maximum over-speed rate and the historical failure rate, the way of starting the PCIe over-speed mode can be adjusted more precisely according to the changes in actual applications, thereby improving the equalization effect, stably and reliably achieving a higher PCIe transmission rate, and improving the utilization rate of the SerDes rate; b. The present invention can ensure the stability of data transmission through flexible equalization adjustment strategies: When adjusting the data transmission rate in this technical solution, a mechanism of real-time monitoring of the link state and adaptive adjustment is adopted, which can adjust the rate of the PCIe link on the premise of ensuring the stability of data transmission, and exit the over-speed mode in time when the transmission is unstable and restore the conservative transmission speed, thereby avoiding the problem of data transmission failure. Description of the Drawings

[0025] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0026] Figure 1 Flowchart of the PCIe over-speed mode implementation method based on the equalization technology provided for an exemplary embodiment of the present invention; Figure 2 Flowchart of the PCIe over-speed mode implementation process when the historical failure rate is less than the maximum over-speed rate provided for an exemplary embodiment of the present invention; Figure 3 Flowchart of the PCIe over-speed mode implementation process when the historical failure rate is greater than the maximum over-speed rate provided for an exemplary embodiment of the present invention; Figure 4 Flowchart of the PCIe over-speed mode implementation process after reaching the maximum over-speed rate provided for an exemplary embodiment of the present invention; Figure 5 Flowchart of the PCIe over-speed mode implementation process applicable to each generation version of PCIe provided for an exemplary embodiment of the present invention; Figure 6 Flowchart of the adaptive adjustment mechanism in the PCIe over-speed mode provided for an exemplary embodiment of the present invention. Detailed implementation manners

[0027] In order to enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the specification, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or equipment comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or equipment.

[0029] Introduction to relevant terms involved in this application: PCIe (PCI Express): A widely used high-speed serial computer expansion bus standard that can provide efficient data transmission and flexible expansion capabilities; PCIe standard mode: The state in which a PCIe device / link / system transmits data at the standard rate corresponding to the PCIe version it supports, and the PCIe device / link / system transmits data at the base rate and bandwidth supported by the link it is in; PCIe high-speed mode: The state in which a PCIe device / link / system transmits data at the standard maximum rate corresponding to the PCIe version it supports, and the PCIe device / link / system operates at the standard maximum rate corresponding to a higher PCIe version it supports; PCIe over-speed mode: The state in which a PCIe device / link / system transmits data at a rate higher than the standard maximum rate corresponding to the highest PCIe version it supports, and the rate at which the PCIe device / link / system operates is higher than the standard maximum rate corresponding to a higher PCIe version it supports; for example, taking a PCIe device / link / system that supports a maximum of PCIe 6.0 version as an example, when the PCIe device / link / system operates in the PCIe high-speed mode, its rate is 64 GT / s, when the PCIe device / link / system operates in the PCIe standard mode, its rate is usually less than 64 GT / s; when the PCIe device / link / system operates in the PCIe over-speed mode, its rate is usually greater than 64 GT / s; Equalization technology: A technology that compensates for problems such as signal loss and distortion caused by channel characteristics and other factors during signal transmission, thereby improving signal quality and transmission reliability; Equalization Success: The PCIe device / link / system can operate stably at the current rate (current data transfer rate), which can be judged specifically according to indicators such as the eye diagram opening degree and equalizer convergence during the equalization process, as well as the data transfer quality (bit error rate). Equalization Failure: The PCIe device / link / system cannot operate stably at the current rate (current data transfer rate), which can be judged specifically according to indicators such as the eye diagram opening degree and equalizer convergence during the equalization process, as well as the data transfer quality (bit error rate). SerDes: Deserializer, which is integrated in the PCIe hardware part to realize serialization and deserialization of data.

[0030] In view of the rapid development in the fields of big data, cloud computing, artificial intelligence, etc., the requirements for the speed and efficiency of data transfer are getting higher and higher. And in PCIe design, deserializer with higher rate is often selected. For example, the SerDes corresponding to the 6.0 version can usually reach 112GT / s, while the standard maximum rate of PCIe corresponding to the 6.0 version is 64GT / s, far from fully utilizing the standard maximum rate of Serdes, which gives SerDes more abundant space for performance potential exploration.

[0031] Based on this, this application proposes an ultra-high-speed Turbo mode based on PCIe and its equalization method. By means of advanced equalization technology, various parameters of the signal are finely adjusted to effectively compensate for signal attenuation and distortion problems caused by factors such as electromagnetic interference, signal reflection, and cable loss during the high-speed transmission process, so that the rate utilization rate of SerDes is significantly improved, and thus creates favorable conditions for the ultra-high-speed mode that attempts to break through the PCIe standard maximum rate limit.

[0032] In an embodiment of the present invention, a method for implementing an ultra-high-speed mode of PCIe based on equalization technology is provided, as Figure 1 shown, the method includes the following steps: Judge whether the current link state of the PCIe link supports the PCIe ultra-high-speed mode according to the link state requirements of the PCIe link corresponding to the preset PCIe ultra-high-speed mode; Judge whether the hardware information of the current PCIe link supports the PCIe ultra-high-speed mode according to the hardware information requirements of the PCIe link corresponding to the preset PCIe ultra-high-speed mode; If both the link state and the hardware information support the PCIe ultra-high-speed mode, then start the PCIe ultra-high-speed mode in the following way: Obtain the maximum ultra-high-speed rate stored in advance; Increase the current rate of the PCIe link by a preset first step length, and perform an equalization operation each time after the current rate is increased, so that the rate of the PCIe link reaches the maximum over-speed rate.

[0033] Wherein, the maximum over-speed rate is greater than the standard maximum rate corresponding to the highest generation of PCIe supported by the PCIe link. The maximum over-speed rate can be determined and pre-stored in the following ways.

[0034] The first way is to determine the upper limit rate at which the PCIe link operates stably in the previous PCIe over-speed mode. The upper limit rate can be the upper limit rate at which the PCIe link operates stably in the most recent PCIe over-speed mode, or the average value of the upper limit rates at which the PCIe link operates stably in multiple previous PCIe over-speed modes. Determine the upper limit rate as the maximum over-speed rate.

[0035] The second way is that the maximum over-speed rate is the upper limit rate at which the PCIe link operates stably in the over-speed mode predicted based on the software and hardware of the PCIe link. The prediction method can be that a technician makes a prediction based on experience, or can be predicted through simulation, experiments, etc. Determine the upper limit rate as the maximum over-speed rate.

[0036] The third way is to determine the maximum over-speed rate using a preset calculation formula. For example, if the standard maximum rate corresponding to the highest generation of PCIe supported by the PCIe link is determined to be V1, then V Turbo = (1 + α)V1, where V Turbo represents the maximum over-speed rate, 0 < α < 1. Preferably, α takes values such as 0.05, 0.1, 0.15, 0.20, etc.

[0037] The first step length can be a fixed value or a variable value. Regardless of which of the above ways is used to determine the maximum over-speed rate, the first step length corresponds to the maximum over-speed rate. The larger the maximum over-speed rate, the larger the first step length. For example, for a relatively large maximum over-speed rate, the first step length can be set to 2 GT / s; while for a relatively small maximum over-speed rate, the first step length can be set to 1 GT / s.

[0038] More preferably, determine the difference between the maximum over-speed rate and the standard maximum rate corresponding to the highest generation of PCIe supported by the PCIe link. The first step length corresponds to the difference (i.e., V Turbo - V1). The larger the difference, the larger the first step length. For example, determine the first step length β1 according to the difference between V Turbo and V1, β1 = (V Turbo-V1) / N, where N is the target update step number, and N can be a natural number not less than 2. Preferably, N can be natural numbers such as 5, 10, 15, 20, 25, 30, etc.

[0039] If the first step size is a variable value, during the process of starting the PCIe over-speed mode, the closer the rate of the PCIe link is to the maximum over-speed rate, the smaller the first step size. In practical applications, it can be set that the first step size decreases step by step during the process of starting the PCIe over-speed mode.

[0040] In an embodiment of the present invention, the method for implementing the PCIe over-speed mode based on the equalization technology is based on Figure 2 and Figure 3 shown in the flowchart to start the PCIe over-speed mode. In this embodiment, if there is no historical failure rate, the PCIe over-speed mode is started according to the Figure 1 shown process. And each time the current rate of the PCIe link is updated according to the preset first step size, an equalization operation is performed. If the equalization fails, the current rate of the PCIe link is reduced according to the preset first step size and the equalization operation is performed until the equalization is successful, then it is determined that the PCIe over-speed mode is completed.

[0041] If there is the historical failure rate, it is not only necessary to obtain the pre-stored maximum over-speed rate, but also necessary to determine whether there is a pre-stored historical failure rate, and the PCIe over-speed mode is started by combining the maximum over-speed rate and the historical failure rate.

[0042] As Figure 2 shown, in this embodiment, there is a pre-stored historical failure rate, and the historical failure rate is not greater than the maximum over-speed rate, then the first over-speed rate is determined: First over-speed rate = Historical failure rate - First step size.

[0043] The current rate of the PCIe link is increased according to the preset first step size, and an equalization operation is performed to make the rate of the PCIe link reach the first over-speed rate. During the process of iteratively updating the rate of the PCIe link from the current rate to the first over-speed rate according to the first step size, if there is a situation where the equalization fails, the current rate of the PCIe link is reduced according to the first step size and the equalization operation is performed until the PCIe link stably operates at an over-speed rate or V1, then it is determined that the PCIe over-speed mode is completed.

[0044] If each equalization operation is successful, when the PCIe link is stably operating at the first over-speed rate, perform the following operations: increase the current rate of the PCIe link by the second step length, and perform an equalization operation each time the current rate is increased, so that the rate of the PCIe link reaches the maximum over-speed rate, where the second step length is less than the first step length. During the iterative update of the rate of the PCIe link from the current rate to the maximum over-speed rate according to the second step length, if there is a case of equalization failure, then reduce the current rate of the PCIe link by the second step length and perform an equalization operation until the PCIe link is stably operating at an over-speed rate or V1, and then determine that the PCIe over-speed mode is completed. If there is no case of equalization failure, then when the PCIe link is stably operating at the maximum over-speed rate, determine that the PCIe over-speed mode is completed.

[0045] As Figure 3 shown, in this embodiment, there is a pre-stored historical failure rate, and the historical failure rate is greater than the maximum over-speed rate, then determine the second over-speed rate: the second over-speed rate = historical failure rate - the third step length, β3 < β2 < β1, where β1 is the first step length, β2 is the second step length, and β3 is the third step length.

[0046] Then increase the current rate of the PCIe link by the preset first step length, and perform an equalization operation each time the current rate is increased, so that the rate of the PCIe link reaches the maximum over-speed rate. During the iterative update of the rate of the PCIe link from the current rate to the maximum over-speed rate according to the first step length, if there is a case of equalization failure, then reduce the current rate of the PCIe link by the first step length and perform an equalization operation until the PCIe link is stably operating at an over-speed rate or V1, and then determine that the PCIe over-speed mode is completed.

[0047] If there is no case of equalization failure, then when the PCIe link is stably operating at the maximum over-speed rate, perform the following operations: increase the current rate of the PCIe link by the third step length, and perform an equalization operation each time the current rate is increased, so that the rate of the PCIe link reaches the second over-speed rate.

[0048] During the iterative update of the rate of the PCIe link from the current rate to the second over-speed rate according to the third step length, if there is a case of equalization failure, then reduce the current rate of the PCIe link by the third step length and perform an equalization operation until the PCIe link is stably operating at an over-speed rate or V1, and then determine that the PCIe over-speed mode is completed. If there is no case of equalization failure, then when the PCIe link is stably operating at the second over-speed rate, determine that the PCIe over-speed mode is completed.

[0049] During the process of enabling the PCIe over-speed mode described above, after determining that the PCIe over-speed mode is completed, determine the current rate corresponding to the last successful equalization as the maximum over-speed rate, and store the maximum over-speed rate for use in the next activation of the PCIe over-speed mode.

[0050] In one embodiment of the present invention, as Figure 4 shown, after enabling the PCIe over-speed mode, if the PCIe link is stably operating at the maximum over-speed rate, continue to perform the following steps: Then increase the current rate of the PCIe link in accordance with a preset fourth step size β4, where β4 < β3 < β2 < β1; And perform an equalization operation each time / after increasing the current rate until an equalization failure occurs or the current rate of the PCIe link reaches a preset over-speed rate threshold, which is greater than the maximum over-speed rate.

[0051] After an equalization failure occurs, decrease and update the current rate of the PCIe link in accordance with the fourth step size and perform an equalization operation until successful equalization occurs again. Determine the rate corresponding to the first equalization failure during the current activation of the PCIe over-speed mode as the historical failure rate, or determine the rate corresponding to the last equalization failure during the current activation of the PCIe over-speed mode as the historical failure rate for use in the next activation of the PCIe over-speed mode.

[0052] In any of the above-described embodiments, the specific conditions for enabling the over-speed mode generally include aspects such as link status, hardware conditions, and software conditions.

[0053] First, monitor the link status. It is necessary to continuously and accurately monitor the operating status of the PCIe link, with a focus on whether it can stably and reliably operate at the highest generation (such as Gen6) data rate it supports. This involves real-time evaluation of the bit error rate (BER) of the link, the completion status of each stage of the link training state machine (LTSSM), and various physical layer parameters (such as signal strength, clock synchronization, etc.). Specific BER thresholds (for example, BER below 1×10⁻¹²) and other conditions can be set to determine that the link meets the requirements for reliable operation, thus providing the basic conditions for activating the Turbo mode.

[0054] Specifically, by reading the internal registers of the PCIe controller, obtain the current rate and the standard maximum rate (maximum non-return-to-zero rate) supported, as shown in Table 1. The standard maximum rates supported by each generation of PCIe are shown in Table 1. The BER can be determined based on the hardware error counter on the PCIe link. By reading the internal registers, obtain whether the current link training state machine is in the L0 state (L0 is the normal operating state of the PCIe link, representing the highest performance and health status of the link).

[0055]

[0056] In addition to the standard maximum rate and bit error rate, the link state may further include signal strength and clock synchronization status. The evaluation of signal strength is as follows: through an internal voltage comparison module on the PCIe link, the received signal voltage is compared with a preset threshold to determine whether the signal strength is within an acceptable range, so as to evaluate signal integrity and ensure that the current communication quality meets the requirements.

[0057] The clock synchronization status is evaluated in the following way: through a clock jitter detection module, the quality of the clock signal is judged; a synchronization error counting module: records clock synchronization errors, such as clock jump errors, and then evaluates the reliability and performance of data transmission.

[0058] Secondly, check the hardware support conditions. It is necessary to confirm whether relevant hardware devices (such as PCIe controllers, transceivers, etc.) have the function of supporting the over-speed mode. Whether the hardware supports cross-generation equalization and the over-speed mode can be determined by checking the internal registers of the device. At the hardware level, it is necessary to ensure that its power, heat dissipation, etc. can cope with the possible increased load under the over-speed mode. If the hardware supports the PCIe over-speed mode and the working state of the hardware also supports the PCIe over-speed mode, it is determined that the hardware information of the PCIe link supports the PCIe over-speed mode.

[0059] The working state of the hardware also supporting the PCIe over-speed mode includes: the power of the hardware is lower than a preset power threshold, and the temperature of the hardware is lower than a preset temperature threshold. Specifically, the current power, temperature, and heat dissipation of the hardware can be judged through internal voltage / current sensors and temperature sensors. For the power aspect, the PCIe device is built-in with voltage / current sensors to monitor its own power consumption. The data of these sensors can be read through the internal management controller and compared with the preset power threshold. The PCIe device usually defines a maximum power limit, that is, the power threshold. When the power consumption exceeds this limit, its own performance is limited. For the heat dissipation aspect, the PCIe device is equipped with temperature sensors, such as thermistors or thermocouples, to measure the temperature of the device. The device judges whether the heat dissipation condition is sufficient by comparing with the preset temperature threshold.

[0060] In addition, it is also necessary to check the software support conditions. Specifically, on the software side, it is necessary to ensure that operations such as the startup and rate adjustment of the over-speed mode (Turbo mode) can be correctly configured and managed. Whether it is supported can be judged by the identification bits of the function registers of the hardware device or the corresponding fields in the software configuration file. Of course, in some specific applications, the corresponding driver programs and system software for supporting the over-speed mode can be pre-configured, and in actual applications, it is not necessary to check the software support conditions, and it is defaulted to support the over-speed mode, thereby reducing the judgment conditions for enabling the over-speed mode.

[0061] In an embodiment of the present invention, the method for implementing the PCIe over-speed mode based on the equalization technology is executed according to the Figure 5 flow shown.

[0062] In this embodiment, the PCIe link is configured to bypass the generation-by-generation equalization process at a lower data rate and directly enter the standard maximum rate supported by the PCIe link and perform the equalization operation. Specifically, as Figure 5 shown, when the PCIe version supported by the PCIe link is greater than or equal to 5, the PCIe link first trains at the standard maximum rate corresponding to the first generation (Gen1) until it reaches the L0 state, that is, the stable operating state. Then it is judged whether the PCIe link supports cross-generation equalization.

[0063] If the PCIe link supports cross-generation equalization, that is, it is confirmed that all components on the PCIe link (including components such as retimers if any) can perform cross-generation equalization, then it directly enters the fifth generation (Gen5), changes the rate of the PCIe link to the standard maximum rate corresponding to the fifth generation (Gen5) PCIe, and directly performs the equalization operation in the fifth generation (Gen5).

[0064] If the PCIe link does not support cross-generation equalization, the current rate of the PCIe link is gradually increased to the standard maximum rate corresponding to the fifth generation PCIe, and the equalization operation is performed each time the current rate of the PCIe link is increased.

[0065] In this embodiment, all equalization processes for the 64.0 GT / s (i.e., the sixth generation) rate, including re-equalization, must start from the 32.0 GT / s (fifth generation) data rate to ensure that the PCIe link can transmit data stably and reliably. Specifically, if the PCIe link supports at least the fifth generation PCIe at most, and the current rate of the PCIe link reaches the standard maximum rate corresponding to the fifth generation PCIe, then the current rate of the PCIe link is increased to the standard maximum rate corresponding to the sixth generation PCIe, and the equalization operation is performed.

[0066] If the standard maximum rate equalization corresponding to the 6th generation PCIe is successful, then determine whether the PCIe link supports the PCIe over-speed mode. If it supports, then enable the PCIe over-speed mode; otherwise, the PCIe link maintains its current operating state. If the equalization fails, then reduce the current rate of the PCIe link so that the PCIe link operates stably at the standard maximum rate corresponding to the 5th generation PCIe, and determine whether the PCIe link supports up to the 5th generation PCIe at most. If so, then determine whether the PCIe link supports the PCIe over-speed mode. If it supports, then enable the PCIe over-speed mode; otherwise, the PCIe link maintains its current operating state.

[0067] Only when the PCIe link can operate stably at the standard maximum rate supported by the device does it meet the conditions for the Turbo mode. At this time, the "highest rate over-speed enable" in the Turbo capability register is set to 1b, and the "disable highest rate over-speed enable" in the Turbo control register is set to 0b.

[0068] After meeting the above conditions, it enters the over-speed rate acceleration phase. The rate will increase sequentially for equalization operations until the maximum stable equalization rate is reached. Finally, the link will continuously operate at this maximum stable equalization rate. At the same time, record the initial over-speed rate corresponding to this equalization operation as the standard maximum rate supported by the device (assuming it starts as the standard maximum rate supported by the device based on the set rules).

[0069] This application does not specifically limit the equalization operation and does not limit the protection scope of this application by a specific equalization operation method. The equalization operation may include a transmitter equalization operation, a receiver equalization, and an adaptive equalization, etc.

[0070] Among them, the transmitter equalization operation includes: pre-emphasis, that is, at the transmitter, the amplitude of specific frequency components of the signal, usually high-frequency components, is increased so that it can better resist the attenuation of the channel during transmission; de-emphasis, which is the reverse process of pre-emphasis, that is, at the transmitter, the low-frequency components of the signal are appropriately attenuated, and relatively increase the amplitude of the high-frequency components to improve the spectral characteristics of the signal and reduce ISI.

[0071] The receiving - end equalization operation includes: a continuous - time linear equalizer (CTLE), a type of linear equalizer that compensates for signals in the continuous - time domain by amplifying and filtering the signals to restore the amplitude and shape of the signals. It is suitable for high - speed links, can compensate for signal losses in real - time, and its parameters such as gain and bandwidth are adjustable and can be optimized according to different channel conditions; a decision - feedback equalizer: which uses the already - decided data symbols to estimate and eliminate the interference of subsequent symbols. It further removes inter - symbol interference by feeding back the already - detected signals, thereby improving the quality of the received signal, especially suitable for processing signals with strong inter - symbol interference.

[0072] The adaptive equalization technology includes: dynamically adjusting equalization parameters, such as the gain of the CTLE, the weights of the DFE, etc., to adapt to different channel conditions and transmission environments. Adaptive equalization can automatically optimize the equalization settings according to real - time monitored signal quality indicators, such as bit - error rate, eye - diagram opening, etc., so that the system always maintains good received - signal quality.

[0073] After each equalization operation is completed, it is judged whether the equalization is successful by analyzing relevant indicators during the equalization process (for example, the eye - diagram opening at the receiving end, the convergence of the equalizer, etc.). If the equalization is successful, the current rate of the PCIe link is increased by a predetermined step (such as 1 GT / s), that is, the current rate corresponding to the next equalization operation becomes the previous current rate + 1 GT / s. Then, immediately start the next round of equalization operations to adapt to the new rate requirements and ensure that the link can still maintain good signal transmission quality at a higher over - speed rate.

[0074] If it is determined that the equalization fails after a certain equalization operation, it is necessary to stop increasing the current rate and subsequent equalization attempts. It is necessary to adjust the current rate downward and perform the equalization operation. When the equalization is successful, the current rate value can be recorded, and the PCIe link is locked to run at this current rate. Subsequent data transmissions can be carried out based on this current rate to ensure the stability and continuity of the link.

[0075] After implementing the PCIe over - speed mode, it also includes, for example, by Figure 6The adaptive adjustment mechanism shown maintains the PCIe link operating stably in the PCIe over-speed mode: monitor the link state of the PCIe link, evaluate the current data transmission quality according to the link state, and the link state also includes the signal jitter situation. If the data transmission quality does not meet the preset first-level requirement but meets the preset second-level requirement, the current rate of the PCIe link is reduced by a preset fifth step size and an equalization operation is performed, and the fifth step size is smaller than the fourth step size; if the data transmission quality does not meet the preset second-level requirement but meets the third-level requirement, the current rate of the PCIe link is reduced to the rate corresponding to the previous stable operation and an equalization operation is performed; if the data transmission quality does not meet the preset third-level requirement, the PCIe over-speed mode is turned off and an equalization operation is performed; the first-level requirement, the second-level requirement, and the third-level requirement for data transmission quality decrease in turn.

[0076] Specifically, during the operation stage of the PCIe over-speed mode, the following safeguard measures are adopted to ensure the stable operation state of the PCIe link, including: (1) Real-time monitoring and adaptive adjustment: During the operation of the PCIe link at a determined over-speed rate, continuously monitor the link state in real time. Since there may be various interference factors in the actual operating environment or the hardware performance fluctuates over time, once it is detected that the link quality shows a downward trend (for example, it is evaluated that the data transmission quality does not meet the first-level requirement but meets the second-level requirement according to parameters such as the increasing bit error rate and the intensifying signal jitter), then through an adaptive adjustment mechanism, such as slightly reducing the over-speed rate (i.e., with a small step size, such as 0.5 GT / s), and at the same time re-performing a round of lightweight equalization operations, to try to maintain the reliable operation of the link and avoid serious situations such as link interruption.

[0077] (2) Error handling and recovery mechanism: If a serious error occurs during the operation at the over-speed rate (such as multiple consecutive data frame errors, link loss of lock, etc., and it is evaluated that the data transmission quality does not meet the second-level requirement but meets the third-level requirement), then solve the problem through a perfect error handling and recovery mechanism. It includes: first try to quickly roll back the over-speed rate to the previous lower over-speed rate value of the stable operation, and then restart the complete equalization process to try to restore the normal operation of the link; if multiple attempts still cannot restore (it is evaluated that the data transmission quality does not meet the third-level requirement), then further reduce the rate or even turn off the PCIe over-speed mode, restore to the normal link operation mode, and report the corresponding error information to the system for subsequent fault troubleshooting and repair operations.

[0078] In an embodiment of the present invention, by setting a configuration and management interface, such as setting user-configurable options, certain configuration permissions can be provided to users or system administrators, allowing users to adjust parameters related to the PCIe over-speed mode according to specific application requirements and hardware conditions in actual applications. For example, a switch option to enable or disable the over-speed mode can be set, the initial value of the maximum over-speed rate can be set and adjusted, and the increment step of the over-speed rate after each successful equalization (not necessarily 1 GT / s) can be set, etc. These configurable functions can be implemented through the BIOS setup interface or a dedicated system configuration tool to improve the flexibility of starting the PCIe high-speed mode.

[0079] Compared with the prior art, the present technical solution mainly solves the following technical problems: (1) The present technical solution provides a method for implementing the PCIe over-speed mode (Turbo transmission mode), and correspondingly designs an equalization algorithm implementation solution, which can stably and reliably attempt higher PCIe transmission rates and improve the utilization mode of the SerDes rate; (2) The problem of a fixed equalization adjustment step: The present technical solution adopts a customizable adjustment step, which can be adjusted more finely according to changes in the actual environment, thereby improving the equalization effect; (3) The stability of data transmission can be ensured through a flexible equalization adjustment strategy: When adjusting the data transmission rate, the present technical solution adopts a mechanism of real-time monitoring and adaptive adjustment, which can be adjusted on the premise of ensuring the stability of data transmission, and can exit the Turbo mode in time when the transmission is unstable and restore the conservative transmission speed, thereby avoiding the problem of data transmission failure; (4) Configuration flexibility: The present technical solution provides users with configurable options, allowing them to adjust parameters related to the Turbo mode according to specific application requirements and hardware conditions, thereby improving the flexibility and operability of the system.

[0080] In an embodiment of the present invention, a data transmission method is provided, and data transmission is performed based on the PCIe over-speed mode implementation method based on the equalization technology described in any one of the above embodiments.

[0081] In an embodiment of the present invention, a data transmission system is provided, and the data transmission system performs data transmission based on the PCIe over-speed mode implementation method based on the equalization technology described in any one of the above embodiments.

[0082] It should be noted that the embodiments of the data transmission method and data transmission system provided by the present invention have the same inventive concept as the embodiments of the PCIe over-speed mode implementation method based on the equalization technology. The entire content of the embodiments of the PCIe over-speed mode implementation method based on the equalization technology is incorporated into the embodiments of the data transmission method and data transmission system by introduction.

[0083] The technical solution provided by this application can have a wide range of applications in application fields such as high-speed data transmission, computer hardware, signal processing, etc. In the field of data centers, it can accelerate data transmission between servers and storage devices and optimize the virtualization environment; in the field of high-performance computing, it can help cluster computing and acceleration cards operate efficiently and improve computing efficiency; in the field of consumer electronics, it can provide fast connections for high-end computers and smart home appliances, etc., and improve the user experience; in the field of communication devices, it can enhance the connection between 5G base stations and the core network and internal communication of network devices, and improve network performance.

[0084] Particularly importantly, this technical solution has the downward compatibility characteristic and can be perfectly adapted to the standard version of PCIe. It expands performance on the basis of making full use of the existing PCIe ecosystem, which makes its application deployment in various fields more convenient and plays an important role in many aspects such as data transmission and device interconnection, and has great application value and development potential. Generally speaking, with the development of technologies such as big data, cloud computing, and artificial intelligence, the demand for high-speed data transmission is increasing. This technical solution has significant advantages in improving data transmission speed and stability, and the market demand is broad.

[0085] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

[0086] The above description is only the specific implementation manners of this application. It should be pointed out that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of this application.

Claims

1. A method for implementing the PCIe over-speed mode based on the equalization technology, characterized in that, The steps include: According to the link state requirements of the PCIe link corresponding to the preset PCIe over-speed mode, determine whether the link state of the current PCIe link supports the PCIe over-speed mode; According to the hardware information requirements of the PCIe link corresponding to the preset PCIe over-speed mode, determine whether the hardware information of the current PCIe link supports the PCIe over-speed mode; If both the link state and the hardware information support the PCIe over-speed mode, then start the PCIe over-speed mode in the following manner: Obtain the maximum over-speed rate stored in advance; Increase the current rate of the PCIe link by a preset first step length, and perform an equalization operation each time / after increasing the current rate, so that the rate of the PCIe link reaches the maximum over-speed rate.

2. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 1, wherein Starting the PCIe over-speed mode further includes: Obtain the maximum over-speed rate stored in advance, and determine whether there is a pre-stored historical failure rate; If there is no such historical failure rate, then increase the current rate of the PCIe link by a preset first step length, and perform an equalization operation each time / after increasing the current rate, so that the rate of the PCIe link reaches the maximum over-speed rate.

3. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 2, wherein Starting the PCIe over-speed mode further includes: If there is a pre-stored historical failure rate and the historical failure rate is not greater than the maximum over-speed rate, then determine the first over-speed rate: the first over-speed rate = historical failure rate - first step length; Increase the current rate of the PCIe link by a preset first step length and perform an equalization operation to make the rate of the PCIe link reach the first over-speed rate; If the PCIe link operates stably at the first over-speed rate, then increase the current rate of the PCIe link by a second step length, and perform an equalization operation each time / after increasing the current rate, so that the rate of the PCIe link reaches the maximum over-speed rate, and the second step length is less than the first step length.

4. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 2, wherein Starting the PCIe over-speed mode further includes: If there is a pre-stored historical failure rate and the historical failure rate is greater than the maximum over-speed rate, then determine the second over-speed rate: the second over-speed rate = historical failure rate - third step length, and the third step length is less than the first step length; Then increase the current rate of the PCIe link by a preset first step length, and perform an equalization operation each time / after increasing the current rate, so that the rate of the PCIe link reaches the maximum over-speed rate; If the PCIe link operates stably at the maximum over-speed rate, then increase the current rate of the PCIe link by a third step length, and perform an equalization operation each time / after increasing the current rate, so that the rate of the PCIe link reaches the second over-speed rate.

5. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 1, wherein Starting the PCIe over-speed mode further includes: perform an equalization operation each time the current rate of the PCIe link is updated by a preset first step length. If the equalization fails, then decrease the current rate of the PCIe link by a preset first step length and perform an equalization operation until the equalization is successful; and / or The first step length is a fixed value or a variable value. If the first step length is a variable value, during the process of starting the PCIe over-speed mode, the closer the rate of the PCIe link is to the maximum over-speed rate, the smaller the first step length.

6. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 5, wherein It further includes: Reduce the current rate of the PCIe link by a preset first step length and perform an equalization operation until the equalization is successful. Then, determine the current rate corresponding to the successful equalization as the maximum over-speed rate and store the maximum over-speed rate.

7. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 5, wherein After an equalization failure occurs, reduce the current rate of the PCIe link by a preset first step length and perform an equalization operation until the equalization is successful; Determine the rate corresponding to the first equalization failure during the current process of starting the PCIe over-speed mode as the historical failure rate, or determine the rate corresponding to the last equalization failure during the current process of starting the PCIe over-speed mode as the historical failure rate.

8. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 1, wherein After starting the PCIe over-speed mode, if the PCIe link is stably operating at the maximum over-speed rate, perform the following steps: Then, increase the current rate of the PCIe link by a preset fourth step length, and the fourth step length is smaller than the first step length; And perform an equalization operation each time the current rate is increased until an equalization failure occurs or the current rate of the PCIe link reaches a preset over-speed rate threshold, and the over-speed rate threshold is greater than the maximum over-speed rate.

9. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 1, characterized in that, The maximum over-speed rate is the upper limit rate at which the PCIe link stably operates in the previous PCIe over-speed mode; or, The maximum over-speed rate is the upper limit rate at which the PCIe link stably operates in the over-speed mode predicted based on the software and hardware of the PCIe link; Or, Determine the maximum overspeed rate according to the following calculation formula: V Turbo = (1 + α)V1, where V Turbo represents the maximum overspeed rate, V1 represents the standard maximum rate corresponding to the highest generation of PCIe supported by the PCIe link, and 0 < α < 1.

10. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 1, wherein, The first step length corresponds to the maximum over-speed rate, and the greater the maximum over-speed rate, the greater the first step length; Or, Determine the difference between the maximum over-speed rate and the standard maximum rate corresponding to the highest generation of PCIe supported by the PCIe link. The first step length corresponds to the difference, and the greater the difference, the greater the first step length.

11. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 1, wherein, Judge whether the link state of the PCIe link supports the PCIe over-speed mode through the following method: Determine the highest generation of PCIe supported by the PCIe link. Assume that the PCIe link supports the Kth generation of PCIe, and K takes 2 or 3 or 4 or 5 or 6; If the current rate of the PCIe link is the standard maximum rate corresponding to the Kth generation of PCIe and the bit error rate is lower than a preset bit error rate threshold, determine that the link state of the PCIe link supports the PCIe over-speed mode.

12. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 11, wherein If the PCIe link supports at least the 5th generation of PCIe and the current rate of the PCIe link has not reached the standard maximum rate corresponding to the 5th generation of PCIe, judge whether the PCIe link supports cross-level equalization; If the PCIe link supports cross-level equalization, increase the current rate of the PCIe link to the standard maximum rate corresponding to the 5th generation of PCIe and perform an equalization operation; If the PCIe link does not support cross-level equalization, the current rate of the PCIe link is gradually increased to the standard maximum rate corresponding to the 5th generation PCIe from generation to generation, and an equalization operation is performed each time / after the rate of the PCIe link is increased.

13. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 11, wherein If the PCIe link supports at least the 5th generation PCIe and the current rate of the PCIe link reaches the standard maximum rate corresponding to the 5th generation PCIe, the current rate of the PCIe link is increased to the standard maximum rate corresponding to the 6th generation PCIe, and an equalization operation is performed; If the equalization is successful, it is determined whether the PCIe link supports the PCIe over-speed mode. If it supports, the PCIe over-speed mode is enabled; otherwise, the PCIe link maintains its current operating state; If the equalization fails, the current rate of the PCIe link is decreased to enable the PCIe link to stably operate at the standard maximum rate corresponding to the 5th generation PCIe, and it is determined whether the PCIe link supports at least the 5th generation PCIe. If so, it is determined whether the PCIe link supports the PCIe over-speed mode. If it supports, the PCIe over-speed mode is enabled; otherwise, the PCIe link maintains its current operating state.

14. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 1, wherein, The hardware information of the PCIe link is determined whether it supports the PCIe over-speed mode in the following way: If the hardware supports the PCIe over-speed mode and the operating state of the hardware also supports the PCIe over-speed mode, it is determined that the hardware information of the PCIe link supports the PCIe over-speed mode; Among them, the operating state of the hardware also supporting the PCIe over-speed mode includes: the power of the hardware is lower than a preset power threshold, and the temperature of the hardware is lower than a preset temperature threshold.

15. The method for implementing the PCIe over-speed mode based on the equalization technology according to claim 1, wherein After the PCIe over-speed mode is implemented, it further includes maintaining the PCIe over-speed mode through the following steps: Monitor the link state of the PCIe link, evaluate the current data transmission quality according to the link state, and the link state also includes the signal jitter situation; If the data transmission quality does not meet the preset first-level requirement but meets the preset second-level requirement, the current rate of the PCIe link is decreased by a preset fifth step size and an equalization operation is performed, and the fifth step size is smaller than the first step size; If the data transmission quality does not meet the preset second-level requirement but meets the preset third-level requirement, the current rate of the PCIe link is decreased to the rate corresponding to the previous stable operation and an equalization operation is performed; If the data transmission quality does not meet the preset third-level requirement, the PCIe over-speed mode is turned off and an equalization operation is performed; The requirements for the first-level requirement, the second-level requirement, and the third-level requirement for the data transmission quality decrease in sequence.

16. A data transmission method, characterized in that, Data transmission is performed based on the PCIe over-speed mode implementation method based on the equalization technology according to any one of claims 1 to 15.

17. A data transmission system, characterized in that, The data transmission system performs data transmission based on the PCIe over-speed mode implementation method based on the equalization technology according to any one of claims 1 to 15.

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