SoC interconnection method and device, electronic equipment, storage medium and domain controller

Abstract

The invention provides an SoC interconnection method and device, electronic equipment, a storage medium and a domain controller. The domain controller provided by the embodiment of the invention comprises two or more SoCs, a high-speed change-over switch and an MCU (Microprogrammed Control Unit). According to the SoC interconnection method provided by the embodiment of the invention, the MCU firstly determines the in-place SoC and the physical position of the in-place SoC and then controls the high-speed change-over switch to conduct the channel of the in-place SoC. According to the invention, the SoC interconnection topological structure can be flexibly adjusted according to the in-place condition of the SoC, the bandwidth of the in-place SoC is improved, the computing power and bandwidth resources of the SoC are balanced, and the energy efficiency of a single-side bottleneck limitation domain controller is effectively prevented.

Description

Technical Field

[0001] The present disclosure relates to autonomous driving technology, and particularly to a method and apparatus for interconnecting System-on-Chips (SoCs), an electronic device, a storage medium, and a domain controller. Background Art

[0002] With the widespread application of autonomous driving technology, the domain controller deployed in a vehicle needs to complete many tasks such as perception, positioning, decision-making, planning, and control functions. Therefore, in a domain controller, it is usually necessary to integrate two or more system-on-chips (SoCs) with different computing powers to meet the requirements of high-performance computing and data processing in vehicle intelligence. This design can provide higher flexibility and efficiency, especially when dealing with complex vehicle electronic systems such as intelligent cockpits, autonomous driving assistance systems, autonomous driving systems, and vehicle infotainment systems.

[0003] In the new generation of autonomous driving field, the requirement for computing power is getting higher and higher, mainly by improving computing power, optimizing algorithms, and reducing the number of sensors such as lidar and cameras to save hardware costs. Currently, the improvement of computing power is mainly achieved through the cascading of SoCs. However, although the cascading of SoCs helps to improve the overall computing performance of the domain controller, in the scenario where only some SoCs are used, the number of SoCs decreases, the amount of data that each SoC needs to process increases, but the bandwidth is not adjusted accordingly, thus causing a performance bottleneck. Summary of the Invention

[0004] In view of this, the present disclosure provides a method and apparatus for interconnecting SoCs, an electronic device, a storage medium, and a domain controller.

[0005] According to a first aspect of the present disclosure, a method for interconnecting SoCs is provided. The method is applied to a domain controller, the domain controller includes two or more SoCs, a high-speed switching switch, and an MCU, each of the SoCs is respectively connected to the high-speed switching switch and the MCU, and the high-speed switching switch is connected to the MCU; the method for interconnecting SoCs is executed by the MCU, and the method for interconnecting SoCs includes:

[0006] Determine the in-place SoCs among the two or more SoCs and their physical positions;

[0007] According to the physical positions of the in-place SoCs, control the high-speed switching switch to conduct the channels of the in-place SoCs.

[0008] In some embodiments of the first aspect of the present disclosure, each of the SoCs is connected to the MCU through an independent SPI and an independent GPIO pin group.

[0009] In some embodiments of the first aspect of the present disclosure, determining the in-place SoCs and their physical positions among the two or more SoCs includes: scanning each of the two or more SoCs through SPI to determine the in-place SoCs, and reading the level states of the GPIO pin groups of the in-place SoCs to identify the physical positions of the in-place SoCs.

[0010] In some embodiments of the first aspect of the present disclosure, controlling the high-speed switching switch to conduct the channels of the in-place SoCs includes: when there are two or more in-place SoCs, writing to the internal register of the high-speed switching switch through the I2C channel to conduct the channels between the high-speed switching switch and the in-place SoCs and disconnect the channels between the high-speed switching switch and other SoCs.

[0011] In some embodiments of the first aspect of the present disclosure, the method further includes: if there is only one in-place SoC, controlling the high-speed switching switch to disconnect the channels of all SoCs.

[0012] In some embodiments of the first aspect of the present disclosure, writing to the internal register of the high-speed switching switch through the I2C channel includes: determining the offset address of the in-place SoC based on the physical position of the in-place SoC; and calculating the target address according to the offset address and the register address of the in-place SoC, and writing a preset instruction to the target address to make the high-speed switching switch conduct the channels between the high-speed switching switch and the in-place SoC.

[0013] According to the second aspect of the present disclosure, there is provided an SoC interconnection device, which is applied to a domain controller. The domain controller includes two or more SoCs, a high-speed switching switch, and an MCU. Each of the SoCs is respectively connected to the high-speed switching switch and the MCU, and the high-speed switching switch is connected to the MCU. The SoC interconnection device is disposed in the MCU and includes:

[0014] a determination unit configured to determine the in-place SoCs and their physical positions among the two or more SoCs;

[0015] a control unit configured to control the high-speed switching switch to conduct the channels of the in-place SoCs according to the physical positions of the in-place SoCs.

[0016] According to the third aspect of the present disclosure, there is provided an electronic device, including: a processor and a memory storing a program, where the program includes instructions that, when executed by the processor, implement the above method.

[0017] According to a fourth aspect of the present disclosure, there is provided a computer-readable storage medium storing a program, where the program includes instructions that, when executed by one or more processors of an electronic device, cause the electronic device to execute the above-mentioned method.

[0018] According to a fifth aspect of the present disclosure, there is provided a domain controller, which includes two or more System-on-Chips (SoCs), a high-speed switching switch, and a Microcontroller Unit (MCU). Each of the SoCs is respectively connected to the high-speed switching switch and the MCU, the high-speed switching switch is connected to the MCU, and the MCU is used to implement the above-mentioned method.

[0019] It can be seen from the above technical solutions that the embodiments of the present disclosure can flexibly adjust the SoC interconnection topology according to the in-position situation of the SoCs, improve the bandwidth of the in-position SoCs, balance the computing power and bandwidth resources of the SoCs, avoid unilateral bottlenecks from restricting the energy efficiency of the domain controller, and further release the computing potential of the SoCs. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 It is a schematic structural diagram of the domain controller provided by the embodiment of the present disclosure;

[0022] Figure 2 It is a schematic flowchart of the SoC interconnection method provided by the embodiment of the present disclosure;

[0023] Figure 3 It is a schematic structural diagram of the SoC interconnection device provided by the embodiment of the present disclosure;

[0024] Figure 4 It is an exemplary structural block diagram of the electronic device provided by the embodiment of the present disclosure. Detailed Embodiments

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some embodiments of the present disclosure, rather than all embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present disclosure.

[0026] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. The singular forms "a", "the", and "said" used in the embodiments of the present disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0027] Depending on the context, words such as "if" and "when" used herein may be interpreted as "when" or "while" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)".

[0028] As described above, when improving the overall computing performance of the domain controller through SoC cascading, reducing the number of SoCs used may instead cause performance bottlenecks due to fixed topology and bandwidth limitations.

[0029] Taking the autonomous driving domain controller as an example, assume that the original SoC cascading structure is 4 SoCs interconnected by 4 links with a bandwidth of 8 GB / s. If 4 SoCs are used, the computing power requirement of each SoC is 20 trillion operations per second (TOPS), 4 links are available, and the total bandwidth is 32 GB / s. In a scenario where only 2 SoCs are available, the number of SoCs is halved, and the computing power requirement of each SoC will increase to 40 TOPS. Since the SoC interconnection topology remains the original structure, only 2 links are available, and the total bandwidth will drop to 16 GB / s. It can be seen that while the data volume to be processed doubles, the bandwidth is halved, resulting in data transmission becoming a bottleneck, and the actual effective computing power may decrease.

[0030] In view of this, the embodiments of the present disclosure provide the following SoC interconnection method, device, electronic device, storage medium, and domain controller. The MCU first determines the in-place SoCs and their physical locations, and then controls the high-speed switching switch to conduct the channels of the in-place SoCs. Thus, the SoC interconnection topology structure can be flexibly adjusted according to the in-place situation of the SoCs, the bandwidth of the in-place SoCs can be increased, the computing power and bandwidth resources of the SoCs can be balanced, the energy efficiency of the domain controller can be avoided from being limited by unilateral bottlenecks, and at the same time, the computing potential of the SoCs can be further released.

[0031] Figure 1 The structural schematic diagram of the domain controller provided by the embodiments of the present disclosure is shown. Refer to Figure 1, the domain controller 100 may include: two or more SoCs 110, a high-speed switching switch 120, and an MCU 130. Each SoC 110 is respectively connected to the high-speed switching switch 120 and the MCU 130, and the high-speed switching switch 120 is connected to the MCU 130. Among them, each SoC 110 is respectively connected to the high-speed switching switch 120 and the MCU 130, and the high-speed switching switch 120 is connected to the MCU 130. The MCU 130 can be used to implement the following SoC 110 interconnection method.

[0032] Among them, the high-speed switching switch 120 (High-Speed Switching Switch) refers to a switch used to quickly switch signal paths. In specific applications, the high-speed switching switch can be replaced with other devices or components with the same function as the high-speed switching switch as needed. In this regard, the embodiments of the present disclosure do not make limitations.

[0033] In some examples, the MCU 130 can be connected to the high-speed switching switch 120 through an Inter-Integrated Circuit (I2C) bus. The I2C bus is a serial bus protocol with a synchronous, half-duplex, multi-master and slave architecture. The MCU 130 uses the I2C bus to connect to the high-speed switching switch 120, ensuring flexible switching and efficient management of the signal path.

[0034] In some examples, each SoC 110 is connected to the MCU 130 through an independent SPI and an independent GPIO pin group. Specifically, the MCU 130 acts as an SPI master, and each SoC 110 acts as an SPI slave, and one-to-one communication is achieved through an independent SPI bus. At the same time, the MCU 130 assigns an independent GPIO pin group to each SoC 110, and the GPIO pins of each SoC 110 are connected to the GPIO pin group assigned by the MCU 130 for this SoC 110.

[0035] The Serial Peripheral Interface (SPI) is a synchronous serial communication protocol used for communication between a microcontroller and various peripherals. In the embodiments of the present disclosure, each SoC 110 is connected to the MCU 130 through an independent SPI bus, and the MCU 130 can then scan each SoC 110 through the SPI channel to determine the in-position status of each SoC 110.

[0036] Each SoC110 is connected to the MCU130 via an independent SPI channel. That is, each SoC110 has its own SPI pins (such as CS, chip select signal), and the MCU130 can communicate with each SoC110 individually through these pins without interference. The independent channel design not only facilitates querying the presence status of the SoC110, but also can improve communication efficiency, reduce communication conflicts, and ensure that each SoC110 can be accurately identified and controlled.

[0037] Exemplarily, the SPI bus involves the following signal lines: a clock signal (SCLK, Serial Clock) line, a master device data output line (MOSI, Master Out Slave In), a master device data input line (MISO, Master In SlaveOut), and a chip select signal (CS, Chip Select) line. Among them, the clock signal on the SCLK is provided by the MCU130 for synchronizing data transmission. The master device data input line is used for the MCU130 to send data to the SoC110, the master device data input line is used for the SoC110 to send data to the MCU130, and the chip select signal is used to select the currently communicating SoC110. Each SoC110 requires an independent CS.

[0038] In some examples, the GPIO pins of each SoC110 can be configured in input mode, and a unique location identifier can be assigned to each SoC110 by setting different level combinations (i.e., combinations of high level and / or low level) on the GPIO pins of the SoC110. The MCU130 determines whether the SoC110 at a certain physical location exists by reading the level status of the GPIO pins, and can also identify the physical location of the SoC110 to which it is connected by reading the level status of the GPIO pins.

[0039] The location identifier is used to uniquely identify a SoC110 and its physical location. That is, the physical locations of different SoC110s can be distinguished by the location identifier, and the GPIO pin level combination of each SoC110 can be set to the binary of its location identifier.

[0040] Figure 1 In an example, the domain controller 100 includes 8 SoC110s, and these 8 SoC110s are respectively connected to the MCU130 through independent SPI interfaces and independent GPIO pin groups. That is to say, these 8 SoC110s are respectively connected to the MCU130 through independent SPI buses and GPIO lines. Thus, the MCU130 can conveniently query the presence status of the SoC110 through the SPI channel and identify the physical location of the present SoC110 through the GPIO channel.

[0041] Taking Figure 1 as an example, when the domain controller 100 includes eight SoCs 110, the eight SoCs 110 can be arranged on the left and right sides of the high-speed switching switch 120 in two columns, with four on the left and four on the right. The position identifiers of these eight SoCs 110 can be set as the arrangement serial numbers of the SoCs 110. That is, the position identifiers of these eight SoCs 110 can be set to 0 to 7 respectively. The position identifier of the first row of SoCs 110 on the left is 0, and so on. The position identifier of the last row of SoCs 110 on the right is 7. Correspondingly, the GPIO pin level combinations of these eight SoCs 110 can be set as the binary numbers of the position identifiers, that is, 000 (corresponding to physical position 0), 001 (corresponding to physical position 1), 010 (corresponding to physical position 2), 011 (corresponding to physical position 3), 100 (corresponding to physical position 4), 101 (corresponding to physical position 5), 110 (corresponding to physical position 6), 111 (corresponding to physical position 7). Thus, when the domain controller 100 includes eight SoCs 110, the number of GPIO pins in the GPIO pin group of each SoC 110 can be 3, and the GPIO pin level state of each SoC 110 can uniquely indicate the physical position of the SoC 110 or indicate whether the SoC 110 at the physical position exists. For example, if the return value obtained by the MCU 130 reading the GPIO pin level state at physical position 5 is 101, it indicates that the SoC 110 at physical position 5 (i.e., SoC1105) exists, that is, the MCU 130 and the SoC 1105 can communicate normally.

[0042] In some examples, each SoC 110 can be connected to the high-speed switching switch 120 through its own independent channel, and the channels between each SoC 110 and the high-speed switching switch 120 can be independently controlled. Specifically, taking Figure 1 as an example, each SoC 110 is connected to the high-speed switching switch 120 through a dedicated data channel. If the data channels of SoC0 and SoC7 are turned on and the data channels of SoC1 to SoC6 are all turned off, then SoC0 and SoC1 can be interconnected through the high-speed switching switch 120. For another example, if the data channels of all SoCs are turned on, then these eight SoCs 110 can be interconnected through the high-speed switching switch 120.

[0043] It should be noted that the specific structure of the domain controller and the connection method of each part are not limited to the above methods.

[0044] Figure 2 The flowchart of the SoC interconnection method provided by the embodiments of the present disclosure is shown. The SoC interconnection method provided by the embodiments of the present disclosure can be executed by the MCU in the domain controller 100. Refer to Figure 2 shown, the SoC interconnection method of the embodiments of the present disclosure can include the following steps:

[0045] Step 201, determine the in-place SoC and its physical location;

[0046] Specifically, the MCU scans each of two or more SoCs through SPI to determine the in-place SoC, and reads the level status of the GPIO pin group of the in-place SoC to identify the physical location of the in-place SoC.

[0047] The SPI channels of each SoC and the MCU are independent. A unique ID can be configured for each SoC and the ID value is stored in the register of the SoC, and the address of the register is fixed. The MCU can access the register of the SoC through the SPI channel and read the ID value therein, and determine whether the SoC is in place through the ID value.

[0048] The ID value is a pre-set identifier, which can be used to distinguish different SoCs. In a specific application, it is possible to determine whether the SoC is in place through the ID value by checking whether the ID value is a pre-set valid value, the check code corresponding to the ID value, the format of the ID value, etc. For example, if the read ID value is a pre-set valid value, it indicates that the SoC is in place and can communicate normally; if the read ID value is a pre-set invalid value or any other value, it indicates that the SoC is not in place, and the SoC may not be installed or malfunction. The specific verification method for whether the ID value is valid is not limited in the embodiments of the present disclosure.

[0049] Assume that the register address storing the ID is 0x00001d. The ID value (i.e., the pre-set valid value) when the SoC is in place can be pre-configured as 0xdd, and the ID value (i.e., the pre-set invalid value) when the SoC is not in place can be "0x00". Specifically, after the power-on initialization is completed, the MCU selects an SoC through CS, sends a read command to the SoC through the MOSI line, specifies the register address "0x00001d" in the read command, and receives the ID value returned by the SoC through the MISO. If the ID value is "0xdd", the ID value is valid, and it is determined that the SoC is in place and can communicate normally. If the ID value is "0x00" or any other value, it is determined that the SoC is not in place, and the SoC may not be installed or malfunction. Repeat the above steps for all SoCs to complete the scan. In this way, the MCU can efficiently manage and initialize all SoCs and can timely obtain the in-place status of each SoC.

[0050] For the specific implementation of the MCU to read the level status of the GPIO pin group of the in-place SoC to identify the physical location of the in-place SoC, reference can be made to the relevant records in the foregoing text. Assume that the in-place SoC includes SoC5 at physical location 5 on the high-speed switching switch. The MCU reads the level status of the GPIO pin group at the physical location "5" of SoC5. If the value returned by the MCU when reading physical location 5 is 101, it indicates that the SoC at physical location 5 (i.e., SoC5) exists. If the value returned by physical location 5 is 000 or other values, it indicates that there is no SoC at physical location 5, that is, SoC5 does not exist. Thus, while identifying the physical location of the SoC through the GPIO channel, it is confirmed whether the in-place SoC exists, that is, whether the in-place SoC can communicate normally.

[0051] For example, in some MCUs, the GPIO_ReadInputDataBit() function or other similar functions can be used to read the level status of the GPIO pins. According to the read level combination, the MCU can identify whether the SoC at each physical location exists or the physical location of the connected SoC.

[0052] Step 202, according to the physical location of the in-place SoC, control the high-speed switching switch to conduct the channel of the in-place SoC.

[0053] Specifically, after the MCU obtains the physical location of the in-place SoC, it can control the high-speed switching switch to conduct the channel of the in-place SoC through the I2C channel, thereby changing the topology of the SoC according to the real-time in-place status of the SoC, achieving the effect of improving the bandwidth of the in-place SoC and effectively balancing the computing power and bandwidth of the in-place SoC.

[0054] In some embodiments, step 202 may include: when there are two or more in-place SoCs, the MCU can write to the internal register of the high-speed switching switch through the I2C channel to conduct the channel between the high-speed switching switch and the in-place SoC and disconnect the channel between the high-speed switching switch and other SoCs.

[0055] In some embodiments, step 202 may further include: when there is one in-place SoC, the MCU can write to the internal register of the high-speed switching switch through the I2C channel to conduct the channel between the high-speed switching switch and the in-place SoC and disconnect the channel between the high-speed switching switch and all other SoCs.

[0056] Furthermore, the method of the embodiments of the present disclosure may further include: if there is only one in-place SoC, the MCU controls the high-speed switching switch to disconnect all the channels of the SoCs. Thus, when only one SoC is available, the high-speed switching switch is not used, but the SoC is directly used, enabling better balance of the bandwidth and computing power of the SoC when a single SoC is available in the domain controller.

[0057] The MCU can write the value related to the in-place SoC channel in the internal register of the high-speed switching switch through the I2C channel to turn on the channel between the high-speed switching switch and the in-place SoC. Specifically, the MCU determines the offset address of the in-place SoC based on the physical location of the in-place SoC, calculates the target address according to the offset address of the in-place SoC and the register address, and writes a preset instruction to the target address to turn on the channel between the high-speed switching switch and the in-place SoC.

[0058] Exemplarily, in the address mapping rule of the MCU, the physical location of the SoC is directly associated with its base address. The MCU can determine the base address of the SoC based on the physical location of the SoC, and calculate the offset address of the SoC according to the base address of the SoC. For the specific implementation method of the MCU to determine its offset address based on the physical location of the SoC, the embodiments of the present disclosure do not show.

[0059] Among them, the target address points to a specific register or a specific address bit in the internal register of the high-speed switching switch. The target address can be obtained by adding the register address and the offset address of the in-place SoC.

[0060] Among them, the preset instruction for turning on the channel between the high-speed switching switch and the SoC can be preset. For example, based on the hardware design and register configuration logic, the preset instruction for turning on the channel between the high-speed switching switch and the SoC can be set to the switch channel register "0xFF (i.e., 11111111 in binary)", that is, the MCU can write "0xFF" to the target address corresponding to the in-place SoC, and the high-speed switching switch reads and executes the "0xFF" at the target address to activate or open its own channel with the in-place SoC.

[0061] In a specific application, the value related to the SoC in the internal register of the high-speed switching switch can be default-configured as a preset instruction for disconnecting the channel between the high-speed switching switch and the SoC.

[0062] It should be noted that the preset instruction for turning on the channel between the high-speed switching switch and the SoC is predefined according to the hardware design, and can be flexibly set according to needs in specific applications. The embodiments of the present disclosure do not limit the specific form and its configuration method of the preset instruction. For example, the preset instruction can also be set to 0x01, 0x02 or other specific values.

[0063] As can be seen from the above, the MCU can control the high-speed switching switch to turn on the channel of the in-place SoC and turn off the channel of the non-in-place SoC through a simple write operation, realizing flexible adjustment of the SoC cascade topology.

[0064] Still taking Figure 1 as an example, the domain controller includes 8 SoCs. The specific implementation process of step 202 can include the following several situations:

[0065] If there is only 1 in - place SoC, the high - speed switching switch is not operated, and all SoC channels on the high - speed switching switch are kept disconnected. The cascade function is not used, that is, the high - speed interconnection topology structure is not used. At this time, the domain controller adopts a structure with only 1 SoC, and the bandwidth allocated to this SoC is the total bandwidth B of the high - speed switching switch.

[0066] If there are 2 in - place SoCs and the register address is 0x20, the offset addresses are determined according to the physical positions of these 2 in - place SoCs respectively. The target addresses of each in - place SoC are obtained by adding the offset address of each SoC to this register address. The MCU writes 0xff into the internal register of the high - speed switching switch pointed to by the target address of each in - place SoC to make the channels between these 2 in - place SoCs and the high - speed switching switch conductive. Thus, these 2 in - place SoCs can be interconnected through the high - speed switching switch, forming an interconnection topology structure of 2 SoCs. Only 2 SoCs share the total bandwidth provided by the high - speed switching switch. Assuming the total bandwidth of the high - speed switching switch is B, ideally, the bandwidth that each SoC can be allocated is B / 2, that is, one - half of B.

[0067] If there are 4 in - place SoCs and the register address is 0x30, the offset addresses are determined according to the physical positions of these 4 in - place SoCs respectively. The target addresses of each in - place SoC are obtained by adding the offset address of each SoC to this register address. The MCU writes 0xff into the internal register of the high - speed switching switch pointed to by the target address of each in - place SoC to make the channels between these 4 SoCs and the high - speed switching switch conductive. Thus, these 4 in - place SoCs can be interconnected through the high - speed switching switch, forming an interconnection topology structure of 4 SoCs. Only 4 SoCs share the total bandwidth provided by the high - speed switching switch. Assuming the total bandwidth of the high - speed switching switch is B, ideally, the bandwidth that each SoC can be allocated is B / 4, that is, one - quarter of B.

[0068] If there are 8 in - place SoCs, that is, all SoCs are in - place, and the register address is 0x40, the MCU directly operates the register address and writes 0xff into the internal register of the high - speed switching switch to make the channels between these 8 in - place SoCs and the high - speed switching switch conductive. Thus, these 8 in - place SoCs can be interconnected through the high - speed switching switch, forming an interconnection topology structure of 8 SoCs. 8 SoCs share the total bandwidth provided by the high - speed switching switch. Assuming the total bandwidth of the high - speed switching switch is B, ideally, the bandwidth that each SoC can be allocated is B / 8, that is, one - eighth of B.

[0069] It can be seen that when the domain controller includes 8 SoCs, the interconnection topologies of 1, 2, 4, and 8 SoCs can be realized through the embodiments of the present disclosure. For different interconnection topologies, the bandwidth of each SoC is synchronously adjusted. The bandwidth of each SoC will dynamically increase as the number of turned-on SoCs decreases. Therefore, the present disclosure can flexibly adjust the SoC interconnection topology according to the situation of the in-place SoCs, and adaptively adjust the bandwidth of the SoCs at the same time, so that the computing power and bandwidth of the SoCs can be balanced, thereby effectively preventing unilateral bottlenecks from restricting the energy efficiency of the domain controller, further releasing the computing potential of the SoCs, and at the same time having the advantages of strong scalability and high flexibility.

[0070] Figure 3 FIG. shows a schematic structural diagram of an SoC interconnection device provided by an embodiment of the present disclosure. The SoC can be applied to the aforementioned domain controller 100, and the SoC interconnection device can be arranged in the MCU. Refer to Figure 3 , the fault detection device 300 of the embodiment of the present disclosure may include:

[0071] A determination unit 301, configured to determine the in-place SoCs and their physical positions in two or more SoCs;

[0072] A control unit 302, configured to control the high-speed switching switch to turn on the channels of the in-place SoCs according to the physical positions of the in-place SoCs.

[0073] Further, the determination unit 301 may specifically be configured to: scan each of the two or more SoCs through SPI to determine the in-place SoCs, and read the level status of the GPIO pin group of the in-place SoCs to identify the physical positions of the in-place SoCs.

[0074] Further, the control unit 302 may specifically be configured to: when there are two or more in-place SoCs, write to the internal register of the high-speed switching switch through the I2C channel to turn on the channels between the high-speed switching switch and the in-place SoCs and disconnect the channels between the high-speed switching switch and other SoCs.

[0075] Further, the control unit 302 may also be configured to: if there is only one in-place SoC, control the high-speed switching switch to disconnect all the channels of the SoCs.

[0076] Further, the control unit 302 may specifically be configured to: determine the offset address of the in-place SoC according to the physical position of the in-place SoC; and calculate the target address according to the offset address and the register address of the in-place SoC, and write a preset instruction to the target address to make the high-speed switching switch turn on the channel between the high-speed switching switch and the in-place SoC.

[0077] Other technical details of the SoC interconnection device 300 can be found in the description of the foregoing method, and will not be elaborated here. In specific applications, the SoC interconnection device 300 can be implemented by software, hardware, or a combination of both. For example, the SoC interconnection device 300 can be implemented as software running in the following electronic device 400.

[0078] In addition, an embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored. The program includes instructions that, when executed by one or more processors of a computing device, perform the steps of the foregoing SoC interconnection method.

[0079] Figure 4 The structural schematic diagram of the electronic device provided by the embodiment of the present disclosure is shown. Refer to Figure 4 , the electronic device 400 may include: one or more processors 401, and further includes a memory 402 storing one or more programs, which are executed by the one or more processors 401 to implement the method flow shown in the foregoing embodiments of the present disclosure and / or the program units corresponding to the respective units in the device.

[0080] Each component is interconnected using different buses and can be installed on a common motherboard or otherwise as needed. The processor 401 can process instructions executed within the electronic device, including instructions for storing graphical information in the memory or on the memory to be displayed on an external input / output device (such as a display device coupled to the interface). In other embodiments, if needed, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories.

[0081] The processor 401 may include one or more single-core processors or multi-core processors. The processor 401 may include any combination of general-purpose processors or dedicated processors (such as image processors, application processors, baseband processors, etc.).

[0082] The memory 402 is the computer-readable storage medium provided by the present disclosure and can be used to store non-transitory software programs, non-transitory computer-executable programs, and units, such as the program instructions / units corresponding to the SoC interconnection method shown in the embodiments of the present disclosure. Figure 2 The processor 401 executes non-transitory software programs, instructions, and units stored in the memory 402, thereby executing the programs, instructions, and units corresponding to the SoC interconnection method shown in the foregoing method embodiments. Figure 2 shown.

[0083] The electronic device 400 may further include: an input device 403 and an output device 404. The processor 401, the memory 402, the input device 403, and the output device 404 can be connected by a bus or other means.Figure 4 Take the bus connection as an example.

[0084] The input device 403 can receive input digital or character information, and generate signal inputs related to user settings and function controls, such as input devices like touchscreens, keypads, mice, trackpads, touchpads, pointing sticks, one or more mouse buttons, trackballs, joysticks, etc. The output device 404 can include display devices, auxiliary lighting devices (e.g., LEDs), and tactile feedback devices (e.g., vibration motors), etc. The display device can include, but is not limited to, liquid crystal displays (LCDs), light-emitting diode (LED) displays, and plasma displays. In some embodiments, the display device can be a touchscreen.

[0085] The above program (also referred to as software, software application, or code) includes machine instructions for a programmable processor, and these computing programs can be implemented using object-oriented programming languages, assembly, or machine language.

[0086] With the development of time and technology, the meaning of the medium has become more and more extensive. The dissemination path of computer programs is no longer limited to tangible media, and can also be directly downloaded from the network, etc. Any combination of one or more computer-readable storage media can be adopted. The computer-readable storage medium can be, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or component.

[0087] In a specific application, the electronic device 600 can be implemented as, but is not limited to, an MCU in a domain controller or other similar devices.

[0088] The domain controller provided by the embodiments of the present disclosure can be of any type. For example, the domain controller can be implemented as, but is not limited to, the following types: power domain controller, chassis domain controller, body domain controller, intelligent cockpit domain controller, autonomous driving domain controller. For another example, the domain controller can also be implemented as the following types: L2-level domain controller, L3-level domain controller, L4-level domain controller.

[0089] Embodiments of the present disclosure can be applied to the control of various devices such as multiple wheeled mobile robots, wheeled mobile robots, mobile robots, vehicles, aircraft, ships, intelligent rail rapid transit systems (ART, Autonomous rail Rapid Transit), etc. The vehicle can be, but is not limited to, a passenger vehicle, a commercial vehicle (e.g., a truck, a bus, a freight vehicle, etc.), a special-purpose vehicle (e.g., an ambulance, a fire truck, an engineering vehicle, a rescue vehicle, etc.), an agricultural and industrial vehicle (e.g., a harvester, a forklift, etc.), a transportation and logistics vehicle (e.g., a container truck, a refrigerated truck, etc.), a new energy vehicle (e.g., an electric vehicle, a hybrid vehicle), a special carrier (e.g., a garbage truck, a sprinkler truck, etc.). In other words, the "vehicle" and the like involved in the embodiments of the present disclosure can be replaced by any of the foregoing devices.

[0090] Embodiments of the present disclosure further provide a vehicle, which may include the foregoing domain controller 100. The vehicle can implement, but is not limited to, the foregoing various devices such as multiple wheeled mobile robots, wheeled mobile robots, mobile robots, vehicles, aircraft, ships, intelligent rail rapid transit systems (ART, Autonomous rail Rapid Transit), etc.

[0091] Embodiments of the present disclosure can be applied to scenarios such as ports, highways, logistics, mines, farms, closed parks, urban transportation, etc., and are applicable to many aspects such as logistics distribution, unmanned transportation, last-mile delivery, ride-hailing, automated agricultural operations, automated environmental sanitation, etc. Of course, embodiments of the present disclosure can also be applied to any other scenario involving a domain controller. The present disclosure does not limit the application scenarios and applicable fields of embodiments of the present disclosure.

[0092] The above has introduced the technical solutions provided by the present disclosure in detail. Specific examples are used herein to elaborate on the principles and implementation manners of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of the present disclosure; at the same time, for those of ordinary skill in the art, according to the idea of the present disclosure, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present disclosure.

[0093] The foregoing is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modification, equivalent replacement, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A SoC interconnection method, characterized in that, The method is applied to a domain controller, which includes two or more System on Chips (SoCs), a high-speed switching switch, and a Microcontroller Unit (MCU). Each of the SoCs is respectively connected to the high-speed switching switch and the MCU, and the high-speed switching switch is connected to the MCU. The SoC interconnection method is executed by the MCU, and the SoC interconnection method includes: Determining the present SoCs among the two or more SoCs and their physical positions; Controlling the high-speed switching switch to turn on the channels of the present SoCs according to the physical positions of the present SoCs.

2. The method according to claim 1, wherein Each of the SoCs is connected to the MCU through an independent Serial Peripheral Interface (SPI) and an independent General-Purpose Input / Output (GPIO) pin group.

3. The method according to claim 2, wherein The determining the present SoCs among the two or more SoCs and their physical positions includes: Scanning each of the two or more SoCs through SPI to determine the present SoCs, and reading the level states of the GPIO pin groups of the present SoCs to identify the physical positions of the present SoCs.

4. The method according to claim 1, characterized in that, The controlling the high-speed switching switch to turn on the channels of the present SoCs includes: when there are two or more present SoCs, writing to the internal register of the high-speed switching switch through an Inter-Integrated Circuit (I2C) channel to turn on the channels between the high-speed switching switch and the present SoCs and turn off the channels between the high-speed switching switch and other SoCs.

5. The method according to claim 1 or 4, characterized in that, The method further includes: if there is only one present SoC, controlling the high-speed switching switch to turn off the channels of all SoCs.

6. The method according to claim 4, wherein The writing to the internal register of the high-speed switching switch through the I2C channel includes: Determining the offset address of the present SoC according to the physical position of the present SoC; and Calculating the target address according to the offset address and the register address of the present SoC, and writing a preset instruction to the target address to make the high-speed switching switch turn on the channels between the high-speed switching switch and the present SoC.

7. A SoC interconnection device, characterized in that, The SoC interconnection device is applied to a domain controller, which includes two or more SoCs, a high-speed switching switch, and a MCU. Each of the SoCs is respectively connected to the high-speed switching switch and the MCU, and the high-speed switching switch is connected to the MCU. The SoC interconnection device is arranged in the MCU, and the SoC interconnection device includes: A determining unit, configured to determine the present SoCs among the two or more SoCs and their physical positions; A control unit, configured to control the high-speed switching switch to turn on the channels of the present SoCs according to the physical positions of the present SoCs.

8. An electronic device, characterized in that, including: A processor and a memory storing a program, where the program includes instructions, and the instructions, when executed by the processor, implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium storing a program, where the program includes instructions, and the instructions, when executed by one or more processors of an electronic device, cause the electronic device to execute the method according to any one of claims 1 to 6.

10. A domain controller, characterized in that, The domain controller includes two or more System on Chips (SoCs), a high-speed switching switch, and a Microcontroller Unit (MCU). Each of the SoCs is respectively connected to the high-speed switching switch and the MCU. The high-speed switching switch is connected to the MCU. The MCU is used to implement the method according to any one of claims 1 to 6.

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