Reconfigurable chip hardware acceleration control structure and control method thereof

Abstract

The invention provides a reconfigurable chip hardware acceleration control device. The reconfigurable chip hardware acceleration control device comprises a bus; the first processing core is connected with the bus, the first processing core comprises a signal generation module, a signal processing module, a data acquisition module and an operation module, the signal processing module is connected with the first end of the data acquisition module, and the first processing core is used for data configuration; the second processing core is respectively connected with the bus and the first processing core, the second processing core comprises a node module, a data flow control module, a data storage control module, an interrupt linkage module, a reconstruction module and a protection module, and the node module is connected with the data storage control module. According to the technical scheme of the embodiment, the hardware acceleration control structure can independently run from the MCU core, so that the MCU core and the hardware acceleration control structure independently run, and the running speed of the MCU is increased.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and particularly to a reconfigurable chip hardware acceleration control structure and a control method thereof. Background Art

[0002] At present, with the continuous upgrading of the electronics and electrical industries, the demand for lightweight and high-efficiency electrical or electronic products is becoming increasingly strong. The key to achieving lightweight and high-efficiency for power electronic products is to increase the switching frequency, but increasing the switching frequency poses a great challenge to the MCU processor. In the prior art, the computing time within the switching cycle is reduced by increasing the operating frequency of the MCU. However, the MCU also has some slow modules for communication or detecting digital input signals, resulting in conflicts between the slow modules and the fast modules within a control core. For example, the fast modules frequently enter interrupts, causing the slow modules to wait for a long time without response. In addition, simply increasing the speed of the MCU will also bring potential risks such as high-speed timing, temperature rise, and lifespan. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides a reconfigurable chip hardware acceleration control structure and a control method thereof, which can operate independently of the MCU core, enabling the MCU core and the hardware acceleration control structure to operate independently, thereby improving the operating speed of the MCU.

[0004] In a first aspect, an embodiment of the present invention provides a reconfigurable chip hardware acceleration control structure, including:

[0005] A bus;

[0006] A first processing core, which is connected to the bus. The first processing core includes a signal generation module, a signal processing module, a data acquisition module, and an operation module. The signal processing module is connected to the first end of the data acquisition module. The first processing core is used for data configuration;

[0007] A second processing core, the second processing core is respectively connected to the bus and the first processing core, the second processing core includes a node module, a data flow control module, a data storage control module, an interrupt linkage module, a reconstruction module and a protection module, the node module is connected to the data storage control module, a first end of the interrupt linkage module is connected to the reconstruction module, a first end of the data flow control module, a first end of the protection module and a first end of the signal generation module are all connected to the operation module, a second end of the interrupt linkage module is connected to a second end of the data flow control module, a third end of the data flow control module is connected to a second end of the protection module, a third end of the protection module is connected to a second end of the signal generation module, a third end of the signal generation module is connected to a second end of the data acquisition module, a fourth end of the data flow control module is connected to a fourth end of the signal generation module, the second processing core is used to generate a timing pulse drive, and the node module, the data flow control module, the data storage control module, the interrupt linkage module, the reconstruction module and the protection module operate in sequence according to the timing pulse drive.

[0008] In some embodiments of the present invention, the operation module at least includes a first operation unit, a second operation unit and a third operation unit, the node module is adapted to the data storage control module and forms a first power electronic control core, the interrupt linkage module is adapted to the reconstruction module and forms a second power electronic control core, the data flow control module is adapted to the first operation unit and forms a third power electronic control core, the protection module is adapted to the second operation unit and forms a fourth power electronic control core, the signal generation module is adapted to the third operation unit and forms a fifth power electronic control core, the data acquisition module is adapted to the signal processing module and forms a sixth power electronic control core, and the first power electronic control core to the sixth power electronic control core form a first loop architecture.

[0009] In some embodiments of the present invention, the signal generation module, the signal processing module, the data acquisition module, the first operation unit, the second operation unit, the third operation unit, the node module, the data flow control module, the data storage control module, the interrupt linkage module, the reconstruction module and the protection module are all provided with a bus connection unit, a read-write control unit, a timing pulse reading unit, an end pulse unit, a reset pulse unit and an enable signal unit, and the bus connection unit, the read-write control unit, the timing pulse reading unit, the end pulse unit, the reset pulse unit and the enable signal unit of the corresponding modules in the first power electronic control core to the sixth power electronic control core are correspondingly connected.

[0010] In some embodiments of the present invention, the data stream control module is used to generate a first pulse signal, a reset signal, and an enable signal. The signal generation module, the signal processing module, the data acquisition module, the operation module, the node module, the data stream control module, the data storage control module, the interrupt linkage module, the reconstruction module, and the protection module obtain their own operation sequences according to the first pulse signal. The data storage control module is used to control the data storage of the first processing core and the second processing core. The interrupt linkage module is used to establish the interrupt linkage between the first processing core and the second processing core. The protection module is used to turn off the module flow operation of the signal generation module and the second processing core.

[0011] In some embodiments of the present invention, the end pulse unit is used to generate a pulse end signal, so that the data stream control module determines the end of the current module operation according to the pulse end signal and generates a second pulse signal. The reset pulse unit is used to generate a reset pulse.

[0012] In a second aspect, an embodiment of the present invention provides a control method for a reconfigurable chip hardware acceleration control structure, including:

[0013] Obtain preset module flow timing pulse numbers and module configuration parameters;

[0014] The first processing core and the second processing core are started according to the module flow timing pulse numbers and the module configuration parameters;

[0015] The first processing core and the second processing core start the node module and the data storage control module in the first power electronic control core, the interrupt linkage module and the reconstruction module in the second power electronic control core, the data stream control module and the first operation unit in the third power electronic control core, the protection module and the second operation unit in the fourth power electronic control core, the signal generation module and the third operation unit in the fifth power electronic control core, and the data acquisition module and the signal processing module in the sixth power electronic control core. Among them, the number of modules started in the first power electronic control core to the sixth power electronic control core is the same as the module flow timing pulse numbers, and the start time of the modules in each power electronic control core is the same;

[0016] After each power electronic control core is started, it sends a pulse generation signal to the next power electronic control core;

[0017] When the first power electronic control core to the sixth power electronic control core complete the operation, the end pulse unit generates a pulse end signal, and the data stream control module makes a determination on the modules in operation according to the pulse end signal to obtain a determination result;

[0018] Write the determination result into the read-write control unit in the power electronic control core where the current module is located. The end pulse unit generates a pulse end signal to cause the first processing core and the second processing core to complete the loop.

[0019] In some embodiments of the present invention, the first processing core and the second processing core are started according to the module flow timing pulse number and the module configuration parameters, including:

[0020] Obtain the first module flow sequence number, the second module flow sequence number, the input data start address, the input data length, the output data start address, and the output data length;

[0021] The first processing core and the second processing core start running according to the first module flow sequence number and the second module flow sequence number;

[0022] After the first processing core and the second processing core finish running, the end pulse unit generates a pulse end signal, and the first processing core and the second processing core complete the loop.

[0023] In some embodiments of the present invention, after the first processing core and the second processing core complete the loop, the method further includes:

[0024] When the second data stream serial number is zero and the first module flow sequence number is one, the first power electronic control core starts running and obtains the input data length from the input data start address;

[0025] After the first power electronic control core finishes running, write the operation result into the output data length at the output data start address.

[0026] In a third aspect, an embodiment of the present invention provides a reconfigurable chip hardware acceleration control device, including at least one control processor and a memory communicatively connected to the at least one control processor; the memory stores instructions executable by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to execute the reconfigurable chip hardware acceleration control method as described in the first aspect above.

[0027] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium storing computer-executable instructions for executing the reconfigurable chip hardware acceleration control method as described in the first aspect above.

[0028] The reconfigurable chip hardware acceleration control device according to the embodiment of the present invention has at least the following beneficial effects:

[0029] Bus; a first processing core connected to the bus, the first processing core including a signal generation module, a signal processing module, a data acquisition module, and an operation module, the signal processing module being connected to the first end of the data acquisition module, the first processing core being used for data configuration; a second processing core, the second processing core being connected to the bus and the first processing core respectively, the second processing core including a node module, a data flow control module, a data storage control module, an interrupt linkage module, a reconstruction module, and a protection module, the node module being connected to the data storage control module, the first end of the interrupt linkage module being connected to the reconstruction module, the first ends of the data flow control module, the protection module, and the signal generation module all being connected to the operation module, the second end of the interrupt linkage module being connected to the second end of the data flow control module, the third end of the data flow control module being connected to the second end of the protection module, the third end of the protection module being connected to the second end of the signal generation module, the third end of the signal generation module being connected to the second end of the data acquisition module, the fourth end of the data flow control module being connected to the fourth end of the signal generation module, the second processing core being used for generating a timing pulse drive, and the node module, the data flow control module, the data storage control module, the interrupt linkage module, the reconstruction module, and the protection module operating in sequence according to the timing pulse drive. According to the technical solution of this embodiment, it can operate independently of the MCU core, enabling the MCU core and the hardware acceleration control structure to operate independently of each other, and improving the operating speed of the MCU. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram of the overall structure of a reconfigurable chip hardware acceleration control structure provided by an embodiment of the present invention;

[0031] Figure 2 is a schematic diagram of a conventional control loop provided by an embodiment of the present invention;

[0032] Figure 3 is a conventional timing operation diagram provided by an embodiment of the present invention;

[0033] Figure 4 is a schematic diagram of a PFC control loop provided by an embodiment of the present invention;

[0034] Figure 5 is a PFC timing operation diagram provided by an embodiment of the present invention;

[0035] Figure 6 is a flowchart of a control method for a reconfigurable chip hardware acceleration control structure provided by an embodiment of the present invention;

[0036] Figure 7 is a startup flowchart of the first processing core and the second processing core according to the module flow timing pulse number and the module configuration parameters provided by an embodiment of the present invention;

[0037] Figure 8 is the flowchart after the first processing core and the second processing core provided by an embodiment of the present invention complete a cycle;

[0038] Figure 9 is the structural diagram of a reconfigurable chip hardware acceleration control device provided by another embodiment of the present invention. Detailed implementation manners

[0039] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention.

[0040] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as up, down, front, back, left, right, etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0041] In the description of the present invention, the meaning of several is one or more, the meaning of multiple is two or more, greater than, less than, exceeding, etc. are understood as not including the present number, and above, below, within, etc. are understood as including the present number. If the first and second are described only for the purpose of distinguishing technical features, they should not be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or the sequence relationship of the indicated technical features.

[0042] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installation, connection, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0043] Refer to Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 and Figure 5, an embodiment of the present invention provides a reconfigurable chip hardware acceleration control structure, including a bus 100; a first processing core, the first processing core is connected to the bus 100, the first processing core includes a signal generation module 210, a signal processing module 220, a data acquisition module 230, and an arithmetic module 240, the signal processing module 220 is connected to the first end of the data acquisition module 230, and the first processing core is used for data configuration; a second processing core, the second processing core is respectively connected to the bus 100 and the first processing core, the second processing core includes a node module 310, a data flow control module 320, a data storage control module 330, an interrupt linkage module 340, a reconfiguration module 350, and a protection module 360, the node module 310 is connected to the data storage control module 330, the first end of the interrupt linkage module 340 is connected to the reconfiguration module 350, the first ends of the data flow control module 320, the protection module 360, and the signal generation module 210 are all connected to the arithmetic module 240, the second end of the interrupt linkage module 340 is connected to the second end of the data flow control module 320, the third end of the data flow control module 320 is connected to the second end of the protection module 360, the third end of the protection module 360 is connected to the second end of the signal generation module 210, the third end of the signal generation module 210 is connected to the second end of the data acquisition module 230, the fourth end of the data flow control module 320 is connected to the fourth end of the signal generation module 210, the second processing core is used for generating a timing pulse drive, and the node module 310, the data flow control module 320, the data storage control module 330, the interrupt linkage module 340, the reconfiguration module 350, and the protection module 360 run in sequence according to the timing pulse drive.

[0044] It should be noted that the bus 100, as the main channel for data transmission, connects each functional module in the first processing core and the second processing core to achieve high-speed data transmission and sharing; the first processing core is used for tasks such as signal generation, signal processing, data acquisition, and arithmetic operations; the second processing core is used for generating a timing pulse drive and controlling the node module 310, the data flow control module 320, the data storage control module 330, the interrupt linkage module 340, the reconfiguration module 350, and the protection module 360 to run in sequence, so as to achieve the reconfigurability and high efficiency of the hardware acceleration control structure.

[0045] It should be noted that through hardware acceleration and parallel processing, the computing performance and throughput of the MCU are improved. The dynamic adjustment and configuration of the hardware acceleration control structure are realized through the reconfigurable module 350 to adapt to different application scenarios and algorithm requirements. Further, through the protection module 360 and the interrupt linkage module 340, the security and stability of the system are improved, and system crashes or data loss caused by hardware failures or abnormal operations are prevented. In addition, through modular design in this embodiment, the acceleration control structure can conveniently handle subsequent function expansion and upgrade, reducing the maintenance cost of the system.

[0046] It should be noted that the first processing core of this embodiment includes the PWM (signal generation module 210), IIR (signal processing module 220), ADC (data acquisition module 230), and MATH (operation module 240) that a conventional MCU has, and also includes modules such as STATION (node module 310), CACHE (data storage control module 330), EVENT (interrupt linkage module 340), CONTROL (data flow control module 320), and PROTECT (protection module 360) required by the second processing core. All modules are connected to the original bus 100. Whether the power electronics control core formed by connecting multiple modules through the first processing core is connected to the second processing core is controlled.

[0047] Further, by setting the number of module flow timing pulses in a control loop, each module is driven to run in sequence by the pulse stream. Exemplarily, assuming the pulse is 6, the number of modules participating in the control loop is 6. The first pulse is for determining data refresh, such as the data sent by the bus 100 or the data to be sent out from the acceleration control module. The subsequent modules are A, B, C... in sequence, and the pulse recognition numbers of A, B, C, D, etc. have been pre-configured as 2, 3, 4, 5; each module runs when it recognizes that the number of module flow timing pulses is its pre-set number of modules. When the module starts to run, it first reads the data from the data storage control module 330 according to the set address, and after the calculation module performs the calculation and stores it at the set address, an end pulse is generated to let the timing control module update the module flow timing pulses and enter the operation of the next module.

[0048] Specifically, Figure 4 The acceleration loop configuration information of the shown PFC control loop block diagram is as follows:

[0049]

[0050] The operation module 240 includes at least a first operation unit 241, a second operation unit 242, and a third operation unit 243. The node module 310 is adapted to the data storage control module 330 and forms a first power electronics control core. The interrupt linkage module 340 is adapted to the reconstruction module 350 and forms a second power electronics control core. The data flow control module 320 is adapted to the first operation unit 241 and forms a third power electronics control core. The protection module 360 is adapted to the second operation unit 242 and forms a fourth power electronics control core. The signal generation module 210 is adapted to the third operation unit and forms a fifth power electronics control core. The data acquisition module 230 is adapted to the signal processing module 220 and forms a sixth power electronics control core. The first to the sixth power electronics control cores form a first loop architecture.

[0051] It should be noted that the first power electronics control core is formed by the adaptation of the node module 310 and the data storage control module 330, and is responsible for data storage, reading, and node control. The second power electronics control core: formed by the adaptation of the interrupt linkage module 340 and the reconstruction module 350, is responsible for monitoring the operating state of the system, timely triggering interrupt signals, and dynamically adjusting the configuration of the hardware acceleration control structure as needed. The third power electronics control core is formed by the adaptation of the data flow control module 320 and the first operation unit 241, and is responsible for controlling the operating states of other modules and coordinating the timing relationships between modules. The fourth power electronics control core: formed by the adaptation of the protection module 360 and the second operation unit 242, is responsible for monitoring the security and stability of the system to prevent system crashes or data loss caused by hardware failures or abnormal operations. The fifth power electronics control core: formed by the adaptation of the signal generation module 210 and the third operation unit, is responsible for generating various control signals and timing signals to provide necessary signal support for other modules. The sixth power electronics control core: formed by the adaptation of the data acquisition module 230 and the signal processing module 220, is responsible for collecting data from external devices or sensors, and performing preprocessing and feature extraction. Multiple power electronics control cores notify the bus 100 for data exchange and coordinated control, forming a first loop architecture, so that the acceleration control structure can collect, process, control, protect, and generate signals in real time, thereby realizing efficient, flexible, and reliable power electronics control of the acceleration control structure.

[0052] It should be noted that through hardware acceleration and parallel processing, the computing performance and information throughput of the hardware acceleration control structure are significantly improved. Each power electronics control core can perform operations in parallel without interference, thus achieving efficient data processing and control. The first loop architecture has high flexibility and reconfigurability under the action of the reconstruction module 350, enabling the hardware acceleration structure to dynamically adjust the configuration of the hardware acceleration control structure according to external instructions or internal algorithms. In addition, the presence of the protection module 360 and the interrupt linkage module 340 improves the security and stability of the system. The protection module 360 can monitor the security and stability of the hardware acceleration control structure in real time to prevent system crashes or data loss caused by hardware failures or abnormal operations. The interrupt linkage module 340 can trigger an interrupt signal in a timely manner to notify the data flow control module 320 to perform corresponding processing, thus ensuring the normal operation of the hardware acceleration control structure.

[0053] The signal generation module 210, the signal processing module 220, the data acquisition module 230, the first arithmetic unit 241, the second arithmetic unit 242, the third arithmetic unit, the node module 310, the data flow control module 320, the data storage control module 330, the interrupt linkage module 340, the reconstruction module 350, and the protection module 360 are all provided with a bus 100 connection unit, a read / write control unit, a timing pulse unit, an end pulse unit, a reset pulse unit, and an enable signal unit. The bus 100 connection unit, the read / write control unit, the timing pulse unit, the end pulse unit, the reset pulse unit, and the enable signal unit of the corresponding modules in the first to sixth power electronics control cores are correspondingly connected.

[0054] It should be noted that DATA[0..15] is the data bus 100; ADDR[0..15] is the address bus 100; WR and RD are the read / write control units, and the read / write control units are used to control the read / write operations of data to ensure the integrity and correctness of the data; FLOW is the timing pulse bus, which is used to synchronize the operations between modules; FB is the end pulse unit, which is used to generate an end pulse signal after each module starts successfully or is connected successfully. The data flow control module 320 determines that the current module has ended and generates the next FLOW pulse (the second pulse signal) by identifying this signal; RESET is the reset pulse unit for restarting a cycle, which is used to synchronize the reset pulse signal and restore the initial state of the hardware acceleration control structure; ENA is the enable signal unit, which is used to control the startup and disablement of each module.

[0055] The data flow control module 320 is used to generate a first pulse signal, a reset signal, and an enable signal. The signal generation module 210, the signal processing module 220, the data acquisition module 230, the operation module 240, the node module 310, the data flow control module 320, the data storage control module 330, the interrupt linkage module 340, the reconstruction module 350, and the protection module 360 obtain their own operation sequences according to the first pulse signal. The data storage control module 330 is used to control the data storage of the first processing core and the second processing core. The interrupt linkage module 340 is used to establish the interrupt linkage between the first processing core and the second processing core. The protection module 360 is used to turn off the module flow operation of the signal generation module 210 and the second processing core.

[0056] It should be noted that the data flow control module 320 is used to control the module flow and generate FLOW (the first pulse signal), RESET (the reset signal), and ENA (enable) signals. Each module obtains its own operation sequence through the first pulse signal. Exemplarily, when the configured operation sequence of the node module 310 is 5, the configured data fetching address of the node module 310 is 010, and the result address is 011, then when running to the fifth rising edge of the first pulse signal, the node module 310 is run. First, data is read from the 010 address of the data storage control module 330, operated on, and the result is written to the 011 address of the data storage control module 330. The end pulse unit generates an end pulse signal, and the node module 310 ends its operation;

[0057] The data storage control module 330 is used to control the data storage inside the second processing core. For example, the connection relationship between modules P and Q is that the result x of P (defined at the address 080 in the CACHE) is the input of Q. The result of module P will be stored at the 080 address in the CACHE, and module Q will read the data from the 080 address. The data inside this module is divided into first processing core data and second processing core data. For example, if the first processing core needs to read the intermediate data of a certain process of the second processing core, it will read from the area of the second processing core and set a strategy to avoid simultaneous reading and writing. Among them, P and Q can be any two of the signal generation module 210, the signal processing module 220, the data acquisition module 230, the operation module 240, the node module 310, the data flow control module 320, the data storage control module 330, the interrupt linkage module 340, the reconstruction module 350, and the protection module 360;

[0058] The interrupt linkage module 340 is used to establish the interrupt linkage with the first processing core. For example, when running to a certain process and the first processing core needs to perform FFT operation, it is guided by the interrupt linkage module 340 to the first processing core. After the result is completed, it returns to the interrupt linkage module 340 and then the subsequent modules are run;

[0059] After the protection module 360 meets the set conditions, it can turn off the signal generation module 210 and the module stream operation of the second processing core.

[0060] The end pulse unit is used to generate a pulse end signal, so that the data stream control module 320 determines the end of the current module operation according to the pulse end signal and generates a second pulse signal. The reset pulse unit is used to generate a reset pulse.

[0061] Based on the accompanying drawings below, the control method of the embodiments of the present invention will be further elaborated.

[0062] 1. A conventional control loop includes, for example, an ADC, protection, multiplication, subtraction, IIR, multiplication, PWM module, etc. The control loop configurations of each module are as follows:

[0063]

[0064] 2. The acceleration loop configuration information of the PFC control loop block diagram is as follows:

[0065]

[0066] Refer to Figure 6 , Figure 6 is a flowchart of a control method for a reconfigurable chip hardware acceleration control structure provided by an embodiment of the present invention. The control method of the reconfigurable chip hardware acceleration control structure includes but is not limited to the following steps:

[0067] Step S11, obtaining preset module stream timing pulse numbers and module configuration parameters;

[0068] It should be noted that through the preset module stream timing pulse numbers and module configuration parameters, the chip hardware acceleration control structure can quickly and accurately start the required modules, reducing the waiting time and resource waste during the startup process;

[0069] Step S12, the first processing core and the second processing core are started according to the module stream timing pulse numbers and module configuration parameters;

[0070] It should be noted that when the first processing core and the second processing core receive the startup instruction, the first processing core and the second processing core start to read the module stream timing pulse numbers and module configuration parameters. According to the module stream timing pulse numbers, the first processing core and the second processing core can determine the startup time points of each module, thereby ensuring the sequentiality and coherence of module startup and avoiding conflicts and interferences between modules;

[0071] Further, the first processing core and the second processing core configure and initialize the specified modules according to the module configuration parameters, including but not limited to setting the working modes, parameters, interfaces, etc. of the modules to ensure that the modules can work properly.

[0072] Step S13: The first processing core and the second processing core start the node module 310 and the data storage control module 330 in the first power electronic control core, the interrupt linkage module 340 and the reconstruction module 350 in the second power electronic control core, the data flow control module 320 and the first arithmetic unit 241 in the third power electronic control core, the protection module 360 and the second arithmetic unit 242 in the fourth power electronic control core, the signal generation module 210 and the third arithmetic unit in the fifth power electronic control core, and the data acquisition module 230 and the signal processing module 220 in the sixth power electronic control core according to the module flow timing pulse number. Among them, the number of modules started in the first to sixth power electronic control cores is the same as the module flow timing pulse number, and the start time of the modules in each power electronic control core is the same;

[0073] It should be noted that the same start time of the modules in each power electronic control core ensures the synchronous operation of the modules inside the chip hardware acceleration control structure, improves the overall performance and stability of the hardware acceleration control structure. In addition, starting the corresponding number of modules according to actual needs avoids unnecessary resource waste and ensures that the chip hardware acceleration control structure can meet the requirements of various application scenarios;

[0074] Step S14: After each power electronic control core is started, it sends a pulse generation signal to the next power electronic control core;

[0075] Step S15: When the first to sixth power electronic control cores complete the operation, the end pulse unit generates a pulse end signal, and the data flow control module 320 makes a determination on the modules in operation according to the pulse end signal to obtain a determination result;

[0076] It should be noted that the pulse end signal generated by the end pulse unit and the determination result writing mechanism of the data flow control module 320 enable the chip hardware acceleration control structure to complete one cycle of operation and be ready to enter the next cycle or execute other tasks, thus providing a basis for the continuous operation and automatic control of the chip hardware acceleration control structure.

[0077] Step S16: Write the determination result into the read-write control unit in the power electronic control core where the current module is located, and the end pulse unit generates a pulse end signal to enable the first processing core and the second processing core to complete the cycle.

[0078] It should be noted that writing the determination result into the read-write control unit can accurately record the operation status and results of each module and be used as the basis for sending the pulse end signal, so as to dynamically adjust the working status and resource configuration of each module according to the determination result in the read-write control unit.

[0079] In addition, in one embodiment, referring to Figure 7 , in Figure 6 step S12 of the illustrated embodiment, the following steps are further included but not limited to:

[0080] Step S21, obtain the first module stream sequence number, the second module stream sequence number, the input data start address, the input data length, the output data start address, and the output data length;

[0081] Step S22, the first processing core and the second processing core start running according to the first module stream sequence number and the second module stream sequence number;

[0082] Step S23, after the first processing core and the second processing core finish running, the end pulse unit generates a pulse end signal, and the first processing core and the second processing core complete the loop.

[0083] It should be noted that through parallel processing, each functional module in the first processing core and the second processing core processes in parallel, thus significantly shortening the overall processing time. After the first processing core and the second processing core finish running, the end pulse unit generates a pulse end signal. To enable the first processing core and the second processing core to confirm that the current loop has been completed and allow appropriate subsequent actions (such as saving the results, triggering the next processing stage, etc.). In addition, when an error occurs during the processing, the pulse end signal also helps the chip hardware acceleration control structure to identify and process faster.

[0084] Exemplarily, num1 is the first module stream sequence number; num2 is the second module stream sequence number; in_addr is the input data start address; in_len is the input data length; out_addrwie ld is the output data start address; out_len is the output data length.

[0085] In addition, in one embodiment, referring to Figure 8 , in Figure 7 after step S23 of the illustrated embodiment, the following steps are further included but not limited to:

[0086] Step S31, when the second data stream sequence number is zero and the first module stream sequence number is one, the first power electronics control core starts running and obtains the input data length from the input data start address;

[0087] Step S32, after the first power electronics control core finishes running, write the running result into the output data length at the output data start address.

[0088] It should be noted that by using specific data stream sequence numbers and module stream sequence numbers as triggering conditions, the system can precisely control when to start the first power electronic control core. At the same time, through predefined input and output addresses and lengths, the chip hardware acceleration control structure can efficiently manage memory and data streams.

[0089] Exemplarily, when num2 = 0, the module starts running when the module stream reaches num1, retrieves in_len length data from in_addr, and after completion, writes the result to out_addr for out_len data, generating an FB pulse to end the module. When num2 > 0 and num2 > num1, the module starts running when the module stream reaches num1, retrieves in_len length data from in_addr, generates an FB pulse, and the module starts running; when the module stream reaches num2, it has completed running, writes the result to out_addr for out_len data, and generates an FB pulse to end the module.

[0090] As Figure 8 shown, Figure 8 is the structural diagram of a reconfigurable chip hardware acceleration control device provided by an embodiment of the present invention. The present invention also provides a reconfigurable chip hardware acceleration control device, including:

[0091] A processor 801, which can be implemented in ways such as a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided by the embodiments of the present application;

[0092] A memory 802, which can be implemented in forms such as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 802 can store an operating system and other application programs. When implementing the technical solutions provided by the embodiments of this specification through software or firmware, the relevant program codes are stored in the memory 802 and are called by the processor 801 to execute the reconfigurable chip hardware acceleration control method of the embodiments of the present application;

[0093] An input / output interface 803, which is used to implement information input and output;

[0094] A communication interface 804 is used to implement communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0095] A bus 805 transmits information between various components of the device (such as a processor 801, a memory 802, an input / output interface 803, and a communication interface 804).

[0096] Among them, the processor 801, the memory 802, the input / output interface 803, and the communication interface 804 are communicatively connected to each other inside the device through the bus 805.

[0097] The embodiment of the present application also provides a storage medium. The storage medium is a computer-readable storage medium, and this storage medium stores a computer program. When the computer program is executed by a processor, the above-mentioned reconfigurable chip hardware acceleration control method is implemented.

[0098] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above networks include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0099] Those of ordinary skill in the art will understand that all or some of the steps and systems disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes but is not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, communication media typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery media.

[0100] The above has specifically described the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of the present invention.

Claims

1. A reconfigurable chip hardware acceleration control structure, characterized in that, Comprising: Bus; A first processing core, the first processing core being connected to the bus, the first processing core including a signal generation module, a signal processing module, a data acquisition module, and an operation module, the signal processing module being connected to a first end of the data acquisition module, the first processing core being used for data configuration; A second processing core, the second processing core being respectively connected to the bus and the first processing core, the second processing core including a node module, a data flow control module, a data storage control module, an interrupt linkage module, a reconstruction module, and a protection module, the node module being connected to the data storage control module, a first end of the interrupt linkage module being connected to the reconstruction module, a first end of the data flow control module, a first end of the protection module, and a first end of the signal generation module all being connected to the operation module, a second end of the interrupt linkage module being connected to a second end of the data flow control module, a third end of the data flow control module being connected to a second end of the protection module, a third end of the protection module being connected to a second end of the signal generation module, a third end of the signal generation module being connected to a second end of the data acquisition module, a fourth end of the data flow control module being connected to a fourth end of the signal generation module, the second processing core being used for generating a timing pulse drive, and the node module, the data flow control module, the data storage control module, the interrupt linkage module, the reconstruction module, and the protection module sequentially operating according to the timing pulse drive.

2. The reconfigurable chip hardware acceleration control structure according to claim 1, wherein The operation module at least includes a first operation unit, a second operation unit, and a third operation unit, the node module and the data storage control module being adapted to form a first power electronic control core, the interrupt linkage module and the reconstruction module being adapted to form a second power electronic control core, the data flow control module and the first operation unit being adapted to form a third power electronic control core, the protection module and the second operation unit being adapted to form a fourth power electronic control core, the signal generation module and the third operation unit being adapted to form a fifth power electronic control core, the data acquisition module and the signal processing module being adapted to form a sixth power electronic control core, and the first power electronic control core to the sixth power electronic control core form a first loop architecture.

3. The reconfigurable chip hardware acceleration control structure according to claim 2, characterized in that, The signal generation module, the signal processing module, the data acquisition module, the first arithmetic unit, the second arithmetic unit, the third arithmetic unit, the node module, the data flow control module, the data storage control module, the interrupt linkage module, the reconstruction module, and the protection module are all provided with a bus connection unit, a read / write control unit, a timing pulse reading unit, an end pulse unit, a reset pulse unit, and an enable signal unit. The bus connection unit, the read / write control unit, the timing pulse reading unit, the end pulse unit, the reset pulse unit, and the enable signal unit of the corresponding modules in the first to sixth power electronic control cores are correspondingly connected.

4. The reconfigurable chip hardware acceleration control structure according to claim 1, characterized in that, The data flow control module is used to generate a first pulse signal, a reset signal, and an enable signal. The signal generation module, the signal processing module, the data acquisition module, the arithmetic module, the node module, the data flow control module, the data storage control module, the interrupt linkage module, the reconstruction module, and the protection module obtain their own operation sequences according to the first pulse signal. The data storage control module is used to control the data storage of the first processing core and the second processing core. The interrupt linkage module is used to establish the interrupt linkage between the first processing core and the second processing core. The protection module is used to shut down the module flow operation of the signal generation module and the second processing core.

5. The reconfigurable chip acceleration control structure according to claim 3, wherein The end pulse unit is used to generate a pulse end signal, so that the data flow control module determines the end of the current module operation according to the pulse end signal and generates a second pulse signal. The reset pulse unit is used to generate a reset pulse.

6. A control method for a control structure of a reconfigurable chip hardware acceleration, characterized in that, Including: Obtain the preset module flow timing pulse number and module configuration parameters; The first processing core and the second processing core are started according to the module flow timing pulse number and the module configuration parameters; The first processing core and the second processing core start the node module and the data storage control module in the first power electronic control core, the interrupt linkage module and the reconstruction module in the second power electronic control core, the data flow control module and the first arithmetic unit in the third power electronic control core, the protection module and the second arithmetic unit in the fourth power electronic control core, the signal generation module and the third arithmetic unit in the fifth power electronic control core, and the data acquisition module and the signal processing module in the sixth power electronic control core. Among them, the number of modules started in the first to sixth power electronic control cores is the same as the module flow timing pulse number, and the start time of the modules in each power electronic control core is the same; After each power electronic control core is started, it sends a pulse generation signal to the next power electronic control core; When the first to sixth power electronic control cores complete the operation, the end pulse unit generates a pulse end signal, and the data flow control module determines the modules in operation according to the pulse end signal to obtain a determination result; Write the determination result into the read-write control unit in the power electronic control core where the current module is located. The end pulse unit generates a pulse end signal to cause the first processing core and the second processing core to complete a cycle.

7. The control method of the reconfigurable chip hardware acceleration control structure according to claim 6, characterized in that, The first processing core and the second processing core are started according to the module stream timing pulse number and the module configuration parameters, including: Obtain the first module stream sequence number, the second module stream sequence number, the input data start address, the input data length, the output data start address, and the output data length; The first processing core and the second processing core start running according to the first module stream sequence number and the second module stream sequence number; After the first processing core and the second processing core finish running, the end pulse unit generates a pulse end signal, and the first processing core and the second processing core complete a cycle.

8. The control method of the reconfigurable chip hardware acceleration control structure according to claim 7, characterized in that After the first processing core and the second processing core complete a cycle, the method further includes: When the second data stream sequence number is zero and the first module stream sequence number is one, the first power electronic control core starts running and obtains the input data length from the input data start address; After the first power electronic control core finishes running, write the operation result into the output data length at the output data start address.

9. A control device for a reconfigurable chip hardware acceleration control structure, characterized in that, It includes at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions executable by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to execute the control method of the reconfigurable chip hardware acceleration control structure according to any one of claims 6 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to execute the control method of the reconfigurable chip hardware acceleration control structure according to any one of claims 1 to 7.

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