Display device and driving method

Abstract

The embodiment of the invention relates to a display device and a driving method thereof. A display device according to an exemplary embodiment of the present disclosure may include: a comparison circuit for comparing a source driving voltage and a reference driving voltage and outputting a second control signal; and a discharge circuit for comparing the first control signal and the second control signal output from the comparison circuit and discharging the source driving voltage, thereby stably controlling the voltage.

Description

Technical Field

[0001] Exemplary embodiments of the present disclosure relate to a display device and a driving method, and more particularly, for example but not limited to, a display device and a driving method capable of providing a stable voltage during an active period. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images has increased in various forms, and in recent years, various display devices such as liquid crystal displays and organic light emitting display devices have been used.

[0003] A display device may include a display panel, a data driving circuit, a gate driving circuit, a controller, and a power management integrated circuit.

[0004] The power management integrated circuit may generate various voltages for driving the display device.

[0005] The period during which the display panel is driven may include an active period and a blanking period.

[0006] Since the voltage required during the active period and the voltage required during the blanking period may be different from each other, the voltage required in each period may be changed.

[0007] The descriptions provided in this discussion of the related art should not be assumed to be prior art merely because they are mentioned in or associated with the discussion of the related art. The discussion of the related art may include information that describes one or more aspects of the subject technology, and the descriptions in this section do not limit the present invention. Summary of the Invention

[0008] Therefore, the inventors of the present disclosure have realized that there may be a problem of voltage instability because the voltage change may be delayed.

[0009] Exemplary embodiments of the present disclosure may provide a display device capable of stably controlling a source driving voltage.

[0010] Exemplary embodiments of the present disclosure may provide a display device capable of stably controlling a reference voltage.

[0011] Exemplary embodiments of the present disclosure may provide a display device capable of providing a stable voltage during an active period.

[0012] Exemplary embodiments of the present disclosure may provide a display device capable of reducing power consumption by stably controlling the voltage.

[0013] Exemplary embodiments of the present disclosure may provide a display device, including: a display panel on which a plurality of sub-pixels are provided; a data driving circuit for driving the display panel; a power management integrated circuit for providing a source driving voltage to the data driving circuit; a controller for controlling the power management integrated circuit and outputting a first control signal; a comparison circuit for comparing the source driving voltage and a reference driving voltage and outputting a second control signal; and a discharging circuit for comparing the first control signal output from the controller and the second control signal output from the comparison circuit and discharging the source driving voltage.

[0014] If the source driving voltage is greater than the reference driving voltage, the comparison circuit may output a second control signal in a high level state to the discharging circuit.

[0015] The discharging circuit may discharge the source driving voltage in response to receiving the second control signal in the high level state and the first control signal in the high level state.

[0016] Exemplary embodiments of the present disclosure may provide a driving method for a display device, including: outputting, by a controller that controls the data driving circuit, a first control signal to the discharging circuit; comparing, by the comparison circuit, the source driving voltage and the reference driving voltage and outputting a second control signal; comparing, by the discharging circuit, the first control signal and the second control signal; and discharging, by the discharging circuit, the source driving voltage.

[0017] Exemplary embodiments of the present disclosure may provide a display device, including: a power management integrated circuit configured to provide a source driving voltage; a controller configured to output a first control signal; a comparison circuit configured to compare the source driving voltage and a reference driving voltage and output a second control signal; and a discharging circuit configured to compare the first control signal output from the controller and the second control signal output from the comparison circuit and discharge the source driving voltage.

[0018] According to the exemplary embodiments of the present disclosure, a display device capable of stably controlling the source driving voltage may be provided.

[0019] According to the exemplary embodiments of the present disclosure, a display device capable of stably controlling the reference voltage may be provided.

[0020] According to the exemplary embodiments of the present disclosure, a display device capable of providing a stable voltage during an active period may be provided.

[0021] According to the exemplary embodiments of the present disclosure, a display device capable of reducing power consumption by stably controlling the voltage may be provided. Description of the Drawings

[0022] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, wherein:

[0023] Figure 1 is a system configuration diagram of a display device according to an exemplary embodiment of the present disclosure.

[0024] Figure 2A and Figure 2B is an equivalent circuit of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0025] Figure 3 illustrates a system of a display device according to an exemplary embodiment of the present disclosure.

[0026] Figure 4 illustrates a compensation circuit of a display device according to an exemplary embodiment of the present disclosure.

[0027] Figure 5A is a diagram of a first sensing mode of a display device according to an exemplary embodiment of the present disclosure.

[0028] Figure 5B is a diagram of a second sensing mode of a display device according to an exemplary embodiment of the present disclosure.

[0029] Figure 6 illustrates various sensing timings of a display device according to an exemplary embodiment of the present disclosure.

[0030] Figure 7 illustrates a controller and a power management integrated circuit according to an exemplary embodiment of the present disclosure.

[0031] Figure 8 is a timing diagram of an active period and a blanking period according to an exemplary embodiment of the present disclosure.

[0032] Figure 9 illustrates a comparison circuit and a discharge circuit according to an exemplary embodiment of the present disclosure.

[0033] Figure 10 illustrates a comparison circuit and a discharge circuit according to an exemplary embodiment of the present disclosure.

[0034] Figure 11 is a truth table based on a first control signal and a second control signal according to an exemplary embodiment of the present disclosure.

[0035] Figure 12 is a timing diagram of a discharge mode operation of a display device according to an exemplary embodiment of the present disclosure.

[0036] Figure 13It is a timing diagram of the normal mode operation of a display device according to an exemplary embodiment of the present disclosure.

[0037] Figure 14 It shows a comparison circuit and a discharge circuit according to an exemplary embodiment of the present disclosure.

[0038] Figure 15 It shows a comparison circuit and a discharge circuit according to an exemplary embodiment of the present disclosure.

[0039] Figure 16 It is a flowchart of a driving method of a display device according to an exemplary embodiment of the present disclosure.

[0040] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. The dimensions, lengths, and thicknesses of these layers, regions, and elements, and their descriptions may be exaggerated for clarity, illustration, and convenience. Detailed Embodiments

[0041] Now, embodiments of the present disclosure will be described in detail, and examples thereof may be shown in the drawings. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as known in the art, except for steps and / or operations that must occur in a specific order. The names of the corresponding elements used in the following description may be selected only for the convenience of writing the specification and may thus be different from the names used in actual products.

[0042] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. When assigning reference numerals to the components of each drawing, the same reference numerals may be assigned to the same components even when they are shown in different drawings. Details of known technologies or functions may be skipped when it is determined that they make the subject matter of the present disclosure unclear. As used herein, when a component "includes" another component, "has" another component, or "consists of" another component, the component may add other components, unless the component "only includes", "only has", or "only consists of" another component. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0043] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, number of elements, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements.

[0044] Designations such as "first", "second", "A", "B", "(a)", and "(b)" may be used to describe components of the present disclosure. These designations are provided merely to distinguish one component from another, and the nature, order, or number of components is not limited by the designations.

[0045] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element, and the third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0046] When describing the positional relationship between components, when two or more components are described as "connected", "coupled", or "linked", the two or more components may be directly "connected", "coupled", or "linked", or another component may intervene. Here, other components may be included in one or more of the two or more components that are "connected", "coupled", or "linked" to each other.

[0047] For ease of description, spatial relative terms such as "lower", "below", "beneath", "under", "upper", "above", etc. may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relative terms may also include different orientations of the elements during use or operation. For example, if an element in the figure is inverted, the element described as "below" or "beneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary term "below" may include both orientations of below and above. Similarly, the exemplary terms "above" or "over" may include both orientations of "above" and "below".

[0048] When using terms such as "after", "adjacent to", and "before" to describe the temporal flow relationship related to components, operating methods, and manufacturing methods, unless the term "immediately" or "directly" is used, it may include non - continuous relationships and may also include discontinuous cases.

[0049] When a component is designated with a value or its corresponding information (e.g., level), the value or corresponding information may be interpreted as including tolerances that may arise due to various factors (e.g., process factors, internal or external influences, or noise).

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein. For example, the term "component" or "unit" may be applied, for example, to a separate circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described function, as would be understood by one of ordinary skill in the art.

[0051] In addition, when referring to any dimensions, relative dimensions, etc., the numerical values or corresponding information (such as horizontal, range, etc.) of elements or features should be considered to include the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, or noise), even if the relevant description is not specified. In addition, the word "may" fully encompasses all meanings of the word "can".

[0052] The term "device" used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of display devices may include light-emitting elements, etc. In addition, examples of devices may include laptop computers, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, as well as sets of electronic devices (or equipment) or sets of devices (or equipment), e.g., mobile electronic devices such as smartphones or electronic tablets, which are complete products or end products that respectively include light-emitting elements, etc., but the embodiments of the present disclosure are not limited thereto.

[0053] Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. For ease of description, the scale of each element shown in the drawings is different from the actual scale and is thus not limited to the scale described in the drawings.

[0054] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the drawings.

[0055] Figure 1 is a system configuration diagram of a display device 100 according to an exemplary embodiment of the present disclosure.

[0056] Referring to Figure 1 , a display device 100 according to an exemplary embodiment of the present disclosure may include a display panel 110 and a driving circuit for driving the display panel 110.

[0057] The driving circuit may include a data driving circuit 120 and a gate driving circuit 130, and may also include a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130, etc.

[0058] The display panel 110 may include a substrate SUB and various types of signal lines disposed on the substrate SUB, such as a plurality of data lines DL and a plurality of gate lines GL. The display panel 110 may include a plurality of sub-pixels SP connected to the plurality of data lines DL and the plurality of gate lines GL. Here, each of the plurality of sub-pixels SP is the smallest unit configuring the display area, and n sub-pixels SP form one pixel. Each of the plurality of sub-pixels SP may emit light having different wavelengths from each other. The plurality of sub-pixels may include first to third sub-pixels that emit light of different colors from each other. For example, the plurality of sub-pixels SP may include a red sub-pixel SP, a green sub-pixel SP, and a blue sub-pixel SP. According to an exemplary embodiment, at least some of the plurality of pixels may further include a white sub-pixel SP. Various modifications may be made to the colors and configurations of the plurality of sub-pixels as needed. However, the present disclosure is not limited thereto.

[0059] As an example, in addition to the plurality of data lines DL and the plurality of gate lines GL, one or more additional signal lines (such as a power line, a light emission control line, a sensing line, etc.) may be included.

[0060] The display panel 110 may include a display area DA for displaying an image and a non-display area NDA for not displaying an image. The non-display area NDA may be an external area of the display area DA and may also be referred to as a border area or an edge area. All or part of the non-display area NDA may be an area visible from the front of the display device 100, or may be curved and not visible from the front of the display device 100.

[0061] In the display panel 110, the plurality of sub-pixels SP for displaying an image may be disposed in the display area DA. In the non-display area NDA, the driving circuits 120, 130, and 140 may be electrically connected, or the driving circuits 120, 130, and 140 may be mounted, or a pad portion connected to an integrated circuit or a printed circuit may be provided.

[0062] The data driving circuit 120 is a circuit for driving the plurality of data lines DL and may provide data signals to the plurality of data lines DL. For example, the data driving circuit 120 outputs data voltages through the plurality of data lines DL. The gate driving circuit 130 is a circuit for driving the plurality of gate lines GL and may provide gate signals to the plurality of gate lines GL. For example, the gate driving circuit 130 outputs scan signals to the sub-pixels through the plurality of gate lines GL. The controller 140 is a device for controlling the data driving circuit 120 and the gate driving circuit 30 and may control the driving timing of the plurality of data lines DL and the driving timing of the plurality of gate lines GL.

[0063] The controller 140 may provide a data control signal DCS to the data driving circuit 120 to control the operation timing of the data driving circuit 120. The controller 140 may provide a gate control signal GCS to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130.

[0064] The controller 140 may start scanning according to the timing implemented in each frame, convert the input image data input from the outside to a data signal format suitable for use in the data driving circuit 120, provide the converted image data Data to the data driving circuit 120, and control the data driving at an appropriate time according to the scanning.

[0065] The controller 140 may receive various timing signals from the outside (e.g., the host system 150) together with the input image data, including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal CLK.

[0066] To control the data driving circuit 120 and the gate driving circuit 130, the controller 140 may receive timing signals such as a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal CLK, and generate various control signals DCS and GCS to output to the data driving circuit 120 and the gate driving circuit 130.

[0067] For example, the controller 140 may output various gate control signals GCS including a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE to control the gate driving circuit 130, but is not limited thereto.

[0068] In addition, to control the data driving circuit 120, the controller 140 may output various data control signals DCS, such as a source start pulse SSP, a source sampling clock SSC, and a source output enable signal SOE, but is not limited thereto.

[0069] The controller 140 may be implemented as a component separate from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0070] The data driving circuit 120 may receive the image data Data from the controller 140 and provide data voltages to a plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 may also be referred to as a source driving circuit. For example, the data driving circuit 120 may receive the image data data in digital form from the controller 140, convert the received image data into an analog data signal, and provide the converted image data to the plurality of data lines DL, thereby driving the plurality of data lines DL.

[0071] The data driving circuit 120 may include one or more source driver integrated circuits SDICs.

[0072] Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter DAC, and an output buffer. In some cases, each source driver integrated circuit SDIC may further include an analog-to-digital converter ADC.

[0073] For example, each source driver integrated circuit SDIC may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to the bonding pads of the display panel 110 using a chip-on-glass (COG) method or a chip-on-board (COP) method, or may be connected to the display panel 110 by implementing a chip-on-film (COF) method, but is not limited thereto.

[0074] The gate driving circuit 130 may provide gate signals to a plurality of gate lines GL according to the timing control of the controller 140. For example, the gate driving circuit 130 may output a gate signal of a conductive level voltage or a gate signal of a cut-off level voltage according to the control of the controller 140. The gate driving circuit 130 may sequentially drive a plurality of gate lines GL by sequentially providing gate signals having a conductive level voltage to the plurality of gate lines GL.

[0075] The gate driving circuit 130 may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to the bonding pads of the display panel 110 using a chip-on-glass (COG) method or a chip-on-board (COP) method, or may be connected to the display panel 110 by a chip-on-film (COF) method. Alternatively, the gate driving circuit 130 may be a gate-in-panel (GIP) type and may be formed in the non-display area NDA of the display panel 110. For example, the gate driving circuit 130 may be embedded in the non-display area NDA of the display panel 110 in the form of a gate-in-panel (GIP) type formed together with the thin film transistors in the display area DA, but is not limited thereto. The gate driving circuit 130 may be disposed on the substrate SUB or connected to the substrate SUB. That is, if the gate driving circuit 130 is of the GIP type, the gate driving circuit 130 may be disposed in the non-display area NDA of the substrate SUB, but is not limited thereto. In the case of the chip-on-glass (COG) type or the chip-on-film (COF) type, the gate driving circuit 130 may be connected to the substrate SUB.

[0076] In addition, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA of the display panel 110, but is not limited thereto. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed so as not to overlap with the sub-pixels SP, and may be disposed so as to partially or entirely overlap with the sub-pixels SP.

[0077] If a specific gate line GL is turned on by the gate driving circuit 130, the data driving circuit 120 may convert the image data Data received from the controller 140 into an analog data voltage to be provided to the plurality of data lines DL.

[0078] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Depending on the driving method or the panel design method, the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to two or more sides of the four sides of the display panel 110, but is not limited thereto.

[0079] The gate driving circuit 130 may be connected to one side (e.g., the left side or the right side) of the display panel 110. Depending on the driving method or the panel design method, the gate driving circuit 130 may be connected to both sides (e.g., the left side and the right side) of the display panel 110, or may be connected to two or more sides of the four sides of the display panel 110, but is not limited thereto.

[0080] The controller 140 may be a timing controller used in typical display technologies, or may be a control device capable of further performing other control functions including the timing controller, or may be a control device different from the timing controller, or may be a control device other than the timing controller, or may be a circuit within the control device. In an exemplary embodiment, the gate driving circuit 130 (e.g., embedded in the display panel 110) may receive a plurality of gate control signals from the controller 140. In addition, the data driving circuit 120 may receive a plurality of data control signals from the controller 140. The display controller 140 may be implemented with various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0081] The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, but is not limited thereto.

[0082] The controller 140 may transmit and receive data with the data driving circuit 120 according to one or more predetermined interfaces. For example, the interface may include a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI) interface, or a serial peripheral interface (SPI), but is not limited thereto. In addition, the controller 140 may transmit and receive signals with the gate driving circuit 130.

[0083] The controller 140 may include a storage medium such as one or more registers.

[0084] The display device 100 according to the present embodiment may be a display including a backlight unit, such as a liquid crystal display, or may be a self-luminous display in which the display panel 110 itself emits light, such as an organic light emitting diode (OLED) display, a quantum dot display, or a micro light emitting diode (micro-LED) display.

[0085] In the case where the display device 100 according to the present embodiment is an organic light emitting diode (OLED) display, each sub-pixel SP may include an organic light emitting diode (OLED) that emits light as a light emitting device. If the display device 100 according to the present embodiment is a quantum dot display, each sub-pixel SP may include a light emitting element made of quantum dots, which is a semiconductor crystal that emits light by itself. If the display device 100 according to the present embodiment is a micro-LED display, each sub-pixel SP may include a micro-LED made of an inorganic material and emitting light by itself as a light emitting device.

[0086] Figure 2A and Figure 2B is an equivalent circuit of the sub-pixel SP of the display device 100 according to an exemplary embodiment of the present disclosure.

[0087] Referring to Figure 2A , each of the plurality of sub-pixels SP provided on the display panel 110 of the display device 100 according to an exemplary embodiment of the present disclosure may include a light emitting device ED and a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst for driving the light emitting device ED, but is not limited thereto. More or fewer components may be included.

[0088] Referring to Figure 2A , the light emitting device ED may include a pixel electrode PE and a common electrode CE, and a light emitting layer EL located between the pixel electrode PE and the common electrode CE.

[0089] The pixel electrode PE of the light-emitting device ED can be an electrode provided in each sub-pixel SP, and the common electrode CE can be an electrode commonly provided in all sub-pixels SP. Here, for example, the pixel electrode PE can be an anode electrode, and the common electrode CE can be a cathode electrode, but it is not limited thereto. Conversely, the pixel electrode PE can be a cathode electrode, and the common electrode CE can be an anode electrode.

[0090] For example, the light-emitting device ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode, a light-emitting diode (LED), or a quantum dot light-emitting device, but it is not limited thereto.

[0091] The driving transistor DRT is a transistor for driving the light-emitting device ED, and can include a first node N1 to which a data voltage Vdata can be applied, a second node N2 electrically connected to the light-emitting device ED, and a third node N3 to which a first driving power signal EVDD is applied.

[0092] The first node N1 of the driving transistor DRT can be the gate node of the driving transistor DRT, and can be electrically connected to the source node or the drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT can be the source node or the drain node of the driving transistor DRT, and can be electrically connected to the source node or the drain node of the sensing transistor SENT, and can be electrically connected to the pixel electrode PE of the light-emitting device ED. The third node N3 of the driving transistor DRT can be the drain node or the source node of the driving transistor DRT, and can be electrically connected to the driving voltage line DVL that provides the driving voltage EVDD.

[0093] The scanning transistor SCT can be controlled by a scanning signal SC which is a kind of gating signal, and can be connected between the first node N1 of the driving transistor DRT and the data line DL. That is, the scanning transistor SCT can be turned on or off according to the scanning signal SC provided from the scanning signal line SCL, and the scanning signal line SCL is a gating line GL for controlling the connection between the first node N1 of the driving transistor DRT and the data line DL.

[0094] The scanning transistor SCT can be turned on by the scanning signal SC having a conductive level voltage, and can transmit the data voltage Vdata provided from the data line DL to the first node N1 of the driving transistor DRT.

[0095] Here, if the scanning transistor SCT is an n-type transistor, the conductive level voltage of the scanning signal SC can be a high level voltage. If the scanning transistor SCT is a p-type transistor, the conductive level voltage of the scanning signal SC can be a low level voltage.

[0096] Each of the scan transistor SCT and the driving transistor DRT may be an n-type transistor or a p-type transistor.

[0097] The storage capacitor Cst may be electrically connected between a first node N1 and a second node N2 of the driving transistor DRT. The storage capacitor Cst may be charged with charges corresponding to the voltage difference between both ends, and may maintain the voltage difference between both ends within a set frame period. Accordingly, the corresponding sub-pixel SP may emit light during the set frame period.

[0098] Referring Figure 2B , each of the plurality of sub-pixels SP provided on the display panel 110 of the display device 100 according to an exemplary embodiment of the present disclosure may further include a sensing transistor SENT.

[0099] The sensing transistor SENT may be controlled by a sensing signal SE which is a kind of gate signal, and may be connected between the second node N2 of the driving transistor DRT and a reference voltage line RVL. That is, the sensing transistor SENT may be turned on or off according to the sensing signal SE provided from a sensing signal line SENL which is another kind of gate line GL, and may be turned on and off to control the connection between the reference voltage line RVL and the second node N2 of the driving transistor DRT.

[0100] The sensing transistor SENT may be turned on by the sensing signal SE having a conductive level voltage, and may transfer a reference voltage Vref provided from the reference voltage line RVL to the second node N2 of the driving transistor DRT.

[0101] In addition, the sensing transistor SENT may be turned on by the sensing signal SE having a conductive level voltage, and may transfer the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL.

[0102] In addition, the sensing transistor SENT may be turned off by the sensing signal SE having a cut-off level voltage, so that the second node N2 of the driving transistor DRT and the reference voltage line RVL may be electrically isolated.

[0103] Here, in the case where the sensing transistor SENT is an n-type transistor, the conductive level voltage of the sensing signal SE may be a high level voltage. If the sensing transistor SENT is a p-type transistor, the conductive level voltage of the sensing signal SE may be a low level voltage.

[0104] The function of the sensing transistor SENT to transfer the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL can be used during driving to sense the characteristic value of the sub-pixel SP. In this case, the voltage transferred to the reference voltage line RVL can be a voltage for calculating the characteristic value of the sub-pixel SP or a voltage reflecting the characteristic value of the sub-pixel SP.

[0105] In the present disclosure, the characteristic value of the sub-pixel SP can be the characteristic value of the driving transistor DRT or the light-emitting device ED. The characteristic value of the driving transistor DRT can include the threshold voltage and mobility of the driving transistor DRT, but is not limited thereto. The characteristic value of the light-emitting device ED can include the threshold voltage of the light-emitting device ED.

[0106] Each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can be an n-type transistor or a p-type transistor. In the present disclosure, for ease of explanation, the case where the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT are each n-type will be illustrated.

[0107] The storage capacitor Cst can be an external capacitor intentionally designed outside the driving transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd) of an internal capacitor existing between the gate node and the source node (or drain node) of the driving transistor DRT.

[0108] The scanning signal line SCL and the sensing signal line SENL can be different strobe lines GL. In this case, the scanning signal SC and the sensing signal SE can be separate strobe signals, and the on / off timing of the scanning transistor SCT and the on / off timing of the sensing transistor SENT within one sub-pixel SP can be independent. That is, the on / off timing of the scanning transistor SCT and the on / off timing of the sensing transistor SENT within one sub-pixel SP can be the same or different.

[0109] Alternatively, the scanning signal line SCL and the sensing signal line SENL can be the same strobe line GL. That is, the gate node of the scanning transistor SCT and the gate node of the sensing transistor SENT within one sub-pixel SP can be connected to one strobe line GL. In this case, the scanning signal SC and the sensing signal SE can be the same strobe signal, and the on / off timing of the scanning transistor SCT and the on / off timing of the sensing transistor SENT within one sub-pixel SP can be the same.

[0110] Figure 2A and Figure 2B The structure of the sub-pixel SP shown in and is only an example, and can be modified in various ways by including one or more transistors or one or more capacitors.

[0111] In Figure 2A and Figure 2B , it is assumed that the display device 100 is a self-emissive display device to explain the sub-pixel structure. However, if the display device 100 is a liquid crystal display device, each sub-pixel SP may include a transistor and a pixel electrode.

[0112] Figure 3 Fig. shows a system of a display device 100 according to an exemplary embodiment of the present disclosure.

[0113] Referring to Figure 3 , the display panel 110 may include a display area DA for displaying an image and a non-display area NDA for not displaying an image. The non-display area NDA may be an external area of the display area DA, and may also be referred to as a border area or an edge area.

[0114] Referring to Figure 3 , if the data driving circuit 120 includes one or more source driver integrated circuits SDICs and is implemented by a chip on film (COF) method, each source driver integrated circuit SDIC may be mounted on a circuit film SF connected to the non-display area NDA of the display panel 110.

[0115] The gate driving circuit 130 includes various gate driving circuits, and the gate driving circuit may be directly formed on the substrate. Referring to Figure 3 , the gate driving circuit 130 may be implemented as an in-panel gate (GIP) type, but is not limited thereto. In this case, the gate driving circuit 130 may be formed in the non-display area NDA of the display panel 110. Different from Figure 3 , the gate driving circuit 130 may be implemented as a chip on film (COF) type.

[0116] For the circuit connection between one or more source driver integrated circuits SDICs and other devices, the display device 100 may include at least one source printed circuit board SPCB and a control printed circuit board CPCB for mounting control components and various electrical devices.

[0117] The film SF on which the source driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB. That is, one side of the film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110, and the other side may be electrically connected to the source printed circuit board SPCB.

[0118] The controller 140 and the power management integrated circuit (PMIC) 310 may be mounted on the control printed circuit board CPCB. The controller 140 may perform overall control functions related to driving the display panel 110 and control the operations of the data driving circuit 120 and the gate driving circuit 130. The power management integrated circuit 310 may supply various voltages or currents to the data driving circuit 120 and the gate driving circuit 130, or control the various voltages or currents to be supplied.

[0119] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be connected through at least one connection cable CBL circuit. Here, the connection cable CBL may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc.

[0120] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be integrated and implemented as a single printed circuit board.

[0121] The display device 100 according to an exemplary embodiment of the present disclosure may further include a level shifter 300 for adjusting a voltage level. For example, the level shifter 300 may be provided on the control printed circuit board CPCB or the source printed circuit board SPCB, but is not limited thereto.

[0122] Specifically, in the display device 100 according to an exemplary embodiment of the present disclosure, the level shifter 300 may supply signals required for gate driving to the gate driving circuit 130. For example, the level shifter 300 may supply a plurality of clock signals to the gate driving circuit 130. Accordingly, the gate driving circuit 130 may output a plurality of gate signals to a plurality of gate lines GL based on the plurality of clock signals input from the level shifter 300. Here, the plurality of gate lines GL may transmit a plurality of gate signals to the sub-pixels SP provided in the display area DA of the substrate SUB.

[0123] Figure 4 A compensation circuit of the display device 100 according to an exemplary embodiment of the present disclosure is shown.

[0124] Referring to Figure 4 , the compensation circuit may be a circuit capable of performing sensing and compensation processing on the characteristic values of the circuit elements within the sub-pixel SP.

[0125] The compensation circuit may be connected to the sub-pixel SP and may include a power switch SPRE, a sampling switch SAM, an analog-to-digital converter ADC, a compensator 400, etc.

[0126] The power switch SPRE can control the connection between the reference voltage line RVL and the reference voltage supply node Nref. For example, when the power switch SPRE is turned on, the reference voltage line RVL is electrically connected to the reference voltage supply node Nref. In this case, the reference voltage Vref output from the power supply can be supplied to the reference voltage supply node Nref, and the reference voltage Vref supplied to the reference voltage application node Nref can be supplied to the reference voltage line RVL.

[0127] The sampling switch SAM can control the connection between the analog-to-digital converter ADC and the reference voltage line RVL. For example, when the sampling switch SAM is turned on, the analog-to-digital converter ADC is electrically connected to the reference voltage line RVL. If the analog-to-digital converter ADC is connected to the reference voltage line RVL through the sampling switch (SAM), the analog-to-digital converter ADC can convert the voltage of the connected reference voltage line RVL (e.g., an analog voltage) into a sensed value corresponding to a digital value.

[0128] The line capacitor Crvl can be formed between the reference voltage line RVL and the ground GND. The voltage of the reference voltage line RVL can correspond to the charge amount of the line capacitor Crvl.

[0129] The analog-to-digital converter ADC can provide sensed data including the sensed value to the compensator 400.

[0130] The compensator 400 can determine the characteristic value of the light-emitting device ED or the driving transistor DRT included in the corresponding sub-pixel SP based on the sensed data, calculate the compensation value, and store the compensation value in the memory 410.

[0131] For example, the compensation value can be information for reducing the deviation of the characteristic values between the light-emitting devices ED or the deviation of the characteristic values between the driving transistors DRT, and can include an offset and a gain value for data change.

[0132] The controller 140 can use the compensation value stored in the memory 410 to change the image data, and provide the changed image data to the data driving circuit 120.

[0133] The data driving circuit 120 can use the digital-to-analog converter DAC to convert the changed image data into a data voltage Vdata corresponding to an analog voltage and output the data voltage Vdata. Thus, compensation can be performed.

[0134] Refer to Figure 4 As shown in the figure, the analog-to-digital converter ADC, the power switch SPRE, and the sampling switch SAM can be included in the source driver integrated circuit SDIC included in the data driving circuit 120. The compensator 400 can be included in the controller 140.

[0135] As described above, the display device 100 according to an exemplary embodiment of the present disclosure may perform a compensation process to reduce the deviation of characteristic values between the driving transistors DRT. In addition, in order to perform the compensation process, the display device 100 may perform sensing driving to find out the deviation of characteristic values between the driving transistors DRT.

[0136] The display device 100 according to an exemplary embodiment of the present disclosure may perform sensing driving in two modes (for example, a fast mode and a slow mode). Hereinafter, the sensing driving in Figure 5A and Figure 5B the two modes (for example, the fast mode and the slow mode) will be described.

[0137] Figure 5A FIG. shows a first sensing mode (i.e., S mode) of the display device 100 according to an exemplary embodiment of the present disclosure. Figure 5B FIG. shows a second sensing mode (i.e., F mode) of the display device 100 according to an exemplary embodiment of the present disclosure. For example, threshold voltage sensing may be performed in the first sensing mode (S mode), and mobility sensing may be performed in the second sensing mode (F mode), which will be described in detail below.

[0138] Referring to Figure 5A and Figure 5B , the sensing driving period of the first sensing mode (i.e., S mode) and the sensing driving period of the second sensing mode (i.e., F mode) may each include an initialization period Tinit, a tracking period Ttrack, and a sampling period Tsam.

[0139] The sensing driving period of the first sensing mode (S mode) of the display device 100 will be described with reference to Figure 5A .

[0140] During the initialization period Tinit, the voltage V1 of the first node N1 of the driving transistor DRT may be initialized to the data voltage Vdata_SEN for sensing driving, and the voltage V2 of the second node N2 of the driving transistor DRT may be initialized to the reference voltage Vref for sensing driving.

[0141] During the initialization period Tinit, the scan transistor SCT and the sense transistor SENT may be turned on, and the power switch SPRE may be turned on to connect the reference voltage line RVL to the reference voltage supply node Nref.

[0142] During the tracking period Ttrack, the first node N1 of the driving transistor DRT can be in a constant voltage state using the data voltage Vdata_SEN for sensing driving, but the second node N2 of the driving transistor DRT can be in an electrically floating state. Therefore, during the tracking period Ttrack, the voltage V2 of the second node N2 of the driving transistor DRT can change. For example, the voltage V2 of the second node N2 of the driving transistor DRT may increase over time, and eventually, the voltage V2 of the second node N2 of the driving transistor DRM may saturate.

[0143] More specifically, as the latter part of the tracking period Ttrack progresses, the degree of increase in the voltage of the second node N2 of the driving transistor DRT decreases, and eventually, the voltage V2 of the second node N2 of the driving transistor DRT saturates.

[0144] When the voltage V2 of the second node N2 of the driving transistor DRT saturates, the sampling period Tsam can be started.

[0145] Refer to Figure 5A , during the sampling period (Tsam) in the sensing driving period of the first sensing mode (S mode), it can be a period for measuring the voltages Vdata_SEN - Vth and Vdata_SEN - ΔVth that reflect the threshold voltage Vth of the driving transistor DRT or the change in the threshold voltage Vth of the driving transistor DRT. That is, due to the characteristic of requiring a long sensing time, the threshold voltage sensing can be performed in the first sensing mode (S mode).

[0146] Will refer to Figure 5B Describe the sensing driving period of the second sensing mode (F mode) of the display device 100.

[0147] During the initialization period Tinit, the voltage V1 of the first node N1 of the driving transistor DRT can be initialized to the data voltage Vdata_SEN for sensing driving, and the voltage V2 of the second node N2 of the driving transistor DRT can be initialized to the reference voltage Vref for sensing driving.

[0148] During the tracking period Ttrack, a preset tracking time Δt can be set to be short. Therefore, during the short tracking time Δt, it is difficult for the voltage V2 of the second node N2 of the driving transistor DRT to reflect the threshold voltage Vth. However, during the short tracking time Δt, the voltage V2 of the second node N2 of the driving transistor DRT can change enough to determine the mobility of the driving transistor DRT. That is, due to the characteristic of requiring a short sensing time, the mobility sensing can be performed in the second sensing mode (F mode).

[0149] During the tracking period Ttrack, the voltage V2 of the second node N2 of the driving transistor DRT may increase. At this time, the voltage V1 of the first node N1 of the driving transistor DRT may also increase.

[0150] After a preset tracking time Δt has elapsed during the tracking period Ttrack, that is, after the voltage V2 of the second node N2 of the driving transistor DRT has risen for the preset tracking time Δt, the sampling period Tsam may be performed.

[0151] When the display device 100 provides the data voltage Vdata for display driving to the corresponding sub-pixel SP, the data voltage Vdata changed based on the threshold voltage compensation value and the mobility compensation value may be provided.

[0152] As described above, due to the characteristic of requiring a long sensing time, the threshold voltage sensing may be performed in the first sensing mode (S mode), and due to the characteristic of requiring a short sensing time, the mobility sensing may be performed in the second sensing mode (F mode) as a fast mode.

[0153] Figure 6 Various sensing timings of the display device 100 according to an exemplary embodiment of the present disclosure are shown.

[0154] Refer to Figure 6 , when a power-on signal is generated, the display device 100 according to an exemplary embodiment of the present disclosure may sense the characteristic values of the driving transistors DRT in each sub-pixel SP provided on the display panel 110. This sensing process may be referred to as "turn-on sensing process". The characteristic values of the driving transistor DRT may include, but are not limited to, the threshold voltage and the mobility of the driving transistor DRT.

[0155] Refer to Figure 6 , when a power-off signal is generated, the display device 100 according to an exemplary embodiment of the present disclosure may sense the characteristic values of the driving transistors DRT in each sub-pixel SP provided on the display panel 110 before performing a turn-off sequence such as turning off the power. This sensing process may be referred to as "turn-off sensing process".

[0156] Refer to Figure 6 , the display device 100 according to an exemplary embodiment of the present disclosure may also sense the characteristic values of the driving transistors DRT in each sub-pixel SP during the display driving from the generation of the power-on signal until the generation of the power-off signal. This sensing process may be referred to as "real-time sensing process". For example, the real-time sensing process may be performed after the turn-on sensing process and before the turn-off sensing process, but is not limited thereto.

[0157] Based on the vertical synchronization signal Vsync, real-time sensing processing can be performed during each blanking period BLANK between active periods ACT.

[0158] Since the mobility sensing of the driving transistor DRT only requires a short time, mobility sensing can be performed in the second sensing mode (F mode) among the sensing driving methods.

[0159] Since the mobility sensing that can be performed in the second sensing mode (F mode) as a fast mode only requires a short time, mobility sensing can be performed in any one of the turn-on sensing processing, turn-off sensing processing, and real-time sensing processing, but is not limited thereto.

[0160] For example, the mobility sensing that can be performed in the second sensing mode (F mode) as a fast mode due to the characteristic of requiring a short sensing time can be performed as real-time sensing processing that can reflect the mobility change in real time during display driving. That is, mobility sensing can be performed during each blanking period during display driving.

[0161] In contrast, the threshold voltage sensing of the driving transistor DRT may require a long saturation time Vsat. Therefore, threshold voltage sensing can be performed in the first sensing mode (S mode) as a slow mode among the sensing driving methods.

[0162] Timing that does not interfere with the user's viewing needs to be used to perform threshold voltage sensing. Therefore, while display driving is not being performed (i.e., when the user has no intention of viewing), after generating a power-off signal according to user input or the like, the threshold voltage sensing of the driving transistor DRT can be performed. That is, threshold voltage sensing can be performed as turn-off sensing processing.

[0163] Figure 7 A controller 140 and a power management integrated circuit 310 according to an exemplary embodiment of the present disclosure are shown.

[0164] Refer to Figure 7 , the controller 140 can be electrically connected to the power management integrated circuit 310, and the power management integrated circuit 310 can be electrically connected to the data driving circuit 120.

[0165] The controller 140 can provide a voltage control signal VCS to the power management integrated circuit 310.

[0166] The power management integrated circuit 310 can generate a source driving voltage SVDD based on the voltage control signal VCS.

[0167] The source driving voltage SVDD can be the voltage required to drive the data driving circuit 120.

[0168] The power management integrated circuit 310 may output a source driving voltage SVDD to the data driving circuit 120.

[0169] In addition to the source driving voltage SVDD, the power management integrated circuit 310 may also generate various voltages, such as a driving voltage, a base voltage, and a reference voltage Vref.

[0170] The power consumption of the display device 100 may be reduced by adjusting the voltage level of the source driving voltage SVDD according to the driving environment of the display device 100. For example, in a case where it is necessary to relatively increase the source driving voltage SVDD, a voltage control signal VCS may be provided to the power management integrated circuit 310 to increase the source driving voltage SVDD. If it is necessary to relatively decrease the source driving voltage SVDD, a voltage control signal VCS for decreasing the source driving voltage SVDD may be provided to the power management integrated circuit 310. This may be referred to as an adaptive source driving voltage control method.

[0171] Referring to Figure 8 , if the adaptive source driving voltage control method is applied, the source driving voltage SVDD may change during the active periods ACT1 and ACT2 and during the blanking period BLANK1 between the active periods ACT1 and ACT2.

[0172] Figure 8 is a timing diagram of the active period and the blanking period according to an exemplary embodiment of the present disclosure.

[0173] Referring to Figure 8 , the period during which the display panel 110 is driven may include an active period and a blanking period. For example, it may be in the order of the first active period ACT1, the first blanking period BLANK1, and the second active period ACT2, but is not limited thereto.

[0174] Referring to Figure 8 , the active period may correspond to a period during which the vertical synchronization signal Vsync is at a high level. The blanking period may correspond to a period during which the vertical synchronization signal Vsync is at a low level.

[0175] Referring to Figure 8 , real-time sensing processing may be performed during the first blanking period BLANK1. The real-time sensing processing may include an initialization period, a tracking period, and a sampling period. That is, the sampling period may be performed during the first blanking period BLANK1.

[0176] Referring to Figure 8 , the voltage level of the source driving voltage SVDD may increase during the sampling period. That is, the voltage level of the source driving voltage SVDD may increase during the first blanking period BLANK1. Referring to Figure 8, the first blanking period BLANK1 may start at the first time point t1 and end at the third time point t3. The voltage level of the source driving voltage SVDD may increase at the first time point t1 and reach a specific value over time. Starting from the second time point t2, the voltage level of the source driving voltage SVDD may decrease. Before the display device 100 leaves the factory, a reference value (not shown) may be generated when the display device 100 is driven while a reference source driving voltage (not shown) is provided to the data driving circuit 120. The reference value may be data used as a reference for external compensation. Since the reference value generated before leaving the factory is data derived when the reference source driving voltage is provided to the data driving circuit 120, the source driving voltage SVDD can be set equal to the reference source voltage even when performing real-time sensing processing, which is one of the external compensation methods. For example, the reference source voltage may be 16.8 [V], but the reference source voltage may be greater than or less than 16.8 [V]. Refer to Figure 8 , the source driving voltage SVDD during the first blanking period BLANK1 may be greater than the source driving voltage SVDD during the active periods ACT1 and ACT2.

[0177] Refer to Figure 8 , after the sampling period ends, the voltage level of the source driving voltage SVDD may decrease. The source driving voltage SVDD increased for real-time sensing processing may decrease to the voltage level required for the second active period ACT2. Starting from the second time point t2, the voltage level of the source driving voltage SVDD may decrease. At this time, due to the change in the voltage level of the source driving voltage SVDD, the voltage level of the reference voltage Vref may become unstable. For example, the voltage level of the reference voltage Vref may increase or decrease. For example, refer to Figure 8 , the voltage level of the reference voltage Vref may increase from the second time point t2. In addition, the voltage level of the reference voltage Vref may start to decrease from the third time point t3. However, since the reference voltage Vref is a voltage for reference, the reference voltage Vref needs to be maintained at a constant value.

[0178] The relationship between the reference voltage Vref and the source driving voltage SVDD can be "reference voltage (Vref) = code value / 1023 * source driving voltage (SVDD)". Here, the code value can be digital data used to control the level of the reference voltage Vref. Since the reference voltage Vref is a voltage for reference, the reference voltage Vref needs to be maintained at a constant value. If the source driving voltage SVDD decreases, the voltage level of the reference voltage Vref can be maintained by increasing the code value. At this time, the code value as a digital signal is data that can be increased immediately, while the voltage level of the source driving voltage SVDD as an analog signal may decrease relatively slowly. That is, due to the difference in the change time between the digital signal and the analog signal, there may be a portion where the reference voltage Vref temporarily increases, which can be Figure 8 the portion between the second time point t2 and the third time point t3 shown in. After that, as the source driving voltage SVDD decreases, the reference voltage Vref can also decrease. The portion where the reference voltage Vref decreases can be the portion after the third time point t3. The above-described change phenomenon of the reference voltage Vref can be expressed as the fluctuation of the reference voltage Vref. Exemplary embodiments of the present disclosure can provide a display device capable of stably controlling the reference voltage.

[0179] The first active period ACT1 can be performed before the first blanking period BLANK1, and the second active period ACT2 can be performed after the first blanking period BLANK1. Since the adaptive SVDD control method is applied, the source driving voltage SVDD can be reduced to the required voltage level during the second active period ACT2. The reference voltage Vref can be increased to the required voltage level during the second active period ACT2.

[0180] To stably drive the second active period ACT2, before the second active period ACT2 starts, it is necessary to reduce the voltage level of the source driving voltage SVDD to a predetermined voltage level. That is, after the sampling period included in the first blanking period BLANK1, the voltage level of the source driving voltage SVDD can start to decrease, and the voltage level needs to be reduced to the predetermined voltage level before the second active period ACT2.

[0181] However, the time when the voltage level of the source driving voltage SVDD decreases may be delayed. In this case, even after the second active period ACT2 starts, the voltage level of the source driving voltage SVDD may decrease. As the voltage level of the source driving voltage SVDD decreases even after the second active period ACT2 starts, the voltage level of the reference voltage Vref can also change. For example, as the source driving voltage SVDD decreases, the reference voltage Vref may also decrease or increase.

[0182] Referring to Figure 8 Figure 8 , the third time point t3 may be the timing at which the second active period ACT2 starts. At the third time point t3, the voltage level of the source drive voltage SVDD may decrease, and as the voltage level of the source drive voltage SVDD decreases, a problem of voltage level fluctuation of the reference voltage Vref may occur. For example, at the third time point t3, as the source drive voltage SVDD decreases, the reference voltage Vref may also decrease.

[0183] Accordingly, embodiments of the present disclosure may provide a display device 100 capable of stably controlling the source drive voltage SVDD.

[0184] Embodiments of the present disclosure may provide a display device 100 capable of stably controlling the reference voltage Vref.

[0185] Embodiments of the present disclosure may provide a display device 100 capable of providing a stable voltage during an active period.

[0186] Embodiments of the present disclosure may provide a display device 100 capable of low power consumption due to stable voltage control. This will be explained in detail below.

[0187] Figure 9 A comparison circuit 910 and a discharge circuit 920 according to an exemplary embodiment of the present disclosure are shown.

[0188] The display device 100 may include a data driving circuit 120, a power management integrated circuit 310, a controller 140, a comparison circuit 910, a discharge circuit 920, and the like. The comparison circuit 910 and the discharge circuit 920 may be provided on a source printed circuit board or a control printed circuit board, but are not limited thereto.

[0189] The data driving circuit 120 may drive a display panel 110 on which a plurality of sub-pixels are provided. The data driving circuit 120 may be electrically connected to the power management integrated circuit 310.

[0190] The controller 140 may control the data driving circuit 120, the power management integrated circuit 310, and the discharge circuit 920.

[0191] The controller 140 may be electrically connected to the power management integrated circuit 310 and a first node Na1. In addition, the controller 140 may be electrically connected to the discharge circuit 920.

[0192] The controller 140 may control the power management integrated circuit 310 and may output a first control signal En1 to the discharge circuit 920.

[0193] The controller 140 can output a first control signal En1 to the discharge circuit 920 through a first control line EL1.

[0194] The controller 140 can output a source drive voltage control signal VCS to the power management integrated circuit 310, and the power management integrated circuit 310 can control the voltage level of the source drive voltage SVDD based on the source drive voltage control signal VCS.

[0195] The power management integrated circuit 310 can be electrically connected to the controller 140, the data driving circuit 120, the comparison circuit 910, and the discharge circuit 920.

[0196] The power management integrated circuit 310 can be electrically connected to the controller 140 and the first node Na1.

[0197] The power management integrated circuit 310 can supply the source drive voltage SVDD to the data driving circuit 120.

[0198] In addition, the power management integrated circuit 310 can supply the source drive voltage SVDD to the comparison circuit 910.

[0199] The comparison circuit 910 can output an output signal based on an input signal. For example, the comparison circuit 910 can receive the source drive voltage SVDD and the reference drive voltage SVDD_ref, and output a second control signal En2.

[0200] The comparison circuit 910 can receive the source drive voltage SVDD through a first input line IL1.

[0201] The comparison circuit 910 can receive the reference drive voltage SVDD_ref through a second input line IL2.

[0202] The reference drive voltage SVDD_ref can be the voltage level of the source drive voltage SVDD with the lowest voltage level. For example, the reference drive voltage SVDD_ref can be 12 [V], but is not limited thereto. The reference drive voltage SVDD_ref can be a voltage provided from outside the display device 100. When the display device 100 is driven, the reference drive voltage SVDD_ref can be maintained without changing the voltage level.

[0203] The comparison circuit 910 can compare the source drive voltage SVDD and the reference drive voltage SVDD_ref, and output the second control signal En2 to an output line OL. In addition, the discharge circuit 920 can receive the second control signal En2 through the output line OL. In addition, the discharge circuit 920 can receive the first control signal En1 through the first control line EL1.

[0204] If the source driving voltage SVDD is greater than the reference driving voltage SVDD_ref, the comparison circuit 910 can output a second control signal En2 in a high level state to the discharge circuit 920.

[0205] If the source driving voltage SVDD is less than the reference driving voltage SVDD_ref, the comparison circuit 910 can output a second control signal En2 in a low level state to the discharge circuit 920.

[0206] The discharge circuit 920 can reduce the voltage level of the source driving voltage SVDD. That is to say, the discharge circuit 920 can discharge the source driving voltage SVDD.

[0207] The discharge circuit 920 can be electrically connected to the comparison circuit 910 and the controller 140. For example, the discharge circuit 920 can receive the first control signal En1 output from the controller 140 and the second control signal En2 output from the comparison circuit 910, and discharge the source driving voltage SVDD.

[0208] The discharge circuit 920 can be electrically connected to the comparison circuit 910 through the output line OL of the comparison circuit 910.

[0209] The discharge circuit 920 can be electrically connected to the controller 140 through the first control line EL1.

[0210] The discharge circuit 920 can compare the first control signal En1 with the second control signal En2, and discharge the source driving voltage SVDD.

[0211] The discharge circuit 920 can discharge the source driving voltage SVDD in response to receiving the second control signal En2 in a high level state and the first control signal En1 in a high level state, but is not limited thereto. The timing of the voltage level change of the first control signal En1 and the second control signal En2 will be described below with reference to Figure 12 Describe the timing of the voltage level change of the first control signal En1 and the second control signal En2.

[0212] That is to say, the discharge circuit 920 can quickly discharge the source driving voltage SVDD, so that the problem of time delay in the reduction of the source driving voltage SVDD can be solved. The discharge circuit 920 can quickly discharge the source driving voltage SVDD. Therefore, even during the blanking period before the active period, the problem of fluctuation of the reference voltage Vref due to the rapid discharge of the source driving voltage SVDD can be solved. The voltage level of the reference voltage Vref can be stably maintained, and the reference voltage Vref can also be stably maintained even during the active period. Therefore, even during the active period, there will be no screen abnormality in the display panel 110.

[0213] The comparison circuit 910 and the discharge circuit 920 can be designed in various ways. For example, the comparison circuit 910 and the discharge circuit 920 can be designed as Figure 10 shown, which will be explained below.

[0214] Figure 10 FIG. 6 shows a comparison circuit 910 and a discharge circuit 920 according to an exemplary embodiment of the present disclosure.

[0215] Figure 11 FIG. 10 is a truth table based on a first control signal En1 and a second control signal En2 according to an exemplary embodiment of the present disclosure.

[0216] The comparison circuit 910 may include a comparator circuit 911 including an operational amplifier.

[0217] The comparison circuit 910 may include a first input terminal (+), a second input terminal (-), and an output terminal.

[0218] The first input terminal (+) may be electrically connected to the first input line IL1. The first input terminal (+) may be supplied with a source drive voltage SVDD.

[0219] The second input terminal (-) may be electrically connected to the second input line IL2. The second input terminal (-) may be supplied with a reference drive voltage SVDD_ref.

[0220] The output terminal may be electrically connected to the output line OL. The output terminal may output the second control signal En2.

[0221] The comparison circuit 910 may compare the source drive voltage SVDD and the reference drive voltage SVDD_ref, and output the second control signal En2 to the output line OL.

[0222] If the source drive voltage SVDD is greater than the reference drive voltage SVDD_ref, the comparison circuit 910 may output the second control signal En2 in a high level state to the discharge circuit 920.

[0223] If the source drive voltage SVDD is less than the reference drive voltage SVDD_ref, the comparison circuit 910 may output the second control signal En2 in a low level state to the discharge circuit 920.

[0224] The discharge circuit 920 may include a diode 921, a first discharge transistor 922, a second discharge transistor 923, and a resistive element 924. The discharge circuit 920 may be configured to compare the first control signal En1 output from the controller 140 and the second control signal En2 output from the comparison circuit 910, and discharge the source drive voltage SVDD.

[0225] The diode 921 can prevent reverse voltage phenomenon. The diode 921 can be electrically connected to the node where the source driving voltage SVDD of the data driving circuit 120 is provided. The diode 921 can be electrically connected between the third node Na3 and the seventh node Na7. The diode 921 can be electrically connected to the first discharge transistor 922. The first discharge transistor 922 can be electrically connected to the second discharge transistor 923.

[0226] The first discharge transistor 922 can be electrically connected between the diode 921 and the second discharge transistor 923.

[0227] The first control signal En1 can be provided to the gate node of the first discharge transistor 922. The gate node of the first discharge transistor 922 can be electrically connected to the second node Na2.

[0228] The second discharge transistor 923 can be electrically connected between the first discharge transistor 922 and the ground node. The ground node can be the node to which the ground voltage is provided.

[0229] The gate node of the second discharge transistor 923 can be provided with the second control signal En2. The gate node of the second discharge transistor 923 can be electrically connected to the fifth node Na5.

[0230] The gate node of the second discharge transistor 923 can be electrically connected to one end of the resistance element 924. The other end of the resistance element 924 can be electrically connected to the ground node.

[0231] The resistance element 924 can be electrically connected between the gate node of the second discharge transistor 923 and the ground node. The ground node can be the node to which the ground voltage is provided.

[0232] Since the gate node of the second discharge transistor 923 is electrically connected to the resistance element 924, the voltage of the second discharge transistor 923 can be stably controlled.

[0233] Refer to Figure 11 , a truth table in which the discharge circuit 920 is driven is shown. The discharge circuit 920 can be configured to compare the first control signal En1 output from the controller 140 and the second control signal En2 output from the comparison circuit 910, and discharge the source driving voltage SVDD.

[0234] If the first control signal En1 is a high-level signal and the second control signal En2 is a high-level signal, the discharge circuit 920 can operate in a discharge mode. Therefore, if the first control signal En1 is a high-level signal and the second control signal En2 is a high-level signal, the discharge circuit 920 can discharge the source driving voltage SVDD. When the discharge circuit 920 operates in the discharge mode, the voltage level of the source driving voltage SVDD can be rapidly reduced. In this case, the first discharge transistor 922 and the second discharge transistor 923 can be turned on, and the voltage level of the source driving voltage SVDD on the data driving circuit 120 side can be rapidly discharged to the ground voltage level.

[0235] If the first control signal En1 is a high-level signal and the second control signal En2 is a low-level signal, the discharge circuit 920 cannot operate in the discharge mode.

[0236] If the first control signal En1 is a low-level signal and the second control signal En2 is a high-level signal, the discharge circuit 920 cannot operate in the discharge mode.

[0237] If the first control signal En1 is a low-level signal and the second control signal En2 is a low-level signal, the discharge circuit 920 cannot operate in the discharge mode.

[0238] That is, the discharge circuit 920 can discharge the source driving voltage SVDD only when both the first control signal En1 and the second control signal En2 are high-level signals.

[0239] When it is not necessary to rapidly discharge the source driving voltage SVDD, the discharge circuit 920 can refrain from operating in the discharge mode.

[0240] Hereinafter, the Figure 9 and Figure 10 operation timings of the comparison circuit 910 and the discharge circuit 920 shown will be described.

[0241] Figure 12 is a timing diagram of the discharge mode operation of the display device 100 according to an exemplary embodiment of the present disclosure.

[0242] Figure 13 is a timing diagram of the normal mode operation of the display device 100 according to an exemplary embodiment of the present disclosure.

[0243] Referring to Figure 12 , the first time period T1 can be the time period between the first time point t1 and the second time point t2.

[0244] Real-time sensing processing can be performed during the first period T1. Real-time sensing processing can be performed during the blanking period. For example, real-time sensing processing can be performed based on the vertical synchronization signal during each blanking period, but is not limited thereto. The period during which the discharge circuit 920 is in the discharge mode can be the blanking period.

[0245] Referring to Figure 12 , the source drive voltage SVDD can increase at the first time point t1. Here, the source drive voltage SVDD can be the same as the source drive voltage SVDD-Out on the data driver circuit side.

[0246] Real-time sensing processing can be performed after the first time point t1, and at the second time point t2, the sampling signal SAM can change from a low-level signal to a high-level signal and a sampling operation can be performed. The sampling operation can be performed from the second time point t2 to the third time point t3. For example, at the third time point t3, the sampling signal SAM can change from a high-level signal to a low-level signal.

[0247] Referring to Figure 12 , the second period T2 can be performed after the first period T1. The second period T2 can be the period between the second time point t2 and the third time point t3.

[0248] The period during which the sampling operation is performed can be the second period T2.

[0249] During the second period T2, the first control signal En1 can be in a low-level state.

[0250] During the period from the first time point t1 to the third time point t3, the source drive voltage SVDD can be greater than the reference drive voltage SVDD_ref, and the second control signal En2 can be in a high-level state. That is, the second control signal En2 can be in a high-level state during the third period T3.

[0251] Referring to Figure 12 , the third period T3 can be performed after the second period T2. The third period T3 can be the period between the third time point t3 and the fourth time point t4.

[0252] The first control signal En1 can start to be in a high-level state from the third time point t3. However, according to the design, even before the termination of the sampling period, the first control signal En1 can be in a high-level state. In this case, when the sampling signal SAM is in a high-level state, the first control signal En1 can also be in a high-level state.

[0253] During the third period T3, the first control signal En1 and the second control signal En2 can be at a high level, enabling the discharge circuit 920 to operate in a discharge mode. Thus, if the first control signal En1 is a high-level signal and the second control signal En2 is a high-level signal, the discharge circuit 920 can discharge the source drive voltage SVDD. Refer to Figure 12 , it is shown that the discharge signal DS indicating the discharge mode is in a high level state. When the discharge circuit 920 operates in the discharge mode, the source drive voltage SVDD can be rapidly discharged.

[0254] Refer to Figure 12 , during the third period T3 between the third time point t3 and the fourth time point t4, the source drive voltage SVDD can decrease, and the source drive voltage SVDD can be equal to the reference drive voltage SVDD_ref at the fourth time point t4. Thus, the second control signal En2 can change from a high level state to a low level state. Since the first control signal En1 is in a high level state while the second control signal En2 is in a low level state, the discharge circuit 920 cannot operate in the discharge mode.

[0255] Refer to Figure 12 , the fourth period T4 can occur after the third period T3. The fourth period T4 can be the period between the fourth time point t4 and the fifth time point t5.

[0256] The source drive voltage SVDD can be equal to the reference drive voltage SVDD_ref at the fourth time point t4. Since the source drive voltage SVDD has dropped to the voltage level of the reference drive voltage SVDD_ref, the discharge mode can be in an off state.

[0257] Refer to Figure 12 , during the fourth period T4, the first control signal En1 can be a high-level signal. After the voltage level of the source drive voltage SVDD has been sufficiently discharged, the first control signal En1 can change from a high level state to a low level state. According to the design, the fourth period T4 can be set to be short. For example, the first control signal En1 can also change to a low level immediately after the second control signal En2 changes to a low level, but it is not limited to this. For example, the first control signal En1 can change to a low level after a predetermined time after the second control signal En2 changes to a low level.

[0258] The first control signal En1 can be in a low level state during the blanking period. In this case, the source drive voltage SVDD can be discharged before the active period. However, if the sampling period is delayed, the first control signal En1 can be in a low level during the active period after the blanking period.

[0259] The fifth time period T5 can occur after the fourth time period T4. The fifth time period T5 can be a time period between the fifth time point t5 and the sixth time point T6.

[0260] During the fifth time period T5, the first control signal En1 can be in a low level state.

[0261] During the fifth time period T5, the second control signal En2 can be in a low level state.

[0262] When the fifth time period T5 has been reached, the voltage level of the source drive voltage can be rapidly decreased. That is, the source drive voltage required for the active period has been reached, and thus the reference voltage can be stably controlled.

[0263] Next, the Figure 13 shown timing operation will be described.

[0264] Referring to Figure 13 , a diagram showing the timing of the discharge circuit 920 operating in the normal mode is shown.

[0265] Referring to Figure 13 , after the off-sensing process is performed, the discharge circuit 920 can operate in the normal mode. Since the off-sensing process has also been completed, the sampling signal SAM can remain at a low level even during the second time period T2.

[0266] When the normal mode is in progress, it is not necessary to rapidly discharge the source drive voltage SVDD, so that the discharge circuit 920 can operate in the normal mode. Therefore, the source drive voltage SVDD can be gradually decreased. For example, the source drive voltage SVDD can be gradually decreased between the third time point t3 and the sixth time point t6.

[0267] Figure 14 A comparison circuit 910 and a discharge circuit 920 according to an exemplary embodiment of the present disclosure are shown.

[0268] Figure 15 A comparison circuit 910 and a discharge circuit 920 according to an exemplary embodiment of the present disclosure are shown.

[0269] Referring to Figure 14 and Figure 15 , the controller 140 can be electrically connected to the comparison circuit 910.

[0270] Referring to Figure 14 and Figure 15 , the controller 140 can supply the first control signal En1 to the comparison circuit 910.

[0271] Referring to Figure 14, the comparison circuit 910 can be controlled to be turned on or off according to the first control signal En1.

[0272] Refer to Figure 15 , in addition to the comparator circuit 911, the comparison circuit 910 may further include a control discharge transistor 912.

[0273] Refer to Figure 15 , the control discharge transistor 912 may be electrically connected between the output terminal of the comparison circuit 910 and the gate node of the second discharge transistor 923. For example, the control discharge transistor 912 may be electrically connected between the output terminal of the comparator circuit 911 and the gate node of the second discharge transistor 923.

[0274] Refer to Figure 15 , the gate node of the control discharge transistor 912 may be electrically connected to the controller 140. The first control signal En1 may be provided to the gate node of the control discharge transistor 912.

[0275] That is to say, since the comparison circuit 910 further includes the control discharge transistor 912, the comparison circuit 910 can be controlled to be turned on or off according to the first control signal En1.

[0276] Figure 16 is a flowchart of a driving method of the display device 100 according to an exemplary embodiment of the present disclosure.

[0277] The driving method of the display device 100 may include a first control signal output step (S1610), a second control signal output step (S1620), a control signal comparison step (S1630), a voltage discharge step (S1640), etc.

[0278] The first control signal output step (S1610) may be a step in which the controller 140 for controlling the data driving circuit 120 outputs the first control signal En1 to the discharge circuit 920.

[0279] The second control signal output step (S1620) may be a step in which the comparison circuit 910 compares the source driving voltage SVDD and the reference driving voltage SVDD_ref and outputs the second control signal En2.

[0280] The control signal comparison step (S1630) may be a step in which the discharge circuit 920 compares the first control signal En1 and the second control signal En2.

[0281] In the control signal comparison step (S1630), when the comparison circuit 910 receives the first control signal En1 in a low level state, the comparison circuit 910 may be in an off state.

[0282] The voltage discharging step (S1640) may be a step in which the discharging circuit 920 discharges the source driving voltage SVDD.

[0283] In the voltage discharging step (S1640), if the source driving voltage SVDD is greater than the reference driving voltage SVDD_ref, the discharging circuit 920 may discharge the source driving voltage SVDD.

[0284] In the voltage discharging step (S1640), when receiving the first control signal En1 in a high level state, the discharging circuit 920 may discharge the source driving voltage SVDD.

[0285] In the voltage discharging step (S1640), when receiving the first control signal En1 in a low level state, the discharging circuit 920 may not discharge the source driving voltage SVDD.

[0286] In the voltage discharging step (S1640), when receiving the first control signal En1 in a high level state and the second control signal En2 in a high level state, the discharging circuit 920 may discharge the source driving voltage SVDD.

[0287] The above embodiments of the present disclosure will be briefly described below.

[0288] A display device according to an exemplary embodiment of the present disclosure may include: a display panel on which a plurality of sub-pixels are provided; a data driving circuit for driving the display panel; a power management integrated circuit for supplying a source driving voltage to the data driving circuit; a controller for controlling the power management integrated circuit and outputting a first control signal; a comparison circuit for comparing the source driving voltage and the reference driving voltage and outputting a second control signal; and a discharging circuit for comparing the first control signal and the second control signal output from the comparison circuit and discharging the source driving voltage.

[0289] If the source driving voltage is greater than the reference driving voltage, the comparison circuit may output a second control signal in a high level state to the discharging circuit.

[0290] The discharging circuit may discharge the source driving voltage in response to receiving the second control signal in a high level state and the first control signal in a high level state.

[0291] The comparison circuit may include a first input terminal, a second input terminal, and an output terminal. The first input terminal is supplied with the source driving voltage, the second input terminal is supplied with the reference driving voltage, and the output terminal is used to output the second control signal.

[0292] The discharge circuit may include a first discharge transistor having its gate node provided with a first control signal and a second discharge transistor having its gate node provided with a second control signal.

[0293] The discharge circuit may further include a diode, and the first discharge transistor may be electrically connected between the diode and the second discharge transistor.

[0294] The discharge circuit may further include a resistive element, and the resistive element may be electrically connected to the gate node of the second discharge transistor.

[0295] The comparison circuit may include a control discharge transistor electrically connected between the gate node of the second discharge transistor and the output terminal of the comparison circuit.

[0296] The control discharge transistor may be configured to control the turning on or off of the comparison circuit according to the first control signal.

[0297] The controller may output a source drive voltage control signal to the power management integrated circuit, and the power management integrated circuit may control the voltage level of the source drive voltage based on the source drive voltage control signal.

[0298] The period during which a plurality of sub-pixels are driven may include an active period for displaying an image on the display panel and a blanking period for detecting characteristic values of the plurality of sub-pixels. In this case, the discharge circuit may discharge the source drive voltage during the blanking period.

[0299] The discharge circuit may be provided with a first control signal in a high level state during the blanking period.

[0300] The comparison circuit may be turned off in response to receiving a first control signal in a low level state during the blanking period.

[0301] A driving method of a display device according to an exemplary embodiment of the present disclosure may include: outputting, by a controller of a control data driving circuit, a first control signal to a discharge circuit; comparing, by a comparison circuit, a source drive voltage and a reference drive voltage and outputting a second control signal; comparing, by the discharge circuit, the first control signal and the second control signal; and discharging, by the discharge circuit, the source drive voltage.

[0302] Discharging may include: discharging the source drive voltage when the source drive voltage is greater than the reference drive voltage.

[0303] Discharging may include: discharging the source drive voltage when the discharge circuit receives a first control signal in a high level state.

[0304] Discharging may include: discharging the source drive voltage when the discharge circuit receives a second control signal in a high level state.

[0305] The discharging may include: not discharging the source driving voltage when the discharging circuit receives a first control signal in a low level state.

[0306] When comparing the first control signal and the second control signal, the comparison circuit may be turned off when the comparison circuit receives the first control signal in a low level state.

[0307] A display device according to an exemplary embodiment of the present disclosure may include: a power management integrated circuit configured to provide a source driving voltage; a controller configured to output a first control signal; a comparison circuit configured to compare the source driving voltage and a reference driving voltage and output a second control signal; and a discharging circuit configured to compare the first control signal output from the controller and the second control signal output from the comparison circuit, and discharge the source driving voltage.

[0308] The above description and the drawings provide examples of the technical concept of the present disclosure for illustrative purposes only. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. Additionally, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present disclosure. Therefore, the scope of the present disclosure is not limited to the illustrated embodiments.

[0309] Cross - reference to related applications

[0310] This application claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0008687, filed on January 19, 2024, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A display device, the display device comprising: A display panel, on which a plurality of sub-pixels are provided; A data driving circuit for driving the display panel; A power management integrated circuit for providing a source driving voltage to the data driving circuit; A controller for controlling the power management integrated circuit and outputting a first control signal; A comparison circuit for comparing the source driving voltage and a reference driving voltage and outputting a second control signal; And A discharge circuit for comparing the first control signal and the second control signal output from the comparison circuit and discharging the source driving voltage.

2. The display device according to claim 1, wherein, If the source driving voltage is greater than the reference driving voltage, the comparison circuit outputs the second control signal in a high level state to the discharge circuit.

3. The display device according to claim 2, wherein, The discharge circuit discharges the source driving voltage in response to receiving the second control signal in the high level state and the first control signal in the high level state.

4. The display device according to claim 1, wherein, The comparison circuit includes: A first input terminal to which the source driving voltage is provided; A second input terminal to which the reference driving voltage is provided; and An output terminal for outputting the second control signal.

5. The display device according to claim 1, wherein, The discharge circuit includes: A first discharge transistor, the gate node of which is provided with the first control signal; and A second discharge transistor, the gate node of which is provided with the second control signal.

6. The display device according to claim 5, wherein, The discharge circuit further includes a diode, and the first discharge transistor is electrically connected between the diode and the second discharge transistor.

7. The display device according to claim 5, wherein, The discharge circuit further includes a resistance element, and the resistance element is electrically connected to the gate node of the second discharge transistor.

8. The display device according to claim 5, wherein, The comparison circuit includes a control discharge transistor, and the control discharge transistor is electrically connected between the gate node of the second discharge transistor and the output terminal of the comparison circuit.

9. The display device according to claim 8, wherein, The control discharge transistor is configured to control the turning on or off of the comparison circuit according to the first control signal.

10. The display device according to claim 1, wherein, The controller outputs a source driving voltage control signal to the power management integrated circuit, wherein the power management integrated circuit controls the voltage level of the source driving voltage based on the source driving voltage control signal.

11. The display device according to claim 1, wherein, The period during which the plurality of sub-pixels are driven includes: An active period for displaying an image on the display panel; and A blanking period for detecting a characteristic value of the plurality of sub-pixels, wherein the discharge circuit can discharge the source driving voltage during the blanking period.

12. The display device according to claim 11, wherein, The discharge circuit is provided with the first control signal in a high level state during the blanking period.

13. The display device according to claim 11, wherein, The comparison circuit is turned off in response to receiving the first control signal in a low level state during the blanking period.

14. A driving method for a display device, the driving method comprising the following steps: A controller that controls a data driving circuit outputs a first control signal to a discharge circuit; A comparison circuit compares a source driving voltage with a reference driving voltage and outputs a second control signal; The discharge circuit compares the first control signal with the second control signal; And The discharge circuit discharges the source driving voltage.

15. The driving method according to claim 14, wherein, The discharging step includes: when the source driving voltage is greater than the reference driving voltage, discharging the source driving voltage.

16. The driving method according to claim 14, wherein The discharging step includes: when the discharge circuit receives the first control signal in a high level state, discharging the source driving voltage.

17. The driving method according to claim 14 or 16, wherein, The discharging step includes: when the discharge circuit receives the second control signal in a high level state, discharging the source driving voltage.

18. The driving method according to claim 14, wherein, The discharging step includes: when the discharge circuit receives the first control signal in a low level state, not discharging the source driving voltage.

19. The driving method according to claim 14, wherein, When comparing the first control signal with the second control signal, the comparison circuit is turned off when the comparison circuit receives the first control signal in a low level state.

20. A display device, the display device includes: A power management integrated circuit configured to provide a source driving voltage; A controller configured to output a first control signal; A comparison circuit configured to compare the source driving voltage with a reference driving voltage and output a second control signal; And A discharge circuit configured to compare the first control signal output from the controller with the second control signal output from the comparison circuit and discharge the source driving voltage.

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