Gate signal masking circuit, gate emission driver and display device

Abstract

The invention provides a gate signal masking circuit, a gate emission driver and a display device. The gate signal masking circuit includes: a first switching element including a control electrode connected to a masking control node, a first electrode connected to a first input node, and a second electrode connected to an output control node; a second switching element including a control electrode connected to the second input node, a first electrode receiving the first power supply voltage, and a second electrode connected to the first intermediate node; a third switching element receiving an enable signal and connected to the first intermediate node and the second intermediate node; a fourth switching element receiving an enable signal and connected to the second intermediate node and the third intermediate node; a fifth switching element connected to a third input node and a third intermediate node and receiving a second power supply voltage; and a floating switching element receiving the floating control signal and connected to the mask control node and the second intermediate node.

Description

Technical Field

[0001] Embodiments of the present invention relate to a gate signal masking circuit, a gate emission driver including the gate signal masking circuit, and a display device including the gate emission driver. More specifically, embodiments of the present invention relate to a gate signal masking circuit for reducing power consumption and reducing dead zones, a gate emission driver including the gate signal masking circuit, and a display device including the gate emission driver. Background Art

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver generally includes a gate driver, a data driver, and a driving controller. The gate driver outputs a gate signal to the gate lines. The data driver outputs a data voltage to the data lines. The driving controller controls the gate driver and the data driver. Summary of the Invention

[0003] In a display device, when an image displayed on the display panel is a static image or the display panel operates in a normally-on mode, the driving frequency of the display panel can be reduced to reduce power consumption.

[0004] In a display device, when a part of an image displayed on the display panel is a static image and a part of the image displayed on the display panel is a moving image, it is desirable to reduce the driving frequency of the part of the display panel corresponding to the static image to further reduce power consumption.

[0005] However, in a conventional display device, since a stage of the gate driver receives an output of a previous stage as a carry signal to output a gate signal, it may not be possible to effectively reduce the driving frequency of only a part of the display panel.

[0006] Embodiments of the present invention provide a gate signal masking circuit that supports multiple division of a driving frequency to reduce power consumption of a display device and reduce dead zones of the display device.

[0007] Embodiments of the present invention also provide a gate emission driver including the gate signal masking circuit.

[0008] Embodiments of the present invention also provide a display device including the gate emission driver.

[0009] In an embodiment of the gate signal masking circuit according to the present invention, the gate signal masking circuit includes a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, and a floating switching element. In this embodiment, the first switching element includes a control electrode connected to a masking control node, a first electrode connected to a first input node, and a second electrode connected to an output control node. In this embodiment, the second switching element includes a control electrode connected to a second input node, a first electrode receiving a first power supply voltage, and a second electrode connected to a first intermediate node. In this embodiment, the third switching element includes a control electrode receiving an enable signal, a first electrode connected to the first intermediate node, and a second electrode connected to a second intermediate node. In this embodiment, the fourth switching element includes a control electrode receiving an enable signal, a first electrode connected to the second intermediate node, and a second electrode connected to a third intermediate node. In this embodiment, the fifth switching element includes a control electrode connected to a third input node, a first electrode connected to the third intermediate node, and a second electrode receiving a second power supply voltage. In this embodiment, the floating switching element includes a control electrode receiving a floating control signal, a first electrode connected to the masking control node, and a second electrode connected to the second intermediate node. In this embodiment, the second switching element and the third switching element are P-type transistors. In this embodiment, the fourth switching element and the fifth switching element are N-type transistors.

[0010] In an embodiment, the gate signal masking circuit may further include a sixth switching element and a seventh switching element. The sixth switching element includes a control electrode connected to the output control node, a first electrode receiving the first power supply voltage, and a second electrode connected to the gate output node. The seventh switching element includes a control electrode connected to the first input node, a first electrode connected to the gate output node, and a second electrode receiving the second power supply voltage.

[0011] In an embodiment, the gate signal masking circuit may further include an eighth switching element. The eighth switching element includes a control electrode connected to the masking control node, a first electrode receiving the first power supply voltage, and a second electrode connected to the output control node.

[0012] In an embodiment, the gate signal masking circuit may further include a first capacitor including a first electrode connected to the masking control node and a second electrode receiving the second power supply voltage.

[0013] In an embodiment, the floating control signal may be a transmit signal.

[0014] In an embodiment, when the floating control signal has a high level, the signal of the masking control node may maintain the previous state.

[0015] In an embodiment, the signal of the third input node may be the inverted signal of the signal of the second input node.

[0016] In an embodiment, when the enable signal has a high level, the signal of the second input node has a high level, and the floating control signal has a low level, the signal of the masking control node may maintain its previous state.

[0017] In an embodiment, when the enable signal has a high level, the signal of the second input node has a low level, and the floating control signal has a low level, the signal of the masking control node may have a low level.

[0018] In an embodiment, when the enable signal has a low level, the signal of the second input node has a high level, and the floating control signal has a low level, the signal of the masking control node may maintain its previous state.

[0019] In an embodiment, when the enable signal has a low level, the signal of the second input node has a low level, and the floating control signal has a low level, the signal of the masking control node may have a high level.

[0020] In an embodiment of the gate-emitter driver according to the present invention, the gate-emitter driver includes a first driver, a second driver, a third driver, and a gate signal masking circuit. In such an embodiment, the first driver generates a carry signal of the first gate signal based on the previous carry signal of the first gate signal. In such an embodiment, the second driver generates the second gate signal based on the previous second gate signal. In such an embodiment, the third driver generates the emitter signal based on the previous emitter signal. In such an embodiment, the gate signal masking circuit controls the output of the first gate signal based on the enable signal, the signal of the first input node of the first driver connected to the gate node of the first driver, the signal of the second input node of the second driver connected to the gate node of the second driver, the signal of the third input node of the second driver connected to the output node of the second driver, and the emitter signal.

[0021] In an embodiment, the gate signal masking circuit may include: a first switching element including a control electrode connected to a masking control node, a first electrode connected to a first input node, and a second electrode connected to an output control node; a second switching element including a control electrode connected to a second input node, a first electrode receiving a first power supply voltage, and a second electrode connected to a first intermediate node; a third switching element including a control electrode receiving an enable signal, a first electrode connected to the first intermediate node, and a second electrode connected to a second intermediate node; a fourth switching element including a control electrode receiving the enable signal, a first electrode connected to the second intermediate node, and a second electrode connected to a third intermediate node; a fifth switching element including a control electrode connected to a third input node, a first electrode connected to the third intermediate node, and a second electrode receiving a second power supply voltage; and a floating switching element including a control electrode receiving a transmission signal, a first electrode connected to the masking control node, and a second electrode connected to the second intermediate node. In this embodiment, the second switching element and the third switching element may be P-type transistors. In this embodiment, the fourth switching element and the fifth switching element may be N-type transistors.

[0022] In an embodiment, the gate signal masking circuit may further include: a sixth switching element including a control electrode connected to the output control node, a first electrode receiving the first power supply voltage, and a second electrode connected to a gate output node; a seventh switching element including a control electrode connected to the first input node, a first electrode connected to the gate output node, and a second electrode receiving the second power supply voltage; and an eighth switching element including a control electrode connected to the masking control node, a first electrode receiving the first power supply voltage, and a second electrode connected to the output control node.

[0023] In an embodiment, the first driver may include: a first first-gate switching element including a control electrode receiving one of a first clock signal and a second clock signal, a first electrode receiving a previous carry signal, and a second electrode connected to a first first-gate node; a second first-gate switching element including a control electrode receiving the other of the first clock signal and the second clock signal, a first electrode receiving the previous carry signal, and a second electrode connected to the first first-gate node; a third first-gate switching element including a control electrode connected to the first first-gate node, a first electrode receiving a first power supply voltage, and a second electrode connected to a second first-gate node; a fourth first-gate switching element including a control electrode connected to the first first-gate node, a first electrode connected to the second first-gate node, and a second electrode receiving a second power supply voltage; a fifth first-gate switching element including a control electrode connected to the second first-gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to a carry output node; and a sixth first-gate switching element including a control electrode connected to the second first-gate node, a first electrode connected to the carry output node, and a second electrode receiving the second power supply voltage. In this embodiment, the first first-gate switching element, the third first-gate switching element, and the fifth first-gate switching element may be P-type transistors. In this embodiment, the second first-gate switching element, the fourth first-gate switching element, and the sixth first-gate switching element may be N-type transistors. In this embodiment, the gate node connected to the first input node may be the second first-gate node.

[0024] In an embodiment, the first driver may include: a first first-gate switching element including a control electrode receiving one of a first clock signal and a second clock signal, a first electrode receiving a previous carry signal, and a second electrode connected to a first first-gate node; a third first-gate switching element including a control electrode connected to the first first-gate node, a first electrode receiving a first power supply voltage, and a second electrode connected to a second first-gate node; a fourth first-gate switching element including a control electrode connected to the first first-gate node, a first electrode connected to the second first-gate node, and a second electrode receiving a second power supply voltage; a fifth first-gate switching element including a control electrode connected to the second first-gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to a carry output node; and a sixth first-gate switching element including a control electrode connected to the second first-gate node, a first electrode connected to the carry output node, and a second electrode receiving the second power supply voltage. In this embodiment, the first first-gate switching element, the third first-gate switching element, and the fifth first-gate switching element may be P-type transistors. In this embodiment, the fourth first-gate switching element and the sixth first-gate switching element may be N-type transistors.

[0025] In an embodiment, the second driver may include: a first second-gate switching element including a control electrode receiving one of a first clock signal and a second clock signal, a first electrode receiving a previous second gate signal, and a second electrode connected to a first second-gate node; a second second-gate switching element including a control electrode receiving the other of the first clock signal and the second clock signal, a first electrode receiving the previous second gate signal, and a second electrode connected to the first second-gate node; a third second-gate switching element including a control electrode connected to the first second-gate node, a first electrode receiving a first power supply voltage, and a second electrode connected to a second second-gate node; a fourth second-gate switching element including a control electrode connected to the first second-gate node, a first electrode connected to the second second-gate node, and a second electrode receiving a second power supply voltage; a fifth second-gate switching element including a control electrode connected to the second second-gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to a second-gate output node; and a sixth second-gate switching element including a control electrode connected to the second second-gate node, a first electrode connected to the second-gate output node, and a second electrode receiving the second power supply voltage. In this embodiment, the first second-gate switching element, the third second-gate switching element, and the fifth second-gate switching element may be P-type transistors. In this embodiment, the second second-gate switching element, the fourth second-gate switching element, and the sixth second-gate switching element may be N-type transistors. In this embodiment, the gate node connected to the second input node may be the second second-gate node. In this embodiment, the output node connected to the third input node may be the second-gate output node.

[0026] In an embodiment, the second driver may include: a first second-gate switching element including a control electrode receiving one of a first clock signal and a second clock signal, a first electrode receiving a previous second gate signal, and a second electrode connected to a first second-gate node; a third second-gate switching element including a control electrode connected to the first second-gate node, a first electrode receiving a first power supply voltage, and a second electrode connected to a second second-gate node; a fourth second-gate switching element including a control electrode connected to the first second-gate node, a first electrode connected to the second second-gate node, and a second electrode receiving a second power supply voltage; a fifth second-gate switching element including a control electrode connected to the second second-gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to a second-gate output node; and a sixth second-gate switching element including a control electrode connected to the second second-gate node, a first electrode connected to the second-gate output node, and a second electrode receiving the second power supply voltage. In this embodiment, the first second-gate switching element, the third second-gate switching element, and the fifth second-gate switching element may be P-type transistors. In this embodiment, the fourth second-gate switching element and the sixth second-gate switching element may be N-type transistors.

[0027] In an embodiment of a display device according to the present invention, the display device includes a display panel, a gate-emission driver, and a data driver. In this embodiment, the display panel includes pixels. In this embodiment, the gate-emission driver outputs a gate signal and an emission signal to the pixels. In this embodiment, the data driver outputs a data voltage to the pixels. In this embodiment, the gate-emission driver includes a first driver, a second driver, a third driver, and a gate signal masking circuit, the first driver generates a carry signal of a first gate signal based on a previous carry signal of the first gate signal, the second driver generates a second gate signal based on a previous second gate signal, the third driver generates an emission signal based on a previous emission signal, and the gate signal masking circuit controls the output of the first gate signal based on an enable signal, a signal of a first input node of the first driver connected to a gate node of the first driver, a signal of a second input node of the second driver connected to a gate node of the second driver, a signal of a third input node of the second driver connected to an output node of the second driver, and the emission signal.

[0028] In an embodiment, the third driver may be disposed at a first side of the display panel. In this embodiment, the first driver and the second driver may be disposed at a second side of the display panel. In this embodiment, the gate signal masking circuit may receive the emission signal from an outermost pixel of the display panel in a first direction.

[0029] According to an embodiment of a gate signal masking circuit, a gate emission driver including the gate signal masking circuit, and a display device including the gate emission driver, the output of the first gate signal can be controlled based on an enable signal, a signal of a first input node of a first driver connected to a gate node of the first driver, a signal of a second input node of a second driver connected to a gate node of the second driver, a signal of a third input node of the second driver connected to an output node of the second driver, and an output signal of a third driver (e.g., an emission signal), thereby supporting multiple frequency divisions of a driving frequency.

[0030] In this embodiment, the power consumption of the display device can be effectively reduced through multiple frequency divisions of the driving frequency. In this embodiment, multiple frequency divisions of the driving frequency of a gate signal having two or more pulses can be supported.

[0031] In this embodiment, a circuit of the gate emission driver is disposed at a first side of the display panel, and another circuit of the gate emission driver is disposed at a second side of the display panel, thereby reducing a dead zone of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features of the embodiments of the present invention will become more apparent by describing the embodiments of the present invention in detail with reference to the accompanying drawings, in which:

[0033] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention;

[0034] Figure 2 is a circuit diagram showing an example of a pixel of a display panel of Figure 1 ;

[0035] Figure 3 is a circuit diagram showing an example of a pixel of a display panel of Figure 1 ;

[0036] Figure 4 is a conceptual diagram showing a gate emission driver of Figure 1 ;

[0037] Figure 5 is a conceptual diagram showing an enable signal of a gate emission driver to which a driving frequency of a part of a display panel according to Figure 1 is applied to Figure 1 ;

[0038] Figure 6 is a timing diagram showing input signals applied to a pixel of Figure 2 during a data writing period;

[0039] Figure 7 is a timing diagram showing input signals applied to a pixel of Figure 2Timing diagram of the input signal of the pixel;

[0040] Figure 8 is a block diagram showing an example of a gate emission driver of; Figure 1 ;

[0041] Figure 9 is a circuit diagram showing the first driver, the second driver, and the gate signal masking circuit of the gate emission driver of; Figure 1 ;

[0042] Figure 10 is a table showing the state of the signal of the masking control node of the input signal of the gate signal masking circuit according to; Figure 9 ;

[0043] Figure 11 is a table showing the state of the switching element of the input signal of the gate signal masking circuit according to; Figure 9 and the operation of the gate signal masking circuit of; Figure 9 ; Figure 9 ;

[0044] Figure 12 is a timing diagram showing the output of the first gate signal when the low pulse of the enable signal is at the first time position;

[0045] Figure 13 is a timing diagram showing the output of the first gate signal when the low pulse of the enable signal is at the second time position;

[0046] Figure 14 is a timing diagram showing the output of the first gate signal when the low pulse of the enable signal is at the third time position;

[0047] Figure 15 is a circuit diagram showing the first driver, the second driver, and the gate signal masking circuit of the gate emission driver according to an embodiment of the present invention;

[0048] Figure 16 is a block diagram showing an electronic device according to an embodiment of the present invention; and

[0049] Figure 17 is a diagram showing an example in which the electronic device of; Figure 16 is implemented as a smart phone. DETAILED DESCRIPTION

[0050] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which various embodiments are shown. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

[0051] It should be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements.

[0052] It should be understood that although the terms “first”, “second”, “third”, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a “first element”, “first component”, “first region”, “first layer” or “first section” discussed below may be referred to as a second element, second component, second region, second layer or second section without departing from the teachings herein.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, “a”, “an”, “the” and “at least one” do not denote a limitation of quantity and are intended to include both the singular and the plural. Thus, a reference to “an” element followed by a reference to “the” element includes one element and a plurality of elements. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element”. “At least one” should not be construed as limiting “one” or “a”. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that when the terms “comprises”, “comprising”, “includes” and / or “including” are used in this specification, they specify the presence of the stated features, regions, wholes, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0054] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe a relationship of one element to another element as shown in the figures. It should be understood that relative terms are also intended to cover different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is flipped, an element described as being on the "lower" side of another element will then be oriented on the "upper" side of the other element. Thus, the term "lower" can cover both the orientation of "lower" and "upper" depending on the specific orientation of the figure. Similarly, if the device in one of the figures is flipped, an element described as "below" or "beneath" another element will then be oriented "above" the other element. Thus, the terms "below" or "beneath" can cover both the orientation of above and below.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0056] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0057] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0058] Referring to Figure 1 , an embodiment of the display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate emission driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0059] The display panel 100 has a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0060] The display panel 100 includes a plurality of gate lines GWL, GCL, GIL, and GBL, a plurality of emission lines EML, a plurality of data lines DL, and a plurality of pixels electrically connected to the gate lines GWL, GCL, GIL, and GBL, the emission lines EML, and the data lines DL. The gate lines GWL, GCL, GIL, and GBL may extend in a first direction D1, the emission lines EML may extend in the first direction D1, and the data lines DL may extend in a second direction D2 intersecting the first direction D1.

[0061] The driving controller 200 receives input image data IMG and an input control signal CONT from an external device. In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0062] The driving controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0063] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate emission driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate emission driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0064] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0065] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0066] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0067] The gate emission driver 300 generates gate signals for driving gate lines GWL, GCL, GIL, and GBL in response to the first control signal CONT1 received from the driving controller 200. The gate emission driver 300 may output the gate signals to the gate lines GWL, GCL, GIL, and GBL. The gate emission driver 300 generates an emission signal for driving an emission line EML in response to the first control signal CONT1 received from the driving controller 200. The gate emission driver 300 may output the emission signal to the emission line EML.

[0068] Although for the convenience of illustration and description,Figure 1 An embodiment is shown in which the gate emission driver 300 is disposed at the first side of the display panel 100, but the present invention is not limited thereto. In another embodiment, the gate emission driver 300 may be disposed at both sides of the display panel 100. In an embodiment, for example, some portions of the gate emission driver 300 may be disposed at the first side of the display panel 100, and other portions of the gate emission driver 300 may be disposed at the second side of the display panel 100.

[0069] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0070] In an embodiment, the gamma reference voltage generator 400 may be disposed in the driving controller 200 or in the data driver 500.

[0071] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the driving controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage having an analog type using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0072] Figure 2 is a circuit diagram showing Figure 1 an example of a pixel of the display panel 100.

[0073] Referring to Figure 1 and Figure 2 , in an embodiment, the display panel 100 includes a plurality of pixels. Each of the pixels includes a light emitting element EE.

[0074] The pixel receives a data write gate signal GW[n], a compensation gate signal GC[n], a data initialization gate signal GI[n], a light emitting element initialization gate signal GB[n], an emission signal EM[n], and a data voltage VDATA, and the light emitting element EE of the pixel emits light having a brightness corresponding to the level of the data voltage VDATA to display an image.

[0075] In an embodiment, a pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a polysilicon thin film transistor. For example, the first type of switching element may be a low temperature polysilicon (LTPS) thin film transistor. For example, the second type of switching element may be an oxide semiconductor thin film transistor. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor. Although in an embodiment, some of the pixel switching elements are oxide semiconductor thin film transistors and other pixel switching elements are polysilicon thin film transistors, the present invention is not limited thereto. The embodiments of the present invention described herein may be applied to pixels including only oxide semiconductor thin film transistors. Although in an embodiment, some of the pixel switching elements are N-type transistors and other pixel switching elements are P-type transistors, the present invention is not limited thereto. The embodiments of the present invention described herein may be applied to pixels including only N-type transistors.

[0076] At least one of the pixels may include a first pixel switching element PT1 to a seventh pixel switching element PT7 and a light emitting element EE.

[0077] The first pixel switching element PT1 may include a control electrode connected to a first pixel node PN1, a first electrode connected to a second pixel node PN2, and a second electrode connected to a third pixel node PN3. The second pixel switching element PT2 may include a control electrode receiving a data write gate signal GW[n], a first electrode receiving a data voltage VDATA, and a second electrode connected to the second pixel node PN2. The third pixel switching element PT3 may include a control electrode receiving a compensation gate signal GC[n], a first electrode connected to the first pixel node PN1, and a second electrode connected to the third pixel node PN3. The fourth pixel switching element PT4 may include a control electrode receiving a data initialization gate signal GI[n], a first electrode receiving an initialization voltage VINIT, and a second electrode connected to the first pixel node PN1. The fifth pixel switching element PT5 may include a control electrode receiving an emission signal EM[n], a first electrode receiving a pixel high power supply voltage ELVDD, and a second electrode connected to the second pixel node PN2. The sixth pixel switching element PT6 may include a control electrode receiving the emission signal EM[n], a first electrode connected to the third pixel node PN3, and a second electrode connected to an anode of the light emitting element EE. The seventh pixel switching element PT7 may include a control electrode receiving a light emitting element initialization gate signal GB[n], a first electrode receiving a light emitting element initialization voltage VAINIT, and a second electrode connected to the anode of the light emitting element EE. The light emitting element EE may include an anode and a cathode receiving a pixel low power supply voltage ELVSS.

[0078] The pixel may further include a storage capacitor CST and a boosting capacitor CBOOST. The storage capacitor CST includes a first electrode receiving a pixel high power supply voltage ELVDD and a second electrode connected to a first pixel node PN1. The boosting capacitor CBOOST includes a first electrode receiving a data write gate signal GW[n] and a second electrode connected to the first pixel node PN1.

[0079] In this embodiment, the signal output from the gate signal masking circuit of the gate emission driver 300 may be a data initialization gate signal GI[n]. Alternatively, the signal output from the gate signal masking circuit of the gate emission driver 300 may be a compensation gate signal GC[n].

[0080] A driving current may flow through a fifth pixel switching element PT5, a first pixel switching element PT1, and a sixth pixel switching element PT6 to drive a light emitting element EE. The intensity of the driving current may be determined by the level of a data voltage VDATA. The luminance of the light emitting element EE may be determined by the intensity of the driving current.

[0081] In an embodiment, when the image displayed on the display panel 100 is a static image or the display panel 100 operates in an always-on mode, the driving frequency of the display panel 100 may be reduced to reduce power consumption. In the case where all of the switching elements of the pixels of the display panel 100 are polysilicon thin film transistors, in a low-frequency driving mode, flicker may occur due to leakage current of the pixel switching elements. Therefore, oxide semiconductor thin film transistors may be used to design some of the pixel switching elements. In an embodiment, for example, a third pixel switching element PT3 and a fourth pixel switching element PT4 may be oxide semiconductor thin film transistors, and a first pixel switching element PT1, a second pixel switching element PT2, a fifth pixel switching element PT5, a sixth pixel switching element PT6, and a seventh pixel switching element PT7 may be polysilicon thin film transistors.

[0082] Figure 3 is a circuit diagram showing Figure 1 an example of a pixel of the display panel 100.

[0083] Referring to Figure 1 and Figure 3 , in an embodiment, the display panel 100 includes a plurality of pixels. Each of the pixels includes a light emitting element EE.

[0084] The pixel receives a data write gate signal GW[n], a compensation gate signal GC[n], a data initialization gate signal GI[n], a light emitting element initialization gate signal GB[n], an emission signal EM[n], and a data voltage VDATA, and the light emitting element EE of the pixel emits light having a luminance corresponding to the level of the data voltage VDATA to display an image.

[0085] In an embodiment, a pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a polysilicon thin film transistor. For example, the first type of switching element may be a low temperature polysilicon (LTPS) thin film transistor. For example, the second type of switching element may be an oxide semiconductor thin film transistor. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor. Although in an embodiment, some of the pixel switching elements are oxide semiconductor thin film transistors and other pixel switching elements are polysilicon thin film transistors, the present invention is not limited thereto. The embodiments of the present invention described herein may be applied to pixels including only oxide semiconductor thin film transistors. Although in an embodiment, some of the pixel switching elements are N-type transistors and other pixel switching elements are P-type transistors, the present invention is not limited thereto. The embodiments of the present invention described herein may be applied to pixels including only N-type transistors.

[0086] At least one of the pixels may include a first pixel switching element PT1 to an eighth pixel switching element PT8 and a light emitting element EE.

[0087] The first pixel switching element PT1 may include a control electrode connected to the first pixel node PN1, a first electrode connected to the second pixel node PN2, and a second electrode connected to the third pixel node PN3. The second pixel switching element PT2 may include a control electrode receiving the data write gate signal GW[n], a first electrode receiving the data voltage VDATA, and a second electrode connected to the second pixel node PN2. The third pixel switching element PT3 may include a control electrode receiving the compensation gate signal GC[n], a first electrode connected to the first pixel node PN1, and a second electrode connected to the third pixel node PN3. The fourth pixel switching element PT4 may include a control electrode receiving the data initialization gate signal GI[n], a first electrode receiving the initialization voltage VINIT, and a second electrode connected to the first pixel node PN1. The fifth pixel switching element PT5 may include a control electrode receiving the emission signal EM[n], a first electrode receiving the pixel high power supply voltage ELVDD, and a second electrode connected to the second pixel node PN2. The sixth pixel switching element PT6 may include a control electrode receiving the emission signal EM[n], a first electrode connected to the third pixel node PN3, and a second electrode connected to the anode of the light emitting element EE. The seventh pixel switching element PT7 may include a control electrode receiving the light emitting element initialization gate signal GB[n], a first electrode receiving the light emitting element initialization voltage VAINIT, and a second electrode connected to the anode of the light emitting element EE. The eighth pixel switching element PT8 may include a control electrode receiving the light emitting element initialization gate signal GB[n], a first electrode receiving the bias voltage VBIAS, and a second electrode connected to the second pixel node PN2. The light emitting element EE may include an anode and a cathode receiving the pixel low power supply voltage ELVSS.

[0088] The pixel may further include a storage capacitor CST and a boost capacitor CBOOST. The storage capacitor CST includes a first electrode receiving the pixel high power supply voltage ELVDD and a second electrode connected to the first pixel node PN1. The boost capacitor CBOOST includes a first electrode receiving the data write gate signal GW[n] and a second electrode connected to the first pixel node PN1.

[0089] In this embodiment, the signal output from the gate signal masking circuit of the gate emission driver 300 may be the data initialization gate signal GI[n] (for ease of description, in the following embodiments, it may be referred to as the first gate signal GI[n]). Alternatively, the signal output from the gate signal masking circuit of the gate emission driver 300 may be the compensation gate signal GC[n].

[0090] In an embodiment, when the image displayed on the display panel 100 is a static image or the display panel 100 operates in the always-on mode, the driving frequency of the display panel 100 may be reduced to reduce power consumption. In the case where all of the switching elements of the pixels of the display panel 100 are polysilicon thin film transistors, in the low-frequency driving mode, flicker may occur due to the leakage current of the pixel switching elements. Therefore, oxide semiconductor thin film transistors may be used to design some of the pixel switching elements. In an embodiment, for example, the third pixel switching element PT3 and the fourth pixel switching element PT4 may be oxide semiconductor thin film transistors, and the first pixel switching element PT1, the second pixel switching element PT2, the fifth pixel switching element PT5, the sixth pixel switching element PT6, the seventh pixel switching element PT7, and the eighth pixel switching element PT8 may be polysilicon thin film transistors.

[0091] Figure 4 is a conceptual diagram showing Figure 1 the gate emission driver 300. Figure 5 is a conceptual diagram showing the driving frequency applied to Figure 1 a part of the display panel 100 according to Figure 1 the enable signal EN of the gate emission driver 300.

[0092] Referring to Figures 1 to 5 , an embodiment of the gate emission driver 300 may include a carry generator ST that generates a carry signal based on a previous carry signal and a gate signal masking circuit MC connected to the carry generator ST.

[0093] The gate signal masking circuit MC may output or not output a gate pulse based on the enable signal EN. In an embodiment, for example, the gate signal masking circuit MC may control the output of the gate signal based on the enable signal EN, the signal of the first input node of the first driver, the signal of the second input node of the second driver, the signal of the third input node of the second driver, and the output signal of the third driver.

[0094] In an embodiment, for example, when the enable signal EN has a high level H, the gate signal masking circuit MC may output a gate pulse.

[0095] In an embodiment, for example, when the enable signal EN has a low level L, the gate signal masking circuit MC may not output a gate pulse.

[0096] As Figure 5 shown, an embodiment of the gate emission driver 300 may output a gate pulse at a high frequency (e.g., 120 Hz) for a part of the display panel 100 that requires high-frequency driving according to the enable signal EN, and may output a gate pulse at a low frequency (e.g., 1 Hz) for a part of the display panel 100 that requires low-frequency driving.

[0097] The gate signal masking circuit MC can mask the output of the gate pulse to output the gate pulse at a low frequency (e.g., 1 Hz). The carry generator ST transmits the carry signal to the next stage regardless of the operation of the gate signal masking circuit MC for masking the output of the gate pulse, so that the gate emission driver 300 can support multiple frequency divisions of the driving frequency.

[0098] Figure 6 is a timing diagram showing the input signals applied to the Figure 2 pixels during the data writing period. Figure 7 is a timing diagram showing the input signals applied to the Figure 2 pixels during the holding period.

[0099] Referring to Figures 1 to 7 , in the low-frequency driving mode, the driving timing of the display panel 100 includes a data writing period in which the data voltage is written to the pixels and the pixels emit light, and a holding period in which the data voltage is not written to the pixels and the pixels emit light.

[0100] The data writing period may include at least one data writing frame. The data writing period may include a data writing frame and a self-scanning frame. On the contrary, the holding period may not include a data writing frame, but only include a self-scanning frame.

[0101] In Figure 6 the first frame P1 as the data writing frame, the data initialization gate signal GI, the compensation gate signal GC, and the data writing gate signal GW may have valid pulses. Figure 6 The second frame P2 to the fourth frame P4 of

[0102] For example, as shown in the first frame P1 of Figure 6 , the data initialization gate signal GI may output a single pulse in this frame. For example, as shown in the first frame P1 of Figure 6 , the compensation gate signal GC may output two pulses in this frame.

[0103] On the contrary, in Figure 7 the first frame P1 as the self-scanning frame, the data initialization gate signal GI, the compensation gate signal GC, and the data writing gate signal GW may not have any valid pulses. Figure 7 The second frame P2 to the fourth frame P4 of

[0104] Figure 8 is a block diagram showing an example of the Figure 1 gate emission driver 300.

[0105] Referring to Figures 1 to 8, some drivers of the gate emission driver 300 may be disposed at a first side of the display panel 100, and some other drivers of the gate emission driver 300 may be disposed at a second side of the display panel 100.

[0106] For example, an emission driver EMD that generates an emission signal EM, a compensation gate driver GCD that generates a compensation gate signal GC, and a first data write gate driver GWD1 that generates a data write gate signal GW may be disposed at the first side of the display panel 100.

[0107] In an embodiment, for example, a second data write gate driver GWD2 that generates a data write gate signal GW, a data initialization gate driver GID that generates a data initialization gate signal GI, and a light emitting element initialization gate driver GBD that generates a light emitting element initialization gate signal GB may be disposed at the second side of the display panel 100. For example, as Figure 8 shown, an active area including pixels of the display panel 100 may be disposed between the first side and the second side.

[0108] In this embodiment, the data initialization gate driver GID may receive the emission signal EM from the emission driver EMD, may receive the light emitting element initialization gate signal GB and an inverted signal GB_B of the light emitting element initialization gate signal GB from the light emitting element initialization gate driver GBD, and may output the data initialization gate signal GI to support multiple frequency divisions of the driving frequency.

[0109] In this embodiment, the light emitting element initialization gate driver GBD may be disposed adjacent to the data initialization gate driver GID such that the data initialization gate driver GID may directly receive the light emitting element initialization gate signal GB and the inverted signal GB_B of the light emitting element initialization gate signal GB from the light emitting element initialization gate driver GBD.

[0110] In this embodiment, the emission driver EMD may be disposed at a relative side of the data initialization gate driver GID with respect to the display panel 100 such that the data initialization gate driver GID may not directly receive the emission signal EM from the emission driver EMD. In this embodiment, the data initialization gate driver GID may receive the emission signal EM from the outermost pixel of the display panel 100 in a first direction D1.

[0111] Figure 9 is a circuit diagram of a first driver GICC, a second driver GBD, and a gate signal masking circuit GIMC of the gate emission driver 300 shown Figure 1 .

[0112] Referring to Figures 1 to 9, An implementation of the first driver GICC may be a carry generator that generates a carry signal CR_GI[n] for the data initialization gate signal GI. The first driver GICC may be a complementary metal oxide semiconductor (CMOS) driver. The first driver GICC may generate the carry signal CR_GI[n] based on the previous carry signal CR_GI[n-1].

[0113] The first driver GICC may include a first first gate switch element GIT1, a second first gate switch element GIT2, a third first gate switch element GIT3, a fourth first gate switch element GIT4, a fifth first gate switch element GIT5, and a sixth first gate switch element GIT6.

[0114] The first first gate switch element GIT1 may include a control electrode that receives one of the first clock signal CK and the second clock signal CKB, a first electrode that receives the previous carry signal CR_GI[n-1], and a second electrode that is connected to the first first gate node NGI1. The second first gate switch element GIT2 may include a control electrode that receives the other of the first clock signal CK and the second clock signal CKB, a first electrode that receives the previous carry signal CR_GI[n-1], and a second electrode that is connected to the first first gate node NGI1. The third first gate switch element GIT3 may include a control electrode that is connected to the first first gate node NGI1, a first electrode that receives the first power supply voltage VGH, and a second electrode that is connected to the second first gate node NGI2. The fourth first gate switch element GIT4 may include a control electrode that is connected to the first first gate node NGI1, a first electrode that is connected to the second first gate node NGI2, and a second electrode that receives the second power supply voltage VGL. The fifth first gate switch element GIT5 may include a control electrode that is connected to the second first gate node NGI2, a first electrode that receives the first power supply voltage VGH, and a second electrode that is connected to the carry output node NGIO. The sixth first gate switch element GIT6 may include a control electrode that is connected to the second first gate node NGI2, a first electrode that is connected to the carry output node NGIO, and a second electrode that receives the second power supply voltage VGL.

[0115] In this implementation, the first power supply voltage VGH and the second power supply voltage VGL may be the power supply voltages of the gate emission driver 300. In an implementation, for example, the first power supply voltage VGH may be greater than the second power supply voltage VGL.

[0116] When the first clock signal CK is applied to the control electrode of the first first gate switch element GIT1, the second clock signal CKB may be applied to the control electrode of the second first gate switch element GIT2. Conversely, when the second clock signal CKB is applied to the control electrode of the first first gate switch element GIT1, the first clock signal CK may be applied to the control electrode of the second first gate switch element GIT2.

[0117] The first driver GICC may further include a first gate capacitor GIC having a first electrode connected to the first first gate node NGI1 and a second electrode receiving the second power supply voltage VGL.

[0118] The first first gate switch element GIT1, the third first gate switch element GIT3, and the fifth first gate switch element GIT5 may be P-type transistors. The second first gate switch element GIT2, the fourth first gate switch element GIT4, and the sixth first gate switch element GIT6 may be N-type transistors.

[0119] The first first gate switch element GIT1 and the second first gate switch element GIT2 may be synchronized with the first clock signal CK and the second clock signal CKB, and may send the previous carry signal CR_GI[n - 1] to the first first gate node NGI1.

[0120] The third first gate switch element GIT3 and the fourth first gate switch element GIT4 may invert the signal GI_A[n] of the first first gate node NGI1 and may send the inverted signal to the second first gate node NGI2.

[0121] The fifth first gate switch element GIT5 and the sixth first gate switch element GIT6 may invert the signal GI_B[n] of the second first gate node NGI2 and may output the inverted signal to the carry output node NGIO.

[0122] The carry output node NGIO may output a carry signal CR_GI[n].

[0123] The second driver GBD may be a light-emitting element initialization gate driver that generates a light-emitting element initialization gate signal GB. The second driver GBD may be a CMOS driver. The second driver GBD may generate a light-emitting element initialization gate signal GB[n] based on the previous light-emitting element initialization gate signal GB[n - 1].

[0124] The second driver GBD may include a first second gate switch element GBT1, a second second gate switch element GBT2, a third second gate switch element GBT3, a fourth second gate switch element GBT4, a fifth second gate switch element GBT5, and a sixth second gate switch element GBT6.

[0125] The first and second gate switching elements GBT1 may include a control electrode that receives one of the first clock signal CK and the second clock signal CKB, a first electrode that receives the previous light-emitting element initialization gate signal GB[n-1], and a second electrode connected to the first and second gate nodes NGB1. The second and second gate switching elements GBT2 may include a control electrode that receives the other of the first clock signal CK and the second clock signal CKB, a first electrode that receives the previous light-emitting element initialization gate signal GB[n-1], and a second electrode connected to the first and second gate nodes NGB1. The third and second gate switching elements GBT3 may include a control electrode connected to the first and second gate nodes NGB1, a first electrode that receives the first power supply voltage VGH, and a second electrode connected to the second and second gate nodes NGB2. The fourth and second gate switching elements GBT4 may include a control electrode connected to the first and second gate nodes NGB1, a first electrode connected to the second and second gate nodes NGB2, and a second electrode that receives the second power supply voltage VGL. The fifth and second gate switching elements GBT5 may include a control electrode connected to the second and second gate nodes NGB2, a first electrode that receives the first power supply voltage VGH, and a second electrode connected to the second gate output node NGBO. The sixth and second gate switching elements GBT6 may include a control electrode connected to the second and second gate nodes NGB2, a first electrode connected to the second gate output node NGBO, and a second electrode that receives the second power supply voltage VGL.

[0126] When the first clock signal CK is applied to the control electrode of the first and second gate switching elements GBT1, the second clock signal CKB may be applied to the control electrode of the second and second gate switching elements GBT2. Conversely, when the second clock signal CKB is applied to the control electrode of the first and second gate switching elements GBT1, the first clock signal CK may be applied to the control electrode of the second and second gate switching elements GBT2.

[0127] The second driver GBD may further include a second gate capacitor GBC including a first electrode connected to the first and second gate nodes NGB1 and a second electrode that receives the second power supply voltage VGL.

[0128] The first and second gate switching elements GBT1, the third and second gate switching elements GBT3, and the fifth and second gate switching elements GBT5 may be P-type transistors. The second and second gate switching elements GBT2, the fourth and second gate switching elements GBT4, and the sixth and second gate switching elements GBT6 may be N-type transistors.

[0129] The first and second gate switching elements GBT1 and the second and second gate switching elements GBT2 can be synchronized with the first clock signal CK and the second clock signal CKB, and can send the previous light-emitting element initialization gate signal GB[n-1] to the first and second gate nodes NGB1.

[0130] The third and second gate switching elements GBT3 and the fourth and second gate switching elements GBT4 can invert the signal GB_A[n] of the first and second gate nodes NGB1, and can send the inverted signal to the second and second gate nodes NGB2.

[0131] The fifth and second gate switching elements GBT5 and the sixth and second gate switching elements GBT6 can invert the signal GB_B[n] of the second and second gate nodes NGB2, and can output the inverted signal to the second gate output node NGBO.

[0132] The second gate output node NGBO can output the light-emitting element initialization gate signal GB[n].

[0133] The third driver EMD can be a transmission driver for generating a transmission signal EM. The third driver EMD can be a CMOS driver. The third driver EMD can generate a transmission signal EM[n] based on the previous transmission signal EM[n-1].

[0134] The gate signal masking circuit GIMC can control the output of the first gate signal GI[n] based on the enable signal EN, the signal of the first input node of the first driver GICC (e.g., the signal GI_B[n] of the second and first gate nodes NGI2), the signal of the second input node of the second driver GBD (e.g., the signal GB_B[n] of the second and second gate nodes NGB2), the signal of the third input node of the second driver GBD (e.g., the signal GB[n] of the second gate output node NGBO), and the output signal of the third driver EMD (e.g., the transmission signal EM[n]).

[0135] In an embodiment, for example, the first input node of the first driver GICC can be the second and first gate nodes NGI2. In an embodiment, for example, the second input node of the second driver GBD can be the second and second gate nodes NGB2. In an embodiment, for example, the third input node of the second driver GBD can be the second gate output node NGBO.

[0136] The gate signal masking circuit GIMC can include a first switching element S1, a second switching element S2, a third switching element S3, a fourth switching element S4, a fifth switching element S5, and a floating switching element SS.

[0137] The first switching element S1 may include a control electrode connected to the masking control node S_node, a first electrode connected to the first input node NGI2, and a second electrode connected to the output control node NO. The second switching element S2 may include a control electrode connected to the second input node NGB2, a first electrode receiving the first power supply voltage VGH, and a second electrode connected to the first intermediate node NI1. The third switching element S3 may include a control electrode receiving the enable signal EN, a first electrode connected to the first intermediate node NI1, and a second electrode connected to the second intermediate node NI2. The fourth switching element S4 may include a control electrode receiving the enable signal EN, a first electrode connected to the second intermediate node NI2, and a second electrode connected to the third intermediate node NI3. The fifth switching element S5 may include a control electrode connected to the third input node NGBO, a first electrode connected to the third intermediate node NI3, and a second electrode receiving the second power supply voltage VGL. The floating switching element SS may include a control electrode receiving the floating control signal, a first electrode connected to the masking control node S_node, and a second electrode connected to the second intermediate node NI2. In this embodiment, the floating control signal may be the transmission signal EM[n].

[0138] In this embodiment, the second switching element S2 and the third switching element S3 are P-type transistors, and the fourth switching element S4 and the fifth switching element S5 are N-type transistors.

[0139] In an embodiment, for example, the first switching element S1 may be a P-type transistor. In an embodiment, for example, the floating switching element SS may be a P-type transistor.

[0140] The gate signal masking circuit GIMC may further include a sixth switching element S6 and a seventh switching element S7. The sixth switching element S6 includes a control electrode connected to the output control node NO, a first electrode receiving the first power supply voltage VGH, and a second electrode connected to the gate output node for outputting the first gate signal GI[n]. The seventh switching element S7 includes a control electrode connected to the first input node NGI2, a first electrode connected to the gate output node, and a second electrode receiving the second power supply voltage VGL.

[0141] The gate signal masking circuit GIMC may further include an eighth switching element S8. The eighth switching element S8 includes a control electrode connected to the masking control node S_node, a first electrode receiving the first power supply voltage VGH, and a second electrode connected to the output control node NO.

[0142] In this embodiment, the sixth switching element S6 may be a P-type transistor, the seventh switching element S7 may be an N-type transistor, and the eighth switching element S8 may be an N-type transistor.

[0143] The gate signal masking circuit GIMC may further include a first capacitor C1 including a first electrode connected to a masking control node S_node and a second electrode receiving a second power supply voltage VGL.

[0144] The signal GB_B[n] of the second input node NGB2 may be an inverted signal of the signal GB[n] of the third input node NGBO.

[0145] When the signal of the masking control node S_node has a low level, the first switching element S1 is turned on, so that the first input node NGI2 is connected to the output control node NO. When the signal of the masking control node S_node has a low level, the sixth switching element S6 and the seventh switching element S7 invert the signal GI_B[n] of the first input node NGI2, and output the inverted signal as the first gate signal GI[n].

[0146] When the signal of the masking control node S_node has a low level, the sixth switching element S6 and the seventh switching element S7 operate similarly to the fifth first gate switching element GIT5 and the sixth first gate switching element GIT6, so that the first gate signal GI[n] having the same waveform as the carry signal CR_GI[n] is output to the pixel.

[0147] On the contrary, when the signal of the masking control node S_node has a high level, the first switching element S1 is turned off. In addition, when the signal of the masking control node S_node has a high level, the eighth switching element S8 is turned on, so that the first power supply voltage VGH having a high level is applied to the output control node NO.

[0148] When the first power supply voltage VGH having a high level is applied to the output control node NO, the sixth switching element S6 is turned off, so that the first gate signal GI[n] having a high level is not generated.

[0149] Figure 10 is a table showing the state of the signal of the masking control node S_node of the input signal of the gate signal masking circuit GIMC according to Figure 9 of the gate signal masking circuit GIMC. Figure 11 is a table showing the state of the signal of the masking control node S_node of the input signal of the gate signal masking circuit according to Figure 9 of the gate signal masking circuit Figure 9 of the switching elements S2, S3, S4, S5 and SS of the gate signal masking circuit GIMC and Figure 9 of the operation of the gate signal masking circuit GIMC.

[0150] As Figure 10As shown, the state of the signal of the masking control node S_node that can represent the input signals EN, GB_B[n], GB[n], and EM[n] of the gate signal masking circuit GIMC can be shown in the table.

[0151] Referring to Figure 10 , when the enable signal EN has a high level, the signal GB_B[n] of the second input node has a high level, and the floating control signal EM[n] has a low level, the signal of the masking control node S_node can maintain the previous state. This situation can be defined as the first case CN1.

[0152] When the enable signal EN has a high level, the signal GB_B[n] of the second input node has a low level, and the floating control signal EM[n] has a low level, the signal of the masking control node S_node can have a low level. This situation can be defined as the second case CN2.

[0153] When the enable signal EN has a low level, the signal GB_B[n] of the second input node has a high level, and the floating control signal EM[n] has a low level, the signal of the masking control node S_node can maintain the previous state. This situation can be defined as the third case CN3.

[0154] When the enable signal EN has a low level, the signal GB_B[n] of the second input node has a low level, and the floating control signal EM[n] has a low level, the signal of the masking control node S_node can have a high level. This situation can be defined as the fourth case CN4.

[0155] When the floating control signal EM[n] has a high level, the floating switch element SS is turned off, so that the signal of the masking control node S_node can maintain the previous state regardless of the state of the enable signal EN and the state of the signal GB_B[n] of the second input node. This situation can be defined as the fifth case CN5.

[0156] Referring to Figure 11 , in the first case CN1, the enable signal EN has a high level, so that the third switch element S3 can be turned off, and the fourth switch element S4 can be turned on. In the first case CN1, the signal GB_B[n] of the second input node has a high level, and the signal GB[n] of the third input node has a low level, so that the second switch element S2 and the fifth switch element S5 can be turned off. As described above, in the first case CN1, among the second switch element S2 to the fifth switch element S5, only the fourth switch element S4 is turned on, so that the masking control node S_node can have a floating state and can maintain the previous state.

[0157] In the second case CN2, the enable signal EN has a high level, such that the third switching element S3 can be turned off and the fourth switching element S4 can be turned on. In the second case CN2, the signal GB_B[n] at the second input node has a low level and the signal GB[n] at the third input node has a high level, such that the second switching element S2 and the fifth switching element S5 can be turned on. In the second case CN2, the floating control signal EM[n] has a low level, such that the floating switching element SS can be turned on. As described above, in the second case CN2, the second switching element S2, the fourth switching element S4, and the fifth switching element S5 among the second switching element S2 to the fifth switching element S5 are turned on, such that the second power supply voltage VGL having a low level can be applied to the mask control node S_node through the fifth switching element S5, the fourth switching element S4, and the floating switching element SS. In the second case CN2, the second power supply voltage VGL having a low level is applied to the mask control node S_node, and the first switching element S1 is turned on, such that the gate signal masking circuit GIMC can normally output the first gate signal GI[n].

[0158] In the third case CN3, the enable signal EN has a low level, such that the third switching element S3 can be turned on and the fourth switching element S4 can be turned off. In the third case CN3, the signal GB_B[n] at the second input node has a high level and the signal GB[n] at the third input node has a low level, such that the second switching element S2 and the fifth switching element S5 can be turned off. As described above, in the third case CN3, among the second switching element S2 to the fifth switching element S5, only the third switching element S3 is turned on, such that the mask control node S_node can have a floating state and can maintain the previous state.

[0159] In the fourth case CN4, the enable signal EN has a low level, enabling the third switching element S3 to conduct and the fourth switching element S4 to turn off. In the fourth case CN4, the signal GB_B[n] at the second input node has a low level, and the signal GB[n] at the third input node has a high level, enabling the second switching element S2 and the fifth switching element S5 to conduct. In the fourth case CN4, the floating control signal EM[n] has a low level, enabling the floating switching element SS to conduct. As described above, in the fourth case CN4, among the second switching element S2 to the fifth switching element S5, the second switching element S2, the third switching element S3, and the fifth switching element S5 conduct, enabling the first power supply voltage VGH with a high level to be applied to the mask control node S_node through the second switching element S2, the third switching element S3, and the floating switching element SS. In the fourth case CN4, the first power supply voltage VGH with a high level is applied to the mask control node S_node, and the first switching element S1 turns off, enabling the gate signal masking circuit GIMC to block the output of the first gate signal GI[n].

[0160] In the fifth case CN5, the floating control signal EM[n] has a high level, enabling the floating switching element SS to turn off. In the fifth case CN5, when the floating switching element SS turns off, the signal at the second intermediate node NI2 determined by the conduction and turn-off of the second switching element S2 to the fifth switching element S5 is not sent to the mask control node S_node. Therefore, in the fifth case CN5, the mask control node S_node can have a floating state regardless of the state of the enable signal EN, the state of the signal GB_B[n] at the second input node, and the state of the signal GB[n] at the third input node, and can maintain the previous state.

[0161] Figure 12 is a timing diagram showing the output of the first gate signal GI when the low pulse of the enable signal EN is at the first time position. Figure 13 is a timing diagram showing the output of the first gate signal GI when the low pulse of the enable signal EN is at the second time position. Figure 14 is a timing diagram showing the output of the first gate signal GI when the low pulse of the enable signal EN is at the third time position.

[0162] Refer to Figure 12 , at the time point immediately before the rising edge TP1 where the floating control signal EM[n] rises from a low level to a high level, the enable signal EN has a high level, the signal GB_B[n] at the second input node has a low level, and the floating control signal EM[n] has a low level. At Figure 12 the time point immediately before the rising edge TP1 of the floating control signal EM[n], the gate signal masking circuit GIMC can be inFigure 10 In the second case CN2, the signal of the masking control node S_node may have a low level.

[0163] exist Figure 12 After the rising edge TP1 of the floating control signal EM[n], the floating control signal EM[n] has a high level, and the gate signal masking circuit GIMC may be in Figure 10 In the fifth case CN5.

[0164] Therefore, when the signal of the masking control node S_node is Figure 12 When the first gate signal GI has a low level at a time point immediately before the rising edge TP1 of the floating control signal EM[n], the first gate signal GI may be output normally.

[0165] Reference Figure 13 , at a time point immediately before the rising edge TP1 at which the floating control signal EM[n] rises from a low level to a high level, the enable signal EN has a low level, the signal GB_B[n] of the second input node has a low level, and the floating control signal EM[n] has a low level. Figure 13 At a time point immediately before the rising edge TP1 of the floating control signal EM[n], the gate signal masking circuit GIMC may be in Figure 10 In the fourth case CN4, the signal of the masking control node S_node may have a high level.

[0166] exist Figure 13 After the rising edge TP1 of the floating control signal EM[n], the floating control signal EM[n] has a high level, and the gate signal masking circuit GIMC may be in Figure 10 In the fifth case CN5.

[0167] Therefore, when the signal of the masking control node S_node is Figure 13 When TP1 has a high level at a time point immediately before the rising edge TP1 of the floating control signal EM[n], the output of the first gate signal GI may be blocked.

[0168] Reference Figure 14 , at a time point immediately before the rising edge TP1 at which the floating control signal EM[n] rises from a low level to a high level, the enable signal EN has a high level, the signal GB_B[n] of the second input node has a low level, and the floating control signal EM[n] has a low level. Figure 14 At a time point immediately before the rising edge TP1 of the floating control signal EM[n], the gate signal masking circuit GIMC may be in Figure 10 In the second case CN2, the signal of the masking control node S_node may have a low level.

[0169] After Figure 14 the rising edge TP1 of the floating control signal EM[n], the floating control signal EM[n] has a high level, and the gate signal masking circuit GIMC can be in Figure 10 the fifth case CN5 of

[0170] Therefore, when the signal of the masking control node S_node has a low level at the time point immediately before the rising edge TP1 of the floating control signal EM[n], the first gate signal GI can be normally output. Figure 14

[0171] According to an embodiment, as described herein, the output of the first gate signal GI[n] can be controlled based on the enable signal EN, the signal of the first input node NGI2 of the first driver GICC, the signal of the second input node NGB2 of the second driver GBD, the signal of the third input node NGBO of the second driver GBD, and the output signal of the third driver EMD (e.g., the emission signal EM[n]), so that multiple frequency divisions of the driving frequency can be supported or effectively performed.

[0172] In this embodiment, the power consumption of the display device can be effectively reduced by multiple frequency divisions of the driving frequency. In this embodiment, multiple frequency divisions of the driving frequency of the gate signal (e.g., GC[n]) having two or more pulses can be supported.

[0173] In this embodiment, the circuit of the gate emission driver 300 is disposed at the first side of the display panel 100, and another circuit of the gate emission driver 300 is disposed at the second side of the display panel 100, so that the dead zone of the display device can be reduced.

[0174] Figure 15 is a circuit diagram showing the first driver GICC, the second driver GBD, and the gate signal masking circuit GIMC of the gate emission driver 300 according to an embodiment of the present invention.

[0175] Except that the first driver does not include the second first gate switch element and the second driver does not include the second second gate switch element, the gate signal masking circuit, the gate emission driver, and the display device according to the embodiment shown in Figure 15 are substantially the same as the gate signal masking circuit, the gate emission driver, and the display device according to the embodiment described above with reference to Figures 1 to 14 Therefore, the same reference numerals will be used to refer to the parts that are the same or similar to the parts described above with reference to Figures 1 to 14 and any repeated detailed descriptions thereof will be omitted or simplified.

[0176] Referring to Figures 1 to 8 and​Figures 10 to 15 , in an embodiment, the first driver GICC may be a carry generator that generates a carry signal CR_GI[n] for initializing a gate signal GI of data. The first driver GICC may be a CMOS driver. The first driver GICC may generate the carry signal CR_GI[n] based on a previous carry signal CR_GI[n-1].

[0177] The first driver GICC may include a first first gate switch element GIT1, a third first gate switch element GIT3, a fourth first gate switch element GIT4, a fifth first gate switch element GIT5, and a sixth first gate switch element GIT6.

[0178] The first first gate switch element GIT1 may include a control electrode that receives one of a first clock signal CK and a second clock signal CKB, a first electrode that receives the previous carry signal CR_GI[n-1], and a second electrode that is connected to a first first gate node NGI1. The third first gate switch element GIT3 may include a control electrode that is connected to the first first gate node NGI1, a first electrode that receives a first power supply voltage VGH, and a second electrode that is connected to a second first gate node NGI2. The fourth first gate switch element GIT4 may include a control electrode that is connected to the first first gate node NGI1, a first electrode that is connected to the second first gate node NGI2, and a second electrode that receives a second power supply voltage VGL. The fifth first gate switch element GIT5 may include a control electrode that is connected to the second first gate node NGI2, a first electrode that receives a first power supply voltage VGH, and a second electrode that is connected to a carry output node NGIO. The sixth first gate switch element GIT6 may include a control electrode that is connected to the second first gate node NGI2, a first electrode that is connected to the carry output node NGIO, and a second electrode that receives a second power supply voltage VGL.

[0179] The first driver GICC may further include a first gate capacitor GIC having a first electrode connected to the first first gate node NGI1 and a second electrode receiving a second power supply voltage VGL.

[0180] The first first gate switch element GIT1, the third first gate switch element GIT3, and the fifth first gate switch element GIT5 may be P-type transistors. The fourth first gate switch element GIT4 and the sixth first gate switch element GIT6 may be N-type transistors.

[0181] The first first gate switch element GIT1 may be synchronized with one of the first clock signal CK and the second clock signal CKB, and may send the previous carry signal CR_GI[n-1] to the first first gate node NGI1.

[0182] The second driver GBD can be a light-emitting element initialization gate driver that generates a gate signal GB for the light-emitting element. The second driver GBD can be a CMOS driver. The second driver GBD can generate a light-emitting element initialization gate signal GB[n] based on a previous light-emitting element initialization gate signal GB[n-1].

[0183] The second driver GBD can include a first second gate switch element GBT1, a third second gate switch element GBT3, a fourth second gate switch element GBT4, a fifth second gate switch element GBT5, and a sixth second gate switch element GBT6.

[0184] The first second gate switch element GBT1 can include a control electrode that receives one of a first clock signal CK and a second clock signal CKB, a first electrode that receives a previous light-emitting element initialization gate signal GB[n-1], and a second electrode connected to a first second gate node NGB1. The third second gate switch element GBT3 can include a control electrode connected to the first second gate node NGB1, a first electrode that receives a first power supply voltage VGH, and a second electrode connected to a second second gate node NGB2. The fourth second gate switch element GBT4 can include a control electrode connected to the first second gate node NGB1, a first electrode connected to the second second gate node NGB2, and a second electrode that receives a second power supply voltage VGL. The fifth second gate switch element GBT5 can include a control electrode connected to the second second gate node NGB2, a first electrode that receives a first power supply voltage VGH, and a second electrode connected to a second gate output node NGBO. The sixth second gate switch element GBT6 can include a control electrode connected to the second second gate node NGB2, a first electrode connected to the second gate output node NGBO, and a second electrode that receives a second power supply voltage VGL.

[0185] The second driver GBD can further include a second gate capacitor GBC having a first electrode connected to the first second gate node NGB1 and a second electrode that receives a second power supply voltage VGL.

[0186] The first second gate switch element GBT1, the third second gate switch element GBT3, and the fifth second gate switch element GBT5 can be P-type transistors. The fourth second gate switch element GBT4 and the sixth second gate switch element GBT6 can be N-type transistors.

[0187] The first second gate switch element GBT1 can be synchronized with one of the first clock signal CK and the second clock signal CKB, and can send a previous light-emitting element initialization gate signal GB[n-1] to the first second gate node NGB1.

[0188] The gate signal masking circuit GIMC can control the output of the first gate signal GI[n] based on the enable signal EN, the signal of the first input node of the first driver GICC (e.g., the signal GI_B[n] of the second first gate node NGI2), the signal of the second input node of the second driver GBD (e.g., the signal GB_B[n] of the second second gate node NGB2), the signal of the third input node of the second driver GBD (e.g., the signal GB[n] of the second gate output node NGBO), and the output signal of the third driver EMD (e.g., the emission signal EM[n]).

[0189] In an embodiment, for example, the first input node of the first driver GICC may be the second first gate node NGI2. In an embodiment, for example, the second input node of the second driver GBD may be the second second gate node NGB2, and the third input node of the second driver GBD may be the second gate output node NGBO.

[0190] According to an embodiment, as described above, the output of the first gate signal GI[n] can be controlled based on the enable signal EN, the signal of the first input node NGI2 of the first driver GICC, the signal of the second input node NGB2 of the second driver GBD, the signal of the third input node NGBO of the second driver GBD, and the output signal of the third driver EMD (e.g., the emission signal EM[n]), thereby supporting multiple frequency divisions of the driving frequency.

[0191] In this embodiment, the power consumption of the display device can be effectively reduced through multiple frequency divisions of the driving frequency. In this embodiment, multiple frequency divisions of the driving frequency of the gate signal (e.g., GC[n]) having two or more pulses can be supported or effectively performed.

[0192] In this embodiment, the circuit of the gate emission driver 300 is disposed at the first side of the display panel 100, and another circuit of the gate emission driver 300 is disposed at the second side of the display panel 100, thereby reducing the dead zone of the display device.

[0193] Figure 16 is a block diagram showing an electronic device according to an embodiment of the present invention. Figure 17 is a diagram showing an example in which Figure 16 the electronic device is implemented as a smart phone.

[0194] Referring to Figure 16 and Figure 17 , an embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may beFigure 1 A display device. In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc.

[0195] In an embodiment, as Figure 17 shown, the electronic device 1000 may be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. In an embodiment, for example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart board, a smart watch, a tablet personal computer (PC), a car navigation system, a computer monitor, a notebook computer, a head-mounted display (HMD) device, or the like.

[0196] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), or the like. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0197] The processor 1010 may output the input image data IMG and the input control signal CONT to Figure 1 the driving controller 200.

[0198] The memory device 1020 may store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, or the like, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, or the like.

[0199] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, or the like. The I / O device 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touchpad, a touch screen, or the like, and output devices such as a printer, a speaker, or the like. In some embodiments, the display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication link.

[0200] According to embodiments of a gate signal masking circuit, a gate emission driver, and a display device, power consumption of the display device may be reduced, and a dead zone of the display device may be reduced.

[0201] The present invention should not be construed as limited to the embodiments described herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0202] Although the present invention has been specifically shown and described with reference to embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A gate signal masking circuit, comprising: A first switching element, the first switching element including a control electrode connected to a masking control node, a first electrode connected to a first input node, and a second electrode connected to an output control node; A second switching element, the second switching element including a control electrode connected to a second input node, a first electrode receiving a first power supply voltage, and a second electrode connected to a first intermediate node; A third switching element, the third switching element including a control electrode receiving an enable signal, a first electrode connected to the first intermediate node, and a second electrode connected to a second intermediate node; A fourth switching element, the fourth switching element including a control electrode receiving the enable signal, a first electrode connected to the second intermediate node, and a second electrode connected to a third intermediate node; A fifth switching element, the fifth switching element including a control electrode connected to a third input node, a first electrode connected to the third intermediate node, and a second electrode receiving a second power supply voltage; And A floating switching element, the floating switching element including a control electrode receiving a floating control signal, a first electrode connected to the masking control node, and a second electrode connected to the second intermediate node, Wherein, the second switching element and the third switching element are P-type transistors, and Wherein, the fourth switching element and the fifth switching element are N-type transistors.

2. The gate signal masking circuit according to claim 1, further comprising: A sixth switching element, the sixth switching element including a control electrode connected to the output control node, a first electrode receiving the first power supply voltage, and a second electrode connected to a gate output node; And A seventh switching element, the seventh switching element including a control electrode connected to the first input node, a first electrode connected to the gate output node, and a second electrode receiving the second power supply voltage.

3. The gate signal masking circuit according to claim 2, further comprising: An eighth switching element, the eighth switching element including a control electrode connected to the masking control node, a first electrode receiving the first power supply voltage, and a second electrode connected to the output control node.

4. The gate signal masking circuit according to claim 2, further comprising: A first capacitor, the first capacitor including a first electrode connected to the masking control node and a second electrode receiving the second power supply voltage.

5. The gate signal masking circuit according to claim 1, wherein, The floating control signal is a transmit signal.

6. The gate signal masking circuit according to claim 1, wherein, When the floating control signal has a high level, the signal of the masking control node maintains the previous state.

7. The gate signal masking circuit according to claim 1, wherein The signal of the third input node is the inverted signal of the signal of the second input node.

8. The gate signal masking circuit according to claim 1, wherein, When the enable signal has a high level, the signal of the second input node has a high level and the floating control signal has a low level, the signal of the masking control node maintains the previous state.

9. The gate signal masking circuit according to claim 1, wherein, When the enable signal has a high level, the signal of the second input node has a low level and the floating control signal has a low level, the signal of the masking control node has a low level.

10. The gate signal masking circuit according to claim 1, wherein, When the enable signal has a low level, the signal of the second input node has a high level, and the floating control signal has a low level, the signal of the mask control node remains in the previous state.

11. The gate signal masking circuit according to claim 1, wherein, When the enable signal has a low level, the signal of the second input node has a low level, and the floating control signal has a low level, the signal of the mask control node has a high level.

12. A gate emission driver, comprising: A first driver that generates a carry signal of the first gate signal based on a previous carry signal of the first gate signal; A second driver that generates a second gate signal based on a previous second gate signal; A third driver that generates an emission signal based on a previous emission signal; And A gate signal masking circuit that controls the output of the first gate signal based on an enable signal, a signal of a first input node of the first driver connected to a gate node of the first driver, a signal of a second input node of the second driver connected to a gate node of the second driver, a signal of a third input node of the second driver connected to an output node of the second driver, and the emission signal.

13. The gate emission driver according to claim 12, wherein, The gate signal masking circuit includes: A first switching element that includes a control electrode connected to a mask control node, a first electrode connected to the first input node, and a second electrode connected to an output control node; A second switching element that includes a control electrode connected to the second input node, a first electrode receiving a first power supply voltage, and a second electrode connected to a first intermediate node; A third switching element that includes a control electrode receiving the enable signal, a first electrode connected to the first intermediate node, and a second electrode connected to a second intermediate node; A fourth switching element that includes a control electrode receiving the enable signal, a first electrode connected to the second intermediate node, and a second electrode connected to a third intermediate node; A fifth switching element that includes a control electrode connected to the third input node, a first electrode connected to the third intermediate node, and a second electrode receiving a second power supply voltage; and A floating switching element that includes a control electrode receiving the emission signal, a first electrode connected to the mask control node, and a second electrode connected to the second intermediate node, wherein the second switching element and the third switching element are P-type transistors, and wherein the fourth switching element and the fifth switching element are N-type transistors.

14. The gate emission driver according to claim 13, wherein The gate signal masking circuit further includes: A sixth switching element that includes a control electrode connected to the output control node, a first electrode receiving the first power supply voltage, and a second electrode connected to a gate output node; A seventh switching element, the seventh switching element including a control electrode connected to the first input node, a first electrode connected to the gate output node, and a second electrode receiving the second power supply voltage; and An eighth switching element, the eighth switching element including a control electrode connected to the masking control node, a first electrode receiving the first power supply voltage, and a second electrode connected to the output control node.

15. The gate emission driver according to claim 13, wherein, The first driver includes: A first first-gate switching element, the first first-gate switching element including a control electrode receiving one of a first clock signal and a second clock signal, a first electrode receiving the previous carry signal, and a second electrode connected to a first first-gate node; A second first-gate switching element, the second first-gate switching element including a control electrode receiving the other of the first clock signal and the second clock signal, a first electrode receiving the previous carry signal, and a second electrode connected to the first first-gate node; A third first-gate switching element, the third first-gate switching element including a control electrode connected to the first first-gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to a second first-gate node; A fourth first-gate switching element, the fourth first-gate switching element including a control electrode connected to the first first-gate node, a first electrode connected to the second first-gate node, and a second electrode receiving the second power supply voltage; A fifth first-gate switching element, the fifth first-gate switching element including a control electrode connected to the second first-gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to a carry output node; and A sixth first-gate switching element, the sixth first-gate switching element including a control electrode connected to the second first-gate node, a first electrode connected to the carry output node, and a second electrode receiving the second power supply voltage, wherein the first first-gate switching element, the third first-gate switching element, and the fifth first-gate switching element are P-type transistors, wherein the second first-gate switching element, the fourth first-gate switching element, and the sixth first-gate switching element are N-type transistors, and wherein the gate node connected to the first input node is the second first-gate node.

16. The gate emission driver according to claim 13, wherein, The first driver includes: A first first-gate switching element, the first first-gate switching element including a control electrode receiving one of a first clock signal and a second clock signal, a first electrode receiving the previous carry signal, and a second electrode connected to a first first-gate node; A third first-gate switching element, the third first-gate switching element including a control electrode connected to the first first-gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to a second first-gate node; A fourth first gate switching element, the fourth first gate switching element including a control electrode connected to the first first gate node, a first electrode connected to the second first gate node, and a second electrode receiving the second power supply voltage; A fifth first gate switching element, the fifth first gate switching element including a control electrode connected to the second first gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to the carry output node; and A sixth first gate switching element, the sixth first gate switching element including a control electrode connected to the second first gate node, a first electrode connected to the carry output node, and a second electrode receiving the second power supply voltage, wherein the first first gate switching element, the third first gate switching element, and the fifth first gate switching element are P-type transistors, and wherein the fourth first gate switching element and the sixth first gate switching element are N-type transistors.

17. The gate emission driver according to claim 13, wherein, The second driver includes: A first second gate switching element, the first second gate switching element including a control electrode receiving one of the first clock signal and the second clock signal, a first electrode receiving the previous second gate signal, and a second electrode connected to the first second gate node; A second second gate switching element, the second second gate switching element including a control electrode receiving the other of the first clock signal and the second clock signal, a first electrode receiving the previous second gate signal, and a second electrode connected to the first second gate node; A third second gate switching element, the third second gate switching element including a control electrode connected to the first second gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to the second second gate node; A fourth second gate switching element, the fourth second gate switching element including a control electrode connected to the first second gate node, a first electrode connected to the second second gate node, and a second electrode receiving the second power supply voltage; A fifth second gate switching element, the fifth second gate switching element including a control electrode connected to the second second gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to the second gate output node; and A sixth second gate switching element, the sixth second gate switching element including a control electrode connected to the second second gate node, a first electrode connected to the second gate output node, and a second electrode receiving the second power supply voltage, wherein the first second gate switching element, the third second gate switching element, and the fifth second gate switching element are P-type transistors, wherein the second second gate switching element, the fourth second gate switching element, and the sixth second gate switching element are N-type transistors, wherein the gate node connected to the second input node is the second second gate node, and wherein the output node connected to the third input node is the second gate output node.

18. The gate emission driver according to claim 13, wherein, The second driver includes: First and second gate switching elements, the first and second gate switching elements including a control electrode receiving one of a first clock signal and a second clock signal, a first electrode receiving the previous second gate signal, and a second electrode connected to a first and second gate node; Third and second gate switching elements, the third and second gate switching elements including a control electrode connected to the first and second gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to a second and second gate node; Fourth and second gate switching elements, the fourth and second gate switching elements including a control electrode connected to the first and second gate node, a first electrode connected to the second and second gate node, and a second electrode receiving the second power supply voltage; Fifth and second gate switching elements, the fifth and second gate switching elements including a control electrode connected to the second and second gate node, a first electrode receiving the first power supply voltage, and a second electrode connected to a gate output node; and Sixth and second gate switching elements, the sixth and second gate switching elements including a control electrode connected to the second and second gate node, a first electrode connected to the gate output node, and a second electrode receiving the second power supply voltage, wherein the first and second gate switching elements, the third and second gate switching elements, and the fifth and second gate switching elements are P-type transistors, and wherein the fourth and second gate switching elements and the sixth and second gate switching elements are N-type transistors.

19. A display device, comprising: A display panel, the display panel including pixels; A gate emission driver, the gate emission driver outputting a gate signal and an emission signal to the pixels; And A data driver, the data driver outputting a data voltage to the pixels, wherein the gate emission driver includes: A first driver, the first driver generating a carry signal of the first gate signal based on a previous carry signal of the first gate signal; A second driver, the second driver generating a second gate signal based on a previous second gate signal; A third driver, the third driver generating the emission signal based on a previous emission signal; and A gate signal masking circuit, the gate signal masking circuit controlling the output of the first gate signal based on an enable signal, a signal of a first input node of the first driver connected to a gate node of the first driver, a signal of a second input node of the second driver connected to a gate node of the second driver, a signal of a third input node of the second driver connected to an output node of the second driver, and the emission signal.

20. The display device according to claim 19, wherein, The third driver is disposed at a first side of the display panel, wherein the first driver and the second driver are disposed at a second side of the display panel, and wherein the gate signal masking circuit receives the emission signal from an outermost pixel of the display panel in a first direction.

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