Charge control method, charge control circuit and electronic device

Abstract

The invention discloses a charge control method, a charge control circuit and electronic equipment, the charge control method is applied to charge control of a multi-phase voltage conversion circuit, and the multi-phase voltage conversion circuit comprises a set number of switch sub-circuits. The charge control method comprises the following steps: acquiring power supply characteristic parameters of a pulse reference current and a multi-phase voltage conversion circuit; in response to the rising edge of the pulse reference current, generating a set number of driving control signals by using the set number, the pulse reference current and the power supply characteristic parameters; wherein the first rising edges of the driving control signals are synchronous; performing phase modulation on each driving control signal by using a set number and a preset switching period; and respectively sending each driving control signal after phase modulation to each switch sub-circuit so as to respectively trigger each switch sub-circuit to change the switching state. Through the above mode, the charge control method provided by the invention can give consideration to the faster rise time of the output current, and avoids the occurrence of overshoot.

Description

Technical Field

[0001] This application relates to the field of circuit control technologies, and in particular, to a charge control method, a charge control circuit, and an electronic device. Background Art

[0002] Currently, with the increasing richness of electronic devices, the performance requirements for the driving power supply of electronic devices are becoming increasingly stringent. Especially for a switching constant current source, its high requirements for rise time, fall time, and overshoot are a technical challenge. Most common switching constant current sources mostly use a BUCK converter (step-down converter) or a BOOST converter (step-up converter) as their basic circuit structure. For a BUCK converter and a BOOST converter, to make the rise time of the output current short enough, the duty cycle needs to be as large as possible during the rising stage of the output current to ensure a fast enough rising speed.

[0003] However, when using conventional PI (Proportional Integral) closed-loop control, to make the duty cycle large enough when the rising edge arrives, the required PI parameters will be relatively large. This is beneficial to the optimization of the rise time, but at the same time, it will bring the problem of a large overshoot. Therefore, it is impossible to simultaneously balance the contradiction between the output current rise time and overshoot in the PI closed-loop control loop. Summary of the Invention

[0004] The main technical problem to be solved by this application is to provide a charge control method, a charge control circuit, and an electronic device, which can solve the problem that the charge control method in the related technology cannot simultaneously balance the contradiction between the output current rise time and overshoot in the PI closed-loop control loop.

[0005] To solve the above technical problem, a technical solution adopted by this application is: to provide a charge control method applied to the charge control of a multiphase voltage conversion circuit. The multiphase voltage conversion circuit includes a set number of switch sub-circuits, and the set number is greater than 1. Wherein, the charge control method includes: obtaining a pulse reference current and the power supply characteristic parameters of the multiphase voltage conversion circuit; in response to the rising edge of the pulse reference current, generating a set number of drive control signals by using the set number, the pulse reference current, and the power supply characteristic parameters; wherein, the first rising edges of the drive control signals are synchronized; performing phase modulation on each drive control signal by using the set number and a preset switching period; and respectively sending the phase-modulated drive control signals to each switch sub-circuit to respectively trigger each switch sub-circuit to change its switching state.

[0006] Among them, the power supply characteristic parameters include input voltage, output voltage, output current, equivalent inductance, and a preset adjustment coefficient. The drive control signals include a first control signal and a second control signal. The step of generating a set number of drive control signals in response to the rising edge of the pulse reference current using the pulse reference current and the power supply characteristic parameters includes: in response to the rising edge of each pulse reference current, obtaining a reference turn-on time using the input voltage, output voltage, pulse reference current, set number, equivalent inductance, and preset adjustment coefficient; generating a set number of first control signals using the reference turn-on time; among them, the rising edges of the first control signals are synchronized; generating a second control signal using the difference between the pulse reference current and the output current until the rising edge of the next pulse reference current.

[0007] Among them, the step of phase-adjusting each drive control signal using the set number and the preset switching period includes: adjusting the phase difference between the falling edges of every two adjacent first control signals to the quotient of the preset switching period divided by the set number, and making the sum of the turn-on times of the first control signals equal to the product of the reference turn-on time and the set number.

[0008] Among them, the step of generating a second control signal using the difference between the pulse reference current and the output current includes: in response to the falling edge of each first control signal, delaying for a set duration and generating a second control signal using the difference between the pulse reference current and the output current.

[0009] Among them, the step of obtaining a reference turn-on time using the input voltage, output voltage, pulse reference current, set number, equivalent inductance, and preset adjustment coefficient includes: calculating the reference turn-on time using a preset adjustment function for the input voltage, output voltage, pulse reference current, set number, equivalent inductance, and preset adjustment coefficient; among them, the preset adjustment function is: tj= ; Among them, tj is the reference turn-on time, is the pulse reference current, is the preset adjustment coefficient, n is the set number, is the input voltage, is the output voltage, is the equivalent inductance.

[0010] Among them, the power supply characteristic parameters further include input current. The step of generating a second control signal using the difference between the pulse reference current and the output current includes: performing proportional-integral regulation on the current difference between the pulse reference current and the output current to obtain a target current integral value; performing energy storage integral regulation on the input current to obtain an integral voltage value; obtaining an integral reference value using the difference between the given reference voltage and the integral voltage value; obtaining a second control signal using the target current integral value and the integral reference value.

[0011] Among them, the power supply characteristic parameter includes the output current. The steps of generating a set number of drive control signals by using the pulse reference current and the power supply characteristic parameter include: performing proportional-integral regulation on the current difference between the pulse reference current and the output current to obtain a target current integral value; and obtaining a set number of drive control signals by using the target current integral value.

[0012] Among them, in the step of obtaining a set number of drive control signals by using the target current integral value, it further includes: detecting whether the current difference is less than a set current threshold; if the current difference is less than the set current threshold, multiplying the target current integral value by a set multiple; where the set multiple is less than 1 and greater than 0; or multiplying the duty cycle of the drive control signal by the set multiple.

[0013] Among them, the step of phase-adjusting each drive control signal by using the set number and the preset switching period includes: in the switching period of each drive control signal, gradually adjusting the phase difference between every two adjacent drive control signals by using a preset positive correlation function until the phase difference between every two adjacent drive control signals is the quotient of the preset switching period divided by the set number.

[0014] To solve the above technical problems, another technical solution adopted by this application is: to provide a charge control circuit, where the charge control circuit is coupled to a multi-phase voltage conversion circuit; and the charge control circuit performs charge control on the multi-phase voltage conversion circuit by using the charge control method described in any one of the above.

[0015] To solve the above technical problems, another technical solution adopted by this application is: to provide an electronic device, where the electronic device includes a housing and a charge control circuit connected to the housing; and the charge control circuit is the charge control circuit described above.

[0016] The beneficial effect of this application is: Different from the prior art, the charge control method provided by this application obtains the pulse reference current and the power supply characteristic parameter of the multi-phase voltage conversion circuit, and in response to the rising edge of the pulse reference current, generates a set number of drive control signals by using the set number, the pulse reference current and the power supply characteristic parameter, and the first rising edges of the drive control signals are synchronized, so as to be able to trigger each switching sub-circuit to conduct simultaneously by using each drive control signal, effectively improving the rising speed of the output current, significantly reducing the rising time of the output current, and by using the set number and the preset switching period to phase-adjust each drive control signal, so that each switching sub-circuit conducts gradually and staggeredly, it can also effectively avoid the possible overshoot problem, thereby being able to simultaneously take into account a faster rising time of the output current and avoid the occurrence of overshoot. Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings, where: Figure 1 is a schematic flowchart of the first implementation manner of the charge control method of the present application; Figure 2 is a schematic structural diagram of the first implementation manner of the charge control circuit of the present application; Figure 3 is Figure 1 a schematic flowchart of an embodiment of S12 in Figure 4 is a schematic structural diagram of the second implementation manner of the charge control circuit of the present application; Figure 5 is Figure 3 a schematic waveform diagram of each related signal of the charge control method in an embodiment of Figure 6 is Figure 3 a schematic waveform diagram of each related signal of the charge control method under different load states in an embodiment of Figure 7 is Figure 3 a schematic flowchart of an embodiment of S123 in Figure 8 is Figure 6 a logic framework diagram of signal processing in the charge control method of Figure 9 is a schematic flowchart of the second implementation manner of the charge control method of the present application; Figure 10 is Figure 9 a schematic waveform diagram of each related signal of the charge control method in an embodiment of Figure 11 is a schematic structural diagram of an embodiment of the electronic device of the present application. Specific Embodiments

[0018] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0019] The terms "first", "second", and "third" in this application are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of this application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of this application are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include unlisted steps or units, or may optionally further include other steps or units inherent to these processes, methods, products, or devices.

[0020] Reference to "embodiments" herein means that specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0021] The following describes this application in detail with reference to the drawings and embodiments.

[0022] Please refer to Figure 1 and Figure 2 , where Figure 1 is a schematic flowchart of the first embodiment of the charge control method of this application, Figure 2 is a schematic structural diagram of the first embodiment of the charge control circuit of this application. Specifically, the following steps may be included: S11: Obtain the pulse reference current and the power supply characteristic parameters of the polyphase voltage conversion circuit.

[0023] It can be understood that the charge control method in this embodiment is specifically applied to the charge control of the first polyphase voltage conversion circuit 30 as shown in Figure 2 . Among them, the first charge control circuit 20 uses the charge control method described in any item herein to implement charge control on the first polyphase voltage conversion circuit 30.

[0024] Among them, the first polyphase voltage conversion circuit 30 specifically includes a set number n of switch sub - circuits, and the set number n is a positive integer greater than 1.

[0025] It should be noted that the first polyphase voltage conversion circuit 30 can specifically be a polyphase parallel interleaved BUCK circuit, or a polyphase parallel interleaved BOOST circuit, or any other reasonable form of circuit topology, and this embodiment does not limit this.

[0026] In some embodiments, the first charge control circuit 20 can specifically include a control chip, a DSP (Digital Signal Processing) chip, an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a single - chip microcomputer, a field - programmable gate array, a programmable logic device, discrete gates or transistor logic devices, discrete hardware, or any other reasonable circuit unit with signal - processing functions. This application does not limit this.

[0027] In addition, "coupled" in this article refers to including any direct and indirect connection means. Therefore, if it is described in the text that the first circuit is coupled to the second circuit, it means that the first circuit can be directly connected to the second circuit through electrical connection, wireless transmission, optical transmission, or other signal - connection methods, or can be indirectly electrically connected or signal - connected to the second circuit through other circuits or connection means.

[0028] Specifically, the first charge control circuit 20 monitors and obtains various circuit parameters of the first polyphase voltage conversion circuit 30 in real - time, such as one or more of any reasonable power - supply characteristic parameters such as input voltage, output current, output voltage, etc., and sets a pulse reference current according to a preset control program, or receives a pulse reference current obtained through experimental calibration or simulation optimization by the host computer for the specific working conditions and power - supply requirements of the load circuit.

[0029] Among them, the power - supply characteristic parameters can specifically be obtained through any reasonable sampling method such as sensors, sampling resistors, experimental calibration, simulation optimization, or circuit - model estimation. This application does not limit this.

[0030] It should be noted that the host computer generally refers to a computer system with powerful computing and data - processing capabilities. It is responsible for the monitoring, instruction issuing, data acquisition, processing and analysis, and user interaction of the entire control system. As the "brain" of the system, the host computer can process complex algorithms, perform long - term data storage, and provide a graphical interface for users to operate.

[0031] The lower computer refers to the device or controller directly connected to hardware such as sensors and actuators in a control system. It is responsible for executing specific control instructions issued by the upper computer, such as the output of switch signals, the adjustment of analog quantities, and the acquisition of data. The lower computer usually performs simple logic judgments and real-time control tasks.

[0032] In this embodiment, the upper computer can be specifically understood as the central controller of the front-end circuit of the first polyphase voltage conversion circuit 30, and the lower computer is the first polyphase voltage conversion circuit 30.

[0033] S12: In response to the rising edge of the pulse reference current, generate a set number of drive control signals using the set number, pulse reference current, and power supply characteristic parameters.

[0034] It can be understood that the pulse reference signal is the control target of the current output by the first polyphase voltage conversion circuit 30. When the pulse reference signal is obtained, it indicates that the current output needs to be adjusted to be close to the pulse reference signal. And there is a conversion of the pulse reference signal from a low level to a high level, that is, a rising edge, and a conversion from a high level to a low level, that is, a falling edge. When the first rising edge is detected, it corresponds to the arrival of the first wave of the pulse reference signal.

[0035] The first charge control circuit 20 is used to identify and detect the rising edge of the pulse reference signal. For example, this can be achieved by any reasonable means such as a hardware circuit (such as an edge trigger), a software algorithm (for example, writing corresponding code in an embedded system), or a controller counter. The present application does not make any limitations in this regard.

[0036] And when the rising edge of the pulse reference current is detected, use a preset control algorithm or a preset adjustment function to perform arithmetic processing on the set number n, pulse reference current, and power supply characteristic parameters to obtain a set number n of drive control signals.

[0037] Among them, the first rising edges of the drive control signals are synchronized, that is, the drive control signals are started simultaneously, and the first rising edges correspond to the same moment.

[0038] In some embodiments, the drive control signal can specifically be one or more of any reasonable control signals such as a PWM (Pulse Width Modulation) signal or a PFM (Pulse Frequency Modulation) signal. The present application does not make any limitations in this regard.

[0039] S13: Phase-modulate each drive control signal using the set number and a preset switching period.

[0040] Further, based on the total number of switching sub - circuits, i.e., the set number n and the preset switching period, the phase of each drive control signal is adjusted in sequence so that the drive control signals are out of phase with each other.

[0041] It should be noted that the preset switching period is the switching period set according to the physical characteristics of each switching sub - circuit, that is, the set period of each drive control signal, which can be a constant value or adjusted reasonably according to control requirements. This application does not make any limitations in this regard.

[0042] S14: Send each phase - adjusted drive control signal to each switching sub - circuit respectively to trigger each switching sub - circuit to change its switching state.

[0043] Send each phase - adjusted drive control signal to each switching sub - circuit respectively to trigger each switching sub - circuit to change its switching state, so as to adjust the output current and output voltage of the first multi - phase voltage conversion circuit 30.

[0044] In the above - mentioned solution, by synchronizing the first rising edges of the drive control signals to trigger each switching sub - circuit to conduct simultaneously, the rising speed of the output current can be effectively increased, and the rising time of the output current can be significantly reduced. Moreover, by using the set number n and the preset switching period to adjust the phase of each drive control signal so that the switching sub - circuits conduct gradually and alternately, the possible over - shoot problem can also be effectively avoided. Thus, it can take into account both the faster rising time of the output current and avoid the occurrence of over - shoot, thereby improving the power supply stability and reliability of the first multi - phase voltage conversion circuit 30, having better dynamic response performance, and simplifying the control strategy.

[0045] It should be noted that over - shoot refers to the phenomenon that the controlled parameter temporarily exceeds its set value before the control system reaches the steady state. Specifically, when the system is disturbed, the controlled parameter temporarily exceeds the set value under the action of the regulator and then returns to the set value. This phenomenon is called over - shoot.

[0046] Please continue to refer to Figure 3 , Figure 3 is Figure 1 a schematic flowchart of an embodiment of S12 in S121: In response to the rising edge of each pulse reference current, obtain the reference turn - on time by using the input voltage, output voltage, pulse reference current, set number, equivalent inductance, and preset adjustment coefficient.

[0047] Please continue to refer to Figure 4 and Figure 5, wherein, Figure 4 is a schematic structural diagram of a second embodiment of the charge control circuit of the present application, Figure 5 and Figure 3 is a waveform schematic diagram of an embodiment of each relevant signal of the charge control method in

[0048] It can be understood that the charge control method in this embodiment may specifically be that a second charge control circuit (not shown in the figure) implements charge control on a second polyphase voltage conversion circuit 40 as shown in Figure 4 to supply power to the load circuit 101 using the DC power supply DC. Among them, the second polyphase voltage conversion circuit 40 includes a switch sub-circuit 41 and an adjustment output sub-circuit 42. The number of the switch sub-circuit 41 is a set number n (n is a positive integer greater than 1); for ease of understanding, here the set number n is specifically taken as 3 as an example for illustration, that is, the switch sub-circuit 41 includes a first switch tube Q1, a second switch tube Q2, and a third switch tube Q3. The adjustment output sub-circuit 42 includes a first diode D1, a second diode D2, a third diode D3, a first inductor L1, a second inductor L2, a third inductor L3, and an output capacitor C1; the load circuit 101 includes an equivalent diode DF and an equivalent resistor R1.

[0049] Among them, the first end of the first switch tube Q1 is coupled to the first end of the second switch tube Q2 and the first end of the third switch tube Q3, and is used to be coupled to the first end of the DC power supply DC. The second end of the first switch tube Q1 is coupled to the first end of the first inductor L1 and the second end of the first diode D1. The second end of the second switch tube Q2 is coupled to the first end of the second inductor L2 and the second end of the second diode D2. The second end of the third switch tube Q3 is coupled to the first end of the third inductor L3 and the second end of the third diode D3. The second end of the first inductor L1 is coupled to the second end of the second inductor L2, the second end of the third inductor L3, and the first end of the output capacitor C1, and is used to be coupled to the first end of the equivalent diode DF. The first end of the first diode D1 is coupled to the first end of the second diode D2, the first end of the third diode D3, and the second end of the output capacitor C1, and is used to be coupled to the second end of the DC power supply DC and the second end of the equivalent resistor R1. The second end of the equivalent diode DF is coupled to the first end of the equivalent resistor R1. The third ends of the first switch tube Q1, the second switch tube Q2, and the third switch tube Q3 are all coupled to the second charge control circuit.

[0050] In some embodiments, the first switching transistor Q1, the second switching transistor Q2, and the third switching transistor Q3 may specifically be one of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a triode, a thin film transistor, a field effect transistor, or any other reasonable switching transistor. The present application does not limit this.

[0051] In other embodiments, the second multi-phase voltage conversion circuit 40 may specifically also be a multi-phase BOOST circuit, or a multi-phase BUCK circuit including 2, 5, 6, or any other reasonable number of switching sub-circuits 41; and the load circuit 101 may specifically also include one or more of any reasonable circuit elements such as an equivalent series resistance, an equivalent capacitance, an equivalent series diode, etc. The present embodiment does not limit this.

[0052] Among them, the power supply characteristic parameters may specifically include an input voltage, an output voltage, an output current Io, an equivalent inductance, and a preset adjustment coefficient; the drive control signal includes a first control signal and a second control signal.

[0053] Specifically, the second charge control circuit detects each rising edge of the pulse reference current in real time, and in response to each rising edge of the pulse reference current, uses a preset control program or a preset adjustment function to perform arithmetic processing on the input voltage, the output voltage, the pulse reference current, the set number n, the equivalent inductance, and the preset adjustment coefficient to obtain a reference turn-on time.

[0054] S122: Generate a set number of first control signals using the reference turn-on time.

[0055] Furthermore, a set number n of first control signals are sequentially generated according to the currently obtained reference turn-on time, and it is ensured that the rising edges of the first control signals are synchronized, that is, the first rising edges of the first drive control signal G1, the second drive control signal G2, and the third drive control signal G3 correspond to the same moment, so as to trigger the first switching transistor Q1, the second switching transistor Q2, and the third switching transistor Q3 to conduct simultaneously, thereby effectively improving the rising speed of the output current and significantly reducing the rising time of the output current.

[0056] It is understandable that the first drive control signal G1, the second drive control signal G2, and the third drive control signal G3 are respectively the leading edge control signals of the first switching transistor Q1, the second switching transistor Q2, and the third switching transistor Q3, that is, the control signals sent to the first switching transistor Q1, the second switching transistor Q2, and the third switching transistor Q3 first when the leading edge of the pulse reference current arrives, and specifically, it can be a set duty cycle, that is, an open-loop control signal set according to the reference turn-on time. When the rising edge of the pulse reference current arrives, the first control signal synchronized with the rising edge can trigger the first switching transistor Q1, the second switching transistor Q2, and the third switching transistor Q3 to conduct simultaneously. At this time, the multi-phase inductor current, that is, the first inductor current I L1 、the second inductor current I L2 and the third inductor current I L3 will rise simultaneously, and the output current Io will also rise accordingly, so that the rising speed of the output current Io can be effectively increased, and the rising time of the output current Io can be significantly reduced.

[0057] Please continue to refer to Figure 6 , Figure 6 which Figure 3 is a waveform schematic diagram of an embodiment of each relevant signal of the charge control method in different load states.

[0058] It is understandable that in the load switching working condition, that is, when the amplitude of the pulse reference current changes, the same scheme can also be adopted to calculate the pulse width of the open-loop wave generation, that is, the turn-on time of each first control signal, so as to optimize the rising time of the output current Io during load switching, and the multi-phase starts simultaneously to optimize the rising time, and the determination method of the open-loop conduction time is also simpler.

[0059] S123: Generate a second control signal by using the difference between the pulse reference current and the output current until the rising edge of the next pulse reference current.

[0060] After the leading edge control signal, the current difference is obtained by subtracting the output current Io from the pulse reference current, and the current difference is adjusted by proportional integral regulation or any other reasonable arithmetic regulation to obtain the second control signal until the rising edge of the next pulse reference current is detected again, and S121 - S123 are repeatedly executed in a loop.

[0061] It should be noted that the second control signal can be understood as a closed-loop control signal obtained by adjusting the control loop according to the current feedback after the first control signal of the first wave. That is, the first drive control signal G1, the second drive control signal G2, and the third drive control signal G3 are generated by using a current closed-loop control strategy after the first control signals of the first switching transistor Q1, the second switching transistor Q2, and the third switching transistor Q3, that is, the first control signal. And after the falling edge of the pulse reference current and before the arrival of the next rising edge, it is reset, that is, the first control signal and the second control signal are cycled alternately for corresponding drive control again.

[0062] It can be understood that the first drive control signal G1, the second drive control signal G2, and the third drive control signal G3 are actually generated based on two different control strategies and operation programs, and are obtained by using a specific alternating cycle generation method, that is, taking the time interval between every two adjacent rising edges of the pulse reference current as the cycle control period, and using two different control strategies to alternately generate the first control signal and the second control signal respectively.

[0063] Among them, the second charge control circuit specifically responds to the rising edge of each pulse reference current, and first calculates the first control signal by using a corresponding preset adjustment function; and the first control signal is the first control signal of the first wave. After it, that is, from the second control signal, until the next rising edge of the pulse reference current is detected again, it is the second control signal generated according to the closed-loop feedback control strategy corresponding to the current loop, so as to be able to make the output current have a faster rising time by using the first control signal synchronized with the rising edge, and at the same time use the second control signal obtained by closed-loop feedback adjustment and phase shift to avoid overshoot.

[0064] It can be seen from this that between every two adjacent rising edges of the pulse reference current, the first drive control signal G1, the second drive control signal G2, and the third drive control signal G3 alternate between the first control signal and the second control signal; and the first control signal is the first control signal of the first wave, and after that, they are all the second control signals until the next rising edge of the pulse reference current, and the first control signal and the second control signal are generated alternately in a cycle again, and so on, which will not be elaborated here.

[0065] Furthermore, in one embodiment, the above S121 may specifically include: calculating the reference turn-on time tj by using a preset adjustment function for the input voltage, the output voltage, the pulse reference current, the set number n, the equivalent inductance, and the preset adjustment coefficient; Among them, the preset adjustment function is: tj= ; Among them, tj is the reference turn-on time, is the pulse reference current, is a preset adjustment coefficient, and n is a set quantity. is the input voltage. is the output voltage. is the equivalent inductance.

[0066] It should be noted that the ideal turn-on times of the first switching transistor Q1, the second switching transistor Q2, and the third switching transistor Q3 can be obtained through calculation. Different ideal turn-on times can be given according to different pulse reference currents. In order to avoid overshoot problems during the subsequent open-loop and closed-loop connection, the ideal turn-on time can be multiplied by a preset adjustment coefficient to obtain the reference turn-on time tj.

[0067] In addition, the preset adjustment coefficient is specifically a coefficient less than 1 and greater than 0, and this application does not limit it.

[0068] The equivalent inductance L can be understood as the same equivalent inductance value corresponding to the first inductance L1, the second inductance L2, and the third inductance L3, and the single-phase inductance current rising slope: .

[0069] The rising slope of the output current Io is the number of parallel phases, that is, the set quantity n multiplied by the rising slope of the single-phase inductance current. Therefore, it can be obtained that: Tj = = .

[0070] Further, in an embodiment, the above S123 may specifically include: in response to the falling edge of each first control signal, generating a second control signal by delaying a set duration and using the difference between the pulse reference current and the output current Io.

[0071] It can be understood that in a switching cycle, there are a turn-on time and a turn-off time, and the turn-off time also includes an inevitable dead time. Therefore, at the falling edge of each first control signal, it is also necessary to delay a specific turn-off time, that is, the set duration, and then generate a second control signal by using the difference between the pulse reference current and the output current Io.

[0072] Further, in an embodiment, the above S13 may specifically include: adjusting the phase difference between every two adjacent falling edges of the first control signals to the quotient of the preset switching cycle T divided by the set quantity n, and making the sum of the turn-on times of each first control signal equal to the product of the reference turn-on time tj and the set quantity n.

[0073] It is understandable that, in order to avoid the problem of the output current Io dropping caused by the simultaneous wave blocking of multiple phases during the open-loop and closed-loop connection, when the open-loop blocks the wave, the wave cannot be blocked simultaneously, that is, the falling edges of the first control signals cannot be at the same moment. The closed-loop feedback regulation can be carried out in a direct phase interleaving manner, that is, ensuring that the rising edges of the second control signals are directly phase interleaved, and for every two adjacent second control signals, that is, corresponding to two adjacent switching tubes, the phase difference is T / n, where T is the preset switching period.

[0074] Correspondingly, the phase difference between the falling edges of every two adjacent first control signals needs to be adjusted to the quotient of the reference switching period divided by the set number n, and the sum of the on-times of the first control signals is equal to the product of the reference on-time tj and the set number n.

[0075] Among them, when the set number n is 3, to ensure that the on-times of the first control signals are as evenly distributed as possible, the first on-time of the second drive control signal G2 can specifically be equal to the reference on-time tj; and the first on-time of the first drive control signal G1 is the reference on-time tj minus T / n; the first on-time of the third drive control signal G3 is the reference on-time tj plus T / n.

[0076] In other embodiments, when the set number n is 4, the first on-time of the first drive control signal G1 can specifically be equal to the reference on-time tj minus 3T / 2n; the first on-time of the second drive control signal G2 is the reference on-time tj minus T / 2n; the first on-time of the third drive control signal G3 is the reference on-time tj plus T / 2n; the first on-time of the fourth drive control signal is the reference on-time tj plus 3T / 2n; and so on. The specific on-times of the first control signals when the set number n is even or odd can be obtained respectively, which will not be elaborated here.

[0077] It should be noted that when the rising edges of the first control signals are synchronized and there is a phase difference in the falling edges, the first control signals actually correspond to different signal waveforms and have different conduction times and signal periods.

[0078] Please continue to refer to Figure 7 , Figure 7 is Figure 3 a schematic flowchart of an embodiment of S123 in S1231: Perform proportional-integral regulation on the current difference between the pulse reference current and the output current to obtain the target current integral value.

[0079] Please continue to refer to Figure 8 , Figure 8 which Figure 6 is the logic framework diagram of signal processing in the charge control method in

[0080] Specifically, subtract the output current Io from the pulse reference current Iref to obtain a current difference, and perform proportional-integral regulation on the current difference to obtain a target current integral value.

[0081] S1232: Perform energy storage integral regulation on the input current to obtain an integral voltage value.

[0082] Furthermore, sample and obtain the first input current Iin1, the second input current Iin2, and the third input current Iin3 from the first switching transistor Q1, the second switching transistor Q2, and the third switching transistor Q3 respectively, so as to use the first input current Iin1, the second input current Iin2, and the third input current Iin3 to charge the integral capacitors (not shown in the figure) in the second charge control circuit respectively, and perform integral regulation to obtain the first integral voltage value, the second integral voltage value, and the third integral voltage value.

[0083] S1233: Obtain an integral reference value by using the difference between the given reference voltage and the integral voltage value.

[0084] Set the given reference voltage according to the power supply demand, or receive the given reference voltage sent by the upper controller, so as to subtract the first integral voltage value, the second integral voltage value, and the third integral voltage value from the given reference voltage respectively to obtain the first integral reference value, the second integral reference value, and the third integral reference value.

[0085] S1234: Obtain a second control signal by using the target current integral value and the integral reference value.

[0086] Compare the target current integral value with the first integral reference value, the second integral reference value, and the third integral reference value respectively to obtain each second control signal, that is, the first drive control signal G1, the second drive control signal G2, and the third drive control signal G3 obtained by closed-loop control after the first wave. For example, determine the turn-off moment, that is, the falling edge, of the first drive control signal G1 when the target current integral value is equal to the first integral reference value, and determine the rising edge of the first drive control signal G1 according to the preset switching period, and obtain the second drive control signal G2 and the third drive control signal G3 respectively according to this signal processing logic.

[0087] Please refer to Figure 9 , Figure 9 which Figure 1Flow schematic diagram of a refined implementation of the charge control method in [reference], specifically including the following steps: S51: Obtain the pulse reference current and the power supply characteristic parameters of the polyphase voltage conversion circuit.

[0088] Please continue to refer to Figure 10 , Figure 10 is Figure 9 Waveform schematic diagram of an embodiment of each relevant signal of the charge control method in [reference].

[0089] Specifically, the first charge control circuit 20 monitors and obtains various circuit parameters of the first polyphase voltage conversion circuit 30 in real time, such as one or more of any reasonable power supply characteristic parameters such as input voltage, output current Io, output voltage, etc., and sets the pulse reference current according to a preset control program, or receives the pulse reference current obtained by the host computer through experimental calibration or simulation optimization for the specific working conditions and power supply requirements of the load circuit.

[0090] Among them, the power supply characteristic parameter specifically includes the output current Io.

[0091] S52: In response to the rising edge of the pulse reference current, perform proportional-integral regulation on the current difference between the pulse reference current and the output current to obtain the target current integral value.

[0092] The first charge control circuit 20 is used to identify and detect the rising edge of the pulse reference signal, so as to subtract the output current Io from the pulse reference current to obtain a current difference when detecting the rising edge of the pulse reference current, and perform proportional-integral regulation on the current difference to obtain the target current integral value.

[0093] S53: Detect whether the current difference is less than the set current threshold.

[0094] It can be understood that, in order to balance the contradiction between the rising time and overshoot of the output current Io, a control strategy with variable PI parameters can be specifically adopted, that is, when the actual output current Io is small, the PI parameters are large to ensure that the duty cycle of the PWM wave is large enough and the integral amount of PI can be saturated quickly, while when the actual output current Io is close to the pulse reference current, that is, when the current difference is too small, the PI parameters need to be adjusted to prevent overshoot.

[0095] Specifically, detect whether the currently obtained current difference is less than the set current threshold.

[0096] It should be noted that the set current threshold is a specific current threshold reasonably set when the actual output current Io is relatively close to the pulse reference current and there is a risk of overshoot, and it is determined by the actual application scenario, and this application does not limit it.

[0097] Among them, if the current difference is less than the set current threshold, S54 is executed; if the current difference is not less than the set current threshold, S55 is executed.

[0098] S54: Multiply the target current integral value by a set multiple.

[0099] It can be understood that when it is determined that the current difference is less than the set current threshold, in order to avoid overshoot, the corresponding PI parameters can be reduced.

[0100] Specifically, multiply the target current integral value by a set multiple.

[0101] In some embodiments, the set multiple is less than 1 and greater than 0, and is preferably 0.5. The present application does not limit this.

[0102] S55: Obtain a set number of drive control signals by using the target current integral value.

[0103] Further, a set number n of drive control signals are sequentially obtained by using the adjusted target current integral value.

[0104] It should be noted that the first charge control circuit 20 can specifically obtain a set number n of drive control signals by sequentially processing the target current integral value through a current loop feedback regulation control strategy, or can also obtain a set number n of drive control signals by using the control strategy such as S1231 - S1234 as described above. The present application does not limit this.

[0105] S56: In the switching period of each drive control signal, use a preset positive correlation function to gradually adjust the phase difference between every two adjacent drive control signals until the phase difference between every two adjacent drive control signals is the quotient of the preset switching period divided by the set number n.

[0106] Further, in each switching cycle of the drive control signal, a preset positive correlation function, such as an arithmetic function, a linearly increasing function, or a non - linear increasing function, or any other reasonable function, is used to gradually adjust the phase difference between every two adjacent drive control signals. Taking the set number n as 3 as an example, the first rising edge and falling edge of the first drive control signal G1, the second drive control signal G2, and the third drive control signal G3 are synchronized, and the phase of the first drive control signal G1 is kept unchanged. The preset positive correlation function is respectively used to adjust the phases of the second drive control signal G2 and the third drive control signal G3, so that the second drive control signal G2 gradually increases relative to the first drive control signal G1, and the third drive control signal G3 gradually increases relative to the second drive control signal G2, until the phase difference between every two adjacent drive control signals, that is, the phase difference between the second drive control signal G2 and the first drive control signal G1 and the phase difference between the third drive control signal G3 and the second drive control signal G2, are both the quotient of the reference switching cycle divided by the set number n, then the phase adjustment is terminated.

[0107] S57: Send each drive control signal after phase adjustment to each switching sub - circuit respectively to trigger each switching sub - circuit to change its switching state.

[0108] Among them, S57 is the same as Figure 1 S14 in, for specific details, please refer to S14 and its related written description, which will not be elaborated here.

[0109] Further, in an embodiment, S54 above can specifically be replaced by multiplying the duty cycle of the drive control signal by a set multiple; or, multiplying the adjustment output parameter of the corresponding PI controller by a set multiple to generate a drive control signal using the adjusted adjustment output signal.

[0110] It can be understood that, in order to simultaneously balance the contradiction between the rising time and overshoot of the output current Io, a multi - phase parallel switching sub - circuit can be gradually phase - shifted and the PI parameters can be changed to modulate the rising process of the output current Io. In order to further avoid the vertical line of overshoot, based on the above - mentioned method, specifically, the difference between the actual output current Io and the reference current can be detected. When the difference is lower than a certain range, the duty cycle of the drive control signal or other reasonable PI parameters such as the adjustment output parameter of the PI controller can be directly reduced to achieve fast desaturation and prevent the occurrence of overshoot. This application does not make a limitation on this.

[0111] This application also provides an electronic device, please refer to Figure 11 , Figure 11 is a schematic structural diagram of an embodiment of the electronic device of this application. In this embodiment, the electronic device 60 includes a housing 61 and a third charge control circuit 62 connected to the housing 61.

[0112] It should be noted that the third charge control circuit 62 described in this embodiment is the first charge control circuit 20 or the second charge control circuit described in any of the above embodiments. For details, please refer to Figures 1 - 10 the relevant text content and will not be elaborated here.

[0113] The beneficial effects of this application are as follows: Different from the prior art, the charge control method provided by this application obtains the pulse reference current and the power supply characteristic parameters of the multiphase voltage conversion circuit. In response to the rising edge of the pulse reference current, a set number of drive control signals are generated by using the set number, the pulse reference current, and the power supply characteristic parameters, and the first rising edges of the drive control signals are synchronized, so that each switch sub-circuit can be triggered to conduct simultaneously, effectively improving the rising speed of the output current and significantly reducing the rising time of the output current. Moreover, by using the set number and the preset switching period to phase-shift each drive control signal, the switch sub-circuits are gradually staggered to conduct, which can also effectively avoid the possible overshoot problem, so that the faster rising time of the output current can be taken into account while avoiding the occurrence of overshoot.

[0114] The above are only the embodiments of this application, and do not limit the patent scope of this application accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of this application, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of this application.

Claims

1. A charge control method is applied to the charge control of a multiphase voltage conversion circuit. The multiphase voltage conversion circuit includes a set number of switch sub - circuits, and the set number is greater than 1. The method is characterized in that, The charge control method includes: Obtaining a pulse reference current and power supply characteristic parameters of the polyphase voltage conversion circuit; wherein, the power supply characteristic parameters include an input voltage, an output voltage, an output current, an equivalent inductance, and a preset adjustment coefficient; In response to a rising edge of the pulse reference current, generating the set number of drive control signals by using the set number, the pulse reference current, and the power supply characteristic parameters; wherein, the first rising edges of the drive control signals are synchronized, and the drive control signals include a first control signal and a second control signal; the step of generating the set number of drive control signals by using the pulse reference current and the power supply characteristic parameters in response to the rising edge of the pulse reference current includes: in response to the rising edge of each pulse reference current, obtaining a reference turn-on time by using the input voltage, the output voltage, the pulse reference current, the set number, the equivalent inductance, and the preset adjustment coefficient; generating the set number of the first control signals by using the reference turn-on time; wherein, the rising edges of the first control signals are synchronized; generating the second control signal by using a difference between the pulse reference current and the output current until the next rising edge of the pulse reference current; Phase-adjusting each of the drive control signals by using the set number and a preset switching period; Sending each of the phase-adjusted drive control signals to each of the switch sub-circuits respectively to trigger each of the switch sub-circuits to change the switch state.

2. The charge control method according to claim 1, wherein The step of phase-adjusting each of the drive control signals by using the set number and the preset switching period includes: Adjusting a phase difference between the falling edges of every two adjacent first control signals to a quotient of the preset switching period divided by the set number, and making a sum of the turn-on times of the first control signals equal to a product of the reference turn-on time and the set number.

3. The charge control method according to claim 2, wherein The step of generating the second control signal by using a difference between the pulse reference current and the output current includes: In response to the falling edge of each first control signal, generating the second control signal by using the difference between the pulse reference current and the output current after a set time delay.

4. The charge control method according to claim 1, characterized in that The step of obtaining the reference turn-on time by using the input voltage, the output voltage, the pulse reference current, the set number, the equivalent inductance, and the preset adjustment coefficient includes: Calculating the reference turn-on time by using a preset adjustment function for the input voltage, the output voltage, the pulse reference current, the set number, the equivalent inductance, and the preset adjustment coefficient; wherein, the preset adjustment function is: tj= ; where tj is the reference turn-on time, is the pulse reference current, is the preset adjustment coefficient, n is the set number, is the input voltage, is the output voltage, is the equivalent inductance.

5. The charge control method according to claim 1, wherein The power supply characteristic parameters further include an input current, and the step of generating the second control signal by using a difference between the pulse reference current and the output current includes: Performing proportional-integral regulation on a current difference between the pulse reference current and the output current to obtain a target current integral value; Performing energy storage integral regulation on the input current to obtain an integral voltage value; An integration reference value is obtained by using the difference between a given reference voltage and the integration voltage value; A second control signal is obtained by using the target current integration value and the integration reference value.

6. The charge control method according to claim 1, wherein The power supply characteristic parameter includes an output current, and the step of generating the set number of drive control signals by using the pulse reference current and the power supply characteristic parameter includes: Performing proportional-integral regulation on the current difference between the pulse reference current and the output current to obtain a target current integration value; Obtaining the set number of drive control signals by using the target current integration value.

7. The charge control method according to claim 6, wherein In the step of obtaining the set number of drive control signals by using the target current integration value, it further includes: Detecting whether the current difference is less than a set current threshold; If the current difference is less than the set current threshold, multiplying the target current integration value by a set multiple; wherein, the set multiple is less than 1 and greater than 0; Or, multiplying the duty cycle of the drive control signal by the set multiple.

8. The charge control method according to claim 6, characterized in that, The step of performing phase modulation on each drive control signal by using the set number and a preset switching period includes: In the switching period of each drive control signal, gradually adjusting the phase difference between every two adjacent drive control signals by using a preset positive correlation function until the phase difference between every two adjacent drive control signals is the quotient of the preset switching period divided by the set number.

9. A charge control circuit, characterized in that, The charge control circuit is coupled to a multiphase voltage conversion circuit; Wherein, the charge control circuit performs charge control on the multiphase voltage conversion circuit by using the charge control method according to any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes a housing and a charge control circuit connected to the housing; Wherein, the charge regulation circuit is the charge control circuit according to claim 9.

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