32-bit ASIC (Application Specific Integrated Circuit) hardware external interrupt counting fault injection triggering device

Abstract

The invention is applicable to the technical field of network security, and relates to a 32-bit ASIC (Application Specific Integrated Circuit) hardware external interrupt counting fault injection triggering device, which comprises a high-speed high-performance MCU / CPU (Microprogrammed Control Unit / Central Processing Unit) system, a 32-bit high-speed hardware synchronous counter module, a 32-bit high-speed hardware equivalent comparison module and a system power supply management module, the high-speed high-performance MCU / CPU system is respectively in communication connection with the 32-bit high-speed hardware synchronous counter module and the 32-bit high-speed hardware equivalent comparison module, and the 32-bit high-speed hardware synchronous counter module is in communication connection with the 32-bit high-speed hardware equivalent comparison module. According to the method, diversified hardware of a high-speed communication interface protocol, chip safety penetration detection and communication routine test index test evaluation are met, technical conditions are laid for simulating the real operation environment of hardware / chips, and the precision and real-time performance of interrupt trigger response and fault injection are effectively improved.

Description

Technical Field

[0001] The invention belongs to the technical field of network security, and in particular relates to a 32-bit ASIC hardware external interrupt counting fault injection triggering device. Background Art

[0002] The precision fault injection technology based on diversified physical layer electrical signals (hereinafter referred to as "fault injection technology") cannot be underestimated in its ability to crack and penetrate, and conduct security testing and evaluation of core components / equipment such as hardware devices, computing processing chips, and interface communication devices. Different from the traditional concept of network security penetration, this technology goes deep into the bottom layer of the network and directly reaches the hardware circuits and internal structures of chips / components of the object under test, and emits highly adjustable, controllable, and configurable diversified fault injection signals at a specific time and location. It can not only be used in application fields such as penetration testing, security testing and evaluation of hardware security, chip security, and firmware security, but is also very practical and effective in testing and evaluating the reliability, availability, conventional technical indicators, communication vulnerability, and error correction of traditional hardware / chips / key components.

[0003] Traditional fault injection technology is single and has weak performance. Fault injection signals cannot achieve comprehensive balance in terms of diversity, automation, high quality, high precision, high performance, ultra-high speed, and high user customization. In particular, they cannot adapt to the application scenarios of diversified hardware / chip interface devices, high-speed communication protocols, and hardware circuit security penetration / traditional testing. This greatly limits the breadth and depth of its application scenarios in the fields of hardware / chip security and conventional testing. In particular, in terms of ultra-high-speed precision trigger fault injection, traditional fault injection technology cannot meet the requirements. Even though many manufacturers have improved the high-speed CPU software and hardware technical solutions and optimized the instruction operation mechanism, they can effectively improve the trigger response speed and optimize the precision fault injection performance. However, there are still inherent factors such as the instruction jump of the CPU pipeline architecture, the CPU field protection instruction dead zone execution time, and the inability to integrate the trigger and fault injection behaviors, which seriously affect the precision and real-time performance of the interrupt trigger response and fault injection. In particular, in the face of the external interrupt trigger precision fault injection application scenario of the high-speed interface communication protocol, it still cannot play its core value. This not only greatly limits the application scenarios and fields of precision fault injection, but also greatly weakens the success rate of precision fault injection, an advanced penetration technology.

[0004] Therefore, how to improve the precision and real-time performance of interrupt trigger response and fault injection in the prior art to improve the success rate of precise fault injection is an urgent problem to be solved by personnel in this technical field. Summary of the invention

[0005] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a 32-bit ASIC hardware external interrupt counting fault injection triggering device to solve the problems of poor precision and real-time performance of interrupt triggering response and fault injection in the prior art, resulting in a low success rate of precise fault injection.

[0006] To solve the above technical problems, the present invention adopts the following technical solutions:

[0007] The present invention provides a 32-bit ASIC hardware external interrupt counting fault injection triggering device, including:

[0008] A high-speed and high-performance MCU / CPU system, which is used to configure a 32-bit high-speed hardware synchronous counter module and a 32-bit high-speed hardware equal value comparison module according to control instructions sent by an external software-defined fault injection device; a 32-bit high-speed hardware synchronous counter module, which is used to perform high-speed hardware automatic counting on the external interrupt trigger signal source signal; a 32-bit high-speed hardware equal value comparison module, which is used to compare a known 32-bit comparison value set by the user with the 32-bit value output by the 32-bit high-speed hardware synchronous counter module, and output a valid trigger signal to an external software-defined fault injection algorithm core device; a system power management module, which is used to convert an external DC power supply to supply power to the high-speed and high-performance MCU / CPU system, the 32-bit high-speed hardware synchronous counter module, and the 32-bit high-speed hardware equal value comparison module; the high-speed and high-performance MCU / CPU system is respectively communicatively connected to the 32-bit high-speed hardware synchronous counter module and the 32-bit high-speed hardware equal value comparison module, and the 32-bit high-speed hardware synchronous counter module and the 32-bit high-speed hardware equal value comparison module are communicatively connected.

[0009] Further, the high-speed and high-performance MCU / CPU system drives digital control signals S1 and S0 to control the actual working mode of the 32-bit high-speed hardware synchronous counter module.

[0010] Further, the high-speed and high-performance MCU / CPU system drives / ENT and / ENP to control the counting enable or disable of the 32-bit high-speed hardware synchronous counter module.

[0011] Further, the 32-bit high-speed hardware synchronous counter module includes an 8-bit integrated high-speed hardware synchronous counter chip U1, an 8-bit integrated high-speed hardware synchronous counter chip U2, an 8-bit integrated high-speed hardware synchronous counter chip U3, and an 8-bit integrated high-speed hardware synchronous counter chip U4. The / RCO terminal of the 8-bit integrated high-speed hardware synchronous counter chip U1 is connected to the CLK terminal of the 8-bit integrated high-speed hardware synchronous counter chip U2. The / RCO terminal of the 8-bit integrated high-speed hardware synchronous counter chip U2 is connected to the CLK terminal of the 8-bit integrated high-speed hardware synchronous counter chip U3. The / RCO terminal of the 8-bit integrated high-speed hardware synchronous counter chip U3 is connected to the CLK terminal of the 8-bit integrated high-speed hardware synchronous counter chip U4.

[0012] Further, the 32-bit high-speed hardware equality comparison module includes an 8-bit integrated high-speed hardware equality comparison chip U5, an 8-bit integrated high-speed hardware equality comparison chip U6, an 8-bit integrated high-speed hardware equality comparison chip U7, an 8-bit integrated high-speed hardware equality comparison chip U8, and an 8-bit integrated high-speed hardware equality comparison chip U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equality comparison chip U5 is connected to the P0 terminal of the 8-bit integrated high-speed hardware equality comparison chip U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equality comparison chip U6 is connected to the P2 terminal of the 8-bit integrated high-speed hardware equality comparison chip U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equality comparison chip U7 is connected to the P2 terminal of the 8-bit integrated high-speed hardware equality comparison chip U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equality comparison chip U8 is connected to the P3 terminal of the 8-bit integrated high-speed hardware equality comparison chip U9.

[0013] Further, the system power management module includes a power conversion module 0. The power conversion module 0 is connected to an external +5V / DC DC power supply and is used to convert the external +5V / DC DC power supply into a +3.3V / DC voltage. The +5V / DC DC power supply supplies power to the high-speed high-performance MCU / CPU system, the 32-bit high-speed hardware synchronous counter module, and the 32-bit high-speed hardware equality comparison module. The +3.3V / DC voltage supplies power to the high-speed high-performance MCU / CPU system.

[0014] Further, the working modes include up counting, down counting, load counting, and clear counting.

[0015] Further, when all are low-level signals, the 32-bit high-speed hardware synchronous counter module enables counting; otherwise, the 32-bit high-speed hardware synchronous counter module prohibits counting.

[0016] Compared with the prior art, the 32-bit ASIC hardware external interrupt counting fault injection triggering device provided by the present invention has at least the following beneficial effects:

[0017] Traditional fault injection technologies are single and have weak performance. The precision and real-time performance of interrupt triggering response and fault injection are poor, resulting in the success rate of this advanced penetration technology of precise fault injection. The present invention proposes to integrally design the ultra-high-speed precise fault injection triggering technology and the software-defined fault injection algorithm execution mechanism in the ASIC dedicated hardware for execution, that is, to integrally design the ultra-high-speed ASIC dedicated hardware external interrupt trigger response and the fault injection algorithm after triggering. The whole process does not require the intervention of CPU operation processing instructions, fundamentally eliminating the inherent time consumption of the jump / non-jump instructions of the CPU pipeline architecture and the inherent dead zone time of the CPU context protection instructions. The ultra-high-speed external interrupt trigger response and the fault injection action after triggering are integrated with a true "zero dead zone" response time, realizing a trigger + fault injection linkage execution mechanism without CPU participation throughout the process. The fault injection algorithm can be pre-loaded twice in the software-defined fault injection device and run at high speed without relying on the CPU's own environment, achieving ultra-high-speed precise trigger fault injection with strong precision and real-time performance and a high success rate of precise fault injection, meeting the diverse hardware, chip security penetration detection, and communication conventional test index test evaluations of high-speed communication interface protocols, laying technical conditions for simulating the real operating environment of hardware / chips, that is, implementing precise trigger specific fault injection algorithms in the dynamic real-time communication process, and realizing the overall balance of performance characteristics such as compatibility, scalability, and precision in the application fields of hardware security, chip security, and firmware security. Description of the Drawings

[0018] In order to more clearly illustrate the solution of the present invention, the drawings required for description in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a schematic structural diagram of a 32-bit ASIC hardware external interrupt counting fault injection triggering device provided by an embodiment of the present invention;

[0020] Figure 2 It is an internal structure diagram of the 32-bit high-speed hardware synchronous counter module of a 32-bit ASIC hardware external interrupt counting fault injection triggering device provided by an embodiment of the present invention;

[0021] Figure 3 Internal structure diagram of the 32-bit high-speed hardware equal comparison module of a 32-bit ASIC hardware external interrupt counting fault injection trigger device provided by an embodiment of the present invention;

[0022] Figure 4 Internal structure diagram of the system power management module of a 32-bit ASIC hardware external interrupt counting fault injection trigger device provided by an embodiment of the present invention. Detailed implementation manners

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this invention belongs; the terms used in the description of the present invention in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. For example, the terms "length", "width", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or position based on the orientation or position shown in the drawings, and are only for convenience of description and cannot be construed as a limitation to the technical solution of the present invention.

[0024] The terms "comprising" and "having" and any variations thereof in the description and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusion; the terms "first", "second", etc. in the description and claims of the present invention or the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In the description and claims of the present invention and the above-mentioned drawings, when an element is referred to as being "fixed to" or "mounted on" or "disposed on" or "connected to" another element, it can be directly or indirectly located on the other element. For example, when an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element.

[0025] In addition, the mention of "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present invention. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0026] The present invention provides a 32-bit ASIC hardware external interrupt counting fault injection trigger device, which is applied to the processes of diversified hardware of high-speed communication interface protocols, chip security penetration detection, and communication conventional test index test and evaluation. The 32-bit ASIC hardware external interrupt counting fault injection trigger device includes:

[0027] A high-speed and high-performance MCU / CPU system is used to configure a 32-bit high-speed hardware synchronous counter module and a 32-bit high-speed hardware equal-value comparison module according to control instructions sent by an external software-defined fault injection device; the 32-bit high-speed hardware synchronous counter module is used to perform high-speed hardware automatic counting on the external interrupt trigger signal source signal; the 32-bit high-speed hardware equal-value comparison module is used to compare a 32-bit known comparison value set by the user with the 32-bit value output by the 32-bit high-speed hardware synchronous counter module, and output a valid trigger signal to the external software-defined fault injection algorithm core device; the system power management module is used to convert the external DC power supply to supply power to the high-speed and high-performance MCU / CPU system, the 32-bit high-speed hardware synchronous counter module, and the 32-bit high-speed hardware equal-value comparison module; the high-speed and high-performance MCU / CPU system is communicatively connected to the 32-bit high-speed hardware synchronous counter module and the 32-bit high-speed hardware equal-value comparison module respectively, and the 32-bit high-speed hardware synchronous counter module and the 32-bit high-speed hardware equal-value comparison module are communicatively connected.

[0028] The present invention meets the diverse hardware, chip security penetration detection, and communication conventional test index test evaluations of high-speed communication interface protocols, lays technical conditions for simulating the real operating environment of hardware / chips, and effectively improves the precision and real-time performance of interrupt trigger response and fault injection.

[0029] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0030] The present invention provides a 32-bit ASIC hardware external interrupt counting fault injection trigger device, which is applied in the process of diverse hardware, chip security penetration detection, and communication conventional test index test evaluations of high-speed communication interface protocols, and combines Figures 1 to 4 In this embodiment, the 32-bit ASIC hardware external interrupt counting fault injection trigger device includes: a high-speed and high-performance MCU / CPU system, a 32-bit high-speed hardware synchronous counter module, a 32-bit high-speed hardware equal-value comparison module, and a system power module circuit. The high-speed and high-performance MCU / CPU system is communicatively connected to the 32-bit high-speed hardware synchronous counter module and the 32-bit high-speed hardware equal-value comparison module respectively, and the 32-bit high-speed hardware synchronous counter module and the 32-bit high-speed hardware equal-value comparison module are communicatively connected.

[0031] Specifically, in this embodiment, the high-speed and high-performance MCU / CPU system is the core arithmetic processing and control part of the hardware external interrupt counting injection trigger device. It is mainly used to configure a 32-bit high-speed hardware synchronous counter module and a 32-bit high-speed hardware equal value comparison module according to the control instructions sent by the host computer. The UART communication interface communicates with the external software-defined fault injection algorithm core device, receives and processes the control instructions sent by the external software-defined fault injection algorithm core device, and at the same time sends relevant status data to the external software-defined fault injection algorithm core device. Specifically, the S1 and S0 digital control signals are driven by the high-speed and high-performance MCU / CPU system and are used to control the actual working mode of the 32-bit high-speed hardware synchronous counter module, such as up counting (Count up@S1,S0 = bit11), down counting (Count down@S1,S0 = bit01), load counting (Load Count@S1,S0 = bit10), clear counting (Clear Count@S1,S0 = bit00). The / ENT and / ENP digital control signals are driven by the high-speed and high-performance MCU / CPU system and are used to control the counting enable of the 32-bit high-speed hardware synchronous counter module. When both are low-level signals, the 32-bit high-speed hardware synchronous counter module is counting enabled, otherwise the 32-bit high-speed hardware synchronous counter module is counting disabled, and the CUT_Bit[0~31] output is in a high-impedance state; the CML_Bit[0~31] signal is a digital signal with a 32-bit width. This digital signal will be synchronously output to the 32-bit high-speed hardware synchronous counter module and the 32-bit high-speed hardware equal value comparison module. When it is necessary to preload the count value of the 32-bit high-speed hardware synchronous counter module, the S1 and S0 digital control signals are linked (@S1,S0 = bit10), and the CML_Bit[0~31] digital signal is the preloaded count value. At this time, it is invalid data for the 32-bit high-speed hardware equal value comparison module. When it is necessary to set the 32-bit equal value comparison data value of the 32-bit high-speed hardware equal value comparison module, the / G digital control signal is linked at this time ( / G = 0), and the CML_Bit[0~31] digital signal is the equal value comparison value of the 32-bit high-speed hardware equal value comparison module, which is invalid data for the 32-bit high-speed hardware synchronous counter module; the / G digital control signal is driven and controlled by the high-speed and high-performance MCU / CPU system, and is mainly used to enable and control the 32-bit high-speed hardware equal value comparison module.

[0032] Specifically, in this embodiment, the 32-bit high-speed hardware synchronous counter module internally includes four 8-bit integrated high-speed hardware synchronous counter chips U1, U2, U3, and U4. Among them, the / RCO terminal of the 8-bit integrated high-speed hardware synchronous counter chip U1 is connected to the CLK terminal of the 8-bit integrated high-speed hardware synchronous counter chip U2, the / RCO terminal of the 8-bit integrated high-speed hardware synchronous counter chip U2 is connected to the CLK terminal of the 8-bit integrated high-speed hardware synchronous counter chip U3, and the / RCO terminal of the 8-bit integrated high-speed hardware synchronous counter chip U3 is connected to the CLK terminal of the 8-bit integrated high-speed hardware synchronous counter chip U4. It mainly performs high-speed hardware automatic counting on the external interrupt trigger signal source signal, and according to the configuration of the high-speed and high-performance MCU / CPU system, the initial count value can be pre-loaded or set to start counting from 0 to ensure the flexibility of the hardware counting starting value. The TRGIn signal is the external interrupt trigger signal source signal, which is compatible with the TTL level and CMOS level specifications. The S1 and S0 digital control signals are driven by the high-speed and high-performance MCU / CPU system and are used to control the actual working mode of the 32-bit high-speed hardware synchronous counter module, such as up counting (Count up@S1,S0 = bit11), down counting (Count down@S1,S0 = bit01), load counting (Load Count@S1,S0 = bit10), clear counting (Clear Count@S1,S0 = bit00). The / ENT and / ENP digital control signals are driven by the high-speed and high-performance MCU / CPU system and are used to control the counting enable of the 32-bit high-speed hardware synchronous counter module. When both are low-level signals, the 32-bit high-speed hardware synchronous counter module is counting enabled, otherwise the 32-bit high-speed hardware synchronous counter module is counting disabled, and the CUT_Bit[0~31] output is in a high-impedance state; when the 32-bit high-speed hardware synchronous counter module is working in the counting mode, the CUT_Bit[0~31] data signal is the current actual count value output by the 32-bit high-speed hardware synchronous counter module hardware, and the CUT_Bit[0~31] data signal will be synchronously output to the 32-bit high-speed hardware equal value comparison module for specific value equal value comparison;The CML_Bit[0~31] signal is a digital signal with a 32-bit width. This digital signal is driven and output by a high-speed and high-performance MCU / CPU system, and is synchronously output to a 32-bit high-speed hardware synchronous counter module and a 32-bit high-speed hardware equal-value comparison module. When it is necessary to preload the count value of the 32-bit high-speed hardware synchronous counter module, the digital control signals S1 and S0 are linked (@S1, S0 = bit10), and the CML_Bit[0~31] digital signal is the preloaded count value. At this time, it is invalid data for the 32-bit high-speed hardware equal-value comparison module. When it is necessary to set the 32-bit equal-value comparison data value of the 32-bit high-speed hardware equal-value comparison module, the / G digital control signal is linked at this time ( / G = 0), and the CML_Bit[0~31] digital signal is the equal-value comparison value of the 32-bit high-speed hardware equal-value comparison module, and is invalid data for the 32-bit high-speed hardware synchronous counter module; the / G digital control signal is driven and controlled by the high-speed and high-performance MCU / CPU system, and is mainly used to enable and control the 32-bit high-speed hardware equal-value comparison module, such as; Figure 2 As shown, the internal signal CLK0 is the counting carry signal of CUT_Bit[0~7], CLK1 is the counting carry signal of CUT_Bit[8~15], and CLK2 is the counting carry signal of CUT_Bit[16~23]. Based on this cascaded architecture, a 32-bit hardware counting module is formed.

[0033] Specifically, in this embodiment, the 32-bit high-speed hardware equal-value comparison module internally includes five 8-bit integrated high-speed hardware equal-value comparison chips U5, U6, U7, U8, and U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equal-value comparison chip U5 is connected to the P0 terminal of the 8-bit integrated high-speed hardware equal-value comparison chip U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equal-value comparison chip U6 is connected to the P2 terminal of the 8-bit integrated high-speed hardware equal-value comparison chip U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equal-value comparison chip U7 is connected to the P2 terminal of the 8-bit integrated high-speed hardware equal-value comparison chip U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equal-value comparison chip U8 is connected to the P3 terminal of the 8-bit integrated high-speed hardware equal-value comparison chip U9. It mainly compares the known 32-bit comparison value CML_Bit[0~31] set by the user with the 32-bit value output by the previous-stage 32-bit high-speed hardware synchronous counter module. When the two 32-bit values are equal, the 32-bit high-speed hardware equal-value comparison module outputs a valid TRGIn2 trigger signal to provide a trigger control signal for the external software-defined fault injection algorithm core device; the CUT_Bit[0~31] data signal is the current actual count value output by the 32-bit high-speed hardware synchronous counter module hardware and is provided to the 32-bit high-speed hardware equal-value comparison module as one of the two comparison numbers. The CUT_Bit[0~31] data signal will be synchronously output to the 32-bit high-speed hardware equal-value comparison module for specific value equal-value comparison; the CML_Bit[0~31] signal is a 32-bit digital signal, which is driven and output by the high-speed and high-performance MCU / CPU system and is synchronously output to the 32-bit high-speed hardware synchronous counter module and the 32-bit high-speed hardware equal-value comparison module. When it is necessary to preload the count value of the 32-bit high-speed hardware synchronous counter module, the S1 and S0 digital control signals (@S1, S0 = bit10) are linked, and the CML_Bit[0~31] digital signal is the preloaded count value. At this time, it is invalid data for the 32-bit high-speed hardware equal-value comparison module. When it is necessary to set the 32-bit equal-value comparison data value of the 32-bit high-speed hardware equal-value comparison module, the / G digital control signal ( / G = 0) is linked at this time, and the CML_Bit[0~31] digital signal is the equal-value comparison value of the 32-bit high-speed hardware equal-value comparison module and is invalid data for the 32-bit high-speed hardware synchronous counter module; the / G digital control signal is driven and controlled by the high-speed and high-performance MCU / CPU system and is mainly used to enable and control the 32-bit high-speed hardware equal-value comparison module. The specific schematic diagram of the internal module is as follows Figure 3As shown, chips U5~U8 are 4 independent 8-bit integrated high-speed hardware equivalence comparison chips, which are cascaded to form two 32-bit numerical equivalence comparison hardware operation processing units. The two 32-bit numerical values are CUT_Bit[0~31] and CML_Bit[0~31] respectively. Chip U9 is an independent 8-bit integrated high-speed hardware equivalence comparison chip. The signal P=Q output by the comparison result of each independent chip of chips U5~U8 is aggregated to form a final valid 4-bit comparison value, and an equivalence comparison calculation is performed with the known value 0x0F, and the final equivalence comparison valid signal TRGIn2 is output to the external software-defined fault injection algorithm core device.

[0034] Specifically, in this embodiment, Figure 4 As shown, the system power management module is powered by an external +5V / DC direct power supply, and outputs a +3.3V / DC voltage through the power conversion module 0. The +5V power supply is used to power the high-speed and high-performance MCU / CPU system, the 32-bit high-speed hardware synchronous counter module, and the 32-bit high-speed hardware equivalent comparison module; the +3.3V voltage is used to power the high-speed and high-performance MCU / CPU system to ensure that the entire device is powered normally.

[0035] Compared with the prior art, the 32-bit ASIC hardware external interrupt count fault injection trigger device described in the above embodiment has a single traditional fault injection technology and weak performance, and the interrupt trigger response and fault injection have poor precision and real-time performance, which leads to a low success rate of the advanced penetration technology of precise fault injection. The present invention proposes to execute the ultra-high-speed precision fault injection triggering technology and the software-defined fault injection algorithm execution mechanism linkage design inside the ASIC dedicated hardware, that is, the ultra-high-speed ASIC dedicated hardware external interrupt trigger response and the fault injection algorithm after triggering are integrated and linked, and no CPU operation processing instruction intervention is required throughout the process, which fundamentally eliminates the inherent time consumption of jump / non-jump instructions of the CPU pipeline architecture and the inherent dead time of the CPU field protection instruction, and integrates the ultra-high-speed external interrupt trigger response and the fault injection action after triggering with a real "zero dead zone" response time, so as to realize the trigger + fault injection linkage execution mechanism without CPU participation throughout the process, and the fault injection algorithm can be preloaded twice in the software-defined fault injection device and run at high speed without relying on the CPU itself. The ultra-high-speed precision trigger fault injection is realized, the precision and real-time performance are strong, the precision fault injection success rate is high, and the diversified hardware of the high-speed communication interface protocol, the chip security penetration detection and the communication conventional test index test evaluation are met, and the technical conditions are laid for simulating the real operating environment of the hardware / chip, that is, implementing the precision trigger specific fault injection algorithm in the dynamic real-time communication process, and the comprehensive balance of performance characteristics such as compatibility, extensibility, and precision in the application fields of hardware security, chip security, and firmware security is achieved.

[0036] Obviously, the embodiments described above are only the preferred embodiments of the present invention, rather than all embodiments. The preferred embodiments of the present invention are shown in the accompanying drawings, but they do not limit the patent scope of the present invention. The present invention can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosed content of the present invention more thorough and comprehensive. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing specific embodiments, or perform equivalent replacements for some of the technical features. Any equivalent structure made by using the content of the specification and drawings of the present invention, directly or indirectly applied to other related technical fields, is similarly within the scope of the patent protection of the present invention.

Claims

1. A 32-bit ASIC hardware external interrupt counting fault injection trigger device, characterized in that Comprising: A high-speed and high-performance MCU / CPU system, configured to configure a 32-bit high-speed hardware synchronous counter module and a 32-bit high-speed hardware equal value comparison module according to control instructions sent by an external software-defined fault injection device; A 32-bit high-speed hardware synchronous counter module, configured to perform high-speed hardware automatic counting on an external interrupt trigger signal source signal; A 32-bit high-speed hardware equal value comparison module, configured to compare a 32-bit known comparison value set by a user with the 32-bit value output by the 32-bit high-speed hardware synchronous counter module, and output a valid trigger signal to an external software-defined fault injection algorithm core device; A system power management module, configured to convert an external DC power supply to supply power to the high-speed and high-performance MCU / CPU system, the 32-bit high-speed hardware synchronous counter module, and the 32-bit high-speed hardware equal value comparison module; The high-speed and high-performance MCU / CPU system is respectively communicatively connected to the 32-bit high-speed hardware synchronous counter module and the 32-bit high-speed hardware equal value comparison module, and the 32-bit high-speed hardware synchronous counter module and the 32-bit high-speed hardware equal value comparison module are communicatively connected.

2. The 32-bit ASIC hardware external interrupt counting fault injection triggering device according to claim 1, wherein The high-speed and high-performance MCU / CPU system drives digital control signals S1 and S0 to control the actual working mode of the 32-bit high-speed hardware synchronous counter module.

3. A 32-bit ASIC hardware external interrupt counting fault injection trigger device according to claim 2, characterized in that, The high-speed and high-performance MCU / CPU system drives / ENT and / ENP to control the counting enable or disable of the 32-bit high-speed hardware synchronous counter module.

4. A 32-bit ASIC hardware external interrupt counting fault injection triggering device according to claim 1, characterized in that, The 32-bit high-speed hardware synchronous counter module includes an 8-bit integrated high-speed hardware synchronous counter chip U1, an 8-bit integrated high-speed hardware synchronous counter chip U2, an 8-bit integrated high-speed hardware synchronous counter chip U3, and an 8-bit integrated high-speed hardware synchronous counter chip U4. The / RCO terminal of the 8-bit integrated high-speed hardware synchronous counter chip U1 is connected to the CLK terminal of the 8-bit integrated high-speed hardware synchronous counter chip U2, the / RCO terminal of the 8-bit integrated high-speed hardware synchronous counter chip U2 is connected to the CLK terminal of the 8-bit integrated high-speed hardware synchronous counter chip U3, and the / RCO terminal of the 8-bit integrated high-speed hardware synchronous counter chip U3 is connected to the CLK terminal of the 8-bit integrated high-speed hardware synchronous counter chip U4.

5. A 32-bit ASIC hardware external interrupt count fault injection trigger device according to claim 1, characterized in that, The 32-bit high-speed hardware equality comparison module includes 8-bit integrated high-speed hardware equality comparison chips U5, U6, U7, U8, and U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equality comparison chip U5 is connected to the P0 terminal of the 8-bit integrated high-speed hardware equality comparison chip U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equality comparison chip U6 is connected to the P2 terminal of the 8-bit integrated high-speed hardware equality comparison chip U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equality comparison chip U7 is connected to the P2 terminal of the 8-bit integrated high-speed hardware equality comparison chip U9. The output signal terminal P=Q of the 8-bit integrated high-speed hardware equality comparison chip U8 is connected to the P3 terminal of the 8-bit integrated high-speed hardware equality comparison chip U9.

6. The 32-bit ASIC hardware external interrupt counting fault injection trigger device according to claim 1, characterized in that, The system power management module includes a power conversion module 0. The power conversion module 0 is connected to an external +5V / DC DC power supply and is used to convert the external +5V / DC DC power supply into a +3.3V / DC voltage. Among them, the +5V / DC DC power supply supplies power to the high-speed high-performance MCU / CPU system, the 32-bit high-speed hardware synchronous counter module, and the 32-bit high-speed hardware equality comparison module, and the +3.3V / DC voltage supplies power to the high-speed high-performance MCU / CPU system.

7. A 32-bit ASIC hardware external interrupt counting fault injection trigger device according to claim 2, characterized in that, The working modes include up counting, down counting, load counting, and clear counting.

8. A 32-bit ASIC hardware external interrupt counting fault injection trigger device according to claim 3, characterized in that, When all are low-level signals, the 32-bit high-speed hardware synchronous counter module enables counting; otherwise, the 32-bit high-speed hardware synchronous counter module prohibits counting.

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