PCIe link training method, PCIe link training system and PCIe link communication system

Abstract

The invention discloses a PCIe link training method, a PCIe link training system and a communication system. The PCIe link training method comprises the following steps: collecting current state information (current environment temperature and current interface voltage) of target PCIe equipment; screening a target historical record matched with the current state information in a database, wherein the historical record comprises the ambient temperature of PCIe equipment corresponding to previous training, PCIe equipment interface voltage, link configuration, channel mapping and a channel equalization coefficient; if a target historical record is screened, loading link configuration, channel mapping and channel equalization coefficients in the historical record; the target PCIe device generates a TS1 training sequence and sends the TS1 training sequence to the opposite terminal device; and in response to the fact that the opposite terminal equipment judges that the parameters in the TS1 training sequence meet the communication requirements, receiving a TS2 reply sequence sent by the opposite terminal equipment, and enabling the target PCIe equipment to enter a communication state. The invention can shorten the link training time and avoid repeated negotiation.

Description

Technical Field

[0001] The present invention relates to the field of PCIe communication, and in particular, to a PCIe link training method, a training system, and a communication system. Background Art

[0002] PCIe (Peripheral Component Interconnect Express for short), as a high-speed serial computer expansion bus standard, is widely used in fields such as servers, storage, and networks. The PCIe link is the core part of PCIe communication, which is responsible for transmitting data between devices. During PCIe device initialization or link reset, a stable communication connection needs to be established through link training.

[0003] Traditional PCIe link training methods include processes such as detecting the peer device, negotiating link rate and width, and configuring channel mapping and equalization parameters. However, with the popularization of PCIe Gen5 (with a rate of up to 32 GT / s), traditional PCIe link training methods face many challenges, such as high latency, repeated calculations, and power consumption waste.

[0004] During the traditional PCIe link training process, the link training state machine (LTSSM) needs to perform rate negotiation and equalization step by step and cannot skip unnecessary steps, which will cause significant latency at the high data rate of Gen5 and affect the overall response speed of the system. This latency becomes a performance bottleneck in scenarios such as data center hot plug and real-time computing (such as AI inference and high-frequency trading).

[0005] Traditional PCIe link training systems lack the ability to learn from history. Each time power is applied or the link is reset, the traditional LTSSM has to start training from scratch and cannot reuse historical successful parameters (such as the peer device ID, equalization coefficients, etc.). This design ignores the reusability of the same device in the same environment, resulting in repeated negotiation overhead. In the same environment (such as constant temperature, voltage, and device configuration), the traditional PCIe link training method still needs to execute the complete link training process again, repeating the negotiation rate, channel mapping, and equalization parameters. This not only wastes time and computing power but also causes the PHY layer circuit to be frequently activated, increasing the dynamic power consumption. For example, after a server restarts, the PCIe link between the GPU and the switch must be completely retrained, even if no environmental parameters have changed. This inefficient design is particularly prominent in mobile devices and edge computing nodes, limiting the optimization of the energy efficiency ratio. In addition, traditional PCIe link training also lacks the ability to learn from history. Each time power is applied or the link is reset, the traditional LTSSM has to start training from scratch and cannot reuse historical successful parameters (such as the peer device ID, equalization coefficients, etc.). This design ignores the reusability of the same device in the same environment, resulting in repeated negotiation overhead.

[0006] In addition, the traditional PCIe link training method uses fixed training parameters and cannot dynamically adapt to environmental fluctuations (such as temperature and voltage), resulting in communication connection failures. For example, an increase in temperature may cause signal attenuation, and voltage fluctuations may cause timing deviations. At this time, the fixed parameters are likely to lead to training failures, triggering the recovery state or even link interruption. Due to the lack of real-time environmental awareness, the system cannot actively adjust the parameters and can only restore the connection through a retry mechanism, further increasing the latency and uncertainty.

[0007] The disclosure of the above background technical content is only for assisting in understanding the concept and technical solution of the present application. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance; in the absence of clear evidence indicating that the above content was publicly available before the filing date of the present application, the above background technology should not be used to evaluate the novelty and inventiveness of the present application. Summary of the Invention

[0008] The objective of the present invention is to provide a PCIe link training method, a training system, and a communication system, which can shorten the link training time and avoid repeated negotiation.

[0009] To achieve the above objective, the technical solution adopted by the present invention is as follows: A PCIe link training method for establishing a communication connection between a target PCIe device and a peer device, comprising the following steps: Collect the current state information of the target PCIe device, where the current state information includes the current environmental temperature and the current interface voltage; Filter the target historical records that match the current status information in the pre-built database, where the database is configured to store the corresponding historical records after successful historical PCIe link training, and the historical records include the ambient temperature and PCIe device interface voltage, link configuration, channel mapping, and channel equalization coefficient of the PCIe device corresponding to the training; If a matching historical record is filtered out, load the link configuration, channel mapping, and channel equalization coefficient in the historical record; The target PCIe device generates a TS1 training sequence with an identifier, which includes the loaded link configuration, channel mapping, and channel equalization coefficient, and sends the TS1 training sequence to the peer device to be connected; In response to the peer device determining that the link configuration, channel mapping, and channel equalization coefficient in the TS1 training sequence meet its own current communication requirements, receive the TS2 reply sequence sent by the peer device, and then the target PCIe device successfully completes training and enters the communication state.

[0010] Further, if no matching historical record is filtered out, perform training according to the standard process of PCIe link training, including negotiating link rate and width, configuring channel mapping and equalization parameters, obtaining link configuration, channel mapping, and channel equalization coefficient, and entering the communication state.

[0011] Further, based on any one or a combination of the foregoing technical solutions, if the docking device does not complete the response within 5 clock cycles, fallback to polling in the standard process of PCIe link training for training.

[0012] Further, based on any one or a combination of the foregoing technical solutions, add the current status information and the link configuration, channel mapping, and channel equalization coefficient obtained from this training as a new historical record to the database.

[0013] Further, based on any one or a combination of the foregoing technical solutions, the historical record further includes the device identifier of the peer device, and the device identifier includes the vendor ID and / or device ID of the peer device, Filter the target historical records that match the current status information in the following manner: Filter the historical records in the database that match the device identifier of the current peer device to obtain the first filtering result; According to the preset rules, filter the target historical records that match the current status information from the first filtering result.

[0014] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the multiple historical records stored in the database form a historical record table; Filter target history records that match the current state information described by: According to the order of the history record table, each history record is judged in turn to see whether it meets the following preset rules: The difference between the current ambient temperature and the ambient temperature in the historical record is within a preset temperature difference threshold range, and the difference between the current interface voltage and the PCIe device interface voltage in the historical record is within a preset voltage difference threshold range; If it is satisfied, the screening stops and the historical records that currently meet the conditions are used as the target historical records; If not satisfied, continue to judge the next historical record.

[0015] Further, according to any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the timing is started when determining whether the first historical record meets the preset rule; If the preset time period has elapsed after the timing is started and no historical records satisfying the preset rules are found, the screening is stopped and it is determined that no matching historical records are found.

[0016] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, each time a matching target historical record is found, the target historical record is placed at the top of the historical record table.

[0017] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the target PCIe device generates a TS1 training sequence with a marker in the following manner: In each historical record, link configuration, channel mapping, and channel equalization coefficient are respectively configured with preset item identifiers; The corresponding link configuration, channel mapping, and channel equalization coefficient are located according to their respective item identifiers, and the link configuration, channel mapping, and channel equalization coefficient are extracted in parallel to generate the TS1 training sequence.

[0018] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the target PCIe device sends multiple TS1 training sequences to the opposite device, and starts timing when sending the first TS1 training sequence; If the preset time has elapsed after the timing is started and the TS2 reply sequence is not received, the training is performed according to the standard process of PCIe link training. When returning to the standard process, the check status can be skipped.

[0019] According to another aspect of the present invention, there is provided a PCIe link training system, including a training processor, a temperature sensor, a voltage sensor, and a database. The PCIe link training system is configured to execute the PCIe link training method as described above.

[0020] Further, the training processor includes an LTSSM state machine. The LTSSM state machine includes a detection state, a polling state, a configuration state, and an L0 state in the standard process of PCIe link training, and further includes a fast configuration state. The fast configuration state is configured to directly configure the channel mapping and equalization parameters in the target historical record when the target historical record is screened.

[0021] Further, the training processor includes a storage controller, which is configured to read the historical records in the database and write new historical records into the database.

[0022] Further, the PCIe link training system further includes a power supply module, which is configured to supply power to each device in the PCIe link training system.

[0023] According to still another aspect of the present invention, there is provided a PCIe communication system, including a target PCIe device, a peer device, and the PCIe link training system as described above.

[0024] The beneficial effects brought by the technical solution provided by the present invention are as follows: The PCIe link training method of the present invention utilizes historical records. When the current state information of the target PCIe device matches the historical records, it directly loads the link configuration, channel mapping, and channel equalization coefficients in the corresponding historical records, thereby skipping the redundant negotiation process, significantly shortening the link training time, reducing latency, and at the same time avoiding repeated negotiation in the same environment, and significantly reducing energy consumption.

[0025] Further, the PCIe link training method of the present invention seamlessly switches to the standard process of traditional PCIe link training after the matching fails, ensuring system reliability, and at the same time updates the database when the training is successful to avoid repeated negotiation next time.

[0026] Further, the PCIe link training method of the present invention has environmental adaptability, can adapt to fluctuations in environmental temperature and interface voltage, avoid training failures caused by fixed parameters, and significantly improve the robustness and energy efficiency ratio of the training system. Description of the Drawings

[0027] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0028] Figure 1 Flow schematic diagram of the PCIe link training method provided for the embodiment; Figure 2 Flow schematic diagram of target historical record screening in the PCIe link training method provided for the embodiment; Figure 3 Specific flow schematic diagram of target historical record screening in the PCIe link training method provided for the embodiment; Figure 4 Flow schematic diagram of the database construction in the PCIe link training method provided for the embodiment; Figure 5 Specific flow schematic diagram of the PCIe link training method provided for the embodiment; Figure 6 Conceptual framework diagram of the PCIe communication system provided for an exemplary embodiment of the present invention. Detailed implementation manners

[0029] In order to enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0030] It should be noted that the terms "first", "next", etc. in the specification and claims of the present invention and the above accompanying drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or equipment comprising a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or equipment.

[0031] It should be noted that in the present invention, the "target PCIe device" refers to the PCIe device at the current moment, and the PCIe device in the environmental temperature and PCIe device interface voltage in the "historical record" is the same PCIe device as the PCIe device in the "target PCIe device".

[0032] In an embodiment of the present invention, a PCIe link training method for establishing a communication connection between a target PCIe device and a peer device is provided. As Figure 1 shown, it includes the following steps: S1: Collect the current status information of the target PCIe device, where the current status information includes the current environmental temperature and the current interface voltage.

[0033] S2: Screen the target historical records matching the current status information in a pre-built database. The database is configured to store the corresponding historical records after the historical PCIe link training is successful. The historical records include the environmental temperature and PCIe device interface voltage, link configuration, channel mapping, and channel equalization coefficient corresponding to the training.

[0034] S3: If a matching historical record is screened, load the link configuration, channel mapping, and channel equalization coefficient in the historical record. The target PCIe device generates a TS1 training sequence with an identifier, which includes the loaded link configuration, channel mapping, and channel equalization coefficient, and sends the TS1 training sequence to the peer device to be connected. In response to the peer device determining that the link configuration, channel mapping, and channel equalization coefficient in the TS1 training sequence meet its own current communication requirements, receive the TS2 reply sequence sent by the peer device, and then the target PCIe device training is successful and enters the communication state.

[0035] In this embodiment, when matching the historical record, directly bypass unnecessary processes such as polling, thus skipping redundant negotiation processes, significantly shortening the link training time. Reusing the historical record also avoids repeated negotiation in the same environment, thus not only effectively solving the high-latency problem of traditional training methods, but also reducing power consumption.

[0036] In this embodiment, it further includes step S4: If no matching historical record is screened, train according to the standard process of PCIe link training, including negotiating the link rate and width, configuring the channel mapping and equalization parameters, obtaining the link configuration, channel mapping, and channel equalization coefficient, and entering the communication state. This embodiment can switch to the standard process after no matching historical record is screened, negotiate to obtain the training result, and ensure robustness.

[0037] The standard process of PCIe link training includes: Detect: Check whether the peer device exists → Polling: Negotiate the link rate (Gen1 / 2 / 3 / 4 / 5) and width (x1 / x2 / x4 / x8 / x16) → Configuration: Configure the lane mapping and equalization parameters → L0: Normal communication state, the link is in full functional normal state, and the link can transmit data.

[0038] In this embodiment, before collecting the current status information of the target PCIe device, a detection step (Detect) is also set to check whether the peer device exists. In this embodiment, if no matching historical record is screened, it will return to the polling of the standard process of PCIe link training and skip the detection.

[0039] Meanwhile, in this embodiment, the current status information, the link configuration, lane mapping, and channel equalization coefficients obtained from this training are added to the database as new historical records. In this embodiment, the device historical record also includes the device identifier of the peer device. The device identifier includes the vendor ID and device ID of the peer device. A peer device can be uniquely determined by the vendor ID and device ID.

[0040] The storage of historical records usually depends on the software configuration table, with high access latency (>1μs), which cannot meet the requirements of real-time decision-making at the hardware layer and limits the potential for performance optimization. In this embodiment, as Figure 4 shown, the database uses an embedded non-volatile memory (eNVM) as the storage medium, preferably MRAM or ReRAM technology, with high durability (more than 100,000 times of erase / write ability) and low access latency (less than 100ns), which can meet the hardware real-time requirements. In the storage design, each historical record contains 32 - 64 bytes of valid data, supports a storage capacity of 16 - 64 records, and the total space is controlled within the range of 512B - 2KB, which is suitable for embedded hardware implementation. An intelligent trigger mechanism is used for updating, and it is automatically recorded each time the training is successful according to the standard process. During retrieval, the hardware will quickly match the historical record based on the current device identifier and current status information, and load the parameters in the historical record. If the match fails, it will automatically fallback to the standard training process, and the historical record will be updated synchronously in the database when the training is successful.

[0041] Specifically, in this embodiment, rough matching is first performed using the device identifier, and then fine matching is performed using the status information to achieve efficient matching. Specifically, the target historical record matching the current status information is screened in the Figure 2 shown manner: S01: Screen the historical records in the database that match the device identifier of the current peer device to obtain the first screening result.

[0042] S02: According to the preset rules, screen the target historical records that match the current status information from the first screening result.

[0043] More specifically, multiple historical records stored in the database form a historical record table. As Figure 3 shown, screen the target historical records that match the current status information through the following method: In the order of the historical record table, sequentially determine whether each historical record meets the following preset rules: The difference between the current ambient temperature and the ambient temperature in the historical record is within the preset temperature difference threshold range, and the difference between the current interface voltage and the PCIe device interface voltage in the historical record is within the preset voltage difference threshold range.

[0044] If it is satisfied, stop screening and use the current historical record that meets the conditions as the target historical record.

[0045] If it is not satisfied, continue to judge the next historical record.

[0046] In this embodiment, the preset temperature difference threshold range is ±2°C. In other embodiments, a larger or smaller temperature difference threshold range can be set according to the detection accuracy and / or fault tolerance, such as ±1.5°C, ±1°C, ±0.5°C.

[0047] In this embodiment, the preset voltage difference threshold range is ±1%. In other embodiments, a larger or smaller range can be set according to the detection accuracy and / or fault tolerance, such as ±1.5%, ±1.2%, ±0.8%, ±0.5%, ±0.2%.

[0048] The setting of the temperature difference threshold range and the voltage difference threshold range is to adapt to the acceptable environmental fluctuations, avoid the training failure caused by fixed parameters in the traditional training method, and significantly improve the robustness and energy efficiency ratio.

[0049] The objectives of this embodiment include achieving nanosecond response through real-time environmental perception and intelligent decision-making. To this end, a high-precision PTAT temperature sensor is used in this embodiment to detect the current ambient temperature of the target PCIe device, and a 12-bit SARADC voltage monitoring circuit is used to detect the current interface voltage of the target PCIe device. The detected current ambient temperature and current interface voltage are digitally processed to provide real-time input for subsequent fast matching. The temperature detection range of the high-precision PTAT temperature sensor covers the industrial grade -40℃ to +125℃, with an accuracy of ±1℃. Interface voltage monitoring can capture ±1% fluctuations in real time and ensure data accuracy through on-chip calibration technology. These monitoring results are digitally processed to provide real-time input for subsequent rapid screening.

[0050] In this embodiment, the fast matching engine adopts an innovative hardware parallel architecture design, and divides the screening process into two stages: efficient rough matching and fine matching according to the above-mentioned preset rules. In the rough matching stage, the historical records with the same device identification as the peer device are quickly screened through hash acceleration technology, significantly narrowing the search range; in the fine matching stage, a dedicated hardware comparator synchronously compares the ambient temperature and interface voltage. The fast matching engine also integrates an early termination mechanism, which stops the search immediately when the target historical record that matches both the ambient temperature and the interface voltage is detected, which improves efficiency and reduces power consumption.

[0051] In this embodiment, the timing is started when determining whether the first historical record meets the preset rules. If after the timing is started, the preset time has passed and no historical record that meets the preset rules has been screened, the screening is stopped, and it is determined that no matching historical record has been found, that is, the screening has failed, and the standard training process is immediately switched to. Specifically, through RTL design and hardening process, a high-performance, low-power and high-reliability decision state machine is realized, and task parallel processing is realized through a carefully designed pipeline architecture. The full process decision from obtaining current state information to screening and loading matching historical records can be completed within 20 clock cycles. The decision state machine has a built-in intelligent fault-tolerant mechanism, including timeout detection and dynamic fallback strategy, to ensure seamless switching to the standard training process when screening fails, thereby ensuring system reliability.

[0052] This embodiment uses clock gating and intermittent sampling technology to optimize power consumption management, critical path optimization to ensure nanosecond response, and multi-stage pipeline design to achieve task parallel processing, thereby improving training efficiency while reducing power consumption.

[0053] In this embodiment, each time a matching target history record is found, the target history record is placed at the top of the history record table. In subsequent training, the most frequently used history records will be matched first, which can reduce the search time. As the number of training times increases, the training efficiency will be further improved.

[0054] In this embodiment, the target PCIe device generates a TS1 training sequence with an identifier in the following manner: Each piece of historical record is configured with a preset item identifier for link configuration, channel mapping, and channel equalization coefficient respectively; Locate the corresponding link configuration, channel mapping, and channel equalization coefficient according to their respective item identifiers, and extract the link configuration, channel mapping, and channel equalization coefficient in parallel to generate a TS1 training sequence.

[0055] Another objective of this embodiment is parameter preloading and quick verification. For this purpose, a Fast Config state is newly added to the LTSSM state machine. The specific process is shown in Figure 5 , on the basis of being fully compatible with the existing PCIe protocol, this embodiment has made an intelligent transformation to the traditional link training process, and shortened the training time through the dynamic state jump logic. In specific implementation, a Fast Config state is extended on the basis of the standard configuration state. When the target historical record is screened, the system directly enters the Fast Config state. At this time, the PHY layer controller will parallelly load the key parameters stored in the target historical record, including link configuration, channel mapping, and channel equalization coefficient, within 5 clock cycles. Subsequently, the target PCIe device generates a TS1 training sequence with an identifier, and continuously sends 16 TS1 training sequences to the peer device. The peer device completes the parameter comparison within 2 TS1 cycles through a dedicated detection circuit, and replies and confirms through the TS2 sequence. It only takes 200 ns to complete the signal quality detection. If the TS2 sequence confirmation is successful, it directly enters the L0 state and enters the normal communication state. If the docking device fails to complete the response within the preset duration (for example, within 5 clock cycles), it will fallback to the polling state of the standard process of PCIe link training for training.

[0056] In another embodiment of the present invention, a PCIe link training system and a PCIe communication system including the PCIe link training system are provided.

[0057] Such as Figure 6As shown, in this embodiment, the PCIe communication system includes a PCIe device, a peer device, and a PCIe link training system. The PCIe link training system is used to establish a communication connection between the PCIe device and the peer device according to the training method described above. In this embodiment, the PCIe link training system includes a training processor, a temperature sensor, a voltage sensor, and a database. The PCIe link training system is configured to execute the PCIe link training method described above. In this embodiment, the temperature sensor is a high-precision PTAT temperature sensor for detecting the ambient temperature of the PCIe device, and it is electrically connected to the training processor. The voltage sensor is used to detect the interface voltage of the PCIe device. It adopts a 12-bit SAR ADC voltage monitoring circuit and is electrically connected to the training processor. The training processor is communicatively connected to the database, the training processor is communicatively connected to the PCIe device, and the PCIe device is communicatively connected to the peer device. The training processor includes an LTSSM state machine and a storage controller. The LTSSM state machine includes a detection state, a polling state, a configuration state, and an L0 state in the standard process of PCIe link training. It also includes a fast configuration state, which is configured to directly configure the channel mapping and equalization parameters in the target historical record when the target historical record is screened. The storage controller is configured to read the historical records in the database and write new historical records into the database. The PCIe link training system further includes a power module, which is configured to provide power for each device in the PCIe link training system. Referring to the training method described above, the training processor screens the target historical record in the database according to the preset screening conditions and loads the screening result into the PCIe device. The PCIe device generates a TS1 sequence and sends it to the peer device, and the peer device replies with a TS2 sequence. In this embodiment, the training processor can also execute the standard process of the PCIe link and store the training results (link configuration, channel mapping, and channel equalization coefficient) and the ambient temperature of the PCIe device and the PCIe device interface voltage corresponding to this training as new historical records into the database.

[0058] The above are only specific embodiments of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A PCIe link training method for establishing a communication connection between a target PCIe device and a peer device, characterized in that, The steps include: Collect the current status information of the target PCIe device, where the current status information includes the current ambient temperature and the current interface voltage; Filter the target historical records that match the current status information in a pre-built database, where the database is configured to store the corresponding historical records after the successful training of the historical PCIe link, and the historical records include the ambient temperature and PCIe device interface voltage, link configuration, channel mapping, and channel equalization coefficient of the PCIe device corresponding to this training; If a matching historical record is filtered, load the link configuration, channel mapping, and channel equalization coefficient in the historical record; The target PCIe device generates a TS1 training sequence with an identifier, which includes the loaded link configuration, channel mapping, and channel equalization coefficient, and sends the TS1 training sequence to the peer device to be connected; In response to the peer device determining that the link configuration, channel mapping, and channel equalization coefficient in the TS1 training sequence meet its own current communication requirements, receive the TS2 reply sequence sent by the peer device, and then the target PCIe device successfully trains and enters the communication state.

2. The PCIe link training method according to claim 1, wherein If no matching historical record is filtered, perform training according to the standard process of PCIe link training, including negotiating the link rate and width, configuring the channel mapping and equalization parameters, obtaining the link configuration, channel mapping, and channel equalization coefficient, and entering the communication state.

3. The PCIe link training method according to claim 2, wherein, Add the current status information and the link configuration, channel mapping, and channel equalization coefficient obtained from this training as a new historical record to the database.

4. The PCIe link training method according to claim 2, wherein If no matching historical record is filtered, return to the polling state of the standard process of PCIe link training and skip the checking state.

5. The PCIe link training method according to claim 1, wherein The historical record also includes the device identifier of the peer device, and the device identifier includes the vendor ID and / or device ID of the peer device. Filter the target historical records that match the current status information in the following way: Filter the historical records in the database that match the device identifier of the current peer device to obtain the first filtering result; According to the preset rules, filter the target historical records that match the current status information from the first filtering result.

6. The PCIe link training method according to any one of claims 1 to 5, characterized in that, The multiple historical records stored in the database form a historical record table; Filter the target historical records that match the current status information in the following way: In the order of the historical record table, sequentially determine whether each historical record meets the following preset rules: The difference between the current ambient temperature and the ambient temperature in the historical record is within the preset temperature difference threshold range, and the difference between the current interface voltage and the PCIe device interface voltage in the historical record is within the preset voltage difference threshold range; If it is satisfied, stop filtering and use the currently satisfied historical record as the target historical record; If it is not satisfied, continue to judge the next historical record.

7. The PCIe link training method according to claim 6, wherein Start timing when judging whether the first historical record meets the preset rules; If after starting the timing, after a preset duration, and no historical record that meets the preset rules is filtered, stop filtering and determine that no matching historical record is found.

8. The PCIe link training method according to claim 6, wherein, After each time a matching target history record is found, the target history record is placed at the top of the history record table.

9. The PCIe link training method according to claim 1, wherein The target PCIe device generates a TS1 training sequence with a marker in the following manner: In each historical record, link configuration, channel mapping, and channel equalization coefficient are respectively configured with preset item identifiers; The corresponding link configuration, channel mapping, and channel equalization coefficient are located according to their respective item identifiers, and the link configuration, channel mapping, and channel equalization coefficient are extracted in parallel to generate the TS1 training sequence.

10. The PCIe link training method according to claim 1, wherein, The target PCIe device sends a plurality of TS1 training sequences to the opposite device, and starts timing when sending the first TS1 training sequence; If the preset time period has elapsed after the timing is started and the TS2 reply sequence is not received, the training is performed according to the standard process of PCIe link training.

11. A PCIe link training system, characterized in that, The PCIe link training system comprises a training processor, a temperature sensor, a voltage sensor and a database, and is configured to execute the PCIe link training method according to any one of claims 1 to 10.

12. The PCIe link training system according to claim 11, wherein The training processor includes an LTSSM state machine, which includes a detection state, a polling state, a configuration state and an L0 state in a standard process of PCIe link training. The LTSSM state machine also includes a fast configuration state, and the fast configuration state is configured to directly configure the channel mapping and equalization parameters in the target historical record when the target historical record is screened.

13. The PCIe link training system according to claim 11, wherein The training processor includes a storage controller configured to read historical records in the database and write new historical records in the database; And / or, the PCIe link training system further includes a power module configured to provide power to each device in the PCIe link training system.

14. A PCIe communication system, characterized in that, The invention comprises a target PCIe device, a peer device and a PCIe link training system as claimed in any one of claims 11 to 13.

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