A PCIe link training method, a training system and a communication system

Abstract

The application discloses a PCIe link training method, a training system and a communication system. The PCIe link training method comprises the following steps: collecting current state information (current environmental temperature and current interface voltage) of a target PCIe device; screening a target historical record matched with the current state information in a database, wherein the historical record comprises environmental temperature and interface voltage of the PCIe device, link configuration, channel mapping and channel equalization coefficient corresponding to each training of the PCIe device; if the target historical record is screened, loading the link configuration, channel mapping and channel equalization coefficient in the historical record; the target PCIe device generates a TS1 training sequence and sends the TS1 training sequence to a peer device; in response to the fact that parameters in the TS1 training sequence meet communication requirements determined by the peer device, receiving a TS2 reply sequence sent by the peer device, and the target PCIe device enters a communication state. The application can shorten the link training time and avoid repeated negotiation.

Description

Technical Field

[0001] This invention relates to the field of PCIe communication, and more particularly to a PCIe link training method, training system, and communication system. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard widely used in servers, storage, networking, and other fields. The PCIe link is the core of PCIe communication, responsible for transmitting data between devices. During PCIe device initialization or link reset, a stable communication connection needs to be established through link training.

[0003] Traditional PCIe link training methods include processes such as detecting peer devices, negotiating link speed and bandwidth, configuring channel mapping, and equalization parameters. However, with the widespread adoption of PCIe Gen5 (speeds up to 32GT / s), traditional PCIe link training methods face many challenges, such as high latency, redundant computation, and wasted power consumption.

[0004] In traditional PCIe link training, the Link Training State Machine (LTSSM) needs to perform rate negotiation and balancing step by step, and cannot skip unnecessary steps. This leads to significant latency at Gen5's high data rates, affecting the overall system response speed. This latency becomes a performance bottleneck in scenarios such as data center hot-plugging and real-time computing (e.g., AI inference, high-frequency trading).

[0005] Traditional PCIe link training systems lack historical learning capabilities. Each time the link is powered on or reset, a traditional LTSSM must be trained from scratch, unable to reuse historically successful parameters (such as peer device ID and equalization coefficients). This design ignores the reusability of identical devices under the same environment, leading to redundant negotiation overhead. Even under the same environment (e.g., unchanged temperature, voltage, and device configuration), traditional PCIe link training methods still require re-executing the entire link training process, repeatedly negotiating rates, channel mappings, and equalization parameters. This not only wastes time and computing power but also causes frequent activation of the PHY layer circuitry, increasing dynamic power consumption. For example, after a server restart, the PCIe link between the GPU and the switch must be completely retrained, even if environmental parameters remain unchanged. This inefficient design is particularly pronounced in mobile devices and edge computing nodes, limiting energy efficiency optimization. Furthermore, traditional PCIe link training lacks historical learning capabilities; each time the link is powered on or reset, a traditional LTSSM must be trained from scratch, unable to reuse historically successful parameters (such as peer device ID and equalization coefficients). This design ignores the reusability of the same equipment in the same environment, resulting in redundant negotiation overhead.

[0006] Furthermore, traditional PCIe link training methods use fixed training parameters, which cannot dynamically adapt to environmental fluctuations (such as temperature and voltage) that can lead to communication connection failures. For example, increased temperature may cause signal attenuation, while voltage fluctuations may cause timing deviations. In such cases, fixed parameters are prone to causing training failures, triggering recovery states, or even link interruptions. Due to the lack of real-time environmental awareness, the system cannot proactively adjust parameters and can only restore the connection through retry mechanisms, further increasing latency and uncertainty.

[0007] The above background information is provided only to aid in understanding the concept and technical solution of this application. It does not necessarily belong to the prior art of this application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above information was disclosed before the filing date of this application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0008] The purpose of this invention is to provide a PCIe link training method, training system, and communication system that shortens link training time and avoids repeated negotiation.

[0009] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0010] A PCIe link training method for establishing a communication connection between a target PCIe device and a peer device includes the following steps:

[0011] Collect the current status information of the target PCIe device, including the current ambient temperature and the current interface voltage;

[0012] The database is used to filter target historical records that match the current state information. The database is configured to store the corresponding historical records after the historical PCIe link is successfully trained. The historical records include the ambient temperature of the PCIe device corresponding to the training, the PCIe device interface voltage, link configuration, channel mapping and channel equalization coefficient.

[0013] If a matching historical record is found, the link configuration, channel mapping, and channel equalization coefficient in that historical record will be loaded.

[0014] The target PCIe device generates a TS1 training sequence with an identifier, which includes the loaded link configuration, channel mapping and channel equalization coefficient, and sends the TS1 training sequence to the peer device to be connected;

[0015] In response to the peer device determining that the link configuration, channel mapping, and channel equalization coefficient in the TS1 training sequence meet its current communication needs, the target PCIe device receives the TS2 response sequence sent by the peer device, and thus the target PCIe device successfully enters the communication state after training.

[0016] Furthermore, if no matching historical records are found, training is performed according to the standard PCIe link training process, including negotiating link speed and bandwidth, configuring channel mapping and equalization parameters, obtaining link configuration, channel mapping and channel equalization coefficients, and entering the communication state.

[0017] Furthermore, following any one or a combination of the aforementioned technical solutions, if the docking device fails to respond within 5 clock cycles, it will fall back to the standard PCIe link training process of polling for training.

[0018] Furthermore, following any one or a combination of the aforementioned technical solutions, the current state information, along with the link configuration, channel mapping, and channel equalization coefficients obtained during this training, are added to the database as new historical records.

[0019] Furthermore, following any one or a combination of the aforementioned technical solutions, the historical record also includes the device identifier of the peer device, which includes the supplier ID and / or device ID of the peer device.

[0020] Target historical records that match the current state information are filtered using the following method:

[0021] Filter the historical records in the database that match the device identifier of the current peer device to obtain the first filtering result;

[0022] According to preset rules, target historical records that match the current state information are filtered from the first filtering results.

[0023] Furthermore, based on any one or a combination of the aforementioned technical solutions, the multiple historical records stored in the database form a historical record table;

[0024] Target historical records that match the current state information are filtered using the following method:

[0025] Following the order of the historical record table, determine whether each historical record satisfies the following preset rules:

[0026] The difference between the current ambient temperature and the ambient temperature in the historical records is within the preset temperature difference threshold range, and the difference between the current interface voltage and the PCIe device interface voltage in the historical records is within the preset voltage difference threshold range.

[0027] If the conditions are met, stop filtering and use the current history that meets the conditions as the target history.

[0028] If the condition is not met, continue to check the next historical record.

[0029] Furthermore, following any one or a combination of the aforementioned technical solutions, timing is initiated when determining whether the first historical record meets the preset rules;

[0030] If, after the preset time has elapsed since the start of the timer, no historical records matching the preset rules have been found, the filtering will stop and the system will be determined that no matching historical records have been found.

[0031] Furthermore, following any one or a combination of the aforementioned technical solutions, after each matching target historical record is found, the target historical record is pinned to the top of the historical record table.

[0032] Furthermore, following any one or a combination of the aforementioned technical solutions, the target PCIe device generates an identified TS1 training sequence in the following manner:

[0033] Each historical record contains preset item identifiers for link configuration, channel mapping, and channel equalization coefficient.

[0034] The corresponding link configuration, channel mapping, and channel equalization coefficient are located based on their respective item identifiers, and the link configuration, channel mapping, and channel equalization coefficients are extracted in parallel to generate the TS1 training sequence.

[0035] Furthermore, following any one or a combination of the aforementioned technical solutions, the target PCIe device sends multiple TS1 training sequences to the peer device, and starts timing when sending the first TS1 training sequence;

[0036] If, after the preset time has elapsed since the start of the timer, no TS2 response sequence has been received, then training will proceed according to the standard PCIe link training process. When returning to the standard process, the check state can be skipped.

[0037] According to another aspect of the present invention, a PCIe link training system is provided, including a training processor, a temperature sensor, a voltage sensor, and a database, the PCIe link training system being configured to perform the PCIe link training method as described above.

[0038] Furthermore, the training processor includes an LTSSM state machine, which includes the detection state, polling state, configuration state, and L0 state in the standard process of PCIe link training, and also includes a fast configuration state, which is configured to: when the target historical record is filtered, directly configure the channel mapping and equalization parameters in the target historical record.

[0039] Furthermore, the training processor includes a storage controller configured to read historical records from the database and write new historical records to the database.

[0040] Furthermore, the PCIe link training system also includes a power module configured to provide power to the various devices in the PCIe link training system.

[0041] According to another aspect of the present invention, a PCIe communication system is provided, including a target PCIe device, a peer device, and a PCIe link training system as described above.

[0042] The beneficial effects of the technical solution provided by this invention are as follows:

[0043] The PCIe link training method of the present invention utilizes historical records. When the current state information of the target PCIe device matches the historical records, the link configuration, channel mapping and channel equalization coefficient in the corresponding historical records are directly loaded. This skips redundant negotiation processes, significantly shortens link training time, reduces latency, and avoids repeated negotiation in the same environment, thus significantly reducing energy consumption.

[0044] Furthermore, the PCIe link training method of the present invention seamlessly switches to the standard process of traditional PCIe link training after a matching failure, ensuring system reliability. At the same time, it updates the database when training is successful, avoiding repeated negotiation in the next round.

[0045] Furthermore, the PCIe link training method of the present invention is environmentally adaptable, capable of adapting to fluctuations in ambient temperature and interface voltage, avoiding training failures caused by fixed parameters, and significantly improving the robustness and energy efficiency of the training system. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A flowchart illustrating the PCIe link training method provided in this embodiment;

[0048] Figure 2 A schematic diagram of the target history filtering process in the PCIe link training method provided in the embodiment;

[0049] Figure 3 A schematic diagram illustrating the specific process of target history filtering in the PCIe link training method provided in this embodiment;

[0050] Figure 4 A schematic diagram illustrating the database construction process in the PCIe link training method provided in this embodiment;

[0051] Figure 5 A schematic diagram illustrating the specific process of the PCIe link training method provided in this embodiment;

[0052] Figure 6 A conceptual framework diagram of a PCIe communication system provided for an exemplary embodiment of the present invention. Detailed Implementation

[0053] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0054] It should be noted that the terms "first," "next," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0055] It should be noted that in this invention, "target PCIe device" refers to the PCIe device at the current moment. The PCIe device in the "historical record" with the ambient temperature and PCIe device interface voltage is the same PCIe device as the PCIe device in "target PCIe device".

[0056] In one embodiment of the present invention, a PCIe link training method is provided for establishing a communication connection between a target PCIe device and a peer device, such as... Figure 1 As shown, it includes the following steps:

[0057] S1: Collect the current status information of the target PCIe device, including the current ambient temperature and the current interface voltage.

[0058] S2: Filter the target historical records that match the current status information in the pre-built database. The database is configured to store the corresponding historical records after the historical PCIe link is successfully trained. The historical records include the ambient temperature of the PCIe device corresponding to the training, the PCIe device interface voltage, link configuration, channel mapping and channel equalization coefficient.

[0059] S3: If a matching historical record is found, the link configuration, channel mapping, and channel equalization coefficient in the historical record are loaded. The target PCIe device generates a TS1 training sequence with an identifier, which includes the loaded link configuration, channel mapping, and channel equalization coefficient. The TS1 training sequence is then sent to the peer device to be connected. In response to the peer device determining that the link configuration, channel mapping, and channel equalization coefficient in the TS1 training sequence meet its current communication requirements, the target PCIe device receives the TS2 response sequence sent by the peer device. Thus, the target PCIe device successfully trains and enters the communication state.

[0060] In this embodiment, unnecessary processes such as polling are bypassed when matching historical records, thereby skipping redundant negotiation processes, significantly shortening the link training time. Reusing historical records also avoids repeated negotiation in the same environment, thus not only effectively solving the high latency problem of traditional training methods, but also reducing power consumption.

[0061] In this embodiment, step S4 is also included: if no matching historical records are found, training is performed according to the standard PCIe link training process, including negotiating the link rate and bandwidth, configuring channel mapping and equalization parameters, obtaining the link configuration, channel mapping and channel equalization coefficients, and entering the communication state. This embodiment can switch to the standard process after no matching historical records are found, negotiate to obtain the training results, and ensure robustness.

[0062] The standard process for training a PCIe link includes: Detect: Check if the peer device exists → Polling: Negotiate the link rate (Gen1 / 2 / 3 / 4 / 5) and width (x1 / x2 / x4 / x8 / x16) → Configuration: Configure the lane mapping and equalization parameters → L0: Normal communication state, the link is fully functional and can transmit data.

[0063] In this embodiment, a detection step is set before collecting the current status information of the target PCIe device to check whether the peer device exists. In this embodiment, if no matching historical records are found, the process returns to the standard polling process of PCIe link training and skips the detection.

[0064] In this embodiment, the current state information, along with the link configuration, channel mapping, and channel equalization coefficients obtained during this training, are added to the database as new historical records. In this embodiment, the device history also includes the device identifier of the peer device, which includes the vendor ID and device ID of the peer device. The vendor ID and device ID can uniquely identify a peer device.

[0065] Historical data storage typically relies on software configuration tables, resulting in high access latency (>1μs), which fails to meet the real-time decision-making requirements of the hardware layer and limits the potential for performance optimization. In this embodiment, as... Figure 4As shown, the database uses embedded non-volatile memory (eNVM) as the storage medium, preferably MRAM or ReRAM technology, which features high durability (over 100,000 erase / write cycles) and low access latency (below 100ns), meeting the real-time requirements of the hardware. In terms of storage design, each historical record contains 32-64 bytes of valid data, supporting a storage capacity of 16-64 records, with the total space controlled within the range of 512B-2KB, suitable for embedded hardware implementation. An intelligent trigger mechanism is used for updates, automatically recording each successful training session following the standard procedure. During retrieval, the hardware quickly matches historical records based on the current device identifier and current status information, loading the data using the parameters from the historical records. If a match fails, it automatically reverts to the standard training process, and upon successful training, synchronously updates the historical records in the database.

[0066] Specifically, in this embodiment, coarse matching is first performed using device identifiers, followed by fine matching using status information, achieving efficient matching. Specifically, through... Figure 2 The method shown is for filtering target historical records that match the current status information:

[0067] S01: Filter the historical records in the database that match the device identifier of the current peer device to obtain the first filtering result.

[0068] S02: According to the preset rules, filter the target historical records that match the current status information from the first filtering results.

[0069] More specifically, multiple historical records stored in the database form a history table. For example... Figure 3 As shown, target historical records that match the current state information are filtered in the following way:

[0070] Following the order of the historical record table, determine whether each historical record satisfies the following preset rules:

[0071] The difference between the current ambient temperature and the ambient temperature in the historical records is within the preset temperature difference threshold range, and the difference between the current interface voltage and the PCIe device interface voltage in the historical records is within the preset voltage difference threshold range.

[0072] If the condition is met, the filtering stops, and the current history that meets the condition is used as the target history.

[0073] If the condition is not met, continue to check the next historical record.

[0074] In this embodiment, the preset temperature difference threshold range is ±2℃. In other embodiments, a larger or smaller temperature difference threshold range can be set according to the detection accuracy and / or fault tolerance, such as ±1.5℃, ±1℃, ±0.5℃.

[0075] In this embodiment, the preset voltage difference threshold range is ±1%. In other embodiments, a larger or smaller range can be set according to the detection accuracy and / or fault tolerance, such as ±1.5%, ±1.2%, ±0.8%, ±0.5%, ±0.2%.

[0076] The temperature difference threshold range and voltage difference threshold range are set to adapt to acceptable environmental fluctuations, avoiding training failures caused by fixed parameters in traditional training methods, and significantly improving robustness and energy efficiency.

[0077] The objective of this embodiment is to achieve nanosecond-level response through real-time environmental perception and intelligent decision-making. To this end, a high-precision PTAT temperature sensor is used to detect the current ambient temperature of the target PCIe device, and a 12-bit SARADC voltage monitoring circuit is used to detect the current interface voltage of the target PCIe device. The detected ambient temperature and current interface voltage are digitized to provide real-time input for subsequent rapid matching. The high-precision PTAT temperature sensor has a temperature detection range covering industrial-grade -40℃ to +125℃, with an accuracy of ±1℃. The interface voltage monitoring can capture fluctuations of ±1% in real time, and on-chip calibration technology ensures data accuracy. These monitoring results, after digitization, provide real-time input for subsequent rapid screening.

[0078] In this embodiment, the fast matching engine employs an innovative hardware parallel architecture design, dividing the filtering process into two stages: efficient coarse matching and fine matching, according to the aforementioned preset rules. In the coarse matching stage, hash acceleration technology is used to quickly filter historical records with the same device identifier as the peer device, significantly narrowing the search range. In the fine matching stage, a dedicated hardware comparator synchronously compares ambient temperature and interface voltage. The fast matching engine also integrates an early termination mechanism, immediately stopping the search when a target historical record with matching ambient temperature and interface voltage is detected, improving efficiency and reducing power consumption.

[0079] In this embodiment, a timer is started when determining whether the first historical record meets a preset rule. If, after a preset time has elapsed and no historical record meeting the preset rule is found, the filtering stops, and it is determined that no matching historical record was found, i.e., the filtering fails, and the system immediately switches to the standard training process. Specifically, through RTL design and hardening processes, a high-performance, low-power, and highly reliable decision state machine is achieved. A carefully designed pipeline architecture enables parallel task processing, allowing the entire decision-making process—from acquiring the current state information to finding and loading a matching historical record—to be completed within 20 clock cycles. The decision state machine incorporates an intelligent fault-tolerance mechanism, including timeout detection and a dynamic rollback strategy, ensuring a seamless switch to the standard training process when filtering fails, thus guaranteeing system reliability.

[0080] This embodiment employs clock gating and intermittent sampling techniques to optimize power consumption management, critical path optimization to ensure nanosecond-level response, and multi-stage pipeline design to achieve parallel task processing, thereby improving training efficiency while reducing power consumption.

[0081] In this embodiment, after each matching target history record is found, the target history record is placed at the top of the history record table. In subsequent training, the most frequently used history records will be matched first, which can reduce search time. As the number of training sessions increases, the training efficiency will be further improved.

[0082] In this embodiment, the target PCIe device generates an identifiable TS1 training sequence in the following manner:

[0083] Each historical record contains preset item identifiers for link configuration, channel mapping, and channel equalization coefficient.

[0084] Based on their respective item identifiers, the corresponding link configuration, channel mapping, and channel equalization coefficients are located, and the link configuration, channel mapping, and channel equalization coefficients are extracted in parallel to generate TS1 training sequences.

[0085] This embodiment also aims to preload parameters and perform rapid verification. To this end, this embodiment adds a Fast Config state to the LTSSM state machine. See details in the documentation. Figure 5 This embodiment, while fully compatible with existing PCIe protocols, intelligently transforms the traditional link training process, shortening training time through dynamic state transition logic. Specifically, it extends the standard configuration state with a fast configuration state. When a target historical record is selected, the system directly enters the fast configuration state. At this time, the PHY layer controller loads key parameters stored in the target historical record in parallel over 5 clock cycles, including link configuration, channel mapping, and channel equalization coefficients. Subsequently, the target PCIe device generates 16 TS1 training sequences with identifiers and continuously sends them to the peer device. The peer device completes parameter comparison within 2 TS1 cycles using a dedicated detection circuit and confirms via a TS2 sequence. Signal quality detection can be completed in just 200ns. If the TS2 sequence confirmation is successful, it directly enters the L0 state, entering normal communication. If the peer device does not respond within a preset time (e.g., within 5 clock cycles), it reverts to the polling state of the standard PCIe link training process for training.

[0086] In another embodiment of the present invention, a PCIe link training system and a PCIe communication system containing the PCIe link training system are provided.

[0087] like Figure 6As shown, in this embodiment, the PCIe communication system includes a PCIe device, a peer device, and a PCIe link training system. The PCIe link training system establishes a communication connection between the PCIe device and the peer device according to the training method described above. In this embodiment, the PCIe link training system includes a training processor, a temperature sensor, a voltage sensor, and a database. The PCIe link training system is configured to execute the PCIe link training method described above. In this embodiment, the temperature sensor is a high-precision PTAT temperature sensor that detects the ambient temperature of the PCIe device and is electrically connected to the training processor. The voltage sensor is used to detect the interface voltage of the PCIe device and employs a 12-bit SAR ADC voltage monitoring circuit; it is electrically connected to the training processor. The training processor is communicatively connected to the database, the PCIe device, and the peer device. The training processor includes an LTSSM state machine and a memory controller. The LTSSM state machine includes the detection state, polling state, configuration state, and L0 state from the standard PCIe link training process, and also includes a fast configuration state. The fast configuration state is configured to directly configure the channel mapping and equalization parameters in the target historical record when a target historical record is found. The storage controller is configured to read historical records from the database and write new historical records to the database. The PCIe link training system also includes a power module configured to provide power to each device in the PCIe link training system. Referring to the training method described above, the training processor filters target historical records in the database according to preset filtering conditions and loads the filtering results into the PCIe device. The PCIe device generates a TS1 sequence and sends it to the peer device, which replies with a TS2 sequence. In this embodiment, the training processor can also execute the standard PCIe link process and store the training results (link configuration, channel mapping, and channel equalization coefficients) and the ambient temperature and PCIe device interface voltage of the corresponding PCIe device as new historical records in the database.

[0088] The above description is only a specific embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A PCIe link training method for establishing a communication connection between a target PCIe device and a peer device, characterized in that, Includes the following steps: Collect the current status information of the target PCIe device, including the current ambient temperature and the current interface voltage; The database is configured to filter target historical records that match the current status information. The database is configured to store the corresponding historical records after the historical PCIe link is successfully trained. The historical records include the ambient temperature and PCIe device interface voltage, link configuration, channel mapping, channel equalization coefficient and device identifier of the peer device corresponding to the training. The device identifier includes the vendor ID and / or device ID of the peer device. If no matching historical record is found, training is performed according to the standard process of PCIe link training, including negotiating link rate and bandwidth, configuring channel mapping and equalization parameters, obtaining link configuration, channel mapping and channel equalization coefficients, entering the communication state, and adding the current state information and the link configuration, channel mapping and channel equalization coefficients obtained in this training as new historical records to the database. If a matching historical record is found, the link configuration, channel mapping, and channel equalization coefficient in that historical record will be loaded. The target PCIe device generates a TS1 training sequence with an identifier, which includes the loaded link configuration, channel mapping and channel equalization coefficient, and sends the TS1 training sequence to the peer device to be connected; In response to the peer device determining that the link configuration, channel mapping, and channel equalization coefficients in the TS1 training sequence meet its current communication needs, the target PCIe device receives the TS2 response sequence sent by the peer device. Subsequently, the target PCIe device successfully enters the communication state after training. The target PCIe device sends multiple TS1 training sequences to the peer device. A timer is started when the first TS1 training sequence is sent. If, after a preset time has elapsed since the timer started, no TS2 response sequence is received, training proceeds according to the standard PCIe link training process. When returning to the standard process, the check state is skipped. The database stores multiple historical records to form a historical record table, and the target historical record that matches the current status information is filtered using the following method: Filter the historical records in the database that match the device identifier of the current peer device to obtain the first filtering result; According to the order of the historical records table, and based on the preset rules, target historical records that match the current status information are filtered from the first filtering results. The preset rules are: the difference between the current ambient temperature and the ambient temperature in the historical records is within the preset temperature difference threshold range, and the difference between the current interface voltage and the PCIe device interface voltage in the historical records is within the preset voltage difference threshold range. If the conditions are met, the filtering stops, and the current history that meets the conditions is used as the target history, which is then pinned to the top of the history table. If the condition is not met, continue to check the next historical record; The timer starts when it determines whether the first historical record meets the preset rules; if the preset time has elapsed after the timer starts and no historical record that meets the preset rules has been found, the filtering stops and it is determined that no matching historical record has been found.

2. The PCIe link training method according to claim 1, characterized in that, If no matching historical record is found, the process returns to the polling state of the standard PCIe link training process, skipping the checking state.

3. The PCIe link training method according to claim 1, characterized in that, The target PCIe device generates identifiable TS1 training sequences in the following manner: Each historical record contains preset item identifiers for link configuration, channel mapping, and channel equalization coefficient. The corresponding link configuration, channel mapping, and channel equalization coefficient are located based on their respective item identifiers, and the link configuration, channel mapping, and channel equalization coefficients are extracted in parallel to generate the TS1 training sequence.

4. A PCIe link training system, characterized in that, The PCIe link training system includes a training processor, a temperature sensor, a voltage sensor, and a database, and is configured to perform the PCIe link training method according to any one of claims 1 to 3.

5. The PCIe link training system according to claim 4, characterized in that, The training processor includes an LTSSM state machine, which includes detection state, polling state, configuration state and L0 state in the standard process of PCIe link training. The LTSSM state machine also includes a fast configuration state, which is configured to: when the target historical record is filtered, directly configure the channel mapping and channel equalization coefficient in the target historical record.

6. The PCIe link training system according to claim 4, characterized in that, The training processor includes a storage controller configured to read historical records from the database and write new historical records to the database; And / or, the PCIe link training system further includes a power module configured to provide power to the various devices in the PCIe link training system.

7. A PCIe communication system, characterized in that, It includes the target PCIe device, the peer device, and the PCIe link training system according to any one of claims 4 to 6.

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