Method for converting multi-path parallel interface into time division multiplexing multi-path parallel interface

Abstract

The invention relates to a method for converting a multi-path parallel interface into a time division multiplexing multi-path parallel interface, which comprises a PCB (Printed Circuit Board), an FPGA (Field Programmable Gate Array), a clock circuit, a download debugging circuit, a QSPIFLASH circuit, a reset circuit, a power supply circuit and an input and output circuit are integrated on the PCB, and the FPGA is respectively connected with the clock circuit, the download debugging circuit, the QSPIFLASH circuit, the reset circuit, the power supply circuit and the input and output circuit. The clock circuit is used for providing a global clock, the download debugging circuit is used for debugging the PFGA, the QSPIFLASH circuit is used for storing configuration Bin files of the FPGA and other user data files, the reset circuit is used for resetting the FPGA, the power supply circuit is used for providing a power supply, and the input and output driving circuit is used for inputting and outputting signals. According to the invention, data can be split into two channel data components, namely a channel A and a channel B, and the data is transmitted in a time division multiplexing manner.

Description

Technical Field

[0001] The present invention belongs to the technical field of parallel data transmission, and particularly relates to a method for converting a multi-channel parallel interface into a time-division multiplexing multi-channel parallel interface. Background Art

[0002] Parallel transmission refers to the transmission of data in groups on multiple parallel channels simultaneously, that is, the transmission in which multiple data bits are simultaneously transmitted between devices. Commonly, several binary codes constituting a character are simultaneously transmitted on several parallel channels respectively. During parallel transmission, a character can be transmitted at a time, and there is no synchronization problem between the transceiver; and the speed is fast and the control method is simple. Since parallel transmission requires multiple physical channels, parallel transmission is suitable for use in scenarios with short distances and high required transmission speeds. Previously, for the decomposition of parallel transmission, discrete component design was adopted, with complex logic, requiring manual control and low efficiency. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and propose a method for converting a multi-channel parallel interface into a time-division multiplexing multi-channel parallel interface, which can split data into two channel data components of Channel A and Channel B and transmit them in a time-division multiplexing manner.

[0004] The present invention solves its technical problems by adopting the following technical solutions:

[0005] A device for converting a multi-channel parallel interface into a time-division multiplexing multi-channel parallel interface includes a PCB board, on which an FPGA, a clock circuit, a download and debugging circuit, a QSPI FLASH circuit, a reset circuit, a power supply circuit, and an input and output circuit are integrated. The FPGA is respectively connected to the clock circuit, the download and debugging circuit, the QSPI FLASH circuit, the reset circuit, the power supply circuit, and the input and output circuit. The clock circuit is used to provide a global clock, the download and debugging circuit is used to debug the PFGA, the QSPI FLASH circuit is used to store the configuration Bin file of the FPGA and other user data files, the reset circuit is used to reset the FPGA, the power supply circuit is used to provide power, and the input and output drive circuit is used to input signals and output signals.

[0006] Moreover, the clock circuit includes OT503250MIBA4SL and its peripheral circuits. The clock circuit provides a single-ended 50 MHz FPGA system clock source, and the output of the clock circuit is connected to the FPGA CLK pin to form a global clock.

[0007] Moreover, the download and debugging circuit includes JTAG and its peripheral circuits.

[0008] Moreover, the QSPI FLASH circuit includes the EFM25F128A and its peripheral circuits, and the N250128A138S240P / NC machine peripheral circuits. One QSPI FLASH circuit is used to store the configuration Bin file of the FPGA and other user data files, and the other QSPI FLASH circuit is used as a backup.

[0009] Moreover, the reset circuit is connected to the PROGRAM_B pin of the FPGA for reset.

[0010] Moreover, the power supply circuit includes the LTM4644 and its peripheral circuits. The +5V power supply input generates 4 paths of 1.0V power through the power supply chip LTM4644. Among them, 2 paths provide stable power for the VCCINT and VCCBRAM of the FPGA, and the other 2 paths provide stable power for the MGTAVCC of the GTX; the +5V power supply input generates +1.5V, +1.8V, +1.2V and +3.3V power respectively through the power supply chip LTM4644. LTM4644 supplies power to VCCAUX, VCCAUX_IO, VCCIO, DRR3, crystal oscillator and FLASH, and the 1.2V DC supplies power to MGTAVTT.

[0011] Moreover, the input / output drive circuit includes an input signal isolation and conversion circuit and an output signal isolation and conversion circuit. Among them, the input signal isolation and conversion circuit includes the NS18140WO1 and its peripheral circuits, and the output signal isolation and conversion circuit includes the NS18140WO2 and its peripheral circuits, and the latch signal and the data fetch signal are reserved to be output to the output connector through the FPGA.

[0012] A method for converting a multi-channel parallel interface to a time-division multiplexed multi-channel parallel interface includes the following steps:

[0013] Step 1: Set the input terminal signals according to the constructed interface;

[0014] Step 2: Set the output terminal signals according to the constructed interface;

[0015] Step 3: Set the timing signals according to the constructed interface to complete the parallel transmission function of the interface.

[0016] Moreover, the input terminal signals in Step 1 include: 1-bit latch signal, 2-bit data fetch signal, data signal, 1-bit data busy signal and 1-bit GD flag signal.

[0017] The output terminal in Step 2 includes Channel A and Channel B. Among them, the highest bit weight value of the data in Channel A is 180°, and the highest bit weight value of the data in Channel B is 180°×2 －7, the data format at the output end is as follows: the data bits of channel A and channel B are multiplexed by 14 bits, 1 latch signal LATCH_OUT, and 2 data fetch signals.

[0018] Moreover, the specific implementation method of step 3 is as follows: both the latch signal and the data fetch signal are valid for negative pulses, and the pulse width of the data fetch signal is greater than 1 μs; first, the latch signal is sent, and then the data fetch signal is sent. The data fetch starts 80 ns after the falling edge of the data fetch signal, and the next data fetch signal is allowed to be sent 0.5 μs after the rising edge of the data fetch signal.

[0019] The advantages and positive effects of the present invention are:

[0020] The present invention includes a PCB board, on which an FPGA, a clock circuit, a download and debugging circuit, a QSPI FLASH circuit, a reset circuit, a power supply circuit, and an input / output circuit are integrated. The FPGA is respectively connected to the clock circuit, the download and debugging circuit, the QSPI FLASH circuit, the reset circuit, the power supply circuit, and the input / output circuit. The clock circuit is used to provide a global clock, the download and debugging circuit is used to debug the PFGA, the QSPI FLASH circuit is used to store the configuration Bin file of the FPGA and other user data files, the reset circuit is used to implement the reset of the FPGA, the power supply circuit is used to provide power, and the input / output drive circuit is used to input signals and output signals. The present invention can split data into two-channel data components of channel A and channel B and transmit them in a time-division multiplexing manner. Description of the Drawings

[0021] Figure 1 is the block diagram of the parallel data transmission structure of the present invention;

[0022] Figure 2 is the timing diagram of the output data of the present invention;

[0023] Figure 3 is the schematic diagram of the circuit board structure design of the present invention;

[0024] Figure 4 is the circuit diagram of the clock source of the present invention;

[0025] Figure 5 is the JTAG circuit diagram of the present invention;

[0026] Figure 6 is the QSPI FLASH circuit diagram of the present invention;

[0027] Figure 7 is the reset circuit diagram of the present invention;

[0028] Figure 8 is the power supply circuit diagram of the present invention;

[0029] Figure 9Circuit diagram for input signal isolation conversion of the present invention;

[0030] Figure 10 Circuit diagram for output signal isolation conversion of the present invention;

[0031] Figure 11 Circuit diagram for configuration completion indicator light of the present invention;

[0032] Figure 12 Circuit diagram for channel selection instruction indicator light of the present invention;

[0033] Figure 13 Circuit diagram for reserved interface of the present invention. Detailed implementation mode

[0034] The present invention will be further described in detail below with reference to the accompanying drawings.

[0035] A device for converting a multi-channel parallel interface to a time-division multiplexed multi-channel parallel interface includes a PCB board, on which an FPGA, a clock circuit, a download and debugging circuit, a QSPI FLASH circuit, a reset circuit, a power supply circuit, and an input / output circuit are integrated. The FPGA is respectively connected to the clock circuit, the download and debugging circuit, the QSPI FLASH circuit, the reset circuit, the power supply circuit, and the input / output circuit. The clock circuit is used to provide a global clock, the download and debugging circuit is used to debug the PFGA, the QSPI FLASH circuit is used to store the configuration Bin file of the FPGA and other user data files, the reset circuit is used to reset the FPGA, the power supply circuit is used to provide power, and the input / output driving circuit is used for input signals and output signals.

[0036] As Figure 3 shown, the size requirement of the PCB is (228.6×152.4×2)mm. To meet the requirements of the electronic chassis size and the structural strength of the circuit board, a reinforcing rib structure is designed in the middle of the PCB board to enhance the protection of the PCB board; to meet the requirements of the user for in-board testing of the circuit board, a detection hole and an indicator light test strip are designed on the side of the circuit board facing the user end to enhance the user's test friendliness; to meet the requirements of convenient disassembly and assembly of the circuit board, wrenches are designed on both sides of the detection hole and the indicator light test strip to facilitate the user to easily pull out the circuit board; to meet the requirements of the circuit board for locking tightness, locking tight strips are designed on both sides of the circuit board facing the user end, and the fastening part adopts a design of a flat head screw with a cross-shaped small pattern, which can be operated with conventional tools on the market, reducing the requirement for the specificity of the operating tool.

[0037] As Figure 4 shown, the clock circuit includes OT503250MIBA4SL and its peripheral circuits. The clock circuit provides a single-ended 50MHz FPGA system clock source, and the output of the clock circuit is connected to the FPGA CLK pin to form a global clock.

[0038] As Figure 5 shown, a 14PIN JTAG download and debugging interface is designed on the circuit board to facilitate the user to debug the FPGA independently.

[0039] As Figure 6 shown, the QSPI FLASH circuit includes two 128Mbit Quad-SPI Flash chips, model EFM25F128A and its peripheral circuit, and the N250128A138S240P / NC machine peripheral circuit. One QSPI FLASH circuit is used to store the configuration Bin file of the FPGA and other user data files, and the other QSPI FLASH circuit is used as a backup.

[0040] As Figure 7 shown, the reset circuit is connected to the PROGRAM_B pin of the FPGA for reset.

[0041] As Figure 8 shown, the power supply circuit includes LTM4644 and its peripheral circuit. The +5V power supply input generates 4 paths of 1.0V power through the power supply chip LTM4644. Two of them provide stable power for the VCCINT and VCCBRAM of the FPGA, and the other two provide stable power for the MGTAVCC of the GTX; the +5V power supply input generates +1.5V, +1.8V, +1.2V and +3.3V power respectively through the power supply chip LTM4644. LTM4644 supplies power to VCCAUX, VCCAUX_IO, VCCIO, DRR3, crystal oscillator and FLASH, and the 1.2V DC supplies power to MGTAVTT.

[0042] The power-on sequence is that VCCINT, VCCBRAM, and MGTAVCC are powered on first, and then VCCAUX, VCCAUX_IO, IO Bank, MGTVCCAUX, MGTAVTT, and DDR are powered on. Finally, the IO Bank is powered on.

[0043] The input and output drive circuit includes an input signal isolation and conversion circuit and an output signal isolation and conversion circuit.

[0044] As Figure 9 shown, the input signal isolation and conversion circuit includes NS18140WO1 and its peripheral circuit. As Figure 10 shown, the output signal isolation and conversion circuit includes NS18140WO2 and its peripheral circuit, where the latch signal and data fetch signal are reserved and output to the output connector through the FPGA. 3 paths of IO are reserved and output through the FPGA, and 2 of them are directly connected from the input connector to the output connector.

[0045] The present invention also includes an LED circuit, such as Figure 11 and 12 shown. One is the configuration completion indicator (DONE) (on-board indicator). When the FPGA configuration program is completed, the configured green LED will light up. Three are channel selection instruction lights (according to the selection instruction, the three indicator lights are displayed according to the coding combination, where on represents 1 and off represents 0).

[0046] Such as Figure 13 shown is the reserved interface circuit. (Two-bit data input amount is reserved. When the input data increases by two bits, this design can be directly adopted).

[0047] A method for converting a multi-channel parallel interface to a time-division multiplexed multi-channel parallel interface includes the following steps:

[0048] Step 1: Set the input terminal signals according to the constructed interface;

[0049] Step 2: Set the output terminal signals according to the constructed interface;

[0050] Step 3: Set the timing signals according to the constructed interface to complete the parallel transmission function of the interface.

[0051] Such as Figure 1 shown, the input terminal: 1-bit latch signal (LATCH_IN), 2-bit data fetch signals (READ_IN[0:1]), 20-bit data signals (DATA_IN[19:0] valid signal (DATA_EN_IN), 1-bit data busy signal (DATA_BUSY_IN), and 1-bit GD flag signal (GD_IN), a total of 25-bit parallel input signals. DATA_IN[19:0] is judged whether it is valid according to Table 1. The highest bit weight of DATA_IN[19:0] is 180°, and the lowest bit weight is 180°×2 -18 .

[0052] Signal judgment truth table

[0053] Serial number DATA_EN_IN DATA_BUSY_IN Status of DATA_IN[0:18] 1 0 1 Invalid 2 1 1 Invalid, should not occur 3 1 0 Data valid 4 0 0 Data invalid

[0054] Output terminal: Parallel interface data. The highest bit weight of the data of channel A is 180°, and the highest bit weight of the data of channel B is 180°×2 －7 ; The output data format is: The multiplexed data bits of channel A and channel B are 14-bit DATA_OUT[0:13], 1-bit latch signal LATCH_OUT (input control of the output data terminal), 2-bit data fetch signals READ_OUT[0:1] (input control of the output data terminal), a total of 17-bit data bits; When the output data takes channel A, the lowest two bits are invalid; The receiving party level ≥ 3V.

[0055] Both the latch signal and the data fetch signal are valid for negative pulses. The pulse width of the data fetch signal should be greater than 1 μs. First, send the latch signal, and then send the data fetch signal. Data fetching starts 80 ns after the falling edge of the data fetch signal, and the next data fetch signal is allowed to be sent 0.5 μs after the rising edge of the data fetch signal. The PCB board outputs 14-bit data according to Figure 2 the timing shown, and other output signals are output according to their original values. When outputting to channel A, the weight value of the highest bit is 180°, and the weight value of the lowest bit is 180°×2 -13 ; when outputting to channel B, the weight value of the highest bit is 180°×2 -7 , and the weight values decrease successively from the high bit. The lowest 2 bits are invalid (the invalid bits are filled with zeros). That is:

[0056] DATA_OUT channel A[13:0] = DATA_IN[18:5];

[0057] DATA_OUT channel B[13:0] = DATA_IN[11:0] << 2 + 0.

[0058] As Figure 2 shown, t1 ≥ 1 us; t2 ≥ 0.5 us; the data fetch signals (READ_IN0, READ_IN1) start to output the DATA_OUT[0:13] signal 80 ns after their falling edges; at the same time, a self-test function is designed to test whether the input data timing is normal from the test interface.

[0059] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes, but is not limited to, the embodiments described in the specific implementation manners. Any other implementation manners obtained by those skilled in the art according to the technical solutions of the present invention also fall within the scope of protection of the present invention.

Claims

1. A device for converting a multi-channel parallel interface into a time-division multiplexed multi-channel parallel interface, characterized in that: It includes a PCB board, on which an FPGA, a clock circuit, a download and debugging circuit, a QSPI FLASH circuit, a reset circuit, a power supply circuit, and an input and output circuit are integrated. The FPGA is respectively connected to the clock circuit, the download and debugging circuit, the QSPI FLASH circuit, the reset circuit, the power supply circuit, and the input and output circuit. The clock circuit is used to provide a global clock, the download and debugging circuit is used to debug the FPGA, the QSPI FLASH circuit is used to store the configuration Bin file of the FPGA and other user data files, the reset circuit is used to reset the FPGA, the power supply circuit is used to provide power, and the input and output drive circuit is used to input signals and output signals.

2. A multiplexed parallel interface for converting a multi-channel parallel interface to a time-division multiplexed multi-channel parallel interface according to claim 1, characterized in that: The clock circuit includes OT503250MIBA4SL and its peripheral circuit. The clock circuit provides a single-ended 50 MHz FPGA system clock source, and the output of the clock circuit is connected to the FPGA CLK pin to form a global clock.

3. A multiplex parallel interface to time division multiplexed multiplex parallel interface according to claim 1, characterized in that: The download and debugging circuit includes JTAG and its peripheral circuit.

4. A multiplexed parallel interface for converting a multi-channel parallel interface to a time-division multiplexed multi-channel parallel interface according to claim 1, characterized in that: The QSPI FLASH circuit includes EFM25F128A and its peripheral circuit and the N250128A138S240P / NC machine peripheral circuit. One path of the QSPI FLASH circuit is used to store the configuration Bin file of the FPGA and other user data files, and the other path of the QSPI FLASH circuit is used as a backup.

5. A multiplex parallel interface to time-division multiplexed multiplex parallel interface according to claim 1, characterized in that: The reset circuit is connected to the PROGRAM_B pin of the FPGA for reset.

6. A multiplex parallel interface to time-division multiplexed multiplex parallel interface according to claim 1, wherein: The power supply circuit includes LTM4644 and its peripheral circuit. The +5V power input generates 4 paths of 1.0V power through the power supply chip LTM4644. Among them, 2 paths provide stable power for the VCCINT and VCCBRAM of the FPGA, and the other 2 paths provide stable power for the MGTAVCC of the GTX; the +5V power input generates +1.5V, +1.8V, +1.2V, and +3.3V power respectively through the power supply chip LTM4644. LTM4644 supplies power to VCCAUX, VCCAUX_IO, VCCIO, DRR3, the crystal oscillator, and FLASH, and 1.2V DC supplies power to MGTAVTT.

7. A multiplex parallel interface to time-division multiplexed multiplex parallel interface according to claim 1, characterized in that: The input and output drive circuit includes an input signal isolation and conversion circuit and an output signal isolation and conversion circuit. Among them, the input signal isolation and conversion circuit includes NS18140WO1 and its peripheral circuit, and the output signal isolation and conversion circuit includes NS18140WO2 and its peripheral circuit. And a latch signal and a data fetch signal are reserved to be output to the output connector through the FPGA.

8. A method for converting a multi-channel parallel interface to a time-division multiplexed multi-channel parallel interface according to any one of claims 1 to 7, characterized in that: It includes the following steps: Step 1: Set the input terminal signals according to the constructed interface; Step 2: Set the output terminal signals according to the constructed interface; Step 3: Set the timing signals according to the constructed interface to complete the parallel transmission function of the interface.

9. A method for converting a multi-channel parallel interface to a time-division multiplexed multi-channel parallel interface according to claim 8, characterized in that: The input terminal signals in Step 1 include: 1-bit latch signal, 2-bit data fetch signal, data signal, 1-bit data busy signal, and 1-bit GD flag signal. In step 2, the output terminal includes channel A and channel B, where the weight of the highest bit of the data in channel A is 180°, and the weight of the highest bit of the data in channel B is 180°×2 －7 , and the data format at the output terminal is as follows: channels A and B share 14 data bits, 1 latch signal LATCH_OUT, and 2 data fetch signals.

10. A method for converting a multi-channel parallel interface to a time-division multiplexed multi-channel parallel interface according to claim 8, characterized in that: The specific implementation method of step 3 is as follows: both the latch signal and the data fetch signal are valid for negative pulses, and the pulse width of the data fetch signal is greater than 1 μs; first, the latch signal is sent, and then the data fetch signal is sent. Data fetching starts 80 ns after the falling edge of the data fetch signal, and the next data fetch signal is allowed to be sent only 0.5 μs after the rising edge of the data fetch signal.

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