Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps of: after etching and opening a barrier dielectric layer of a silicide barrier layer and before pre-amorphization injection, removing a bottom oxide layer exposed out of the barrier dielectric layer by wet etching, and under the condition of ensuring that the influence on the process is small, improving the performance of the semiconductor device. The problem that the top height of the device isolation structure at the vertex angle of the source-drain region is reduced due to excessive loss of the device isolation structure at the vertex angle of the source-drain region in the process of removing the bottom oxide layer exposed by the barrier dielectric layer through wet etching can be avoided, the top surface height of the device isolation structure at the vertex angle of the source-drain region is ensured, and excessive top side walls of the source-drain region are prevented from being exposed; therefore, the problem that the formed metal silicide extends downwards from the top surface of the vertex angle of the source-drain region to the side wall of the vertex angle of the source-drain region can be avoided, the weakness of the vertex angle of the active region is improved, the junction leakage current of the device is reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] As the device size shrinks, when the conductive channel length of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is reduced to a dozen nanometers or even a few nanometers, the short channel effect (SCE) of the transistor increases significantly, which will cause problems such as increased bulk leakage current (Iboff), seriously affecting the reliability and other performance of the device. Among them, after entering the 28nm and below nodes, the Iboff of MOS devices increases sharply. Therefore, how to reduce the junction leakage current of MOS devices has become one of the focus issues that technicians in this field need to solve urgently.

[0003] The inventors have found that the process of manufacturing metal silicide on the source and drain regions in the prior art will produce leakage paths, which is one of the reasons why the junction leakage current Iboff of the MOS device is too large. Specifically, the process of manufacturing metal silicide on the source and drain regions in the prior art generally includes the following steps:

[0004] S11, please refer to Figure 1A A substrate 100 is provided, in which a device isolation structure 101 (for example, a device isolation structure STI, etc.) is formed. The device isolation structure 101 defines an NMOS active region and a PMOS active region in the substrate 100. Gate structures (which may include a gate dielectric layer 104, a gate layer 103, and a gate hard mask layer such as silicon nitride stacked in sequence) are formed on the substrate 100 in the NMOS active region and the PMOS active region. Gate sidewalls 105 are formed on the sidewalls of each gate structure. Source and drain regions are formed in the substrate 100 on both sides of the gate structure, wherein N-type source and drain regions (i.e., N-type source region 100ns and N-type drain region 100nd) are formed in the NMOS active region, and P-type source and drain regions (i.e., P-type source region 100ps and P-type drain region 100pd) are formed in the PMOS active region.

[0005] S12, please refer to Figure 1A , a silicon oxide layer 106 and a silicon nitride layer 107 are sequentially deposited by any suitable process such as chemical vapor deposition, thereby forming a silicide block (SAB) covering the surface of the substrate 100, the surface of the device isolation structure 101 and the surface of the gate structure.

[0006] S13, please refer to Figure 1B , through photolithography and etching processes, remove the silicon nitride layer 107 on the top surface of each source / drain region and at the top corners of each source / drain region (AA corner, which can also be said to be the junction between the active region and the device isolation structure 101), etc., so as to open the silicon nitride layer 107 and define the region where metal silicide is to be formed. That is, the region where metal silicide is to be formed includes the source / drain region and a part of the top surface of the device isolation structure 101 at the top corner of the source / drain region.

[0007] S14, please refer to Figure 1C , under the blocking action of the silicon oxide layer 106, perform pre-amorphization implantation (PAI IMP) on the region where metal silicide is to be formed defined by the silicon nitride layer 107, so as to form an amorphous layer 108 on the surface layer (or the surface) of each source / drain region. This amorphous layer 108 is beneficial for forming more low-resistance-phase metal silicides subsequently.

[0008] S15, please refer to Figure 1D , use wet etching to remove the silicon oxide layer 106 exposed by the silicon nitride layer 107 to expose the top surface of the source / drain region, facilitating the subsequent formation of metal silicide on the top surface of the source / drain region.

[0009] S16, please refer to Figure 1E , deposit a metal layer (not shown) through any suitable process such as sputtering deposition and electroplating, and perform annealing treatment to form the required metal silicide layer 109 on the surface of each source / drain region.

[0010] Please refer to Figure 2 As shown, in the above manufacturing process, after photolithography and etching of the silicon nitride layer 107 to define the region where metal silicide is to be formed, first perform pre-amorphization implantation, and then use wet etching to remove the silicon oxide layer exposed by the silicon nitride layer. Since this pre-amorphization implantation will be injected into the top corner of the source / drain region (i.e., the top corner of the active region, or the junction between the device isolation structure and the source / drain region), the etching rate of the device isolation structure at the top corner of the source / drain region will increase. Therefore, during the process of using wet etching to remove the silicon oxide layer exposed by the silicon nitride layer after pre-amorphization implantation, a relatively large amount of the device isolation structure at the top corner of each source / drain region will also be removed by wet etching, causing the top surface height of the device isolation structure at the junction to drop by H relative to the top surface of the source / drain region, generating an active region top corner weak point 101a. As a result, the metal silicide 109 formed subsequently on the source / drain region will continue to drill downward from this active region top corner weak point 101a, thereby generating a leakage path, resulting in a relatively large junction leakage current Iboff of the device, seriously affecting the device performance. Summary of the Invention

[0011] The object of the present invention is to provide a manufacturing method of a semiconductor device, which can reduce the junction leakage current of the device and improve the device performance.

[0012] To achieve the above object, the present invention provides a manufacturing method of a semiconductor device, which includes the following steps:

[0013] Provide a substrate, and form a gate structure on the substrate, form source / drain regions in the substrate on both sides of the gate structure, and form a device isolation structure in the substrate outside the source / drain regions;

[0014] Cover a silicide blocking layer on the surface of the substrate, the surface of the device isolation structure, and the surface of the gate structure, and the silicide blocking layer includes a bottom oxide layer and a blocking dielectric layer covering the bottom oxide layer;

[0015] Using the bottom oxide layer as an etching stop layer, etch and open the blocking dielectric layer on the top surface of the region including the top corner of the source / drain region;

[0016] Perform wet etching to remove the bottom oxide layer exposed by the blocking dielectric layer to expose the top surface of the region including the top corner of the source / drain region;

[0017] Using the gate structure and the silicide blocking layer as a mask, perform pre-amorphization implantation on the source / drain region to form an amorphous layer in the surface layer of the source / drain region;

[0018] Deposit a metal layer and perform an annealing process to form a metal silicide on the exposed surface of the source / drain region.

[0019] Optionally, the blocking dielectric layer includes at least one nitride layer and / or at least one oxide layer.

[0020] Optionally, the bottom oxide layer is a silicon oxide layer, the blocking dielectric layer is a silicon nitride layer, and the silicide blocking layer is an ON structure; or, the bottom oxide layer is a silicon oxide layer, the blocking dielectric layer is an ON structure composed of a sequentially formed silicon nitride layer and a silicon oxide layer, and the silicide blocking layer is an ONO structure.

[0021] Optionally, the ions used for the pre-amorphization implantation include at least one of silicon ions, nitrogen ions, fluorine ions, xenon ions, neon ions, argon ions, krypton ions, carbon ions, germanium ions, and antimony ions; and / or, the material of the metal layer includes at least one of nickel, platinum, cobalt, titanium, copper, and tungsten.

[0022] Optionally, a hydrofluoric acid solution is used to perform wet etching to remove the bottom oxide layer exposed by the blocking dielectric layer.

[0023] Optionally, the annealing process includes:

[0024] Performing a first annealing process on the substrate to form a metal silicide with a high-resistance phase;

[0025] Removing the unreacted metal layer;

[0026] Performing a second annealing process on the substrate, and the annealing temperature of the second annealing process is different from that of the first annealing process, to convert the metal silicide with a high-resistance phase into a metal silicide with a low-resistance phase.

[0027] Optionally, the gate structure includes a gate dielectric layer, a gate layer, and a gate hard mask layer stacked in sequence, and a gate spacer is further formed on the sidewall of the gate structure; when a silicide blocking layer is covered on the surface of the substrate and the surface of the gate structure, the silicide blocking layer also covers the surface of the gate spacer.

[0028] Optionally, with the bottom oxide layer as an etch stop layer, while etching and opening the blocking dielectric layer on the top surface of the region including the top corner of the source / drain region, the blocking dielectric layer on the gate hard mask layer and the gate spacer is also etched and removed.

[0029] Optionally, the device isolation structure defines an NMOS active region and a PMOS active region in the substrate, an N-type source / drain region is formed in the NMOS active region, and an embedded P-type source / drain region is formed in the PMOS active region; after performing the annealing process, the metal silicide is formed on both the N-type source / drain region and the embedded P-type source / drain region.

[0030] Optionally, after forming the metal silicide, it further includes: depositing an interlayer dielectric layer, and forming source / drain contact plugs in the interlayer dielectric layer through a contact hole process, and the bottom of the source / drain contact plugs is in electrical contact with the metal silicide on the source / drain region.

[0031] Compared with the prior art, in the technical solution of the present invention, after etching and opening the blocking dielectric layer of the silicide blocking layer and before performing pre-amorphization implantation, the bottom oxide layer exposed by wet etching to remove the blocking dielectric layer is first removed by wet etching. Without significantly affecting the process, it can avoid the problem that the process of wet etching to remove the bottom oxide layer exposed by the blocking dielectric layer causes excessive loss to the device isolation structure at the top corner of the source / drain region and reduces its top height, ensuring the top height of the device isolation structure at the top corner of the source / drain region, preventing it from exposing too much of the top sidewall of the source / drain region, and further avoiding the problem that the formed metal silicide extends downward from the top corner of the source / drain region to the sidewall of the top corner of the source / drain region. Thus, the weakness at the top corner of the active region is improved, and further, the junction leakage current of the device is reduced, and the device performance is improved. Description of the Drawings

[0032] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0033] Figures 1A to 1E is a schematic diagram of a device in the process flow of manufacturing a metal silicide on a source / drain region in the prior art.

[0034] Figure 2 is an enlarged schematic diagram of a source / drain region and its top corner weak point (AA corner weak point) of a semiconductor device formed by the process flow shown in FIG. 1.

[0035] Figure 3 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0036] Figures 4A to 4E is Figure 3 a schematic diagram of a device in the method for manufacturing the semiconductor device shown.

[0037] Figure 5 is a top view structural schematic diagram of a semiconductor device manufactured according to an embodiment of the present invention.

[0038] Figure 6 is a cross-sectional structural schematic diagram of a semiconductor device manufactured according to an embodiment of the present invention.

[0039] Figures 7 to 10 is a schematic diagram for performance analysis of a semiconductor device manufactured according to an embodiment of the present invention. Detailed implementation manners

[0040] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention. It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "comprises" is used to specify the presence of the features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0041] Based on the existing solutions and their technical problems stated in the background art, the present invention provides a method for manufacturing a semiconductor device. The core idea of this solution is that in the case of minor process variations, by swapping the order of the pre-amorphization implantation step and the wet etching step of the silicon oxide layer in the existing process of forming metal silicide on the source and drain regions (i.e., swapping the order of step S13 and step S14 described in the background art), it is possible to avoid the problem that the metal silicide at the top corner of the source and drain regions drills down and increases the junction leakage current caused by the pre-amorphization implantation first and the wet etching of the silicon oxide layer in the silicide barrier layer later, thereby improving the device performance.

[0042] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention.

[0043] Please refer to Figure 3 , an embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps:

[0044] S21, providing a substrate, forming a gate structure on the substrate, forming source and drain regions in the substrate on both sides of the gate structure, and forming a device isolation structure in the substrate surrounding the source and drain regions;

[0045] S22. Cover a silicide blocking layer on the surface of the substrate, the surface of the device isolation structure, and the surface of the gate structure. The silicide blocking layer includes a bottom oxide layer and a blocking dielectric layer covering the bottom oxide layer.

[0046] S23. Using the bottom oxide layer as an etching stop layer, etch to open the blocking dielectric layer on the top surface of the region including the top corner of the source / drain region.

[0047] S24. Wet-etch and remove the bottom oxide layer exposed by the blocking dielectric layer to expose the top surface of the region including the top corner of the source / drain region.

[0048] S25. Using the gate structure and the silicide blocking layer as a mask, perform pre-amorphization implantation on the source / drain region to form an amorphous layer in the surface layer of the source / drain region.

[0049] S26. Deposit a metal layer and perform an annealing process to form a metal silicide on the exposed surface of the source / drain region.

[0050] In step S21, please refer to Figure 4A As shown, the provided substrate 200 can be any suitable semiconductor substrate, such as a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, a germanium-on-insulator (GOI) substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium phosphide substrate, etc. An isolation trench can be formed in the substrate 200 by a shallow trench isolation process or a local field oxide isolation process, etc., and an oxide material such as silicon oxide is filled to form a device isolation structure 201. The device isolation structure 201 can define an NMOS active region and a PMOS active region in the substrate 200. Further, a corresponding P-type well (not shown) or N-type well (not shown) is formed in the NMOS active region and the PMOS active region respectively by a well ion implantation process.

[0051] In step S21, please refer to Figure 4AAs shown, a gate structure can also be formed on the substrate 200 through a front-gate process or a back-gate process, and further, a gate sidewall 205 can be formed on the sidewalls of the gate structure through a gate sidewall process. The gate sidewall 205 can be a single-layer film structure or a multi-layer film structure. For example, the gate sidewall 205 is an ON structure formed by stacking a silicon oxide layer (O) and a silicon nitride layer (N). Another example is that the gate sidewall 205 is an ONO structure formed by stacking a silicon oxide layer (O), a silicon nitride layer (N), and a silicon oxide layer (O). As an example, the gate structure can include a gate dielectric layer 204, a gate layer 203, and a gate hard mask layer (not shown) stacked in sequence. Among them, the gate dielectric layer 204 can include silicon oxide or a high-k oxide, and the gate layer 203 can include one or more of a polysilicon layer, a metal layer (such as tungsten W, nickel Ni, or titanium Ti, etc.), a conductive metal nitride layer (such as titanium nitride TiN or tantalum nitride TaN, etc.), a conductive metal oxide layer (such as iridium oxide IrO2, etc.), and a metal silicide layer (such as titanium silicide TiSi, etc.). The gate hard mask layer can include one or more of an oxide layer, a nitride layer, a nitrogen oxide layer, and amorphous carbon.

[0052] In step S21, please refer to Figure 4A As shown, after the gate structure and the gate sidewall 205 are formed, N-type source / drain regions (one side is the N-type drain region 200nd, and the other side is the N-type source region 200ns) located on both sides of its gate structure can be formed in the NMOS active region through corresponding source / drain ion implantation processes or epitaxial source / drain processes respectively, and P-type source / drain regions (one side is the P-type drain region 200pd, and the other side is the P-type source region 200ps) located on both sides of its gate structure can be formed in the PMOS active region. In one example, an epitaxial SiGe source / drain can be introduced into the PMOS active region (the material of which is silicon) to generate strain and improve the channel carrier mobility of the PMOS device, thereby improving the performance of the PMOS device. In one example, each source / drain region also has doping structures such as a lightly doped drain (LDD) region. In addition, after the source / drain ion implantation is completed, a high-temperature annealing treatment can be performed to activate the ions in the source / drain regions.

[0053] Thus, the purpose of executing step S21 is to fabricate the basic structure of devices such as MOS transistors to prepare the substrate for forming metal silicide.

[0054] In step S22, please continue to refer to Figure 4A, using any suitable deposition process such as atomic layer deposition, chemical vapor deposition, etc., on a substrate 200 having a device isolation structure 201, source and drain regions, and a gate structure and a gate sidewall 205, a bottom oxide layer 206 and a barrier dielectric layer 207 are sequentially deposited. Among them, the bottom oxide layer 206 and the barrier dielectric layer 207 covering its surface form a silicide barrier layer. Among them, the bottom oxide layer 206 may include at least one of silicon oxide (SiO2), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicon glass (USG), spin-on glass (SOG), high density plasma (HDP) oxide, and spin-on dielectric (SOD) oxide. The barrier dielectric layer 207 may include a nitride layer, and the nitride layer may include one or both of a silicon nitride (Si3N4) layer and a silicon oxynitride (SiON).

[0055] In one example, the bottom oxide layer 206 is silicon oxide, and the barrier dielectric layer 207 is a single-layer film structure formed of silicon nitride (N). At this time, the silicide barrier layer formed by the bottom oxide layer 206 and the barrier dielectric layer 207 is an ON structure. In another example, the bottom oxide layer 206 is silicon oxide, and the barrier dielectric layer 207 may be a double-layer film structure formed by laminating silicon nitride and silicon oxide. At this time, the silicide barrier layer formed by the bottom oxide layer 206 and the barrier dielectric layer 207 is an ONO structure.

[0056] In step S23, please refer to Figure 4B , first, an amorphous carbon layer (not shown) and a bottom antireflection layer (BARC, not shown) can be sequentially deposited, and a photoresist (PR, not shown) can be coated, etc., and lithography processes such as exposure and development are performed on the photoresist layer by means of a corresponding photomask, so as to define a region where metal silicide is to be formed in the photoresist layer; then, using the lithographed photoresist layer as a mask and the bottom oxide layer 206 as an etch stop layer, through any suitable etching process such as dry etching, the bottom antireflection layer, the amorphous carbon layer, and the barrier dielectric layer 207 are etched to open, so as to remove the redundant barrier dielectric layer 207, thereby defining a region where metal silicide is to be formed in the barrier dielectric layer 207, and this region is aligned with the top surface of at least a part of the regions including the top corners of each source and drain region. In one example, while etching to open the barrier dielectric layer 207 on the top surface of at least a part of the regions including the top corners of each source and drain region, the barrier dielectric layer 207 on the top surface of the gate structure, the surface of the gate sidewall 205, and the top surface of the NMOS active region and the PMOS active region junction region (including the device isolation structure at the junction of the two) is also etched and removed.

[0057] In step S24, please refer to Figure 4C, under the blocking effect of the blocking dielectric layer 207, the underlying oxide layer 206 exposed by the blocking dielectric layer 207 is etched away by any suitable wet etching process, thereby exposing the top surfaces of at least part of the regions including the top corners of each source / drain region, thus preparing for the formation of metal silicide on the source / drain regions. As an example, the underlying oxide layer exposed by the blocking dielectric layer 207 is wet-etched away using a hydrofluoric acid solution.

[0058] In one embodiment, before or after wet-etching away the underlying oxide layer 206 exposed by the blocking dielectric layer 207, the photoresist layer can be removed by processes such as dry stripping or wet stripping, and the amorphous carbon layer and the bottom anti-reflection layer on the surface of the blocking dielectric layer 207 can be further removed.

[0059] In step S25, please refer to Figure 4D , under the blocking effect of the remaining silicide blocking layer (i.e., the remaining blocking dielectric layer 207 and the underlying oxide layer 206), the gate sidewall 205, and the gate structure, pre-amorphization implantation is performed on the exposed source / drain regions, etc., to form an amorphous layer 208 in the surface layer of each source / drain region. Among them, the ions used for pre-amorphization implantation include at least one of silicon ions, nitrogen ions, fluorine ions, xenon ions, neon ions, argon ions, krypton ions, carbon ions, germanium ions, and antimony ions. Those skilled in the art can reasonably select parameters such as the ion type, implantation dose, and implantation energy of pre-amorphization implantation according to the size and performance requirements of different devices, and the present invention does not make specific limitations thereon.

[0060] In step S25, please refer to Figure 4E , first, a metal layer can be deposited on the surface of the substrate 200 and the gate structure, etc. after pre-amorphization implantation by any suitable process such as sputtering deposition, evaporation, or electroplating. The material of the metal layer includes at least one of nickel, platinum, cobalt, titanium, copper, and tungsten. Then, a first annealing treatment with a relatively low temperature is performed to react the deposited metal layer with the silicon on the exposed surfaces of each source / drain region to form a metal silicide with a high-resistance phase; then, the unreacted metal layer is removed, and a second annealing treatment with a relatively high temperature is performed to convert the metal silicide with a high-resistance phase into a metal silicide with a low-resistance phase, thereby forming the required metal silicide 209. During the two annealing treatments, the amorphous layer 208 formed by pre-amorphization implantation can effectively inhibit the longitudinal growth (in the direction perpendicular to the channel direction) of the formed metal silicide 209 and control the proportion of the longitudinal growth of the metal silicide 209, thereby preventing junction leakage. In one example, after performing the second annealing treatment, metal silicide 209 is formed on the N-type source / drain regions 200ns, 200nd of the NMOS active region and the embedded P-type source / drain regions 200ps, 200pd of the PMOS active region.

[0061] To respectively adopt the solution of this embodiment andFigures 1A to 1E Taking the existing solution (BSL) shown as an example, where an NMOS core device (NCore) and an NMOS input / output device (NIO) are formed on the same substrate, the effects of the solution of this embodiment will be described in detail.

[0062] Among them, the solution of this embodiment (Sequ, solid circle), compared with Figures 1A to 1E the existing solution (BSL, hollow circle) shown, under the condition that other process conditions are the same, only the order of the two steps of pre-amorphization implantation and wet etching to open the bottom oxide layer of the silicide barrier layer is exchanged, that is, after etching to open the barrier dielectric layer of the silicide barrier layer and before performing pre-amorphization implantation, first wet-etch the bottom oxide layer exposed by removing the barrier dielectric layer, and the achieved effects are as Figures 7 to 10 shown. As can be seen from Figures 7 to 8 , in the solution of this embodiment, the junction leakage current Iboff of the NMOS core device (NCore) formed on the same substrate (as Figure 7 shown) and the junction leakage current Iboff of the NMOS input / output device (NIO) (as Figure 8 shown) are both relatively lower; as can be seen from Figure 9 and Figure 10 , the saturation drain current Idsat and source-drain current Isoff achieved by the NMOS core device formed by the solution of this embodiment also respectively approach the corresponding target values Target, that is, the solution of the present invention has no adverse effects on performance parameters such as the saturation drain current Idsat and source-drain current Isoff of the NMOS core device. Generally speaking, the solution of this embodiment greatly improves the junction leakage current Iboff of the MOS device and can improve the device performance.

[0063] Among them, the mechanism analysis of how the technical solution of this embodiment can achieve the above effects is as follows:

[0064] Since the solution of this embodiment exchanges the order of the two steps of pre-amorphization implantation and wet etching to remove the bottom oxide layer exposed by the barrier dielectric layer under the condition that other process conditions remain unchanged, it is possible to avoid the influence of the pre-amorphization implantation on the etching rate of the device isolation structure at the top corner of the source / drain region when it is executed first, and further avoid the problem of excessive loss of the device isolation structure at the top corner of the source / drain region when the process of wet etching to remove the bottom oxide layer exposed by the barrier dielectric layer is executed later, thereby ensuring that the top surface height of the device isolation structure 201a at the top corner of the source / drain region is basically the same as the top surface height of the device isolation structure 201b in other regions, as Figure 5 and Figure 6As shown, the problem that the metal silicide formed at the top corner of the source / drain region extends downward from the top surface of the top corner of the source / drain region to the sidewall of the top corner of the source / drain region is thus avoided, thereby improving the weakness at the top corner of the source / drain region, reducing the junction leakage current of the device, and improving the device performance.

[0065] In addition, in the technical solution of this embodiment, compared with the existing solution, only the order of two steps of pre-amorphization implantation and wet etching to open the bottom oxide layer of the silicide blocking layer is swapped, which has a minor impact on the process and a low implementation cost.

[0066] Optionally, after performing step S26 (i.e., after forming the metal silicide 209 on each source / drain region), the manufacturing method of the semiconductor device of the present invention further includes: depositing an interlayer dielectric layer (not shown), and forming corresponding source / drain contact plugs (not shown) in the interlayer dielectric layer through a contact hole process, and the bottom of each source / drain contact plug is in electrical contact with the metal silicide 209 on its corresponding source / drain region.

[0067] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes the following steps: Providing a substrate, forming a gate structure on the substrate, forming source / drain regions in the substrate on both sides of the gate structure, and forming a device isolation structure in the substrate surrounding the source / drain regions; Covering a silicide blocking layer on the surface of the substrate, the surface of the device isolation structure, and the surface of the gate structure, the silicide blocking layer including a bottom oxide layer and a blocking dielectric layer covering the bottom oxide layer; Using the bottom oxide layer as an etch stop layer, etching to open the blocking dielectric layer on the top surface of the region including the top corners of the source / drain regions; Performing wet etching to remove the bottom oxide layer exposed by the blocking dielectric layer, so as to expose the top surface of the region including the top corners of the source / drain regions; Using the gate structure and the silicide blocking layer as a mask, performing pre-amorphization implantation on the source / drain regions to form an amorphous layer in the surface layer of the source / drain regions; Depositing a metal layer and performing an annealing process to form a metal silicide on the exposed surface of the source / drain regions; 2. The manufacturing method according to claim 1, wherein The blocking dielectric layer includes at least one nitride layer and / or at least one oxide layer; 3. The manufacturing method according to claim 2, characterized in that, The bottom oxide layer is a silicon oxide layer, the blocking dielectric layer is a silicon nitride layer, and the silicide blocking layer is an ON structure; or, the bottom oxide layer is a silicon oxide layer, the blocking dielectric layer is an ON structure composed of a sequentially formed silicon nitride layer and a silicon oxide layer, and the silicide blocking layer is an ONO structure; 4. The manufacturing method according to claim 1, wherein The ions used for the pre-amorphization implantation include at least one of silicon ions, nitrogen ions, fluorine ions, xenon ions, neon ions, argon ions, krypton ions, carbon ions, germanium ions, and antimony ions; and / or, the material of the metal layer includes at least one of nickel, platinum, cobalt, titanium, copper, and tungsten; 5. The manufacturing method according to claim 1, characterized in that, Using a hydrofluoric acid solution to perform wet etching to remove the bottom oxide layer exposed by the blocking dielectric layer; 6. The manufacturing method according to claim 1, characterized in that, The annealing process includes: Performing a first annealing process on the substrate to form a high-resistance phase metal silicide; Removing the unreacted metal layer; Performing a second annealing process on the substrate, and the annealing temperature of the second annealing process is different from that of the first annealing process, so as to convert the high-resistance phase metal silicide into a low-resistance phase metal silicide; 7. The manufacturing method according to any one of claims 1-6, characterized in that, The gate structure includes a gate dielectric layer, a gate layer, and a gate hard mask layer stacked in sequence, and a gate sidewall is further formed on the sidewall of the gate structure; when covering the silicide blocking layer on the surface of the substrate and the surface of the gate structure, the silicide blocking layer also covers the surface of the gate sidewall; 8. The manufacturing method according to claim 7, characterized in that, Using the bottom oxide layer as an etch stop layer, while etching to open the blocking dielectric layer on the top surface of the region including the top corners of the source / drain regions, also etching and removing the blocking dielectric layer on the gate hard mask layer and the gate sidewall; 9. The manufacturing method according to claim 7, wherein The device isolation structure defines an NMOS active region and a PMOS active region in the substrate, an N-type source / drain region is formed in the NMOS active region, and an embedded P-type source / drain region is formed in the PMOS active region; After performing the annealing process, the metal silicide is formed on both the N-type source / drain region and the embedded P-type source / drain region.

10. The manufacturing method according to any one of claims 1-6, characterized in that, After forming the metal silicide, it further includes: depositing an interlayer dielectric layer, and forming source / drain contact plugs in the interlayer dielectric layer through a contact hole process, wherein the bottom of the source / drain contact plugs is in electrical contact with the metal silicide on the source / drain regions.

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