Improved HEMT device, in particular depletion mode device, and process for manufacturing same

Abstract

Embodiments of the present disclosure relate to improved HEMT devices, in particular depletion mode devices and processes for manufacturing the same. The HEMT device includes: a heterostructure including a channel layer and a barrier layer, the barrier layer extending onto the channel layer along a first axis; a dielectric protection layer of a dielectric material, the dielectric protection layer extending along a first axis onto the barrier layer; and a gate region extending along the first axis onto the dielectric protection layer, in which the dielectric protection layer has a thickness of less than 10 nm along the first axis.

Description

Technical Field

[0001] The present disclosure relates to improved high electron mobility transistor (HEMT) devices, particularly depletion mode devices and their manufacturing processes. In addition, the present disclosure relates to electronic assemblies including HEMT devices. Background Art

[0002] HEMT devices are known, in which a conductive channel is based on a layer that forms a two-dimensional electron gas (2DEG) with high mobility at a heterostructure (i.e., at the interface between semiconductor materials with different bandgaps). For example, HEMT devices are known to be based on a heterostructure between an aluminum gallium nitride (AlGaN) barrier layer and a gallium nitride (GaN) channel layer.

[0003] HEMT devices based on the AlGaN / GaN heterostructure offer various advantages, making them particularly suitable for and widely used in different applications. For example, the high breakdown threshold of HEMT devices is used in high-performance power switches; the high mobility of electrons in the conductive channel allows the fabrication of high-frequency amplifiers; in addition, the high concentration of electrons in the 2DEG allows for obtaining a low ON (conducting) state resistance (R ON ). In addition, compared with similar silicon devices, HEMT devices for radio frequency (RF) applications generally have better RF performance.

[0004] Generally, GaN / AlGaN HEMTs operate in depletion mode (also known as "D-mode") and are thus normally-on devices. Specifically, in a D-mode HEMT, the gate structure placed above the barrier layer is biased to a negative gate voltage with respect to the drain and source biasing to deplete the 2DEG.

[0005] More specifically, there are generally two known solutions for manufacturing D-mode HEMTs: using a gate structure that forms a Schottky-type contact with the barrier layer, or using an insulating gate structure. In the first case, the gate structure has a metal gate region (e.g., Ni-Au or Pt), and the metal gate region contacts the barrier layer and thus forms a Schottky-type contact with the barrier layer. In the second case, the gate structure has a metal gate region and a gate insulating layer (e.g., SiO2) between the metal gate region and the barrier layer to prevent the generation of gate current. The thickness of the gate insulating layer is higher than 10 nm and is typically equal to about 20 nm. This allows for obtaining a negative "pinch-off" voltage at gate voltage values below about -10 V, thus avoiding the turn-off of the HEMT device under operating conditions of high drain voltage (e.g., voltage up to 650 V).

[0006] However, several practical applications also use GaN / AlGaN HEMTs operating in enhancement mode (also known as "E-mode") and are thus normally off. These devices allow for safe operation and ensure simplified drive circuitry.

[0007] Different methods are known for obtaining normally-off HEMTs, such as using a recessed p-GaN type gate structure or incorporating fluorine plasma under the metal gate region. Specifically, the pGaN type gate structure is one of the most commonly used products currently available on the market because it has excellent electrical properties and is easier to fabricate compared to the other solutions mentioned above.

[0008] In detail, the pGaN type HEMT has a gate structure that includes a metal gate region and a channel modulation region, which is pGaN (gallium nitride having p-type conductivity due to doping with, for example, magnesium) and extends between the metal gate region and the barrier layer. It is well known that the presence of the channel modulation region changes the band diagram of the HEMT and makes it a normally-off type.

[0009] However, there is currently no known solution that allows both D-mode HEMTs and E-mode HEMTs of the pGaN gate type to be fabricated in an integrated manner while maintaining the high electrical performance of these devices. As a result, it is currently not possible in practice to have both types of devices on a monolithic and small-sized support.

[0010] In fact, it has been verified that known solutions for integrating E-mode HEMTs of the pGaN gate type with D-mode HEMTs having a Schottky type gate structure include D-mode HEMTs with a highly degraded electrical performance. This is because during the step of forming the gate structure of the D-mode HEMT, an etch of the oxide covering the barrier layer is used, and the oxide is removed in the region where the gate structure is desired to be formed to locally expose the barrier layer so that a Schottky contact can be formed. This etch damages the upper surface of the barrier layer, which is intended to contact the metal gate region. Specifically, the etch introduces traps in the barrier layer for charge carriers and this results in unstable gate voltage and a higher on-state resistance. More specifically, the damage to the barrier layer causes leakage current in the reverse-biased Schottky junction and makes the pinch-off voltage very sensitive to various manufacturing process factors.

[0011] On the contrary, it is known that especially for high-power applications (i.e., for a drain voltage that may reach 650 V), currently there is no available solution that allows integrating both an E-mode HEMT with a pGaN gate type and a D-mode HEMT with an insulated gate structure into the same manufacturing process. In fact, the high thickness of the gate insulating layer for D-mode HEMTs makes the fabrication of these D-mode HEMTs incompatible with the manufacturing process flow of E-mode HEMTs with pGaN gate types. Currently, D-mode HEMTs with insulated gate structures and E-mode HEMTs with pGaN gate types are fabricated separately and then these two types of HEMTs are assembled on a single support. As a result, their fabrication is not integrated and the result is not a monolithic solution either.

[0012] An object of the present disclosure is to provide an HEMT device, a manufacturing process thereof, and an electronic component including the HEMT device that overcome the drawbacks of the prior art. Summary of the Invention

[0013] According to the present disclosure, there are provided an HEMT device, a manufacturing process thereof, and an electronic component including the HEMT device. The HEMT device includes: a heterostructure including a channel layer and a barrier layer, the barrier layer extending on a first surface of the channel layer; a dielectric protection layer of a dielectric material, the dielectric protection layer extending on the first surface of the barrier layer, the first surface of the barrier layer being opposite to the channel layer along a first direction; a first conductive terminal extending completely through the dielectric protection layer and the barrier layer along the first direction; and a gate region extending on the dielectric protection layer. Brief Description of the Drawings

[0014] To better understand the present disclosure, reference is now made to the accompanying drawings, and the preferred embodiments are described only by way of non-limiting examples, in which:

[0015] Figure 1 A cross-section of the present HEMT device according to one embodiment is shown;

[0016] Figures 2A to 2J Is shown Figure 1 The cross-section of the HEMT device in subsequent manufacturing steps;

[0017] Figures 3A to 3C Is shown that can be integrated with Figure 1 The cross-section of other HEMT devices in subsequent manufacturing steps of the HEMT device; and

[0018] Figure 4 Is shown according to one embodiment including Figure 1 The HEMT device of Figure 3C And the cross-section of an electronic component of other HEMT devices.

[0019] Specifically, a reference figure is shown in a three-axis Cartesian system defined by an X-axis, a Y-axis, and a Z-axis, the X-axis, the Y-axis, and the Z-axis being orthogonal to each other.

[0020] In the following description, elements common to different embodiments have been denoted by the same reference numerals. Detailed Description

[0021] Figure 1 A HEMT device (also referred to as a first HEMT device) 50 is shown. The HEMT device 50 is specifically normally-on and is thus a depletion "D-mode" HEMT device.

[0022] The HEMT device 50 is particularly suitable for use in RF applications such as, for example, 4G and 5G base stations, which include the evolution and variations of technologies, portable telephones, RF cooking devices, drying and heating devices, avionics and systems, L-band and S-band radars, etc.

[0023] The HEMT device 50 is formed in a body 55. The body 55 has a first surface 55A and a second surface 55B and includes a substrate 60, a heterostructure 62 extending over the substrate 60, and a dielectric protection layer 67 extending over the heterostructure 62.

[0024] A substrate 60 of a semiconductor material (e.g., silicon or silicon carbide, sapphire (Al2O3) or other materials) extends between the second surface 55B of the body 55 and a corresponding surface 60A, the corresponding surface 60A being opposite the first surface 55A along the Z-axis.

[0025] The heterostructure 62 includes a compound semiconductor material having group III-V elements and extends onto the surface 60A of the substrate 60.

[0026] The heterostructure 62 is formed by a channel layer 64 of a first semiconductor material and a barrier layer 66 of a second semiconductor material. The first semiconductor material is, for example, gallium nitride (GaN) or a gallium nitride-based ternary alloy such as InGaN (here intrinsic gallium nitride). The channel layer 64 extends onto the substrate 60 and has a surface 64A opposite the surface 60A along the Z-axis. The second semiconductor material is, for example, a ternary or quaternary alloy based on gallium nitride such as Al x Ga 1-x N, AlInGaN, In x Ga 1-x N, Al x In 1-x Al, AlScN (here intrinsic aluminum gallium nitride AlGaN). The barrier layer 66 extends between the surface 64A of the channel layer 64 and a surface 66A, the surface 66A being opposite the surface 64A along the Z-axis.

[0027] According to an embodiment not shown, the HEMT device 50 may further include a nucleation layer and a buffer layer between the substrate 60 and the heterostructure 62, the buffer layer extending over the nucleation layer. Specifically, the nucleation layer is a material that allows the channel layer 64 to nucleate on the substrate 60, thereby reducing the lattice mismatch between the channel layer 64 and the substrate 60. For example, the nucleation layer is aluminum nitride (AlN). In addition, the buffer layer is a material that reduces the drain current of the zero bias IDSS of the HEMT device 50, for example, it is GaN doped with carbon atoms.

[0028] Dielectric cap layer 67 extends onto surface 66A of barrier layer 66 and forms first surface 55A of body 55 .

[0029] The dielectric protection layer 67 is a dielectric material such as aluminum oxide (Al2O3), silicon oxide (SiO2), silicon nitride (Si3N4), and aluminum nitride (AlN).

[0030] The dielectric protection layer 67 has a thickness t measured along the Z axis. d , thickness t d Less than 10 nm and in particular between approximately 1 nm and approximately 7 nm inclusive.

[0031] As better described below, the dielectric protection layer 67 allows the barrier layer 66 to be protected during the fabrication of the HEMT device 50 , avoiding the formation of traps for charge carriers in the barrier layer 66 that would degrade the electrical performance of the HEMT device 50 .

[0032] The HEMT device 50 may further include a passivation layer 68 of a dielectric material, or formed of a stack of dielectric materials such as, for example, silicon nitride and silicon oxide, and extending onto the first surface 55A of the body 55. Figure 1 In the example of FIG. 1 , the case where the passivation layer 68 is formed of a single layer of dielectric material is exemplarily shown, however, it is similarly possible to have a more complex structure of the passivation layer 68 (such as, for example Figure 2J shown).

[0033] The HEMT device 50 also includes a source region 70 and a drain region 72 extending in direct electrical contact with the heterostructure 62, and a gate region 74 extending between the source region 70 and the drain region 72 and on the dielectric protection layer 67 to be physically insulated from the heterostructure 62 and electrically coupled to the heterostructure 62 by means of a physical phenomenon such as a tunnel effect.

[0034] The main body 55 accommodates Figure 1 An active region 76 is indicated by a dashed line in FIG. 5 , which accommodates a conducting channel of the HEMT device 50 in use.

[0035] The source region 70 and the drain region 72 are made of a conductive material (such as a metallic material) and extend in depth into the body 55, completely through the dielectric protection layer 67 and the barrier layer 66 and up to the surface 64A of the channel layer 64.

[0036] In practice, the source region 70 and the drain region 72 respectively form the source electrode S and the drain electrode D of the HEMT device 50.

[0037] Specifically, the source region 70 and the drain region 72 form an ohmic contact with the heterostructure 62, particularly with the channel layer 64.

[0038] According to different embodiments not illustrated herein, the source region 70 and the drain region 72 may only partially extend through the barrier layer 66 and end within the barrier layer 66.

[0039] According to different embodiments not illustrated herein, the source region 70 and the drain region 72 may only extend through the insulating layer 68 and the dielectric protection layer 67 until reaching the surface 66A of the barrier layer 66, and thus do not need to extend in depth into the barrier layer 66.

[0040] According to other embodiments not illustrated herein, the source region 70 and the drain region 72 may also partially extend through the channel layer 64 and end within the channel layer 64.

[0041] In addition, the source region 70 and the drain region 72 may extend into the body 55 differently from each other in depth.

[0042] In practice, depending on the specific application of the HEMT device 50 and the specific manufacturing process used to obtain the source region 70 and the drain region 72, the source region 70 and the drain region 72 may be in direct ohmic contact with the channel layer 64, or may be in electrical contact with the channel layer 64 due to different physical phenomena (such as, due to the tunneling effect).

[0043] The gate region 74 is made of a conductive material (such as a metallic material) and, depending on the specific application, may be formed by a single conductive layer or by a stack of conductive layers, the stack of conductive layers including, for example, gold, nickel, titanium, etc.

[0044] The dielectric protection layer 67 is directly interposed between the barrier layer 66 and the gate region 74 along the Z axis. In other words, the dielectric protection layer 67 extends to contact both the barrier layer 66 and the gate region 74.

[0045] The gate region 74 forms the gate electrode G of the HEMT device 50.

[0046] In particular, the gate region 74 is physically insulated relative to the heterostructure 62 due to the dielectric cap layer 67. In other words, the gate region 74 and the portion of the dielectric cap layer 67 that is vertically aligned with the gate region 74 (i.e., aligned along the Z-axis) together form an insulated gate structure of the HEMT device 50. However, there may be a tunneling phenomenon between the gate region 74 and the heterostructure 62, which causes the gate region 74 to be electrically coupled to the heterostructure 62.

[0047] Specifically, dielectric cap layer 67 extends uniformly between barrier layer 66 and passivation layer 68 or gate region 74. Alternatively, dielectric cap layer 67 may extend locally between barrier layer 66 and gate region 74, so it may not extend under passivation layer 68. Nevertheless, at least at gate region 74, dielectric cap layer 67 is present.

[0048] For example, gate region 74 may include a surface portion 74A and an upper portion 74B that are continuous with each other. Surface portion 74A extends onto dielectric cap layer 67 and through passivation layer 68 , while upper portion 74B extends onto surface portion 74A and partially extends over passivation layer 68 .

[0049] In detail, the passivation layer 68 extends over both the drain region 72 and the source region 70 , for example such that the gate region 74 is partially exposed.

[0050] In the following, reference Figures 2A to 2J , describes the fabrication steps of the HEMT device 50 , and in particular the fabrication steps leading to the formation of a gate region 74 superimposed on the dielectric cap layer 67 .

[0051] Figures 2A to 2J The focus is on the fabrication of the gate region 74 superimposed on the dielectric protection layer 67, and known (concurrent, preceding and / or subsequent) steps for forming other components of the HEMT device 50, such as electrical contact metallization, general electrical connections and any other elements useful or necessary for the operation of the HEMT device 50, which are known per se and not shown here, are not illustrated.

[0052] Figure 2A 1 and 10. During the manufacturing steps of the HEMT device 50, the first surfaces 100A (corresponding to Figure 1 The cross section of the working body 100 is a cross section of the working body 100 of the surface 66a) and the second surface 100B. Figure 1 Describe and Figure 1 Elements which are common to the contents shown in the drawings are indicated with the same reference numerals and, since their manufacture is known per se, are not described again in detail.

[0053] In the working body 100, a substrate 60 and a heterostructure 62 including a channel layer 64 and a barrier layer 66 have been formed.

[0054] Subsequently, as Figure 2B shown, a dielectric layer 102 of a dielectric layer material (such as Al2O3, SiO2, Si3N4, AlN) is formed on the first surface 100A of the workpiece body 100.

[0055] The dielectric layer 102 has a thickness along the Z-axis, the thickness is less than 10 nm and specifically between about 1 nm and about 7 nm (including the boundary values), and the dielectric layer 102 is formed, for example, by atomic layer deposition (ALD). For example, water-based ALD is used and performed (in a thermal manner or by plasma) at about 300 °C.

[0056] At the end of the manufacturing step, the dielectric layer 102 will form Figure 1 the dielectric protection layer 67 of the HEMT device 50.

[0057] Specifically, in Figure 1 the embodiment, the dielectric layer 102 formed as described herein has defined the dielectric protection layer 67, and for other embodiments of the HEMT device 50, other manufacturing steps can be envisioned to obtain the dielectric protection layer 67 starting from the dielectric layer 102.

[0058] For example, in the case where the dielectric protection layer 67 only extends under the gate region 74, etching is performed after the formation of the dielectric layer 102 described in reference Figure 2B to selectively remove the portions of the dielectric layer 102 that are not vertically aligned with the gate region 74, leaving the portions of the dielectric layer 102 that are vertically aligned with the gate region 74 and form the dielectric protection layer 67.

[0059] Referring again to the HEMT device 50 according to the embodiment described in detail herein, at Figure 2B the end of the step, the dielectric protection layer 67 is formed. As a result, the subsequent figures show the dielectric protection layer 67 instead of the dielectric layer 102. As previously described, the dielectric protection layer 67 together with the heterostructure 62 and the substrate 60 forms the body 55.

[0060] Subsequently, as Figure 2C shown, a first insulating layer 104 of an insulating material (such as silicon oxide) is formed on the dielectric protection layer 67 (for example, on the first surface 55A of the body 55).

[0061] Specifically, the first insulating layer 104 is formed on Figure 1At the position where the gate region 74 of the HEMT device 50 is to be formed. More specifically, the first insulating layer 104 is selectively formed at the position where the gate region 74 will subsequently be formed and is formed laterally along the x-axis to the position where the gate region 74 will be formed (e.g., on both sides of the gate region 74, for several micrometers or tenths of a micrometer starting from the gate region 74, e.g., 0.4 μm). At the end of the manufacturing step, the first insulating layer 104 will form Figure 1 a portion of the passivation layer 68 of the HEMT device 50.

[0062] The first insulating layer 104 has a thickness between about 20 nm and about 100 nm (e.g., equal to 50 nm) and is formed, for example, based on plasma (e.g., SiH4 plasma), by chemical vapor deposition (CVD). The CVD is performed to uniformly deposit an oxide layer on the dielectric protection layer 67 and then chemical etching (e.g., based on CF4) is performed on the deposited layer to leave the portion of the deposited layer that forms the first insulating layer 104, rather than selectively removing the remaining portion of the deposited layer.

[0063] Subsequently, as Figure 2D shown, a second insulating layer 106 of a passivation material (such as silicon nitride) can be formed on the first insulating layer 104 and on the regions of the dielectric protection layer 67 exposed by the first insulating layer 104. However, this second insulating layer 106 is optional and may be absent in different embodiments of the HEMT device 50.

[0064] The second insulating layer 106 has a thickness along the Z-axis that is between about 40 nm and about 150 nm and is, for example, equal to about 80 nm, and the second insulating layer 106 is formed, for example, by CVD, and the CVD is performed to deposit the second insulating layer 106 in a uniform manner as described above.

[0065] At the end of the manufacturing step, the second insulating layer 106 will form Figure 1 a portion of the passivation layer 68 of the HEMT device 50.

[0066] Subsequently, as Figure 2E shown, the source region 70 and the drain region 72 are formed.

[0067] Specifically and in a manner not shown as it is known per se, one or more chemical etchings are performed (e.g., based on BCl3 or ALE process) to create corresponding trenches for the source region 70 and the drain region 72. The trenches are formed through the second insulating layer 106, the dielectric protection layer 67, and the barrier layer 66, where the source region 70 and the drain region 72 will be formed respectively. For example, this etching step is performed using a mask that exposes the regions of the second insulating layer 106 that will form the source region 70 and the drain region 72 respectively and that will be removed after the etching step. Thereafter, the source region 70 and the drain region 72 are formed in the corresponding trenches, for example, by forming a mask that exposes the trenches covering the remaining part of the second insulating layer 106; performing metal deposition (e.g., Ti / AlCu / TiN stack) in the trenches and on the mask; removing the mask and the metal deposition thereon; and performing thermal annealing (e.g., at about 560 °C).

[0068] Subsequently, as Figure 2F shown, a third insulating layer 108 of a passivation material such as silicon nitride can be formed on the second insulating layer 106 and the source region 70 and the drain region 72.

[0069] The third insulating layer 108 has a thickness along the Z-axis that is between about 40 nm and about 150 nm and is, for example, equal to about 80 nm, and the third insulating layer 108 is formed, for example, by CVD, and the CVD is performed to deposit the third insulating layer 108 in a uniform manner as described previously.

[0070] At the end of the manufacturing step, the third insulating layer 108 will form Figure 1 part of the passivation layer 68 of the HEMT device 50.

[0071] Subsequently, as Figure 2G shown, a working window (or opening) 110 is formed through the second insulating layer 106 and the third insulating layer 108 to expose the first insulating layer 104. For example, only a part of the first insulating layer 104 is exposed, that is, parts of the second insulating layer 106 and the third insulating layer 108 can be retained on the first insulating layer 104 at its extreme parts along the X-axis. The working window 110 is formed at the position where the gate region 74 will be formed, specifically, it is formed at the position where the gate region 74 will be formed and in the regions laterally of the gate region 74 along the X-axis.

[0072] The working window 110 is formed by selectively chemically etching the second insulating layer 106 and the third insulating layer 108 to expose the first insulating layer 104 without etching the first insulating layer 104. For example, the chemical etching can be based on BCl3 or carried out by means of an ALE process and is performed using a mask that exposes the area of the second insulating layer 106 that will form the working window 110 and is removed after the etching step.

[0073] Subsequently, as Figure 2H shown, a fourth insulating layer 112 of an insulating material such as tetraethyl orthosilicate (TEOS) is formed on the third insulating layer 108 and the first insulating layer 104 exposed by the working window 110.

[0074] The fourth insulating layer 112 has a thickness along the Z-axis that is between about 80 nm and about 350 nm and is, for example, equal to about 150 nm, and the fourth insulating layer 112 is formed, for example, by CVD, and the CVD is performed to deposit the fourth insulating layer 112 in a uniform manner as described above.

[0075] At the end of the manufacturing step, the fourth insulating layer 112 will form Figure 1 part of the passivation layer 68 of the HEMT device 50.

[0076] Subsequently, as Figure 2I shown, a gate window (or opening) 114 is formed through the fourth insulating layer 112 and the first insulating layer 104 to expose the dielectric protection layer 67 at the location where the gate region 74 will be formed. For example, the gate window 114 has a width along the X-axis that is smaller than the width of the working window 110 described previously, such that portions of the fourth insulating layer 112 and the first insulating layer 104 can remain beside the gate region 74 when formed.

[0077] The gate window 114 is formed by a selective chemical etching step of the fourth insulating layer 112 and the first insulating layer 104 to expose the dielectric protection layer 67 without etching the dielectric protection layer 67 and thus without exposing the underlying barrier layer 66. For example, considering the case where the fourth insulating layer 112 and the first insulating layer 104 are of the same material and thus only one chemical etching is sufficient in this step, the chemical etching can be based on a fluorinated solvent or in any case on a chemical solvent that is configured to etch the materials of the fourth insulating layer 112 and the first insulating layer 104 without etching the material of the dielectric protection layer 67. For example, the chemical etching is performed using a mask that exposes the area of the fourth insulating layer 112 that will form the gate region 74 and is removed after the etching step.

[0078] Subsequently, as Figure 2JAs shown, the gate region 74 is formed on the dielectric protection layer 67 and formed in the gate window 114.

[0079] Specifically, a mask exposing the gate window 114 (and also the region of the fourth insulating layer 112 continuous with the gate window 114) is formed, covering the rest of the fourth insulating layer 112, and then metal (such as a Ti / AlCu / TiN stack) is deposited on the mask and in the gate window 114 (and also possibly on the region of the fourth insulating layer 112 exposed by the gate window 114). Removal of the mask and the metal deposition thereon is performed, and finally thermal annealing (such as at about 560 °C) is performed. Specifically, if the mask used for metal deposition only exposes the gate window 114, the gate region 74 will be aligned with the gate window 114 and thus only include the surface portion 74A, while if the mask used for metal deposition also exposes the region of the fourth insulating layer 112 continuous with the gate window 114, the gate region 74 will also extend beyond the gate window 114 on the fourth insulating layer 112 and thus include both the surface portion 74A and the upper portion 74B.

[0080] Then, further manufacturing steps of the HEMT device 50 can be carried out, which are not shown and not described herein as they are known (such as the formation of metallization layers, etc.).

[0081] From an examination of the features of the present disclosure made in accordance with the present disclosure, the advantages provided by the present disclosure are obvious.

[0082] Specifically, the previously described manufacturing process allows the integration of the fabrication of D-mode HEMTs and E-mode HEMTs with pGaN gate structures, such that these two solutions are integrated and thus their complexity and manufacturing costs are reduced.

[0083] In fact, the dielectric protection layer 67 prevents Figure 2I the surface 66A of the barrier layer 66 from being damaged by the chemical etching performed to form the gate region 74, introducing traps for charge carriers in the barrier layer 66 and causing a degradation in the electrical performance of the HEMT device 50. However, the reduced thickness of the dielectric protection layer 67 does not make the fabrication of D-mode type HEMT devices 50 incompatible with the fabrication of known E-mode HEMTs.

[0084] In detail, in Figure 2IDuring the chemical etching of , the presence of the dielectric protection layer 67 allows the threshold voltage of the HEMT device 50 to be stabilized, the gate leakage current under reverse bias conditions to be reduced, and the on-resistance to be decreased. In addition, the thickness of the dielectric protection layer 67 modifies the pinch-off voltage, and thus this parameter can be changed based on the dielectric protection layer 67 during the design step. More specifically, for gate voltages lower than the pinch-off voltage and the same pinch-off voltage, the drain leakage current decreases as the thickness of the dielectric protection layer 67 increases.

[0085] More specifically, it has been verified that these advantages can be achieved even if the dielectric protection layer 67 covers only the region of the barrier layer 66 located at the gate region 74 (e.g., it is vertically aligned with the gate region 74).

[0086] Specifically, the HEMT device 50 is particularly suitable for operating at low power, i.e., the drain voltage value is typically lower than or equal to about 12V. This further simplifies the structure of the HEMT device 50 because in this case, for example, there may be no field plate.

[0087] Finally, it is clear that modifications and variations can be made to the present disclosure described and illustrated herein without thereby departing from the scope of the present disclosure as defined in the appended claims.

[0088] For example, the different embodiments described can be combined with each other to provide other solutions.

[0089] In addition, although Figures 2A to 2J reference is made to the fabrication of the depletion-mode HEMT device 50, the processes described herein are compatible with simultaneously fabricating at least one other HEMT device (also referred to as a second device HEMT), in particular an enhancement-mode and, for example, having a pGaN-type gate structure, starting from the same working body 100.

[0090] Figure 3C An enhancement-mode HEMT device 80 is shown, and the HEMT device 80 is obtained by means of the previously described fabrication process and starting from the same working body 100 used to fabricate the HEMT device 50. Thus, the HEMT device 80 and the HEMT device 50 are integrated with each other and define a monolithic solution.

[0091] Specifically, the HEMT device 80 and the HEMT device 50 are included in an electronic component (such as Figure 4 shown using the reference numeral 90), and the details of the electronic component are of the monolithic type and are formed starting from the working body 100, such that the HEMT device 80 and the HEMT device 50 share the substrate 60 and the heterostructure 62.

[0092] As Figure 4As exemplarily shown in FIG. 5 , the depletion mode HEMT device 50 and the enrichment mode HEMT device 80 may be lateral to each other, for example, they are arranged side by side with each other along the X-axis.

[0093] Specifically, the HEMT device 80 has a pGaN type gate structure.

[0094] As reference Figures 3A to 3C As shown, fabrication of the HEMT device 80 occurs by performing the same fabrication steps previously described, wherein prior to forming the dielectric layer 102, Figure 2A A local formation of a channel modulation region is added on the barrier layer 66, and the channel modulation region is pGaN (for example, gallium nitride having P-type conductivity due to magnesium doping).

[0095] The channel modulation region (such as Figure 3A The gate region 74 , shown using reference numeral 130 , will become part of a gate structure 132 of the HEMT device 80 .

[0096] In detail, after executing Figure 2A After the steps previously described in , the channel modulation region 130 is formed ( Figure 3A ) on the surface 66A of the barrier layer 66.

[0097] In more detail, this occurs by uniformly depositing a pGaN layer (not shown and having, for example, a thickness between about 30 nm and about 150 nm) on the surface 66A of the barrier layer 66. Thereafter, chemical etching is performed on the pGaN layer so that its portion is placed at the location where the gate structure of the HEMT device 80 will be formed and thus the channel modulation region 130 will be formed, without removing the remaining portion of the pGaN layer that will not be part of the gate structure of the HEMT device 80. In detail, this occurs by forming a mask on the pGaN layer, the mask covering the portion of the pGaN layer intended to form the channel modulation region 130 and leaving the remaining portion of the pGaN layer exposed, performing etching by known techniques with the aid of the mask so as to remove the portion of the pGaN layer that will not be part of the gate structure, and finally removing the mask to obtain Figure 3A The structure shown.

[0098] Then, if Figure 3B As shown, the dielectric layer 102 is formed on both the channel modulation region 130 and the regions of the barrier layer 66 exposed by the channel modulation region 130 in a manner similar to that previously described.

[0099] In the embodiment considered here, the dielectric layer 102 defines a dielectric protection layer 67 .

[0100] Nonetheless and similar to what has been previously described, other steps can be performed to form a dielectric protection layer 67 starting from the dielectric layer 102. For example, in the case where the dielectric protection layer 67 extends only below the gate region 74 of the HEMT device 50, after the formation of the dielectric layer 102, an etching is performed that selectively removes the portions of the dielectric layer 102 that are not intended to be vertically aligned with the gate region 74 of the HEMT device 50, instead leaving the portions of the dielectric layer 102 that are intended to be vertically aligned with the gate region 74 of the HEMT device 50 and thus form the dielectric protection layer 67.

[0101] Similarly, if it is desired to have a Schottky contact between the channel modulation region 130 and the gate region 74 of the HEMT device 80, this chemical etching can be used to remove only the portions of the dielectric layer 102 that extend over the channel modulation region 130.

[0102] Returning to Figure 3B the embodiment of, the steps are similar to the steps previously referenced Figures 2C to 2J described and thus are not described in detail, which results in Figure 3C the structure of the HEMT device 80 shown.

[0103] The HEMT device (50) is generally described as including: a heterostructure (62), the heterostructure (62) including a channel layer (64) and a barrier layer (66), the barrier layer (66) extending along a first axis (Z) over the channel layer (64); a dielectric protection layer (67) of a dielectric material, the dielectric protection layer (67) extending along the first axis (Z) over the barrier layer (66); and a gate region (74), the gate region (74) extending along the first axis (Z) over the dielectric protection layer (67), wherein the dielectric protection layer (67) has a thickness (t d ) along the first axis (Z) that is less than 10 nm.

[0104] The thickness (t d ) of the dielectric protection layer (67) is between 1 nm and 7 nm.

[0105] The dielectric protection layer (67) is of one of the following materials: aluminum oxide, silicon oxide, silicon nitride, and aluminum nitride.

[0106] The channel layer (64) is of gallium nitride or a gallium nitride-based alloy, and the barrier layer (66) is of a gallium nitride-based alloy, specifically AlGaN.

[0107] The dielectric protection layer (67) is directly interposed between the barrier layer (66) and the gate region (74) along the first axis (Z).

[0108] The HEMT device (50) is depletion mode.

[0109] The gate region (74) and the dielectric protection layer (67) form an insulated gate structure of the HEMT device (50).

[0110] The electronic component (90) is generally described as including a depletion-mode HEMT device (50) and other enhancement-mode HEMT devices (80) integrated with each other.

[0111] The other HEMT devices (80) have a pGaN-type gate structure.

[0112] The process of manufacturing a HEMT device (50) including a heterostructure (62) is generally described as including a channel layer (64) and a barrier layer (66), the barrier layer (66) extending onto the channel layer (64) along a first axis (Z), and the manufacturing process includes the following steps: forming a dielectric protection layer (67) of a dielectric material on the barrier layer (66); and forming a gate region (74) on the dielectric protection layer (67), wherein the dielectric protection layer (67) has a thickness (t d ) less than 10 nm along the first axis (Z).

[0113] The manufacturing process further includes the following steps: forming a plurality of insulating layers (104, 106, 108, 112) on the dielectric protection layer (67); and forming a gate window (114) through the insulating layers (104, 106, 108, 112) to at least partially expose the dielectric protection layer (67), wherein the step of forming the gate region (74) occurs by means of the gate window (114).

[0114] The step of forming the gate window (114) includes performing one or more chemical etchings configured to selectively remove at least a portion of the insulating layers (104, 106, 108, 112) without removing the dielectric protection layer (67).

[0115] The steps of forming the insulating layers (104, 106, 108, 112) include: forming a first insulating layer (104) of the insulating layers (104, 106, 108, 112) on the dielectric protection layer (67), the first insulating layer (104) being of an insulating material; sequentially forming a second insulating layer (106) and a third insulating layer (108) of the insulating layers (104, 106, 108, 112) on the first insulating layer (104), the second insulating layer (106) and the third insulating layer (108) being of a passivation material; forming a working window (110) through the second insulating layer (106) and the third insulating layer (108) to at least partially expose the first insulating layer (104); and forming a fourth insulating layer (112) of the insulating layers (104, 106, 108, 112) through the working window (110) and on the exposed first insulating layer (104), the fourth insulating layer (112) being of an insulating material, wherein the step of forming the gate window (114) includes performing one or more chemical etches configured to selectively remove the fourth insulating layer (112) and the first insulating layer (104) to at least partially expose the dielectric protection layer (67).

[0116] The manufacturing process further includes, between the step of forming the second insulating layer (106) and the step of forming the third insulating layer (108): the step of forming a source region (70) and a drain region (72) of the HEMT device (50) through the second insulating layer (106) and the barrier layer (66); and the step of forming the third insulating layer (108), the step of forming the third insulating layer (108) including forming the third insulating layer (108) on the second insulating layer (106), the source region (70), and the drain region (72).

[0117] The manufacturing process further includes, before the step of forming the dielectric protection layer (67): the step of locally forming a channel modulation region (130) of pGaN on the barrier layer (66), the channel modulation region (130) being configured to be included in a gate structure (132) of other HEMT devices (80) lateral to the HEMT device (50); and the step of forming the dielectric protection layer (67), the step of forming the dielectric protection layer (67) including forming the dielectric protection layer (67) on the channel modulation region (130) and the barrier layer (66) exposed by the channel modulation region (130).

[0118] The various embodiments described above can be combined to provide other embodiments. Aspects of the embodiments can be modified as needed to incorporate concepts from various patents, applications, and publications to provide other embodiments.

[0119] These and other changes may be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed so as to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments and the full scope of equivalents to such claims. Accordingly, the claims are not limited by the disclosure.

Claims

1. A HEMT device, comprising: a heterostructure including a channel layer and a barrier layer, the barrier layer extending on a first surface of the channel layer; a dielectric protection layer of a dielectric material, the dielectric protection layer extending on the first surface of the barrier layer, the first surface of the barrier layer being opposite to the channel layer along a first direction; a first conductive terminal extending completely through the dielectric protection layer and the barrier layer along the first direction; and a gate region extending on the dielectric protection layer.

2. The HEMT device according to claim 1, wherein the dielectric protection layer has a first thickness along the first direction, and the first thickness is less than 10 nm.

3. The HEMT device according to claim 2, wherein the first thickness of the dielectric protection layer is in a range of 1 nm to 7 nm.

4. The HEMT device according to claim 1, wherein the dielectric protection layer is made of one of the following materials: aluminum oxide, silicon oxide, silicon nitride, and aluminum nitride.

5. The HEMT device according to claim 1, wherein the channel layer is made of gallium nitride, and the barrier layer is made of a gallium nitride-based alloy.

6. The HEMT device according to claim 1, wherein the dielectric protection layer is directly between the barrier layer and the gate region.

7. The HEMT device according to claim 1, wherein the HEMT device is a depletion mode device.

8. The HEMT device according to claim 1, wherein the gate region and the dielectric protection layer form an insulated gate structure of the HEMT device.

9. The HEMT device according to claim 1, further comprising a passivation layer on the dielectric protection layer, the passivation layer having a first gap along a second direction, the second direction being transverse to the first direction, and the gate region being in the first gap.

10. A method for manufacturing a HEMT device, comprising: forming a dielectric protection layer on a first surface of a heterostructure, the heterostructure including a barrier layer on a channel layer, the first surface being opposite to the channel layer along a first direction; forming a passivation layer on the first surface, the passivation layer including a first portion and a second portion, the first portion having a first depth along the first direction, and the second portion having a second depth along the first direction, the second depth being greater than the first depth; and forming a gate region on the dielectric protection layer, the gate region having a first portion separated from the second portion of the passivation layer along a second direction, the second direction being transverse to the first direction, wherein the dielectric protection layer has a thickness less than 10 nm along the first direction.

11. The manufacturing method according to claim 10, wherein forming the passivation layer comprises: forming a plurality of insulating layers on the dielectric protection layer; and forming a gate window through the insulating layers to expose the dielectric protection layer, wherein the gate region is formed through the gate window.

12. The manufacturing method according to claim 11, wherein forming the gate window comprises: Perform one or more chemical etches configured to selectively remove at least a portion of the insulating layer without removing the dielectric protection layer.

13. The manufacturing method according to claim 12, wherein forming the insulating layer comprises: Forming a first insulating layer of the plurality of insulating layers on the dielectric protection layer; Sequentially forming a second insulating layer and a third insulating layer of the plurality of insulating layers on the first insulating layer, the second insulating layer and the third insulating layer comprising a passivation material; Forming a working window through the second insulating layer and the third insulating layer to expose the first insulating layer; And Forming a fourth insulating layer of the plurality of insulating layers through the working window and on the exposed first insulating layer, wherein forming the gate window comprises: performing one or more chemical etches configured to selectively remove the fourth insulating layer and the first insulating layer to expose the dielectric protection layer.

14. The manufacturing method according to claim 13 further includes: Between forming the second insulating layer and forming the third insulating layer, forming source and drain regions of the HEMT device through the second insulating layer and the barrier layer, and wherein forming the third insulating layer comprises: forming the third insulating layer on the second insulating layer, the source region, and the drain region.

15. The manufacturing method according to claim 10 further comprises: Before forming the dielectric protection layer, locally forming a channel modulation region of pGaN on the barrier layer, wherein forming the dielectric protection layer comprises: forming the dielectric protection layer on the channel modulation region and the barrier layer exposed by the channel modulation region.

16. A device, comprising: A heterostructure, the heterostructure comprising: A channel layer having a first surface; and A barrier layer on the first surface of the channel layer, the barrier layer having a first surface opposite to the channel layer in a first direction; A dielectric layer on the first surface of the barrier layer; A first conductive terminal having a first surface opposite to a second surface in the first direction, the first conductive terminal extending completely through the dielectric protection layer and the barrier layer in the first direction; A gate region on the dielectric layer; and A passivation layer on the first surface of the barrier layer, the passivation layer comprising a first opening exposing the dielectric layer, the gate region being in the first opening, the passivation layer completely covering the first surface of the first conductive terminal.

17. The device according to claim 16, wherein the second surface of the first conductive terminal is coplanar with the first surface of the channel layer.

18. The device according to claim 17, further comprising a second conductive terminal extending completely through the dielectric protection layer and the barrier layer in the first direction.

19. The device according to claim 16, wherein the passivation layer further comprises: A first portion having a first depth in the first direction; And The second part, the second part having a second depth along the first direction, the second depth being greater than the first depth.

20. The apparatus of claim 19, wherein the gate region comprises: a first portion having a first width along a second direction, the second direction being transverse to the first direction, the first portion being in direct contact with the first portion of the passivation layer; and a second portion having a second width along the second direction, the second width being greater than the first width, the second portion being physically separated from the second portion of the passivation layer along the second direction.

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