A gallium nitride device based on a suspended gate process and a manufacturing method thereof

Abstract

The application relates to a gallium nitride device based on a suspended gate process and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device comprises, from bottom to top, a substrate, a GaN buffer layer, a GaN channel layer, an AlN interlayer and an AlGaN barrier layer, source metal and drain metal are arranged on the two sides of the AlGaN barrier layer, the source metal and the drain metal extend to the GaN buffer layer at the bottom, a p-GaN cap layer is arranged on the upper side of the AlGaN barrier layer, and gate metal is arranged on the upper side of the p-GaN cap layer and the side close to the drain metal. The application can effectively improve the gate regulation ability, reduce the leakage, improve the breakdown voltage, inhibit the current collapse and the hot carrier effect, and provides a new solution for the preparation of high-performance GaN power and radio frequency devices.

Description

Technical Field

[0001] The present invention relates to a gallium nitride device based on a suspended gate process and a manufacturing method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] As the performance of Si-based materials approaches theoretical limits, third-generation semiconductor materials, represented by GaN, are becoming the mainstream in semiconductor device development. GaN's exceptional electrical properties, including a wide bandgap, high electron mobility, high saturation velocity, and high breakdown electric field, demonstrate significant potential for application in demanding operating environments such as high frequency, high power, and high temperature. This has led to widespread interest and application of GaN devices in power electronics, microwave radio frequency, and 5G communications.

[0003] However, conventional enhancement-mode GaN HEMT devices still face numerous technical bottlenecks in practical applications, primarily including unstable threshold voltage, limited breakdown voltage, insufficient gate withstand voltage, and high leakage current. First, low threshold voltage with large drift can easily lead to false triggering, complicating drive circuit design and potentially exacerbating device reliability degradation. Second, due to material and process limitations, the device's breakdown voltage is low, limiting its application in high-power, high-voltage applications. Furthermore, insufficient gate withstand voltage increases the risk of device failure, while high leakage current leads to additional power consumption and thermal management issues.

[0004] To address these challenges, researchers have proposed a variety of improvement solutions, such as increasing the threshold voltage by thickening the p-GaN layer, optimizing the interface quality through nitridation, extending the drift region length and introducing a field plate to enhance the breakdown voltage, or optimizing the electron transport characteristics by adjusting the AlGaN composition. However, while these methods improve a certain performance, they often bring new technical difficulties, such as increased process complexity, increased on-resistance, decreased electron mobility, and reliability issues such as gate leakage, parasitic effects, and current collapse. Therefore, how to strike a balance between increasing the threshold voltage, optimizing the breakdown characteristics, and reducing parasitic effects remains an important research direction in the current field of GaN HEMT device design and manufacturing. Summary of the Invention

[0005] In response to the shortcomings of the existing technology, the present invention provides a gallium nitride device based on a suspended gate process, which creates a process method for floating gates. It adopts isotropic dry etching and wet etching as independent implementation schemes to effectively remove the dielectric layer under the gate, improve the electrical performance of the device, and effectively enhance the gate control capability, reduce leakage, increase the breakdown voltage, and suppress current collapse and hot carrier effects, providing a new solution for the preparation of high-performance GaN power and radio frequency devices.

[0006] The present invention also provides a method for manufacturing the gallium nitride device based on the floating gate process.

[0007] The technical solutions of the present invention are as follows:

[0008] A gallium nitride device based on a floating gate process comprises, from bottom to top, a substrate, a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, and an AlGaN barrier layer. Source metal and drain metal are provided on both sides of the AlGaN barrier layer, respectively. The bottoms of the source metal and drain metal extend to the GaN buffer layer. A p-GaN cap layer is provided on the upper side of the AlGaN barrier layer. Gate metal is provided on the upper side of the p-GaN cap layer and on the side close to the drain metal.

[0009] Preferably, according to the present invention, the gate-source spacing of the device is 5 μm, which is the distance from the p-GaN cap layer to the source metal; the gate length is 2 μm, which is the distance between the two ends of the p-GaN cap layer (left to right); the gate-drain spacing is 13 μm, which is the distance from the p-GaN cap layer to the drain metal; and the gate width is 100 μm, which is the extension width of the gate into the paper.

[0010] Preferably, according to the present invention, the length of the gate metal on the upper side of the p-GaN cap layer is the same as the distance between the two ends of the p-GaN cap layer, and the gate metal on one side of the p-GaN cap layer is vertically arranged at one end of the gate metal on the upper side of the p-GaN cap layer. The gate metal on one side of the p-GaN cap layer is called a suspended gate.

[0011] Preferably, according to the present invention, the width of the suspended gate is 5-200 nm, and the height of the suspended gate is 50%-90% of the height of the p-GaN cap layer, so that the bottom of the suspended gate maintains a certain suspended distance from the AlGaN barrier layer.

[0012] According to the present invention, preferably, the material of the substrate is silicon carbide, silicon or sapphire;

[0013] The thickness of the GaN buffer layer is 0.1-50 μm;

[0014] The thickness of the GaN channel layer is 1-1000nm;

[0015] The thickness of the AlN intercalation layer is 0.2-2 nm;

[0016] The thickness of the AlGaN barrier layer is 5-50 nm, and the molar ratio of Al is 5-35%;

[0017] The thickness of the p-GaN cap layer is 1-1000nm and the doping concentration is 1×10 17 -1×10 20 cm -3 , the doping source is magnesium or boron;

[0018] The source metal and the drain metal are made of the same material, which is a Ti / Al / Ni / Au metal stack, a Ti / Al / Ti / Au metal stack, or a Ti / Al / Mo / Au metal stack;

[0019] The gate metal material is Ni / Au metal stack.

[0020] According to the present invention, the substrate is preferably made of silicon carbide.

[0021] The thickness of the GaN buffer layer is 5.2 μm;

[0022] The thickness of the GaN channel layer is 200nm;

[0023] The thickness of the AlN intercalation layer is 0.5 nm;

[0024] The thickness of the AlGaN barrier layer is 12.5 nm, and the molar ratio of Al is 18%;

[0025] The thickness of the p-GaN cap layer is 100 nm and the doping concentration is 3×10 19 cm -3 ;

[0026] The source metal and the drain metal are made of Ti / Al / Ni / Au metal stacks.

[0027] The manufacturing method of the gallium nitride device based on the floating gate process comprises the following steps:

[0028] S1. Growing a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer, and a p-GaN cap layer on a substrate;

[0029] S2, dry etching away the excess p-GaN cap layer;

[0030] S3, removing the GaN channel layer, AlN intercalation layer, and AlGaN barrier layer outside the device by dry etching to form a mesa;

[0031] S4, evaporating source metal and drain metal on the table;

[0032] S5, annealing the drain metal and source metal regions to form ohmic contacts;

[0033] S6. depositing a dielectric layer on the AlGaN barrier layer and the p-GaN cap layer;

[0034] S7, the dielectric layer above the p-GaN cap layer is opened by dry etching;

[0035] S8, evaporating a gate metal on a side of the p-GaN cap layer close to the drain metal and on top of the p-GaN cap layer;

[0036] S9. Remove the dielectric layer on the AlGaN barrier layer by dry etching or wet etching to achieve the floating gate being suspended.

[0037] According to the present invention, preferably, in step S1, the growth method of the GaN buffer layer, the GaN channel layer, the AlN intercalation layer, the AlGaN barrier layer, and the p-GaN cap layer is a high-quality film formation method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE);

[0038] The etching method in steps S2, S3 and S7 is inductively coupled plasma etching (ICP) or reactive ion etching (RIE).

[0039] According to the present invention, further preferably, in step S1, the growth method is metal organic chemical vapor deposition;

[0040] The etching method in steps S2, S3 and S7 is inductively coupled plasma etching.

[0041] Preferably, according to the present invention, in step S9, the etching method is isotropic inductively coupled plasma etching. During the inductively coupled plasma etching process, the RF power is reduced, and SF6 and O2 gases are introduced simultaneously to achieve etching control. Specifically, O2 reacts with the GaN surface to form a protective film, which effectively protects the p-GaN cap layer area; and the lower RF power suppresses the downward anisotropic diffusion during the etching process, prompting the etching to proceed uniformly in the horizontal direction, that is, isotropic etching, thereby removing the dielectric layer under the gate metal and achieving a suspended effect; the ICP power is set to 1000W, the RF power is set to 100W, the SF6 is set to 60sccm, the O2 is set to 20sccm, and the pressure is set to 1.5Pa.

[0042] Wet etching uses a buffered oxide etchant (BOE) solution plus isopropyl alcohol (IPA), with the ratio of oxide etchant solution to isopropyl alcohol being 95%:5% to 60%:40%, supplemented by ultrasonic vibration immersion to ensure that the dielectric layer under the gate is fully removed, thereby achieving gate suspension.

[0043] According to the preferred embodiment of the present invention, in step S5, the annealing treatment method of the source metal and the drain metal is laser selective annealing;

[0044] The thickness of the dielectric layer is 0-100 nm, and the material of the dielectric layer is Si3N4 or SiO2.

[0045] The beneficial effects of the present invention are:

[0046] 1. Increased threshold voltage: The present invention adopts a suspended gate design to form a wider vertical depletion region in the p-GaN cap layer, achieving a significant increase in the threshold voltage, thereby greatly enhancing the device's turn-on control capability and anti-false triggering performance.

[0047] 2. Suppression of parasitic effects and current collapse: The present invention significantly reduces the RC delay problem caused by parasitic capacitance and effectively alleviates the current collapse phenomenon by designing a suspended gate structure, thereby improving the dynamic response and energy efficiency of the device under high-frequency and high-power operating conditions.

[0048] 3. Improved breakdown voltage: Compared with conventional p-GaN HEMT devices, the present invention adopts a suspended gate structure to exhibit higher breakdown voltage under high-voltage operating conditions, thereby greatly enhancing the stability and reliability of the device in high-voltage applications.

[0049] 4. Increase gate voltage resistance: The presence of the floating gate of the present invention makes the electric field distribution in the gate area more uniform, effectively improving the gate voltage resistance level, thereby ensuring that the device operates more stably and reliably in a high voltage environment.

[0050] 5. Significantly reduce leakage current: The present invention avoids the upward sidewall leakage path of channel electrons by setting a gap between the left side of the gate metal and the left side of the p-GaN cap layer, effectively improving the gate voltage resistance level and significantly reducing the gate leakage current, so that the device can still maintain a low leakage state under high temperature or large bias, thereby improving overall energy efficiency and stability.

[0051] 6. Improved current regulation and conduction performance: The optimized suspended gate structure of the present invention not only improves the electric field distribution, but also solves the problems of decreased electron mobility and increased on-resistance that may be caused by the presence of the dielectric layer, further enhancing the conduction capability of the device and making it suitable for high-efficiency power switch applications.

[0052] 7. Enhanced surge resistance: The balanced electric field distribution and omnidirectional depletion region control of the present invention reduce the risk of damage to materials caused by local high fields, thereby significantly improving the device's surge resistance and ensuring reliability in long-term operation.

[0053] 8. Extending the service life of the device: The introduction of the suspended gate structure of the present invention reduces the degradation and damage problems of the device during long-term operation, thereby extending the service life of the device.

[0054] 9. Expanded Application Scope: The GaN HEMT device, which improves the threshold voltage, breakdown voltage, and gate withstand voltage while reducing gate leakage current, can be widely used in high-power fields such as radio frequency communications, radar systems, satellite communications, and power electronics. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1It is a structural schematic diagram of the present invention;

[0056] Figure 2 Schematic diagram of the structure of a conventional device;

[0057] Figure 3 A comparison diagram of the transfer curves of the present invention and conventional devices;

[0058] Figure 4 A comparison diagram of the breakdown curves of the present invention and conventional devices;

[0059] Figure 5 A comparison diagram of gate withstand voltage between the present invention and conventional devices;

[0060] Among them: 1. substrate; 2. GaN buffer layer; 3. GaN channel layer; 4. AlN intercalation layer; 5. AlGaN barrier layer; 6. p-GaN cap layer; 7. source metal; 8. drain metal; 9. gate metal. DETAILED DESCRIPTION

[0061] The present invention will be further described below with reference to embodiments and accompanying drawings, but is not limited thereto.

[0062] Example 1:

[0063] like Figure 1 As shown, a gallium nitride device based on a floating gate process comprises, from bottom to top, a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, an AlN intercalation layer 4, and an AlGaN barrier layer 5. A source metal 7 and a drain metal 8 are provided on both sides of the AlGaN barrier layer 5, respectively. The bottoms of the source metal 7 and the drain metal 8 extend to the GaN buffer layer 2. A p-GaN cap layer 6 is provided on the upper side of the AlGaN barrier layer 5. A gate metal 9 is provided on the upper side of the p-GaN cap layer 6 and on the side close to the drain metal 8.

[0064] The device has a gate-source spacing of 5μm, which is the distance from the p-GaN cap layer 6 to the source metal 7. The gate length is 2μm, which is the distance between the two ends of the p-GaN cap layer 6 (left to right). The gate-drain spacing is 13μm, which is the distance from the p-GaN cap layer 6 to the drain metal 8. The gate width is 100μm, which is the extension width of the gate into the paper.

[0065] The length of the gate metal 9 on the upper side of the p-GaN cap layer 6 is the same as the distance between the two ends of the p-GaN cap layer 6. The gate metal 9 on one side of the p-GaN cap layer 6 is vertically arranged at one end of the gate metal on the upper side of the p-GaN cap layer. The gate metal 9 on the side of the p-GaN cap layer 6 is called a suspended gate. As for gate leakage, its leakage path is that electrons leak upward from the left side wall of the p-GaN cap layer to the gate metal. The two gate metals designed in the present invention do not completely cover the top of the p-GaN cap layer, that is, a gap is left between the left side of the gate metal and the left side of the p-GaN cap layer. For the upper part of the p-GaN cap layer near the source metal, the vacancy of the gate metal can stagger the sidewall leakage path, effectively improving the gate voltage resistance level and significantly reducing leakage.

[0066] The suspended portion below the right side of the p-GaN cap layer 6 can effectively reduce gate capacitance and improve gate control capability. At the same time, the gate sidewall metal does not contact the barrier layer, which can effectively avoid electric field concentration below the gate near the drain, thereby increasing breakdown voltage and suppressing current collapse. In addition, the side gate provides a longitudinal depletion region, and the suspended gate can provide a gradient longitudinal depletion region, which can increase the threshold voltage while suppressing the hot carrier effect.

[0067] The width of the suspended gate is 200 nm, the height of the suspended gate is 70 nm, and the suspended distance between the bottom of the suspended gate and the AlGaN barrier layer is 30 nm, so that a certain suspended distance is maintained between the bottom of the suspended gate and the AlGaN barrier layer.

[0068] The gate metal 9 is made of a Ni / Au metal stack.

[0069] The material of substrate 1 is silicon carbide;

[0070] The thickness of the GaN buffer layer 2 is 5.2 μm;

[0071] The thickness of the GaN channel layer 3 is 200 nm;

[0072] The thickness of the AlN intercalation layer 4 is 0.5 nm;

[0073] The thickness of the AlGaN barrier layer 5 is 12.5 nm, and the molar ratio of Al is 18%;

[0074] The thickness of the p-GaN cap layer 6 is 100 nm and the doping concentration is 3×10 19 cm -3 , the doping source is magnesium or boron;

[0075] The source metal 7 and the drain metal 8 are made of Ti / Al / Ni / Au metal stacks.

[0076] The manufacturing method of the gallium nitride device based on the floating gate process comprises the following steps:

[0077] S1, growing a GaN buffer layer 2, a GaN channel layer 3, an AlN intercalation layer 4, an AlGaN barrier layer 5, and a p-GaN cap layer 6 on a substrate 1;

[0078] S2, dry etching away the excess p-GaN cap layer 6;

[0079] S3, removing the GaN channel layer 3, AlN intercalation layer 4, and AlGaN barrier layer 5 outside the device by dry etching to form a mesa;

[0080] S4, evaporating source metal 7 and drain metal 8 on the mesa;

[0081] S5, annealing in the drain metal 8 and source metal 7 regions to form ohmic contacts;

[0082] S6, depositing a dielectric layer on the AlGaN barrier layer 5 and the p-GaN cap layer 6;

[0083] S7, the dielectric layer above the p-GaN cap layer 6 is opened by dry etching;

[0084] S8, evaporating a gate metal 9 on a side of the p-GaN cap layer 6 close to the drain metal 8 and on top of the p-GaN cap layer 6;

[0085] S9. Remove the dielectric layer on the AlGaN barrier layer by dry etching to achieve the floating gate being suspended.

[0086] In step S1, the growth method of the GaN buffer layer 2, the GaN channel layer 3, the AlN intercalation layer 4, the AlGaN barrier layer 5, and the p-GaN cap layer 6 is metal organic chemical vapor deposition;

[0087] The etching method in steps S2, S3 and S7 is inductively coupled plasma etching.

[0088] In step S9, the etching method is isotropic inductively coupled plasma etching. During the inductively coupled plasma etching process, the RF power is reduced, and SF6 and O2 gases are introduced simultaneously to achieve etching control. Specifically, O2 reacts with the GaN surface to form a protective film, which effectively protects the p-GaN cap layer 6 area; the lower RF power suppresses the downward anisotropic diffusion during the etching process, prompting the etching to proceed uniformly in the horizontal direction, that is, isotropic etching, thereby removing the dielectric layer under the gate metal and achieving a suspended effect; the ICP power is set to 1000W, the RF power is set to 100W, the SF6 is set to 60sccm, the O2 is set to 20sccm, and the pressure is set to 1.5Pa.

[0089] In step S5, the annealing method of the source metal 7 and the drain metal 8 is laser selective annealing;

[0090] The thickness of the dielectric layer is 30 nm, and the material of the dielectric layer is SiO2.

[0091] Conventional devices such as Figure 2 As shown, the gate metal 9 is disposed above the p-GaN cap layer 6 .

[0092] The performance of this embodiment and conventional devices were verified in Sentaurus TCAD simulation;

[0093] (1) Simulation model construction: Two-dimensional structural models of this embodiment and conventional devices were constructed in Sentaurus TCAD software.

[0094] (2) Simulation parameter settings: Set boundary conditions and initial conditions, including voltage and current. For the transfer curve, first apply a 10V drain voltage, then apply a variable gate voltage. For breakdown, first apply a -6V gate voltage to ensure depletion, then apply the drain voltage until breakdown. For gate withstand voltage, first leave the drain floating, then apply the gate voltage until breakdown.

[0095] (3) Simulation process: Simulation is performed to observe the changes in the electrical properties of this embodiment compared with conventional devices.

[0096] (4) Result analysis: According to the constant current method 10-4mA / mm is the judgment standard, Figure 3 It can be seen that the threshold voltage of the floating gate device of this embodiment is increased from 1.7V of the conventional device to 2.07V. Figure 4 In the breakdown curve, with the critical breakdown field strength of GaN material of 3.3MV / cm as the judgment standard, the breakdown voltage of the suspended gate device reached 2228V, which is better than the 957V of conventional devices. Figure 5 In the gate breakdown voltage curve, with a gate current of 1mA / mm, the floating gate device achieved a gate breakdown voltage of 45.28V, exceeding the 11.25V of conventional devices. This demonstrates that the enhancement-mode GaN device architecture based on floating gate regulation can significantly improve overall device performance and reliability.

[0097] Example 2:

[0098] A method for manufacturing a gallium nitride device based on a floating gate process, the steps of which are as described in Example 1, except that:

[0099] In step S9, wet etching is performed using a buffered oxide etchant (BOE) solution plus isopropyl alcohol (IPA), with a BOE to IPA ratio of 80%:20%. That is, about 20% volume fraction of IPA is added to the BOE etchant, and ultrasonic vibration immersion is used to ensure that the dielectric layer under the gate is fully removed, thereby achieving gate suspension.

Claims

1. A method for manufacturing a gallium nitride device based on a floating gate process, characterized in that: From bottom to top, the GaN device consists of a substrate, a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, and an AlGaN barrier layer. Source metal and drain metal are provided on both sides of the AlGaN barrier layer, and the bottoms of the source metal and drain metal extend to the GaN buffer layer. A p-GaN cap layer is provided on the top of the AlGaN barrier layer, and a gate metal is provided on the top of the p-GaN cap layer and on the side close to the drain metal. The length of the gate metal on the upper side of the p-GaN cap layer is the same as the distance between the two ends of the p-GaN cap layer. The gate metal on the side of the p-GaN cap layer close to the drain metal is perpendicularly arranged at one end of the gate metal on the upper side of the p-GaN cap layer. The gate metal on the side of the p-GaN cap layer close to the drain metal is called a suspended gate. A gap is left between the side of the gate metal on the upper side of the p-GaN cap layer close to the source metal and the sidewall of the p-GaN cap layer close to the source metal; The manufacturing method of the gallium nitride device based on the floating gate process comprises the following steps: S1. Growing a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer, and a p-GaN cap layer on a substrate; S2, dry etching away the excess p-GaN cap layer; S3, removing the GaN channel layer, AlN intercalation layer, and AlGaN barrier layer outside the device by dry etching to form a mesa; S4, evaporating source metal and drain metal on the table; S5, annealing the drain metal and source metal regions to form ohmic contacts; S6. depositing a dielectric layer on the AlGaN barrier layer and the p-GaN cap layer; S7, the dielectric layer above the p-GaN cap layer is opened by dry etching; S8, evaporating a gate metal on a side of the p-GaN cap layer close to the drain metal and on top of the p-GaN cap layer; S9. Remove the dielectric layer on the AlGaN barrier layer by dry etching or wet etching to achieve the floating gate being suspended.

2. The method for manufacturing a gallium nitride device based on a floating gate process according to claim 1, wherein: The width of the suspended gate is 5-200nm, and the height of the suspended gate is 50%-90% of the height of the p-GaN cap layer; The device has a gate-source spacing of 5μm, which is the distance from the p-GaN cap layer to the source metal. The gate length is 2μm, which is the distance between the two ends of the p-GaN cap layer. The gate-drain spacing is 13μm, which is the distance from the p-GaN cap layer to the drain metal. The gate width is 100μm, which is the extension width of the gate into the paper.

3. The method for manufacturing a gallium nitride device based on a floating gate process according to claim 2, wherein: The substrate material is silicon carbide, silicon or sapphire; The thickness of the GaN buffer layer is 0.1-50 μm; The thickness of the GaN channel layer is 1-1000nm; The thickness of the AlN intercalation layer is 0.2-2 nm; The thickness of the AlGaN barrier layer is 5-50 nm, and the molar ratio of Al is 5-35%; The thickness of the p-GaN cap layer is 1-1000nm and the doping concentration is 1×10 17 -1×10 20 cm -3 , the doping source is magnesium or boron; The source metal and the drain metal are made of the same material, which is a Ti / Al / Ni / Au metal stack, a Ti / Al / Ti / Au metal stack, or a Ti / Al / Mo / Au metal stack; The gate metal material is Ni / Au metal stack.

4. The method for manufacturing a gallium nitride device based on a floating gate process according to claim 3, wherein: The material of the substrate is silicon carbide; The thickness of the GaN buffer layer is 5.2 μm; The thickness of the GaN channel layer is 200nm; The thickness of the AlN intercalation layer is 0.5 nm; The thickness of the AlGaN barrier layer is 12.5 nm, and the molar ratio of Al is 18%; The thickness of the p-GaN cap layer is 100 nm and the doping concentration is 3×10 19 cm -3 ; The source metal and the drain metal are made of Ti / Al / Ni / Au metal stacks.

5. The method for manufacturing a gallium nitride device based on a floating gate process according to claim 4, wherein: In step S1, the growth method of the GaN buffer layer, the GaN channel layer, the AlN intercalation layer, the AlGaN barrier layer, and the p-GaN cap layer is metal organic chemical vapor deposition or molecular beam epitaxy; The etching method in steps S2, S3 and S7 is inductively coupled plasma etching or reactive ion etching.

6. The method for manufacturing a gallium nitride device based on a floating gate process according to claim 1, wherein: In step S9, the etching method is isotropic inductively coupled plasma etching. During the inductively coupled plasma etching process, the RF power is reduced, and SF6 and O2 gases are introduced simultaneously to achieve etching control. The ICP power is set to 1000 W, the RF power is set to 100 W, the SF6 is set to 60 sccm, the O2 is set to 20 sccm, and the pressure is set to 1.5 Pa; Wet etching uses a buffered oxide etchant solution plus isopropyl alcohol, with the ratio of oxide etchant solution to isopropyl alcohol being 95%:5% to 60%:40%, supplemented by ultrasonic vibration immersion.

7. The method for manufacturing a gallium nitride device based on a floating gate process according to claim 6, wherein: In step S5, the annealing method of the source metal and the drain metal is laser selective annealing; The thickness of the dielectric layer is 0-100 nm, and the material of the dielectric layer is Si3N4 or SiO2.

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