Display substrate, preparation method thereof and display panel

Abstract

The invention provides a display substrate, a preparation method thereof and a display panel. The display substrate comprises a substrate body, a plurality of light-emitting devices, a packaging layer and a spacer. The display substrate is divided into a display area and a peripheral area, and the peripheral area comprises a first sub-area located on one side of the display area and used for bonding and a second sub-area connected with the first sub-area. The boundary line of the display area and the second sub-area is a first boundary line; the packaging layer comprises a first inorganic packaging layer, an organic packaging layer and a second inorganic packaging layer which are sequentially arranged in the direction away from the substrate; the organic packaging layer comprises a first sub organic packaging layer located in the display area and a second sub organic packaging layer which surrounds the first sub organic packaging layer and is located in the display area and the peripheral area; the maximum thickness of the second sub organic packaging layer is smaller than the minimum thickness of the first sub organic packaging layer; the minimum distance between the spacer and the first boundary line is not less than the distance between the outline of the second sub organic packaging layer and the first boundary line.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a display substrate, a method for manufacturing the same, and a display panel. Background Art

[0002] In the manufacturing process of display products, in order to ensure qualified products leaving the factory, reliability tests are usually required. Among them, the defect of Grow Dark Spot (GDS) is an important reason affecting the product qualification rate. The Organic Light-Emitting Diode (OLED) display panel has a certain probability of water vapor oxidation defects caused by defects such as cracks, scratches, and indentations under specific conditions, which is the GDS defect. This defect is named after its characteristics. After the black spots are formed, they will gradually grow until the entire display surface fails. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate, which includes a substrate, a plurality of light-emitting devices disposed on the substrate, a packaging layer for packaging the plurality of light-emitting devices, and spacers located on a side of the packaging layer close to the substrate; wherein,

[0004] The display substrate is divided into a display area and a peripheral area surrounding the display area; the peripheral area includes a first sub-area located on one side of the display area and used for bonding, and a second sub-area connected to the first sub-area; the boundary line between the display area and the second sub-area is the first boundary line;

[0005] The packaging layer includes a first inorganic packaging layer, an organic packaging layer, and a second inorganic packaging layer arranged in sequence in a direction away from the substrate; the organic packaging layer includes a first sub-organic packaging layer located in the display area, and a second sub-organic packaging layer surrounding the first sub-organic packaging layer and located in the display area and the peripheral area; the maximum thickness of the second sub-organic packaging layer is less than the minimum thickness of the first sub-organic packaging layer;

[0006] The minimum distance between the spacer and the first boundary line is not less than the distance between the contour of the second sub-organic packaging layer and the first boundary line.

[0007] In some embodiments, the organic packaging layer further includes a third sub-organic packaging layer surrounding the second sub-organic packaging layer; the maximum thickness of the second sub-organic packaging layer is less than the minimum thickness of the third sub-organic packaging layer;

[0008] The spacer is disposed on a side of the third sub-organic packaging layer close to the substrate.

[0009] In some embodiments, the second sub-region includes a first portion opposite to the first sub-region, and second and third portions connecting the first portion and the first sub-region;

[0010] The spacers located in the first portion are arranged side by side in a first direction; the spacers located in the second and third portions are both arranged side by side in a second direction; the first direction intersects the second direction.

[0011] In some embodiments, the display substrate further includes a pixel defining layer located on the substrate; the pixel defining layer includes pixel barriers and pixel openings defined by the pixel barriers; the light-emitting device includes a first electrode disposed on a side of the pixel defining layer close to the substrate, and an organic light-emitting functional layer and a second electrode that sequentially cover the pixel openings;

[0012] The spacers located in the display area are disposed on the pixel barriers and on a side of the organic light-emitting functional layer close to the substrate.

[0013] In some embodiments, the organic light-emitting functional layer at least includes an electron injection layer;

[0014] The light-emitting device further includes a light extraction layer disposed on a side of the electron injection layer away from the substrate; a positive projection of the light extraction layer on the substrate covers a positive projection of the electron injection layer on the substrate; a first edge line is a positive projection of an edge of the electron injection layer on the substrate, and a second edge line is a positive projection of an edge of the light extraction layer on the substrate;

[0015] The spacers located in the first portion are disposed between a first boundary line portion located in the first portion and a first edge line portion; the spacers located in the second portion are disposed between a first edge line portion located in the second portion and a second edge line portion; the spacers located in the third portion are disposed between a first edge line portion located in the third portion and a second edge line portion.

[0016] In some embodiments, the display substrate further includes a touch control layer disposed on a side of the encapsulation layer away from the substrate; the touch control layer includes a first touch control signal line disposed in the first portion, a second touch control signal line disposed in the second portion, and a third touch control signal line disposed in the third portion;

[0017] The positive projection of the first touch signal line on the substrate covers the positive projection of the spacer disposed in the first portion on the substrate; the positive projection of the second touch signal line on the substrate covers the positive projection of the spacer disposed in the second portion on the substrate; the positive projection of the third touch signal line on the substrate covers the positive projection of the spacer disposed in the third portion on the substrate.

[0018] In some embodiments, the display substrate further includes a first encapsulation dam, a second encapsulation dam, and a third encapsulation dam disposed in the first sub-region and the second sub-region, and all three are annular structures; the second encapsulation dam is disposed between the first encapsulation dam and the third encapsulation dam, and the first encapsulation dam is closer to the first boundary line than the third encapsulation dam;

[0019] The positive projection of the third sub-organic encapsulation layer on the substrate covers the positive projections of the first encapsulation dam and the second encapsulation dam on the substrate, and has no overlap with the positive projection of the third encapsulation dam on the substrate; the spacer is disposed between the first boundary line and the first encapsulation dam.

[0020] In some embodiments, the second encapsulation dam includes a first barrier portion and a first spacer portion stacked in sequence in a direction away from the substrate; the third encapsulation dam includes a second barrier portion and a second spacer portion stacked in sequence in a direction away from the substrate;

[0021] The first spacer portion and the second spacer portion are disposed on the same layer as the spacer.

[0022] In some embodiments, the distance between the surface of the first encapsulation dam on the side away from the substrate and the substrate is greater than the distance between the surface of the second encapsulation dam on the side away from the substrate and the substrate;

[0023] The distance between the surface of the third encapsulation dam on the side away from the substrate and the substrate is greater than the distance between the surface of the first encapsulation dam on the side away from the substrate and the substrate.

[0024] In some embodiments, the boundary line between the display area and the first sub-region is a second boundary line;

[0025] The distance between the spacer and the second boundary line is greater than or equal to zero.

[0026] In some embodiments, the spacers located in the display area are arranged to form multiple sets of nested spacer groups, and each set of spacer groups includes a plurality of the spacers distributed in a ring shape.

[0027] In some embodiments, the orthographic projection of the spacer on the substrate substrate includes any one of a circle, a rectangle, or a square.

[0028] In some embodiments, the arrangement density of the spacers is 10.3% to 15.5%.

[0029] Embodiments of the present disclosure also provide a method for manufacturing a display substrate, wherein the display substrate is divided into a display area and a peripheral area surrounding the display area; the peripheral area includes a first sub-area located on one side of the display area and used for bonding, and a second sub-area connected to the first sub-area; the boundary line between the display area and the second sub-area is a first boundary line; the manufacturing method includes:

[0030] Providing a substrate substrate;

[0031] Forming a plurality of light-emitting devices, a plurality of spacers, and a packaging layer on the substrate substrate; wherein, the packaging layer includes a first inorganic packaging layer, an organic packaging layer, and a second inorganic packaging layer sequentially arranged in a direction away from the substrate substrate; the organic packaging layer includes a first sub-organic packaging layer located in the display area, and a second sub-organic packaging layer surrounding the first sub-organic packaging layer and located in the display area and the peripheral area; the maximum thickness of the second sub-organic packaging layer is less than the minimum thickness of the first sub-organic packaging layer;

[0032] The minimum distance between the spacer and the first boundary line is not less than the distance between the contour of the second sub-organic packaging layer and the first boundary line.

[0033] Embodiments of the present disclosure also provide a display panel, including the display substrate in any of the above embodiments. Description of the Drawings

[0034] Figure 1 Schematic diagram of an existing PT structure formation.

[0035] Figure 2 Top view structural schematic diagram of the display substrate provided by the embodiments of the present disclosure.

[0036] Figure 3 Top view structural schematic diagram of the organic packaging layer provided by the embodiments of the present disclosure.

[0037] Figure 4 Cross-sectional film layer schematic diagram of the display substrate provided by the embodiments of the present disclosure at C-C'.

[0038] Figure 5 Cross-sectional film layer schematic diagram of the display substrate provided by the embodiments of the present disclosure at A-A'.

[0039] Figure 6 Schematic cross-sectional film layer diagram of the display substrate provided by the embodiment of the present disclosure at B-B'.

[0040] Figure 7 Schematic structural diagram of a pixel driving circuit provided by the embodiment of the present disclosure.

[0041] Figure 8 Partial top view structural diagram of the display substrate of Embodiment 1.

[0042] Figure 9 Partial top view structural diagram of the display substrate of Embodiment 2.

[0043] Figure 10 Partial top view structural diagram of the display substrate of Embodiment 1.

[0044] Figure 11 Partial top view structural diagram of the display substrate of Embodiment 2.

[0045] Figure 12 Simulation result diagram of the force on the spacers PS located on the left and right sides of the display substrate in Embodiment 1 and Embodiment 2.

[0046] Figure 13 Simulation result diagram of the force on the spacers PS located on the upper and lower sides of the display substrate in Embodiment 1 and Embodiment 2.

[0047] Figure 14 Schematic diagram of the intermediate product of step S504.

[0048] Figure 15 Deformation trend diagram of the high-precision metal mask FMM provided by the present application.

[0049] Figure 16 Another deformation trend diagram of the high-precision metal mask FMM provided by the present application. Specific embodiments

[0050] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] Unless otherwise defined, technical terms or scientific terms involved in this application shall have the ordinary meanings understood by those with ordinary skills in the technical field to which this application pertains. The words such as "a", "an", "one kind", "the" and the like involved in this application do not indicate a quantity limitation and may represent a singular or plural number. The terms "comprise", "include", "have" and any variations thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may further include steps or units not listed, or may further include other steps or units inherent to these processes, methods, products or devices. The words such as "connect", "be connected", "be coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the front and rear associated objects. The terms "first", "second", "third" and the like involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects. "Up", "down", "left", "right" and the like are only used to represent relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0052] As used herein, "parallel" and "perpendicular" include the described situations and situations similar to the described situations, and the range of the similar situations is within an acceptable deviation range, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and approximate parallel, and the acceptable deviation range of approximate parallel may be, for example, within a deviation of 5°; "perpendicular" includes absolute perpendicular and approximate perpendicular, and the acceptable deviation range of approximate perpendicular may also be, for example, within a deviation of 5°. It should be understood that when a layer or element is said to be on another layer or substrate, it may be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0053] In the present disclosure, the first direction X and the second direction Y intersect. In the present disclosure, taking the first direction X and the second direction Y being perpendicular to each other in the plane of the substrate and the first direction X being the horizontal direction and the second direction Y being the vertical direction as an example for illustration, it does not constitute a limitation to the present disclosure.

[0054] In the related art, there are many causes of GDS defects, and package failure is one of the more important reasons. For example, relatively large-sized particles (abbreviated as PT) in the panel are likely to cut off, scratch, or damage the package layer, resulting in package failure, and then water vapor enters, causing the light-emitting layer to be corroded, and further causing the display device to fail. According to physical analysis, relatively large-sized PT always occurs above the support layer (such as the PS film layer), and the reason for its generation is as follows Figure 1 As shown, spacers (PS) are provided on the substrate SUB. During the process of evaporating (EV) the light-emitting layer, the mask plate is attached to the substrate SUB, and the spacers (PS) at the physical high points are easily scratched during the loading / unloading process of the mask plate. However, the part of the scratched spacers (PS) that has not completely fallen off is lifted to form relatively large-sized PT. Relatively large-sized PT will affect the package film formation (organic package layer OEL and inorganic package layer IEL) and the overlying film (OC) thereon, and finally cause the package layer to be damaged by the etching process, resulting in GDS defects.

[0055] In view of this, the embodiments of the present disclosure provide a display substrate, which substantially eliminates one or more of the problems caused by the limitations and defects of the related art.

[0056] Figure 2 It is a top view structural schematic diagram of the display substrate provided by the embodiments of the present disclosure. Figure 3 It is a top view structural schematic diagram of the organic package layer provided by the embodiments of the present disclosure. Figure 4 It is a cross-sectional film layer schematic diagram of the display substrate provided by the embodiments of the present disclosure at C-C'. Figure 5 It is a cross-sectional film layer schematic diagram of the display substrate provided by the embodiments of the present disclosure at A-A'. Figure 6 It is a cross-sectional film layer schematic diagram of the display substrate provided by the embodiments of the present disclosure at B-B'. Refer to Figures 2 - 6 , the display substrate includes a substrate SUB, a plurality of light-emitting devices provided on the substrate SUB, a package layer EPL for packaging the light-emitting devices, and a plurality of spacers PS provided on the side of the package layer EPL close to the substrate SUB. Among them, as Figure 2As shown, the display substrate is divided into a display area DA and a peripheral area PA surrounding the display area DA. The peripheral area PA includes a first sub-area PA1 (i.e., a bonding area) located on one side of the display area DA for bonding, and a second sub-area PA2 connected to the first sub-area PA1. Generally, the first sub-area PA1 (i.e., the bonding area) is provided on the lower side of the display substrate. It can be understood that the first sub-area PA1 is a rectangular area, in which a plurality of contact pads (or pads) are provided, and each contact pad is configured to be electrically connected to a signal line extending from the display area DA or the second sub-area PA2. The second sub-area PA2 is a C-shaped area that semi-surrounds the display area DA, and mainly a plurality of signal lines for driving the light-emitting devices are provided in the second sub-area PA2. The boundary line between the second sub-area PA2 and the display area DA is a first boundary line XL1, and the first boundary line XL1 is a line segment having a C-shaped structure. The boundary line between the first sub-area PA1 and the display area DA is a second boundary line XL2, and the second boundary line XL2 is a straight line segment.

[0057] Among them, the light-emitting devices in the display substrate can be, for example, organic light-emitting diodes OLEDs, and the organic light-emitting diodes OLEDs can emit, for example, red light, green light, blue light, or white light. A pixel driving circuit PC (Pixel Circuit) for driving the light-emitting devices to emit light is also provided between the light-emitting devices and the substrate SUB. Exemplarily, Figure 7 This is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure. As Figure 7 shown, the pixel driving circuit PC includes a driving thin-film transistor (Thin-film Transistor, TFT) Td, a switching TFT Ts, and a storage capacitor Cst. The switching TFT Ts is connected to a gate line GL and a data line DL, and is configured to transmit a data signal received through the data line DL to the driving TFT Td according to a scan signal received through the gate line GL. The storage capacitor Cst is connected to the switching TFT Ts and a driving voltage line PL, and is configured to store a voltage corresponding to the difference between the voltage received from the switching TFT Ts and the driving voltage ELVDD supplied to the driving voltage line PL. The driving TFT Td is connected to the driving voltage line PL and the storage capacitor Cst, and can be used to control the driving current flowing from the driving voltage line PL to the organic light-emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED can emit light with a desired brightness through the driving current.

[0058] Among them, the gate lines GL and data lines DL are arranged in a grid pattern within the display area DA. The gate lines GL pass through the display area DA and extend into the second sub-region PA2, connecting to the gate driving circuit within the second sub-region PA2. The data lines DL pass through the display area DA and extend into the second sub-region PA2, connecting to the source driver within the second sub-region PA2. A plurality of driving voltage lines PL are disposed between adjacent light-emitting devices and extend into the first sub-region PA1, being electrically connected to a flexible printed circuit board FPCB (Flexible Print Circuit Board) through pads PAD within the first sub-region PA1. The flexible printed circuit board FPCB is electrically connected to an external controller and is configured to transmit signals or power from the external controller.

[0059] In an example of the present disclosure, the encapsulation layer EPL for encapsulating the light-emitting device includes a structure in which an inorganic layer and an organic layer are stacked. Specifically, referring to Figures 4 - 6 , the encapsulation layer EPL includes a first inorganic encapsulation layer EPL1, an organic encapsulation layer EPL3, and a second inorganic encapsulation layer EPL2 that are sequentially stacked in a direction away from the substrate SUB. Among them, the first inorganic encapsulation layer EPL1 and the second inorganic encapsulation layer EPL2 cover the entire display substrate, and the organic encapsulation layer covers the entire display area DA and a part of the peripheral area PA. The first inorganic encapsulation layer EPL1 and the second inorganic encapsulation layer EPL2 may include inorganic materials such as silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), etc. These inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The material of the organic encapsulation layer EPL3 may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer EPL1 and the second inorganic encapsulation layer EPL2, and can also absorb substances such as water and oxygen that intrude into the interior.

[0060] Furthermore, referring to Figures 3 - 6 , in an actual product, according to the different thicknesses at different positions of the organic encapsulation layer, the organic encapsulation layer EPL3 can be divided into a first sub-organic encapsulation layer EP31 located within the display area DA, a second sub-organic encapsulation layer EP32 surrounding the first sub-organic encapsulation layer EP31, and a third sub-organic encapsulation layer EP33 surrounding the second sub-organic encapsulation layer EP32. Among them, the minimum thickness of the first sub-organic encapsulation layer EP31 is greater than the maximum thickness of the second sub-organic encapsulation layer EP32, the minimum thickness of the third sub-organic encapsulation layer EP33 is greater than the maximum thickness of the second sub-organic encapsulation layer EP32, and the minimum thickness of the third sub-organic encapsulation layer EP33 is greater than or equal to the maximum thickness of the first sub-organic encapsulation layer EP31.

[0061] Specifically, referring to Figure 3, the orthographic projection of the first sub-organic encapsulation layer EP31 on the substrate SUB is a rectangle, and there is a certain distance between the edge of the first sub-organic encapsulation layer EP31 and the boundary line between the display area DA and the peripheral area PA. That is to say, the first sub-organic encapsulation layer EP31 is completely disposed within the display area DA and has a certain distance from both the first boundary line XL1 and the second boundary line XL2. The second sub-organic encapsulation layer EP32 is disposed around the first sub-organic encapsulation layer EP31. Therefore, the orthographic projection of the second sub-organic encapsulation layer EP32 on the substrate SUB is an annular structure, and a part of this annular structure is located within the display area DA and a part is located within the peripheral area PA. That is to say, the orthographic projection of the second sub-organic encapsulation layer EP32 on the substrate SUB covers the orthographic projections of the first boundary line XL1 and the second boundary line XL2 on the substrate SUB. Since the second sub-organic encapsulation layer EP32 is an annular structure, it has an inner contour and an outer contour that are oppositely disposed. The inner contour is located within the display area DA, and the outer contour is located within the peripheral area PA. And there is a certain distance between the inner contour and both the first boundary line XL1 and the second boundary line XL2, and there is also a certain distance between the outer contour and both the first boundary line XL1 and the second boundary line XL2. The third sub-organic encapsulation layer EP33 is disposed around the second sub-organic encapsulation layer EP32. Therefore, it is also an annular structure, and this annular structure is located within the peripheral area PA.

[0062] Based on the specific structure of the above organic encapsulation layer, in the present application, the minimum distance between the spacer PS and the first boundary line XL1 is not less than the distance between the contour of the second sub-organic encapsulation layer EP32 and the first boundary line XL1. Specifically, referring to Figure 5 and Figure 6, spacers PS are provided in the display area DA, the first sub-region PA1, and the second sub-region PA2 of the display substrate. For the spacer PS provided in the display area DA, the minimum distance D1 between it and the first boundary line XL1 is not less than the distance D2 between the inner contour of the second sub-organic encapsulation layer EP32 and the first boundary line XL1. In other words, the spacer PS provided in the display area DA is located between the first sub-organic encapsulation layer EP31 and the substrate SUB and is covered by the first sub-organic encapsulation layer EP31. For the spacer PS provided in the second sub-region PA2, the minimum distance D3 between it and the first boundary line XL1 is not less than the distance D4 between the outer contour of the second sub-organic encapsulation layer EP32 and the first boundary line XL1. In other words, the spacer PS provided in the second sub-region PA2 is located between the third sub-organic encapsulation layer EP33 and the substrate SUB and is covered by the third sub-organic encapsulation layer EP33. In this way, it can be ensured that no spacer PS is provided within the range defined by the second sub-organic encapsulation layer EP32 in the display area DA and the second sub-region PA2, that is, no spacer PS is provided at the position where the organic encapsulation layer in the second sub-region PA2 is thinner, thereby changing the force-bearing situation of the spacer PS and reducing the risk of packaging failure.

[0063] It should be noted that for the second sub-organic encapsulation layer EP32 in the first sub-region PA1 (i.e., the bonding area) and the partial display area DA adjacent to the first sub-region PA1, a spacer PS is also provided between it and the substrate SUB, and the shortest distance between the spacer PS and the second boundary line XL2 is greater than or equal to zero. The specific structure is as Figure 10 and Figure 11 shown. That is to say, a spacer PS is provided near the second boundary line XL2, and the distance between the spacer PS and the second boundary line XL2 can be infinitely close. Since the probability of PT occurring in the first sub-region PA1 is zero, such a setting will not increase the risk of packaging failure. For the spacers PS provided in the display area DA and the first sub-region PA1, the spacers PS are arranged to form multiple sets of nested spacer PS groups, and each set of spacer PS groups includes a plurality of spacers PS distributed in a rectangular ring.

[0064] Continue to refer to Figure 3 , the second sub-region PA2 can be further divided into a first part PA21 (i.e., the upper side region of the display substrate) opposite to the first sub-region PA1, and a second part PA22 (i.e., the left side region of the display substrate) and a third part PA23 (i.e., the right side region of the display substrate) connecting the first part PA21 and the first sub-region PA1. For the multiple spacers PS provided in the first part PA21, the spacers PS are arranged at intervals along the first direction (i.e., the row direction), as Figure 11As shown. For a plurality of spacers PS provided in the second part PA22 and the third part PA23, the respective spacers PS are spaced along the second direction (i.e., the column direction), as Figure 9 shown.

[0065] In some examples, referring to Figures 4 - 6 , the display substrate further includes a pixel defining layer PDL provided on the substrate SUB. The pixel defining layer specifically includes a plurality of pixel barriers and a plurality of pixel openings defined by the pixel barriers. One pixel opening is correspondingly provided with one pixel unit, and the pixel unit includes the above-mentioned light-emitting device and a pixel driving circuit. Among them, the pixel driving circuit is provided in the driving circuit layer between the pixel defining layer and the substrate SUB, and is used to provide a driving current for the light-emitting device. It should be noted that Figure 4 schematically shows the switching TFT Ts and the storage capacitor Cst in the pixel driving circuit to represent the driving circuit layer, and the driving TFT Td is not shown. For the sake of simplifying the drawings, Figure 5 and Figure 6 only use a single film layer FILMS to replace Figure 4 each film layer provided between the light-emitting device and the substrate SUB, but their structural essence is the same. Referring to Figure 4 , the light-emitting device includes a first electrode 11, an organic light-emitting functional layer 12, and a second electrode 13 sequentially provided along the direction away from the substrate SUB. Here, the first electrode 11 can be an anode, and the second electrode 13 can be a cathode. The anode is provided between the pixel defining layer PDL and the driving circuit layer, the organic light-emitting functional layer covers the pixel opening, and the cathode covers the organic light-emitting functional layer.

[0066] Among them, the material of the pixel defining layer PDL may include organic insulating materials such as polyimide, polyphthalimide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin, or may include inorganic insulating materials such as silicon oxide and silicon nitride. Both the first electrode 11 and the second electrode 13 may include a conductive material. For example, the conductive material may include metals, metal alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. In the embodiments of the present disclosure, the organic light-emitting diode OLED may adopt a top-emission type or a bottom-emission type. When adopting a top-emission type OLED, the first electrode 11 includes a conductive material having light reflection performance or includes a light reflection film, and the second electrode 13 includes a transparent or semi-transparent conductive material. When adopting a bottom-emission type OLED, the second electrode 13 is made of a conductive material having light reflection performance or includes a light reflection film, and the first electrode 11 includes a transparent or semi-transparent conductive material.

[0067] In some examples, the organic light-emitting function, 12 includes a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EL, an electron transport layer ETL, and an electron injection layer EIL stacked in sequence along the direction away from the substrate SUB. Among them, the hole injection layer HIL can inject holes from the anode into the light-emitting layer EL, and it includes ferrous oxide or zinc oxide. The hole transport layer HTL can improve the hole transport efficiency, and it includes materials such as phthalocyanine or perylene. The light-emitting layer EL can include small molecule organic materials or polymer molecule organic materials, can be a fluorescent light-emitting material or a phosphorescent light-emitting material, can emit red light, green light, blue light, or can emit white light. The electron injection layer EIL can inject electrons in the cathode into the light-emitting layer EL to react with holes. The electron injection layer EIL can include materials such as lithium, magnesium, or lithium fluoride, for example. The electron transport layer ETL can improve the electron transport efficiency, and the electron transport layer ETL can include materials such as aluminum oxide or titanium oxide, for example.

[0068] In some examples, in addition to the anode 11, the organic light-emitting functional layer 12, and the cathode 13, the light-emitting device further includes a light extraction layer CPL disposed between the electron injection layer EIL and the cathode. The light extraction layer CPL can include organic polymer materials such as triarylamine, cyclic urea, acyl structure, dibenzothiophene, dibenzofurazole, carbazole, etc., for example, or can also include inorganic materials such as molybdenum oxide, zirconium oxide, aluminum oxide, titanium oxide, etc. By providing the light extraction layer CPL, the total reflection effect of light can be reduced, the light extraction efficiency can be improved, the spectral characteristics can be improved, and the color purity can be improved. Among them, in order to improve the light utilization rate, the orthographic projection of the light extraction layer CPL on the substrate SUB covers the orthographic projection of other film layers in the organic light-emitting functional layer 12 on the substrate SUB. That is to say, among the respective film layers of the organic light-emitting functional layer 12, the range of the orthographic projection of the edge of the light extraction layer CPL on the substrate SUB is the largest. To facilitate the description of the positional relationship between each film layer in the light-emitting device and the spacer PS, the orthographic projection of the edge of the electron injection layer EIL on the substrate SUB is set as the first edge line BL1, and the orthographic projection of the edge of the light extraction layer on the substrate SUB is set as the second edge line BL2. It can be understood that both the first edge line BL1 and the second edge line BL2 are rectangular coil structures, and the range covered by the second edge line BL2 is larger than that covered by the first edge line BL1.

[0069] In order to reduce the edge visual interference and make the transition between the display area DA and the peripheral area PA more natural, in the embodiments of the present disclosure, at least a part of the organic light-emitting functional layer 12 in the light-emitting device disposed at the outermost edge of the display area DA is disposed in the peripheral area PA, as Figure 5 and Figure 6 shown. Refer to Figure 5, for the light-emitting device disposed at the position of the first boundary line XL1, a part of the organic light-emitting functional layer 12 (only the light-emitting layer EL, the electron injection layer EIL, and the light extraction layer CPL in the organic light-emitting functional layer 12 are shown in the figure) is located in the display area DA, and another part of the organic light-emitting functional layer 12 is located within the third part PA23. Similarly, for the light-emitting device disposed at the second boundary line XL2, a part of the organic light-emitting functional layer 12 is located in the display area DA, and another part of the organic light-emitting functional layer 12 is located within the first sub-region PA1.

[0070] In this application, with reference to Figure 11 , for the plurality of spacers PS disposed within the first part PA21, each spacer PS is arranged to form a row of spacers, and the orthographic projection of the row of spacers on the substrate SUB is disposed between the portion of the first boundary line XL1 within the first part PA21 and the portion of the first edge line BL1. With reference to Figure 9 , for the plurality of spacers PS disposed within the second part PA22, each spacer PS is arranged to form a column of spacers, and the orthographic projection of the column of spacers on the substrate SUB is disposed between the portion of the first edge line BL1 within the second part PA22 and the portion of the second edge line BL2. Since the structures disposed within the second part PA22 and the third part PA23 are substantially symmetric, therefore, for the plurality of spacers PS disposed within the third part PA23, each spacer PS is arranged to form a column of spacers PS, and the orthographic projection of the column of spacers PS on the substrate SUB is disposed between the portion of the first edge line BL1 within the third part PA23 and the portion of the second edge line BL2.

[0071] In some examples, the display substrate further includes a touch electrode layer disposed on the side of the encapsulation layer facing away from the substrate SUB. Specifically, the touch electrode layer is disposed on the side of the second inorganic encapsulation layer EPL2 facing away from the substrate SUB. The touch electrode layer may include, for example, a touch electrode TE (Touching Electrode) and a touch signal line TM. Among them, the touch electrode TE is disposed within the display area DA and is configured to detect the occurrence of a touch within the display area DA. For example, as Figure 4As shown, the touch electrode TE includes a first touch electrode TE1 and a second touch electrode TE2. A plurality of first touch electrodes TE1 form a first touch electrode line extending in the x direction, and a plurality of second touch electrodes TE2 form a second touch electrode line extending in the y direction. The plurality of first touch electrode lines and the plurality of second touch electrode lines cross each other, thereby forming a touch capacitance at the crossing positions of the first touch electrode line and the second touch electrode line. The detection of the touch position is achieved by detecting the change of the touch capacitance caused by, for example, the approach of a finger during touch. The touch signal line TM is disposed in the peripheral area PA and is configured to be electrically connected to the touch electrode TE in the display area DA. For example, the touch signal line includes a first touch signal line, a second touch signal line, and a third touch signal line. Among them, the first touch signal line TM1 is disposed in the first part PA21 and is connected to the second touch electrode line extending in the y direction. The second touch signal line TM2 is disposed in the second part PA22 and is connected to the first touch electrode line extending in the x direction. The third touch signal line TM3 is disposed in the third part PA23 and is connected to the first touch electrode line extending in the x direction. Substantially, the second touch signal line TM2 and the third touch signal line TM3 may be connected to the same first touch electrode line, or the second touch signal line TM2 is connected to the first touch electrode lines in the odd rows, and the third touch signal line TM3 is connected to the first touch electrode lines in the even rows. And, in order to simplify the process, the second touch line disposed in the second part PA22 and the third touch line disposed in the third part PA23 may be designed into a symmetric structure. In this way, the touch signals generated by each touch electrode TE can be transmitted to the first sub-region PA1 (bonding region) through the touch signal line TM and are electrically connected to an external touch chip through the contact pad PAD in the first sub-region PA1.

[0072] Meanwhile, in order to improve the product reliability and enable the spacer PS to have sufficient supporting effect on the touch signal line, it is set that the orthographic projection of the first touch signal line TM1 on the substrate SUB completely covers the orthographic projection of the row of spacers PS located in the first part PA21 on the substrate SUB, as Figure 11 shown. And, it is set that the orthographic projection of the second touch signal line TM2 on the substrate SUB completely covers the orthographic projection of the column of spacers PS located in the second part PA22 on the substrate SUB, and the orthographic projection of the third touch signal line TM3 on the substrate SUB completely covers the orthographic projection of the column of spacers PS located in the third part PA23 on the substrate SUB, as Figure 9 shown.

[0073] In some examples, continue to refer to Figure 4, the display substrate further includes a barrier layer BRL disposed between the driving circuit layer and the substrate SUB. The barrier layer BRL is configured to block moisture and / or oxygen from penetrating through the substrate SUB, and may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and may be formed as a multi-layer or a single layer. Moreover, when the surface of the substrate SUB is relatively uneven, the barrier layer BRL can improve the surface flatness of the flexible substrate SUB.

[0074] In some examples, continuing to refer to Figure 4 , the display substrate further includes a buffer layer BFL disposed between the barrier layer BRL and the driving circuit layer. The buffer layer BFL can prevent or reduce the diffusion of metal atoms and / or impurities from the substrate SUB into the semiconductor layer. For example, the buffer layer BFL may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and may be formed as a multi-layer or a single layer.

[0075] In some examples, the display substrate further includes a plurality of encapsulation dams disposed in the peripheral area PA. Specifically, the encapsulation dams are annular structures disposed in the first sub-region PA1 and the second sub-region PA2. Referring to Figure 5 and Figure 6 , which shows three encapsulation dams. Along the direction from the display area DA to the peripheral area PA, the three encapsulation dams are the first encapsulation dam DAM1, the second encapsulation dam DAM2, and the third encapsulation dam DAM3, respectively.

[0076] Among them, the first encapsulation dam DAM1 and the second encapsulation dam DAM2 are covered by the third sub-organic encapsulation layer EP33, and relative to the spacer PS columns and spacer PS rows disposed in the peripheral area PA, the first encapsulation dam DAM1 is disposed on the side of the spacer PS column or spacer PS row away from the display area DA. The organic encapsulation layer can be prepared by an inkjet printing process. During the preparation process, the first encapsulation dam DAM1 and the second encapsulation dam DAM2 can delay the flow rate of the ink to a certain extent. The third encapsulation dam DAM3 is disposed on the side of the third sub-organic encapsulation layer EP33 facing away from the display area DA and can completely block the flow of the ink, restricting the ink within the defined range of the third encapsulation dam DAM3. To better control the shape of the organic encapsulation layer, the distance between the surface of the first encapsulation dam DAM1 away from the substrate SUB and the substrate SUB is greater than the distance between the surface of the second encapsulation dam DAM2 away from the substrate SUB and the substrate SUB, and the distance between the surface of the third encapsulation dam DAM3 away from the substrate SUB and the substrate SUB is greater than the distance between the surface of the first encapsulation dam DAM1 away from the substrate SUB and the substrate SUB.

[0077] In some examples, the orthographic projection of the spacer PS on the substrate SUB may include any one of a circle, a rectangle, or a square. When the orthographic projection of the spacer PS on the substrate SUB is a circle, the spacer PS is substantially a cylindrical structure. Adopting this structure is beneficial to the uniform distribution of stress and avoids local stress concentration. Moreover, adopting a cylindrical spacer PS is beneficial to achieving a close arrangement and saving space. When the orthographic projection of the spacer PS on the substrate SUB is a rectangle or a square, the spacer PS is substantially a square-columnar structure. Adopting a square-columnar structure is beneficial to improving the load-bearing capacity of the spacer PS and providing higher structural strength. For multiple spacers PS disposed in the display area DA, each spacer PS is arranged to form a spacer PS array. For multiple spacers PS disposed in the peripheral area PA, each spacer PS is arranged to form a row or a column of spacer PS. Regardless of which arrangement method, the arrangement density of the spacer PS is preferably set to 10.3% - 15.5%.

[0078] Preferably, in order to increase the stability of the spacer PS, the spacer PS in this application adopts a structure with a smaller upper part and a larger lower part. Specifically, the spacer PS has a first surface and a second surface that are oppositely disposed along its height direction, and the first surface is farther from the substrate SUB than the second surface. Among them, the area of the second surface is larger than the area of the first surface, and the orthographic projection of the second surface on the substrate SUB completely covers the orthographic projection of the first surface on the substrate SUB. At this time, the spacer PS is substantially a frustum structure. Specifically, when the orthographic projection of the spacer PS on the substrate SUB is a circle, the spacer PS is a frustum of a cone structure. When the orthographic projection of the spacer PS on the substrate SUB is a rectangle or a square, the spacer is a frustum of a pyramid structure. Adopting a frustum structure is beneficial to increasing the stability and support ability of the spacer PS and enhancing the stability of the product.

[0079] Further, continue to refer to Figure 5 and Figure 6, the first encapsulation dam DAM1 is a single-layer structure, and the second encapsulation dam DAM2 and the third encapsulation dam DAM3 are both double-layer structures. Specifically, the second encapsulation dam DAM2 includes a first barrier portion DAM21 and a first spacer portion DAM22 stacked in a direction away from the substrate SUB, and the third encapsulation dam DAM3 includes a second barrier portion DAM31 and a second spacer portion DAM32 stacked in a direction away from the substrate SUB. Among them, the first encapsulation dam DAM1, the first barrier portion DAM21, and the second barrier portion DAM31 can be disposed on the same layer as the pixel definition layer PDL and formed by a single patterning process (for example: a grayscale mask process). The first spacer portion DAM22 and the second spacer portion DAM32 can be disposed on the same layer as the spacer PS and formed by a single patterning process (for example: a grayscale mask process). The single patterning process can simplify the production process and improve the stability of the structure.

[0080] To illustrate that the arrangement method of the spacer PS provided in the present application can effectively reduce the risk of encapsulation failure, the present application also provides the force simulation results of the spacer PS under different conditions, which will be described below in conjunction with specific embodiments.

[0081] Embodiment 1: Figure 8 and Figure 10 are both partial top-view structural schematic diagrams of the display substrate of Embodiment 1. Referring to Figure 8 and Figure 10 , among them, a plurality of spacers PS covered by the first sub-organic encapsulation layer EP31 and the second sub-organic encapsulation layer EP32 are arranged in an array, and no spacer PS is provided within the range defined by the third sub-organic encapsulation layer EP33. Most of the spacers PS are disposed in the display area DA, and a small part is disposed at the boundary position between the display area DA and the peripheral area PA, that is, on the first boundary line XL1 and the second boundary line XL2.

[0082] It should be noted that Figure 8 also schematically shows a part of the spacers PS on the side of the module cutting line Trim line away from the display area DA. These spacers PS can also play a role in supporting the mask plate during the evaporation process. However, since this part of the spacers PS will not actually exist in the finished display substrate, it will not affect the yield of the display substrate.

[0083] Embodiment 2: Figure 9 and Figure 11These are partial top - view structural schematic diagrams of the display substrate in Example 2, that is, the top - view structural schematic diagram of the display substrate provided in this application. Different from Example 1, no spacers PS are provided in the area covered by the second sub - organic encapsulation layer EP32 in this example, and a row of spacer rows PS is added within the coverage of the third sub - organic encapsulation layer EP33 located in the first part PA21, as Figure 11 shown. And, a column of spacer columns is respectively added within the coverage of the third sub - organic encapsulation layer EP33 located in the second part PA22 and the third part PA23, as Figure 9 shown.

[0084] Figure 12 Figures Figure 13 are the force simulation result diagrams of the spacers PS located on the left and right sides of the display substrate in Example 1 and Example 2. Figures Figure 13 are the force simulation result diagrams of the spacers PS located on the upper and lower sides of the display substrate in Example 1 and Example 2. It can be seen from the figures that in Example 1, for the spacers PS distributed on the left and right sides of the display substrate, the spacer PS with the largest force is the one located at the positions of PS5 and PS6. For the spacers PS distributed on the upper and lower sides of the display substrate, the spacer PS with the largest force is the one located at the positions of T - PS1 and T - PS2 on the upper side. And PS5, PS6, T - PS1, and T - PS2 are all covered by the relatively thin second sub - organic encapsulation layer EP32, and the risk of PT occurring at this position is high, which in turn leads to a high risk of encapsulation failure. In Example 2, referring to Figure 13 , the pressure borne by the overall spacers PS has decreased, and for the spacers PS distributed on the left and right sides of the display substrate, the spacer PS with the largest force is the one located at the positions of PS2 and PS9. For the spacers PS distributed on the upper and lower sides of the display substrate, the spacer PS with the largest force is the one located on the lower side. That is to say, the risk of PT is transferred from the upper side to the lower side, and PT occurring on the lower side will not have a great impact on the display substrate. Therefore, the risk of encapsulation failure of the entire display panel can be reduced. Therefore, adopting the setting method in this application can effectively reduce the risk of product encapsulation failure, thereby improving product quality.

[0085] In addition, it should also be noted that the solution of re - designing the spacers located on the upper side, left side, and right side of the display substrate in the above - mentioned Example 2 (that is, adopting the Figure 9 + Figure 11 technical solution) has obvious effects. In fact, if only the spacers located on the upper side of the display panel are adjusted (that is, adopting the Figure 8 + Figure 11 technical solution), or only the spacers located on the left and right sides of the display panel are adjusted (that is, adopting the Figure 9 +Figure 10 the technical solution), compared with the prior art (i.e., Figure 8 + Figure 10 the technical solution), can still reduce the risk of packaging failure to a certain extent.

[0086] The embodiments of the present disclosure further provide a method for manufacturing a display substrate. Referring to Figure 4 and Figure 5 the schematic diagram of the film layer structure shown, and referring to Figure 14 the schematic diagram of the intermediate product of step S504 shown, the manufacturing method may include the following steps S1 to S6.

[0087] S1. Provide a substrate SUB, which is divided into a display area DA and a peripheral area PA surrounding the display area DA. The peripheral area PA includes a first sub-area PA1 located on one side of the display area DA for bonding, and a second sub-area PA2 connected to the first sub-area PA1. The second sub-area PA2 includes a first portion PA21 opposite to the first sub-area PA1, and a second portion PA22 and a third portion PA23 connecting the first sub-area PA1 and the first portion PA21. The boundary line between the display area DA and the first sub-area PA1 is the second boundary line XL2, and the boundary line between the display area DA and the second sub-area PA2 is the first boundary line XL1.

[0088] In some examples, the substrate SUB may be made of a flexible organic material, such as resin materials like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate.

[0089] S2. Form a barrier layer BRL and a buffer layer BFL on the substrate SUB.

[0090] Among them, the barrier layer BRL and the buffer layer BFL can be formed by a deposition process. The barrier layer BRL may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and may be formed as a multi-layer or a single layer. The buffer layer BFL is disposed on the barrier layer BRL and may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and may be formed as a multi-layer or a single layer.

[0091] S3. Form a driving circuit layer on the buffer layer BFL.

[0092] Among them, the driving circuit layer may include a pixel driving circuit PC, and the pixel driving circuit PC includes a driving thin film transistor Td, a switching TFT Ts, and a storage capacitor Cst. Step S3 may specifically include the following steps S301 to S305.

[0093] S301. A semiconductor layer is formed on the buffer layer BFL. The semiconductor layer includes the active layer of the driving TFT Td and the active layer of the switching TFT Ts (only the switching TFT Ts is schematically shown in the figure). The active layer may include a channel region and a source region and a drain region respectively disposed on both sides of the channel region. Both the source region and the drain region may include impurities having a higher impurity concentration than the channel region. The impurities may include N-type impurities or P-type impurities. The semiconductor layer may include, for example, an inorganic semiconductor material (e.g., polysilicon, amorphous silicon, etc.), an organic semiconductor material, an oxide semiconductor material.

[0094] S302. A gate insulating layer GI is formed on the semiconductor layer. The gate insulating layer GI may cover the active layer. For example, the gate insulating layer GI sufficiently covers the thickness of the active layer. The gate insulating layer GI may include, for example, a silicon compound, a metal oxide. For example, it may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbonitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The gate insulating layer GI1 may be formed as a single layer or multiple layers.

[0095] S303. A gate electrode layer is formed on the gate insulating layer GI. The gate electrode layer may include the gate of the driving thin film transistor Td, the gate G of the switching TFT Ts, the first electrode plate C1 of the storage capacitor Cst, and the gate line GL connected to the switching TFT Ts, and each part is insulated from each other. The gate electrode layer may include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the gate electrode layer may include gold (Au), an alloy of gold, silver (Ag), an alloy of silver, aluminum (Al), an alloy of aluminum, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), an alloy of copper, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), an alloy of molybdenum, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The gate electrode may have a single layer or multiple layers.

[0096] S304. Form an interlayer insulating layer ILD on the gate electrode layer. The interlayer insulating layer ILD can cover the gate electrode layer, and the interlayer insulating layer ILD can include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbonitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The interlayer insulating layer ILD can be formed as a single layer or multiple layers.

[0097] S305. Form a source-drain conductive layer SD on the interlayer insulating layer ILD, which includes the source and drain of the driving TFT Td, the source S and drain D of the switching TFT Ts, the second electrode plate C2 of the storage capacitor Cst, the data line DL, and the driving voltage line PL, and each pattern is insulated from each other. The source-drain conductive layer SD can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. For example, the source-drain conductive layer SD can be a single layer or multiple layers composed of metals, such as Mo / Al / Mo or Ti / Al / Ti.

[0098] S4. Form a first planarization layer PLN1 on the source-drain conductive layer SD. The first planarization layer PLN1 covers the source-drain conductive layer SD, and the first planarization layer PLN1 can have a substantially flat upper surface. The first planarization layer PLN1 can include an organic insulating material, which, for example, includes resinous materials such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, silicone, etc. For another example, the organic insulating material includes elastic materials, such as urethane, thermoplastic polyurethane (TPU), etc.

[0099] S5. Form a pixel defining layer PDL, a plurality of spacers PS, and a plurality of light-emitting devices on the first planarization layer PLN1. Among them, the pixel defining layer PDL includes a plurality of pixel barriers and pixel openings defined by the pixel barriers, and one pixel opening is provided with one pixel unit. The pixel unit includes a pixel driving circuit and a light-emitting device in the driving circuit layer. The light-emitting device includes a first electrode 11, an organic light-emitting functional layer 12, and a second electrode 13 stacked in a direction away from the substrate SUB. Specifically, step S5 can include:

[0100] S501. Form a plurality of mutually insulated first electrodes 11 on the planarization layer PLN. The first electrode can be formed by a deposition process, and the first electrode 11 can include a conductive material. For example, the conductive material can include metals, metal alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc.

[0101] S502. Form a plurality of pixel barriers on the first electrode 11, and at the same time form a first encapsulation dam DAM1, a first barrier DAM21, and a second barrier DAM31 located in the peripheral area PA, as Figure 5 shown. The plurality of pixel barriers define a plurality of pixel openings, and one pixel opening is correspondingly arranged with one first electrode.

[0102] S503. Form a plurality of spacers PS on the pixel barriers, and at the same time form a first spacer DAM22 and a second spacer DAM32 located in the peripheral area PA, as Figure 4 and Figure 5 shown. Among them, for the spacers PS located in the display area DA, they are arranged on the side of the pixel barrier away from the substrate SUB. The first spacer DAM22 is arranged on the first barrier DAM21, and the two together form a second encapsulation dam DAM2. The second spacer DAM32 is arranged on the second barrier DAM31, and the two together form a third encapsulation dam DAM3.

[0103] S504. Place a high-precision metal mask FMM and a full mask F-MASK on the spacers PS and fix them. Then, invert and adsorb the display substrate formed with the spacers PS, the high-precision metal mask FMM, and the full mask F-MASK on the magnetic plate MG, and form the light-emitting layer EL of each light-emitting device by evaporation deposition.

[0104] It should be noted that the high-precision metal mask FMM is a thin metal mask with small and dense holes, which can precisely control the deposition position of the evaporation deposition material. The full mask F-MASK is used to block the peripheral areas that do not need to be evaporated. During the evaporation deposition process, due to the adsorption effect of the magnetic plate on the full mask F-MASK, the boundary of the full mask F-MASK is prone to warping upwards, causing local slight wrinkling of the FMM and scratching the PS, thereby resulting in the generation of PT particles. In this application, by changing the arrangement pattern of the spacers PS, this problem can be solved.

[0105] Figure 15 is the deformation trend diagram of the high-precision metal mask FMM provided by this application. It can be seen from the figure that when the arrangement pattern shown in Figure 10 is adopted, the deformation amount of the FMM in the y direction is 0.011747, while when the arrangement pattern shown in Figure 11 is adopted, the deformation amount of the FMM in the y direction is 0.0071493, and the deformation amount decreases by 39%, so the possibility of generating PT is lower. Figure 16 is another deformation trend diagram of the high-precision metal mask FMM provided by this application. It can be seen from the figure that when the arrangement pattern shown in Figure 8 is adopted, the deformation amount of the FMM in the y direction is 26.25, while when the arrangement pattern shown inFigure 9 When in the arrangement shown, the deformation amount of the FMM in the y direction is 26.72, and the deformation amounts are basically the same. Therefore, generally speaking, adopting the arrangement of the present application can reduce the risk of packaging failure.

[0106] S505. An electron transport layer ETL, an electron injection layer EIL, and a light extraction layer CPL are sequentially formed on the light-emitting layer EL. Among them, the projection of the edge of the electron injection layer EIL on the substrate SUB is the first edge line BL1, and the projection of the edge of the light extraction layer CPL on the substrate SUB is the second edge line BL2. The spacers PS located in the first part PA21 are arranged between the part of the first boundary line XL1 located in the first part PA21 and the part of the first edge line BL1; the spacers PS located in the second part PA22 are arranged between the part of the first edge line BL1 located in the second part PA22 and the part of the second edge line BL2; between the part of the first edge line BL1 and the part of the second edge line BL2 located in the third part PA23.

[0107] S505. The second electrode 13 of the light-emitting device is formed on the light extraction layer CPL. Among them, the second electrodes 13 of the respective light-emitting devices can be an integrated structure, that is, the second electrode is a full-surface electrode.

[0108] S6. A second planarization layer PLN2 and a packaging layer EPL are sequentially formed on the side of the second electrode 13 facing away from the substrate SUB. Among them, the packaging layer EPL includes a first inorganic packaging layer EPL1, an organic packaging layer, and a second inorganic packaging layer EPL2 arranged in sequence along the direction away from the substrate SUB. Among them, the first inorganic packaging layer EPL1 and the second inorganic packaging layer EPL2 are prepared by a deposition process, and the organic packaging layer EPL3 is prepared by an inkjet printing process.

[0109] Among them, the first inorganic packaging layer EPL1 and the second inorganic packaging layer EPL2 can include inorganic materials such as silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), etc. These inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The organic packaging layer can include a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin. The organic packaging layer can planarize the surface of the display substrate and can relieve the stress of the first inorganic packaging layer EPL1 and the second inorganic packaging layer EPL2.

[0110] S7. A touch layer is formed on the side of the packaging layer facing away from the substrate SUB. Specifically, the touch layer includes a first touch conductive layer TL1, a touch insulating layer TIL, and a second touch conductive layer TL1 (not shown in the figure) arranged in sequence along the direction away from the substrate SUB.

[0111] For example, in the embodiments of the present disclosure, each touch electrode TE in the display area DA includes two layers, the lower layer is the first touch conductive layer TL1, and the upper layer is the second touch conductive layer TL2. The two are insulated from each other through the touch insulation layer TIL. In the peripheral area PA, each touch signal line 5 also includes two layers, the lower layer is the first touch conductive layer TL1, and the upper layer is the second touch conductive layer TL2. The two are insulated from each other through the touch insulation layer TIL. In the touch insulation layer TIL of each touch signal line 5, a contact hole for electrically connecting the first touch conductive layer TL1 and the second touch conductive layer TL2 is provided. In this way, the two touch conductive layers can be used to transmit the same signal and reduce the transmission resistance. For example, in the display area DA, the first touch conductive layer TL1 includes a bridge electrode, and the second touch conductive layer TL2 includes a touch electrode (TX electrode) and a sensing electrode (RX electrode). Among them, the RX electrode 152 is electrically connected to the bridge electrode 154 through a via hole 103 provided in the touch insulation layer TIL. Each of the first touch conductive layer TL1 and the second touch conductive layer TL2 may include a conductive material. The conductive material may include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0112] The present disclosure also provides a display panel, which includes the display substrate in any of the above embodiments. The display panel can be applied in a display device, which can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, or any other product with a display function. Other essential components of the display device are understood by those of ordinary skill in the art and will not be elaborated herein, nor should they be regarded as a limitation to the present disclosure.

[0113] In this article, the following points need to be noted:

[0114] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures can refer to the general design.

[0115] (2) For clarity, in the drawings for describing the embodiments of the present disclosure, the thickness of the layer or area is enlarged or reduced, that is, these drawings are not drawn according to the actual ratio.

[0116] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

Claims

1. A display substrate, which includes a substrate, a plurality of light-emitting devices disposed on the substrate, a packaging layer for packaging the plurality of light-emitting devices, and spacers located on a side of the packaging layer close to the substrate; wherein, the display substrate is divided into a display area and a peripheral area surrounding the display area; the peripheral area includes a first sub-area located on one side of the display area and used for bonding, and a second sub-area connected to the first sub-area; a boundary line between the display area and the second sub-area is a first boundary line; the packaging layer includes a first inorganic packaging layer, an organic packaging layer, and a second inorganic packaging layer sequentially disposed in a direction away from the substrate; the organic packaging layer includes a first sub-organic packaging layer located in the display area, and a second sub-organic packaging layer surrounding the first sub-organic packaging layer and located in the display area and the peripheral area; a maximum thickness of the second sub-organic packaging layer is less than a minimum thickness of the first sub-organic packaging layer; a minimum distance between the spacer and the first boundary line is not less than a distance between a contour of the second sub-organic packaging layer and the first boundary line.

2. The display substrate according to claim 1, wherein, The organic packaging layer further includes a third sub-organic packaging layer surrounding the second sub-organic packaging layer; the maximum thickness of the second sub-organic packaging layer is less than the minimum thickness of the third sub-organic packaging layer; the spacer is disposed on a side of the third sub-organic packaging layer close to the substrate.

3. The display substrate according to claim 2, wherein, The second sub-area includes a first part opposite to the first sub-area, and second and third parts connecting the first part and the first sub-area; the spacers located in the first part are arranged side by side in a first direction; the spacers located in the second and third parts are both arranged side by side in a second direction; the first direction intersects with the second direction.

4. The display substrate according to claim 3, wherein, The display substrate further includes a pixel defining layer disposed on the substrate; the pixel defining layer includes pixel barriers and pixel openings defined by the pixel barriers; the light-emitting device includes a first electrode disposed on a side of the pixel defining layer close to the substrate, and an organic light-emitting functional layer and a second electrode sequentially covering the pixel openings; the spacers located in the display area are disposed on the pixel barriers and on a side of the organic light-emitting functional layer close to the substrate.

5. The display substrate according to claim 4, wherein, The organic light-emitting functional layer at least includes an electron injection layer; the light-emitting device further includes a light extraction layer disposed on a side of the electron injection layer away from the substrate; a positive projection of the light extraction layer on the substrate covers a positive projection of the electron injection layer on the substrate; a positive projection of an edge of the electron injection layer on the substrate is a first edge line, and a positive projection of an edge of the light extraction layer on the substrate is a second edge line; the spacers located in the first part are disposed between a part of the first boundary line located in the first part and a part of the first edge line located in the first part; The spacer located within the second part is disposed between the first edge line part and the second edge line part located within the second part; the spacer located within the third part is disposed between the first edge line part and the second edge line part located within the third part.

6. The display substrate according to claim 3, wherein, The display substrate further includes a touch layer disposed on a side of the encapsulation layer away from the substrate; the touch layer includes a first touch signal line disposed within the first part, a second touch signal line disposed within the second part, and a third touch signal line disposed within the third part; The orthographic projection of the first touch signal line on the substrate covers the orthographic projection of the spacer disposed within the first part on the substrate; the orthographic projection of the second touch signal line on the substrate covers the orthographic projection of the spacer disposed within the second part on the substrate; the orthographic projection of the third touch signal line on the substrate covers the orthographic projection of the spacer disposed within the third part on the substrate.

7. The display substrate according to claim 2, wherein, The display substrate further includes a first encapsulation dam, a second encapsulation dam, and a third encapsulation dam disposed within the first sub-region and the second sub-region, and all three are annular structures; the second encapsulation dam is disposed between the first encapsulation dam and the third encapsulation dam, and the first encapsulation dam is closer to the first boundary line than the third encapsulation dam; The orthographic projection of the third sub-organic encapsulation layer on the substrate covers the orthographic projections of the first encapsulation dam and the second encapsulation dam on the substrate, and has no overlap with the orthographic projection of the third encapsulation dam on the substrate; the spacer is disposed between the first boundary line and the first encapsulation dam.

8. The display substrate according to claim 7, wherein, The second encapsulation dam includes a first barrier part and a first spacer part stacked in sequence in a direction away from the substrate; the third encapsulation dam includes a second barrier part and a second spacer part stacked in sequence in a direction away from the substrate; The first spacer part and the second spacer part are disposed on the same layer as the spacer.

9. The display substrate according to claim 7, wherein, The distance between the surface of the first encapsulation dam away from the substrate and the substrate is greater than the distance between the surface of the second encapsulation dam away from the substrate and the substrate; The distance between the surface of the third encapsulation dam away from the substrate and the substrate is greater than the distance between the surface of the first encapsulation dam away from the substrate and the substrate.

10. The display substrate according to claim 1, wherein, The boundary line between the display area and the first sub-region is the second boundary line; The distance between the spacer and the second boundary line is greater than or equal to zero.

11. The display panel according to claim 1, wherein, Each of the spacers located within the display area is arranged to form multiple sets of nested spacer groups, and each set of spacer groups includes a plurality of the spacers distributed in a ring shape.

12. The display substrate according to claim 1, wherein The orthographic projection of the spacer on the substrate includes any one of a circle, a rectangle, or a square.

13. The display substrate according to claim 1, wherein, The arrangement density of the spacers is 10.3% - 15.5%.

14. A method for preparing a display substrate according to any one of claims 1-13, wherein, The display substrate is divided into a display area and a peripheral area surrounding the display area; the peripheral area includes a first sub-area located on one side of the display area and used for bonding, and a second sub-area connected to the first sub-area; the boundary line between the display area and the second sub-area is the first boundary line; the manufacturing method includes: Providing a substrate; Forming a plurality of light-emitting devices, a plurality of spacers, and a packaging layer on the substrate; wherein, the packaging layer includes a first inorganic packaging layer, an organic packaging layer, and a second inorganic packaging layer sequentially arranged in a direction away from the substrate; the organic packaging layer includes a first sub-organic packaging layer located in the display area, and a second sub-organic packaging layer surrounding the first sub-organic packaging layer and located in the display area and the peripheral area; the maximum thickness of the second sub-organic packaging layer is less than the minimum thickness of the first sub-organic packaging layer; The minimum distance between the spacer and the first boundary line is not less than the distance between the contour of the second sub-organic packaging layer and the first boundary line.

15. A display panel, comprising the display substrate according to any one of claims 1-13.

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