Display device and driving method thereof

Abstract

A display device and a driving method thereof are disclosed. A display device driving method according to one embodiment includes the steps of: receiving a scan rate from a host system; generating a control signal according to a result obtained by comparing the scanning rate with a preset reference value, the control signal is used for controlling whether to perform a first chopping operation of a frame unit with respect to an offset voltage polarity supplied to a display panel displaying an image and whether to perform a second chopping operation of a pixel row with respect to the offset voltage polarity; and outputting the control signal to a panel driving unit for driving the display panel.

Description

Technical Field

[0001] An embodiment relates to a display device and a driving method thereof. Background Art

[0002] In accordance with the information age, the display field for visually expressing electrical information signals has rapidly developed, and thus, various display devices having excellent performance are being developed.

[0003] A display device includes a display panel, a source driver that generates driving voltages for driving a plurality of data lines, and a gate driver that drives a plurality of gate lines.

[0004] In order to display an image without distortion on the display panel, it is necessary to eliminate an offset value of an output signal generated from an output buffer included in the source driver. This is disclosed in Korean Registered Patent No.10-0697287.

[0005] A display panel having a scanning rate of 60 Hz or higher performs a frame unit chopping operation and a pixel row unit chopping operation to eliminate an offset value of an output signal, and the frame unit chopping operation chops the polarity of an offset voltage of the entire screen according to the scanning rate.

[0006] However, in a low scanning rate range having a scanning rate of 60 Hz or lower, when the frame unit chopping operation is performed according to the low scanning rate, a user can easily perceive a brightness difference caused by a voltage difference, and this difference may be perceived by the user as a flicker phenomenon. Summary of the Invention

[0007] Technical Problem

[0008] An embodiment can provide a technology capable of eliminating a flicker phenomenon of a display panel within a scanning rate range detectable by a human eye.

[0009] The object of the present invention is not limited to the above object, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

[0010] Technical Solution

[0011] A driving method of a display device according to an embodiment includes: receiving a scanning rate from a host system by a timing controller; generating, by the timing controller, a control signal based on a result of comparing the scanning rate with a preset reference value, the control signal controlling whether to perform a first chopping operation in a frame unit for a polarity of an offset voltage supplied to a display panel configured to display an image and whether to perform a second chopping operation in a pixel row unit for the polarity of the offset voltage; and outputting, by the timing controller, the control signal to a panel driver configured to drive the display panel.

[0012] Generating the control signal may include: when the scanning rate is equal to or lower than the preset reference value, generating the control signal that turns off the first chopping operation and keeps the second chopping operation on.

[0013] The reference value may have a range of 1 Hz to 60 Hz.

[0014] The control signal may include a first control signal and a second control signal. The first control signal is used to control the first chopping operation of a source driver that supplies a data voltage to the display panel, and the second control signal is used to control the second chopping operation. When the scanning rate is equal to or lower than the preset reference value, the first control signal may control the polarity of the offset voltage in a frame unit to be maintained as a positive voltage or a negative voltage.

[0015] The display panel may be an LTPO (Low Temperature Polycrystalline Oxide) panel.

[0016] A display device according to an embodiment includes: a host system configured to output a scanning rate; a display panel configured to display an image; a panel driver configured to drive the display panel; and a timing controller configured to control the panel driver. Wherein, the timing controller is configured to output a control signal based on a result of comparing the scanning rate with a preset reference value, and the control signal controls whether to perform a first chopping operation on the polarity of an offset voltage supplied to the display panel in a frame unit and whether to perform a second chopping operation on the polarity of the offset voltage in a pixel row unit.

[0017] The timing controller may be configured to: when the scanning rate is equal to or lower than the preset reference value, output the control signal that turns off the first chopping operation and keeps the second chopping operation on.

[0018] The reference value may have a range of 1 Hz to 60 Hz.

[0019] The panel driver may include: a gate driver configured to supply a gate signal to the display panel; and a source driver configured to supply a data voltage to the display panel. Wherein, the control signal may include a first control signal and a second control signal. The first control signal is used to control the first chopping operation of the source driver, and the second control signal is used to control the second chopping operation. When the scanning rate is equal to or lower than the preset reference value, the first control signal may control the polarity of the offset voltage in a frame unit to be maintained as a positive voltage or a negative voltage.

[0020] The display panel may be an LTPO (Low Temperature Polycrystalline Oxide) panel.

[0021] Advantages of the Invention

[0022] In a display with a scanning rate of 60 Hz or lower that is detectable by the human eye, the present invention can prevent the flickering phenomenon that a user may perceive when viewing a display panel with a low scanning rate by turning off the frame unit chopping operation for the polarity of the offset voltage supplied to the display panel and keeping the pixel row unit chopping operation on.

[0023] The advantages of the present invention are not limited to the above advantages, and other advantages not mentioned will be clearly understood by those skilled in the art from the description of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram schematically showing a display device according to an embodiment.

[0025] Figure 2 is schematically showing Figure 1 the block diagram of the source driver shown.

[0026] Figure 3 is a flowchart for explaining a driving method of a display device according to an embodiment.

[0027] Figure 4 and Figure 5 are diagrams showing signal relationships when the display device operates at a reference value or higher and when the display device operates at a reference value or lower.

[0028] Figure 6 is an example showing that the frame unit chopping operation is turned off for the display panel and the pixel row unit chopping operation is maintained during one frame.

[0029] Figure 7 is an example showing that the frame unit chopping operation and the pixel row unit chopping operation are performed for the display panel during one frame. DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, when explaining the embodiments disclosed in this specification in detail with reference to the accompanying drawings, the same or similar components will be assigned the same reference numerals regardless of their reference numerals in the drawings, and redundant explanations thereof will be omitted. In the following description, the suffixes "module" and "unit" for components are only assigned or used interchangeably for convenience in writing the specification, and do not have their own distinct meanings or functions. In addition, when explaining the embodiments disclosed in this specification, when it is determined that a detailed description of related known technologies may obscure the gist of the embodiments disclosed in this specification, such detailed descriptions will be omitted. In addition, the drawings are intended to assist in understanding the embodiments disclosed herein, and the technical concepts disclosed herein are not limited by these drawings. The technical concepts include all modifications, equivalents, or alternatives within the spirit and scope of the present invention.

[0031] Terms including ordinal numbers, such as first, second, etc., may be used to describe different components, but the components are not limited by these terms. These terms are only for the purpose of distinguishing one component from another.

[0032] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that it can be directly coupled or connected to that other component. However, there may be other components between them. In contrast, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components between them.

[0033] Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0034] As used herein, terms such as "comprising" or "having" are intended to indicate the existence of features, figures, steps, actions, components, parts, or any combination thereof described in the specification. However, they do not exclude the possibility of the existence or addition of one or more other features, figures, steps, actions, components, parts, or any combination thereof.

[0035] Figure 1 is a block diagram schematically showing a display device according to an embodiment, and Figure 2 is schematically showing Figure 1 a block diagram of the source driver 310 shown in

[0036] The display device 1 includes a host system 100, a timing controller 200, a panel driver 300, and a display panel 400.

[0037] In a display with a scanning rate of 60 Hz or lower that is detectable by the human eye, the display device 1 can prevent the flicker phenomenon that a user may perceive when viewing the display panel 400 with a low scanning rate by turning off the frame unit chopping operation for the polarity of the offset voltage supplied to the display panel 400 and keeping the pixel row unit chopping operation on.

[0038] That is, the display device 1 can eliminate the offset value by chopping the polarity of the offset voltage supplied to the display panel 400 so as to display an image without distortion on the display panel 400. And when the display panel 400 operates at a scanning rate equal to or lower than a specific scanning rate detectable by the human eye, the display device 1 can eliminate the flicker phenomenon by turning off the frame unit chopping operation that operates according to the scanning rate among the chopping operations for the polarity of the offset voltage.

[0039] The host system 100 can be any one of a TV (television), a set-top box, a navigation system, a personal computer (PC), a home theater, a mobile system, and a wearable system. In mobile devices and wearable devices, the panel driver 300 and the timing controller 200 can be integrated into a single driving IC (not shown).

[0040] For example, in a mobile system, the host system 100 can be implemented as an AP (application processor). The host system 100 can send the pixel data of the input image to the driving IC via MIPI (Mobile Industry Processor Interface). The host system 100 can be connected to the driving IC via a flexible printed circuit (e.g., FPC (Flexible Printed Circuit)).

[0041] The timing controller 200 can receive the image data of the input image and the driving signal synchronized with the image data from the host system 100.

[0042] The timing controller 200 can receive the scanning rate from the host system 100.

[0043] The timing controller 200 can output a control signal in response to the scanning rate, and the control signal controls whether to perform the frame unit offset voltage chopping operation and the pixel row unit offset voltage chopping operation for the display panel 400.

[0044] For example, the pixel row unit can vary according to the pixel configuration of the display panel 400. For example, in the case of a panel whose pixel configuration of the display panel 400 is configured by chopping the rows where RGBG (Red, Green, Blue, Green) repeats and the rows where BGRG (Blue, Green, Red, Green) repeats, the rows where RGBG repeats and the rows where BGRG repeats can be defined as one row unit.

[0045] That is to say, the operation of pixel row unit offset voltage chopping can be performed line by line during one horizontal period (1H).

[0046] For example, the control signal can include a first control signal Chopping 1 for controlling the frame unit offset voltage chopping operation of the source driver 310 and a second control signal Chopping2 for controlling the row unit offset voltage chopping operation.

[0047] For example, when the scanning rate is equal to or lower than a preset reference value, the first control signal Chopping 1 can control the polarity of the offset voltage in the frame unit to maintain a positive voltage or a negative voltage.

[0048] For another example, the first control signal Chopping 1 can include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, a data enable signal DE, etc. The second control signal Chopping 2 can include a start pulse (gating start pulse, VST) and a shift clock GCLK, etc.

[0049] For example, when the scanning rate is equal to or lower than a preset reference value, the timing controller 200 can output a control signal to turn off the frame unit offset voltage chopping operation. That is to say, turning off can mean controlling the polarity of the offset voltage in the frame unit to maintain a positive voltage or a negative voltage.

[0050] For example, the range of the preset reference value can be from 1Hz to 60Hz, and can be set to the following range or a specific scanning rate, which can eliminate the flickering phenomenon detectable by the human eye caused by the brightness difference due to the voltage difference of the display panel 400 at a low scanning rate. For example, the reference value can be set to 1Hz.

[0051] The panel driver 300 can drive the display panel 400.

[0052] The panel driver 300 can include a source driver 310 and a gate driver 320.

[0053] The source driver 310 can output a signal corresponding to the image data to the display panel 400 through the data line DL in response to the image data and the horizontal synchronization signal HSYNC output from the timing controller 200.

[0054] The source driver 310 can include a plurality of amplifiers (not shown) for outputting an output signal corresponding to the image data.

[0055] The source driver 310 can be implemented to perform a chopping operation by using AODC (Amplifier Offset related Chopping) to eliminate the offset of the amplifier.

[0056] The source driver 310 uses a spatial offset cancellation method or a temporal offset cancellation method through a chopping operation.

[0057] The source driver 310 uses the DAC 314 to convert the pixel data of the input image received from the timing controller 200 as a digital signal for each frame into an analog gamma-compensated voltage to output data signals Vdata1 to Vdata3. The data signals Vdata1 to Vdata3 can be provided to the data lines DL.

[0058] The source driver 310 may include a serial-to-parallel converter 311, a shift register unit 312, a data latch unit 313, a DAC (digital-to-analog converter) 314, an output buffer unit 315, and a regulator 316.

[0059] The serial-to-parallel converter (SPC) 311 may receive at least one clock and RGB data in a serialized low-voltage differential signaling method and convert them into parallel RGB data.

[0060] The shift register unit 312 receives the clock from the serial-to-parallel converter 311 and sequentially shifts the clock. Here, the clock can be used to synchronize the output of the shift register unit 312.

[0061] The data latch unit 313 includes a plurality of latch circuits (not shown). Each latch circuit may receive the clock output from the shift register unit 312 and the parallelized RGB data output from the serial-to-parallel converter 311. That is, the data latch unit 313 may sequentially store the parallelized RGB data from one end to the other end of the latch circuit based on the shifted clock.

[0062] The DAC (digital-to-analog converter) 314 may convert the parallelized RGB data (data corresponding to one pixel row) stored in the data latch unit 313 into analog data using gamma reference voltages VG1 to VGk (k is a natural number).

[0063] The output buffer unit 315 may include a plurality of output buffers (not shown). Each of the plurality of output buffers may output the analog data converted by the DAC 314 to the corresponding pixel.

[0064] The regulator 316 may output the voltage required for pixel driving to the display panel 400. For example, the regulator 316 may output a reference voltage Vref and / or an initialization voltage Vinit for pixel driving of the display panel 400.

[0065] At least one of the output buffer unit 315 and the regulator 316 may perform a frame unit chopping operation on the polarity of the offset voltage for the display panel 400 in response to a first control signal Chopping 1 from the timing controller 200.

[0066] At least one of the output buffer unit 315 and the regulator 316 may perform a pixel row unit chopping operation on the polarity of the offset voltage in response to a second control signal Chopping 2 from the timing controller 200.

[0067] That is, at least one of the output buffer unit 315 and the regulator 316 may, in response to control signals Chopping 1 and Chopping 2, chop the polarity of the offset voltage of the display panel 400 in a frame unit or a pixel row unit from a positive voltage high (+) to a negative voltage low (-), or from a low (-) to a high (+).

[0068] For example, at least one of the output buffer unit 315 and the regulator 316 may, in response to a first control signal Chopping 1, chop the polarity of the offset voltage in a frame unit from a positive voltage high (+) to a negative voltage low (-), or from a low (-) to a high (+), or may maintain a positive voltage high or a negative voltage low. At least one of the output buffer unit 315 and the regulator 316 may, in response to a second control signal Chopping 2, chop the polarity of the offset voltage in a pixel row unit from a positive voltage high (+) to a negative voltage low (-), or from a low (-) to a high (+).

[0069] At least one of the output buffer unit 315 and the regulator 316 may include an operational amplifier (not shown), and may eliminate the frame unit offset as a time offset and the pixel row unit offset as a spatial offset of the operational amplifier (not shown) by performing a chopping operation.

[0070] The gate driver 320 receives a gate timing control signal, outputs gate signals GATE1 to GATE3 synchronized with data signals Vdata1 to Vdata3, and supplies them to the pixel row GL. The gate signals GATE1 to GATE3 applied to the pixel row GL turn on the switching elements of the sub-pixels SP to select the pixel row to which the voltages of the data signals Vdata1 to Vdata3 are charged.

[0071] The display panel 400 may display an image.

[0072] The display panel 400 may perform a chopping operation in a frame unit or a pixel row unit according to the polarity of the offset voltage of the regulator 316 from the source driver 310.

[0073] The display panel 400 may prevent a flickering phenomenon recognizable by a user during a low scan rate operation by, in response to a reference value (e.g., a scan rate of 60 Hz or lower) through the timing controller 200, turning off the frame unit chopping operation and keeping the row unit chopping operation on.

[0074] The display panel 400 may be implemented as an LTPO (Low Temperature Polycrystalline Oxide) panel.

[0075] For example, when the display panel 400 is implemented as an LTPO panel, even when the scanning rate is 1 Hz, the pixel row unit chopping operation operates in a sufficiently short period that cannot be recognized by the human eye as an interval between rows, so the user does not feel the flicker phenomenon. However, the frame unit chopping operation chops at the same rate as the scanning rate, so the user feels the flicker phenomenon. However, in the present invention, when operating at a preset reference value or below the preset reference value (e.g., a scanning rate of 60 Hz or less), the flicker phenomenon can be eliminated by turning off the frame unit chopping operation.

[0076] The display panel 400 may include a pixel array AA that displays pixel data of an input image on the screen.

[0077] The pixel array AA includes a plurality of data lines DL, a plurality of pixel rows GL intersecting the data lines DL, and pixels arranged in a matrix form. In addition to the matrix form, the arrangement form of the pixels may be formed differently, such as a form that shares pixels emitting the same color, a stripe form, or a diamond form.

[0078] When the resolution of the pixel array AA is n*m, the pixel array AA includes n pixel columns and m pixel rows L1-Lm intersecting the pixel columns. The pixel columns include pixels arranged in the y-axis direction. The pixel rows include pixels arranged in the x-axis direction.

[0079] One horizontal period (1H) is the time obtained by dividing one frame period by the number of m pixel rows L1 to Lm. Pixel data may be written to the pixels of one pixel row in one horizontal period (1H). For example, one pixel row may represent the row to which a data voltage is simultaneously applied in one horizontal period (1H).

[0080] Each pixel may be divided into a red sub-pixel (Red), a green sub-pixel (Green), and a blue sub-pixel (Blue) for color implementation. Each pixel may also include a white sub-pixel.

[0081] Each sub-pixel SP includes a pixel circuit. The pixel circuit includes a pixel electrode, a plurality of TFTs (Thin Film Transistors), and a capacitor. The pixel circuit may be connected to the data line DL and the pixel row GL.

[0082] Figure 3 It is a flowchart for explaining a driving method of a display device according to an embodiment.

[0083] The timing controller 200 may receive a scanning rate (3100) from the host system 100.

[0084] The timing controller 200 may generate a control signal based on a result of comparing a scanning rate with a preset reference value, and the control signal is used to control whether to perform a first chopping operation in a frame unit for a polarity of an offset voltage supplied to a display panel 400 of a display image and to perform a second chopping operation in a pixel row unit for the polarity of the offset voltage (3200).

[0085] For example, the timing controller 200 may generate a control signal for controlling an operation of the source driver 310 to turn off the first chopping operation and keep the second chopping operation on when the scanning rate is equal to or lower than the preset reference value.

[0086] For example, the reference value may have a range of 1 Hz to 60 Hz.

[0087] For example, the control signal may include a first control signal for controlling the first chopping operation of the source driver 310 and a second control signal for controlling the second chopping operation of the source driver 310.

[0088] For example, the source driver 310 may perform a frame unit chopping operation for the polarity of the offset voltage of the display panel 400 in response to the first control signal Chopping 1 from the timing controller 200.

[0089] The source driver 310 may perform a pixel row unit chopping operation for the polarity of the offset voltage in response to the second control signal Chopping 2 from the timing controller 200.

[0090] That is, the source driver 310 may chop the polarity of the offset voltage of the display panel 400 in the frame unit or the pixel row unit from a positive voltage high (+) to a negative voltage low (-), or from low (-) to high (+) in response to the control signals Chopping 1 and Chopping 2.

[0091] For example, the source driver 310 may chop the polarity of the offset voltage in the frame unit from a positive voltage high (+) to a negative voltage low (-), or from low (-) to high (+), or may maintain a positive voltage high or a negative voltage low in response to the first control signal Chopping 1. The source driver 310 may chop the polarity of the offset voltage in the pixel row unit from a positive voltage high (+) to a negative voltage low (-), or from low (-) to high (+) in response to the second control signal Chopping 2.

[0092] The timing controller 200 can generate a first control signal Chopping 1 for controlling the first chopping operation of the source driver 310 and a second control signal Chopping 2 for controlling the second chopping operation. For example, when the scanning rate is equal to or lower than a preset reference value, the first control signal Chopping 1 can control the polarity of the offset voltage in the frame unit to be maintained as a positive voltage or a negative voltage.

[0093] The timing controller 200 can output a control signal to the panel driver 300 (3300) that drives the display panel 400.

[0094] In the panel driver 300, the source driver 310 can turn on or off the chopping operation (3400) of the polarity of the offset voltage for the display panel 400 according to the control signal.

[0095] For example, in the panel driver 300, the source driver 310 can perform a frame unit chopping operation on the polarity of the offset voltage for the display panel 400 in response to the first control signal Chopping 1. The source driver 310 can perform a pixel row unit chopping operation on the polarity of the offset voltage in response to the second control signal Chopping 2.

[0096] For example, when the first control signal Chopping 1 is a signal to turn off the first chopping operation and the second control signal Chopping 2 is a signal to keep the second chopping operation on, the panel driver 300 can turn off the first chopping operation on the polarity of the offset voltage in the frame unit and keep the second chopping operation on the polarity of the offset voltage in the pixel row unit on in response to each signal.

[0097] Figure 4 and Figure 5 are diagrams showing the signal relationships when the display device operates at the reference value or higher and when the display device operates at the reference value or lower, Figure 6 is an example showing that the frame unit chopping operation is turned off and the pixel row unit chopping operation is maintained for the display panel during one frame, and Figure 7 is an example showing that the frame unit chopping operation and the pixel row unit chopping operation are performed for the display panel during one frame.

[0098] Figure 4Schematically shows an example where the scan rate received by the timing controller 200 from the host system 100 is equal to or higher than the reference value or exceeds the reference value, and can show the periods of the vertical synchronization signal Vsync, the latch signal Data Latch, the first control signal chopping 1 as the first chopping operation signal for the frame unit, and the second control signal chopping 2 as the second chopping operation signal for the pixel row unit when the scan rate is 120 Hz.

[0099] When the scan rate received from the host system 100 is a scan rate of 120 Hz, the timing controller 200 can output the first control signal chopping 1 to perform a frame unit offset voltage chopping operation for the display panel 400 every 1 / 120 second, and can output the second control signal chopping 2 to perform a row unit offset voltage chopping operation every horizontal period (1H).

[0100] That is, when the scan rate is a scan rate of 120 Hz, the user cannot recognize the frame chopping operation, so the flickering phenomenon cannot be felt.

[0101] Figure 5 Schematically shows an example within the reference value range, and can show the periods of the vertical synchronization signal Vsync, the latch signal Data Latch, the first control signal chopping 1 as the first chopping operation signal for the frame unit, and the second control signal chopping 2 as the second chopping operation signal for the pixel row unit when the scan rate received from the host system 100 is a scan rate of 1 Hz.

[0102] When the scan rate received from the host system 100 is a scan rate of 1 Hz that is equal to or lower than the reference value, the timing controller 200 can output the first control signal chopping 1 to turn off the frame unit offset voltage chopping operation of the display panel 400 by maintaining the positive voltage high or the negative voltage low, and can output the second control signal chopping 2 to perform a pixel row unit offset voltage chopping operation every horizontal period (1H).

[0103] Figure 6 Is a diagram showing the polarities of the offset voltages of the sub-pixels of the display panel 400, and 1 can represent a positive voltage while 0 can represent a negative voltage.

[0104] Figure 6 In (a) shows the polarities of the offset voltages of the sub-pixels in the first frame, and Figure 6 In (b) can show the polarities of the offset voltages in the second frame as a subsequent frame period of the first frame.

[0105] When the scanning rate is equal to or lower than a preset reference value, the timing controller 200 may turn off the first chopping operation in the frame unit for the polarity of the offset voltage supplied to the display panel 400 and keep the second chopping operation in the pixel row unit for the polarity of the offset voltage turned on.

[0106] That is to say, when the scanning rate is equal to or lower than a preset reference value, by maintaining the polarity of the offset voltage in the frame unit as a positive voltage or a negative voltage, the chopping operation for the frame unit of the display panel 400 during one frame period from (a) in Figure 6 to Figure 6 in (b) is turned off, and the pixel row unit chopping operation may be performed for the display panel 400 every horizontal period (1H).

[0107] Figure 7 FIG. is a diagram showing the polarities of the offset voltages of the sub-pixels of the display panel 400, and 1 may represent a positive voltage while 0 may represent a negative voltage.

[0108] Figure 7 (a) in Figure 7 shows the polarities of the offset voltages of the sub-pixels in the third frame, and

[0109] in (b) may show the polarities of the offset voltages in the fourth frame which is the next frame period of the third frame.

[0110] That is to say, when the scanning rate is higher than or equal to a preset reference value, the timing controller 200 may keep the first chopping operation in the frame unit for the polarity of the offset voltage supplied to the display panel 400 and the second chopping operation in the pixel row unit for the polarity of the offset voltage turned on. Figure 7 That is to say, when the scanning rate is higher than or equal to a preset reference value, the chopping operation for the frame unit of the display panel 400 during one frame period from (a) in Figure 7 to

[0111] in (b) is performed for each frame, and the pixel row unit chopping operation may be performed for the display panel 400 every horizontal period (1H).

[0112] For example, when the scanning rate is equal to or lower than a preset reference value, if the chopping operation for the frame unit of the display panel 400 is performed for each frame during one frame period, the user may feel it as a flickering phenomenon.

[0113] Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, they are not necessarily limited to such embodiments and can be modified in various ways within the scope without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in this specification are provided for illustrative purposes only and are not intended to limit the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited to these embodiments. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present invention. The protection scope of the present invention should be interpreted based on the following claims, and all technical concepts within the scope of their equivalents should be interpreted as falling within the scope of the present invention.

Claims

1. A driving method for a display device, the driving method comprising the following steps: Receiving a scanning rate from a host system by a timing controller; Generating, by the timing controller, a control signal based on a result of comparing the scanning rate with a preset reference value, the control signal controlling whether to perform a first chopping operation in a frame unit for a polarity of an offset voltage supplied to a display panel configured to display an image and whether to perform a second chopping operation for the polarity of the offset voltage in a pixel row unit; And Outputting, by the timing controller, the control signal to a panel driver configured to drive the display panel.

2. The driving method of the display device according to claim 1, wherein, The step of generating the control signal includes: when the scanning rate is equal to or lower than the preset reference value, generating the control signal for turning off the first chopping operation and keeping the second chopping operation on.

3. The driving method of the display device according to claim 2, wherein, The reference value has a range of 1 Hz to 60 Hz.

4. The driving method of the display device according to claim 3, wherein, The control signal includes a first control signal and a second control signal, the first control signal being used to control the first chopping operation of a source driver for supplying a data voltage to the display panel, the second control signal being used to control the second chopping operation, and when the scanning rate is equal to or lower than the preset reference value, the first control signal controls the polarity of the offset voltage in the frame unit to maintain a positive voltage or a negative voltage.

5. The driving method of the display device according to claim 4, wherein, The display panel is a low-temperature polycrystalline oxide LTPO panel.

6. A display device, the display device comprising: A host system configured to output a scanning rate; A display panel configured to display an image; A panel driver configured to drive the display panel; And A timing controller configured to control the panel driver, wherein the timing controller is configured to output a control signal based on a result of comparing the scanning rate with a preset reference value, the control signal controlling whether to perform a first chopping operation in a frame unit for a polarity of an offset voltage supplied to the display panel and whether to perform a second chopping operation for the polarity of the offset voltage in a pixel row unit.

7. The display device according to claim 6, wherein, The timing controller is configured to: when the scanning rate is equal to or lower than the preset reference value, output the control signal for turning off the first chopping operation and keeping the second chopping operation on.

8. The display device according to claim 7, wherein, The reference value has a range of 1 Hz to 60 Hz.

9. The display device according to claim 8, wherein, The panel driver includes: A gate driver configured to supply a gate signal to the display panel; and A source driver configured to supply a data voltage to the display panel, wherein the control signal includes a first control signal and a second control signal, the first control signal being used to control the first chopping operation of the source driver, the second control signal being used to control the second chopping operation, and when the scanning rate is equal to or lower than the preset reference value, the first control signal controls the polarity of the offset voltage in the frame unit to maintain a positive voltage or a negative voltage.

10. The display device according to claim 9, wherein, The display panel is a low-temperature polycrystalline oxide LTPO panel.

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