Method for testing resistance of semiconductor wafer made of monocrystalline silicon against thermally induced dislocation

Abstract

The invention relates to a method for testing the resistance of a semiconductor wafer made of monocrystalline silicon against thermally induced dislocations, comprising: subjecting the semiconductor wafer, which has a diameter and rests on contact points of a plurality of fingers of a boat, to a heat treatment adapted to the properties of the semiconductor material in a shaft furnace, the distance from the contact point to the boundary of the semiconductor wafer has a length not less than 5% of the diameter of the semiconductor wafer and not greater than 40% of the diameter of the semiconductor wafer; a BFA analysis is performed on one or more partial surfaces of the semiconductor wafer around the contact point by means of an SIRD system, wherein the shortest distance of the one or more partial surfaces to the boundary of the semiconductor wafer is not less than 1 mm and not greater than 33% of the diameter of the semiconductor wafer.

Description

Technical Field

[0001] The present invention provides a method for testing the resistance of a semiconductor wafer made of single crystal silicon to thermally induced stress. Thermally induced stress causes plastic deformation of the semiconductor wafer and has an adverse effect on the yield of semiconductor components. Background Art

[0002] Manufacturers of electronic devices require semiconductor wafers that are mechanically robust in high-temperature processes and thus need suppliers of semiconductor wafers to provide reliable information about their robustness (or ruggedness) to thermal stress.

[0003] US2010 0 015 817A1 states that heat treatment of a semiconductor wafer in a vertical furnace (or upright furnace) may cause thermally induced slip, which results from contact stress of the fingers (wafer supports) of the boat on which the semiconductor wafer lies during the heat treatment.

[0004] US2002 0 119 641A1 describes high-temperature treatment for a substrate made of silicon, in which a boat having fingers made of polysilicon is used.

[0005] US2004 0 021 097A1 describes a way in which SIRD (scanning infrared depolarization) can be used to examine the mechanical stress of a semiconductor wafer.

[0006] JP2015-73049 A shows that thermally induced stress and strain can be quantitatively described by means of SIRD and BFA (bad fraction area or bad area) analysis.

[0007] According to JP2006 269 896A, the duration and temperature of heat treatment affect the occurrence of thermally induced stress.

[0008] US2016 0 247 694A1 describes a method for evaluating the quality of the robustness of a semiconductor wafer made of silicon to thermally induced stress. One finding is that the higher the concentration of interstitial oxygen and the lower the temperature of the heat treatment to which the tested semiconductor wafer is subjected to induce stress, the higher the critical stress. Summary of the Invention

[0009] The object of the present invention is to provide a method that allows for the reliable and reproducible evaluation of the robustness of a semiconductor wafer made of silicon to thermally induced stress in a simple manner.

[0010] The object of the present invention is achieved by a method for testing the robustness of a semiconductor wafer made of single crystal silicon to thermally induced stress, the method comprising:

[0011] Subject the semiconductor wafer to a heat treatment in a vertical furnace that matches the properties of the semiconductor material, where the semiconductor wafer has a diameter and is rested on the contact sites (or locations) of several (or multiple) fingers of a boat, and the distance of the contact site from the edge of the semiconductor wafer has a length that is not less than 5% of the diameter of the semiconductor wafer and not greater than 40% of the diameter of the semiconductor wafer;

[0012] Perform BFA analysis on one or more regions around the contact site of the semiconductor wafer by means of an SIRD system, where the shortest distance of the one or more regions from the edge of the semiconductor wafer is not less than 1 mm and not greater than 33% of the diameter of the semiconductor wafer.

[0013] The inventors have found that when a heat treatment matching the semiconductor material to be tested is carried out in a vertical furnace, the semiconductor wafer to be tested is rested on the fingers of a long-finger boat and the distance of the contact site from the edge of the semiconductor wafer is relatively long, a test that can be easily performed and reproduced can be designed. This increases the distance that the thermally induced dislocations need to travel to reach the edge of the semiconductor wafer and prevents the edge effect from affecting the test results. For all semiconductor wafers to be tested, the positions of the contact sites where the semiconductor wafers to be tested contact the fingers of the boat are similar (or equivalent). The number of fingers and thus the number of contact sites is at least three, preferably three or four.

[0014] The semiconductor wafer to be tested is made of single crystal silicon and preferably has a diameter of at least 200 mm. It is possible to test, for example, a substrate wafer made of single crystal silicon with a polished side or additionally a substrate wafer with an epitaxial layer deposited on the upper side or an SOI (silicon-on-insulator) wafer.

[0015] Regarding the properties of the semiconductor material that are important for the design of the heat treatment, the parameters that can be envisioned are in principle all the parameters that affect the mechanical stability of the semiconductor material under thermal stress. For a semiconductor wafer made of silicon, these parameters are, for example, the concentration of interstitial oxygen (O i ) and the resistivity (which depends on the concentration of electrically active dopants).

[0016] The duration and temperature of the heat treatment are matched to the characteristics of the semiconductor material of the semiconductor wafer to be tested. The heat treatment is intended to induce stresses, the degree of which remains in the form of slip lines in the depolarization map in the region, and they are analyzed by BFA analysis. Of course, it is also possible to test semiconductor wafers of which the characteristics of the semiconductor material are unknown. If it is found that the tests with the selected heat treatment do not give satisfactory results, it may be necessary to perform tests on semiconductor wafers of the same kind, in which different heat treatments are carried out. The heat treatment is designed such that its duration at the target temperature is long enough to generate thermally induced dislocations / slips, but also short enough to be economical and to avoid the formation of slip lines extending to the edge of the semiconductor wafer. The duration of the heat treatment at the target temperature is preferably from 5 to 30 minutes. The atmosphere for carrying out the heat treatment can be selected independently of the semiconductor material. Suitable examples are oxygen, nitrogen or an inert gas such as argon or a combination of the gases mentioned.

[0017] Prior to this heat treatment, the semiconductor wafer to be tested may have undergone a prior heat treatment (pre-annealing), for example a heat treatment by which the nuclei of oxygen precipitates are evolved into BMD (bulk microdefects), or an RTA (rapid thermal annealing) treatment. If the prior heat treatment was also carried out on a boat in a vertical furnace, the boat contact points should preferably not overlap. To achieve this, the semiconductor wafer can be placed in a boat that has been rotated after the prior heat treatment. The prior heat treatment for BMD evolution preferably comprises a period of heating the semiconductor wafer at a temperature of 780 °C for 3 hours in an oxygen atmosphere, followed by a period of heating at 1000 °C for 16 hours.

[0018] For semiconductor wafers made of p-doped monocrystalline silicon with boron, it is recommended to provide at least two different heat treatments for selection. One heat treatment is matched to a relatively lightly doped (p - doping), i.e. a semiconductor material having a specific resistivity of about 1 ohm cm or greater, and the other heat treatment is matched to a semiconductor material containing a relatively large amount of dopant (p + doping), i.e. having a specific resistivity of 100 m ohm cm or less. If there are additional dopants in the semiconductor wafer besides boron, it is possible to find out by simple experiments whether and if so, how the conditions of the heat treatment must be adjusted. The design of the boat-shaped area at the contact site also affects the mechanical stress on the semiconductor wafer, and thus, such tests should take this fact into account if necessary. The purpose of the test is to induce stresses / slip dislocations by means of heat treatment, the degree of which remains in a specified area around the boat contact site and can be characterized by using a SIRD system.

[0019] Table 1 below contains the temperature steps (ramp to) and temperature change rates (ramp rate) of two preferred heat treatments (Procedure 1 (left) and Procedure 2 (right)) in an oxygen and a nitrogen atmosphere. The two preferred heat treatments differ particularly in the target temperatures of 1100 °C and 1200 °C. Procedure 1 is particularly suitable for testing p - -doped semiconductor wafers made of single-crystalline silicon with a diameter of 300 mm, while Procedure 2 is used for testing p + -doped semiconductor wafers or epitaxially coated semiconductor wafers made of p + -type single-crystalline silicon. The heat treatment is optimized for use with a polysilicon boat sold by Ferrotec Material Technologies Corporation.

[0020] Table 1

[0021]

[0022] After the heat treatment and any prior heat treatment, BFA analysis is carried out by means of a SIRD system. The SIRD system gives a stress field map in the form of a depolarization map (full wafer map), which is optionally smoothed by a high-pass filter and indicates the depolarization depending on the position on the area of the semiconductor wafer. The highest resolution provided by the SIRD system is preferably used. The process (or method) of the present invention contemplates evaluating the depolarization of one or more areas restricted to the vicinity of the boat contact points where contact exists between the semiconductor wafer and the fingers of the boat during the heat treatment. The distance of the contact site from the edge of the semiconductor wafer has a length of not less than 5% and not more than 40% of the diameter of the semiconductor wafer, preferably not less than 10% and not more than 35% of the diameter of the semiconductor wafer, and more preferably not less than 45 mm for a semiconductor wafer with a diameter of 300 mm. The shortest distance of the one or more areas from the edge of the semiconductor wafer has a length of not less than 1 mm and not more than 33% of the diameter of the semiconductor wafer, preferably not less than 3 mm and not more than 25% of the diameter of the semiconductor wafer, and more preferably not less than 10 mm for a semiconductor wafer with a diameter of 300 mm. This distance from the edge is advantageous because it can largely exclude the influence of the edge region on the depolarization, so that the measurement result basically depends on the characteristics of the semiconductor material itself.

[0023] The one or more regions are preferably circular, and if two or more such regions work together, their radii are preferably the same. Circular regions can be used, the center of which is the contact site, or two or more contact sites are located on the circular region. Shapes other than the circular shape are also possible, for example, one or more regions having a rectangular or square shape or a shape with a triangle or a ring.

[0024] During the BFA analysis, the depolarization situation is determined for the cells of a grid virtually placed on the depolarization map. The grid preferably consists of square cells with a side length preferably of 2 mm. If the depolarization value in a cell within a region exceeds a set threshold, the cell is added to the number (or count) of bad cells. The upper and lower limits of the threshold setting are preferably from ±10 DU to ±30 DU. The ratio of the number of bad cells to the number of all cells evaluated is a measure of the resistance of the semiconductor wafer to thermally induced stress. Only when at least 50% of the area of the cell in question is involved, the cell that is not completely located within a region is counted. This evaluation can be selectively implemented by determining this ratio for one, more than one, or each of the one or more regions and optionally averaging the partial results. In addition, the distribution of bad cells can also be statistically evaluated additionally within the one or more regions in order to describe the range or homogeneity of the stress field within the one or more regions.

[0025] The analysis of highly doped semiconductor wafers made of silicon using the SIRD system has physical limitations. Outside (or beyond) a specific resistivity range below 6 mohmcm, the absorption of free charge carriers begins to block the transmission of IR radiation.

[0026] The present invention will be further described below by way of example with reference to the accompanying drawings. Description of the Drawings

[0027] Figure 1 A typical depolarization map is shown, on which the circular regions for performing the BFA analysis are highlighted.

[0028] Figure 2 A region and a grid virtually placed thereon are shown.

[0029] Figure 3 The results of the BFA analysis for groups of single-crystalline silicon semiconductor wafers are shown.

[0030] List of Reference Numerals

[0031] 1 Semiconductor wafer

[0032] 2 Region

[0033] 3 Contact site

[0034] 4 Edge

[0035] 5 Slip line

[0036] 6 Grid Detailed implementation manner

[0037] Detailed description of the working example of the present invention

[0038] Figure 1 The depolarization map of the semiconductor wafer 1 made of single-crystalline silicon is shown, on which three circular regions 2 for performing BFA analysis are highlighted. The contact part 3 is located at the center of the region 2, where there is contact between the semiconductor wafer 1 and the fingers of the boat during the heat treatment. The distance between the contact part 3 and the edge 4 of the semiconductor wafer has a required length. Due to the thermal stress and gravity-induced mechanical stress on and around the contact part, the slip / dislocation lines 5 extend along the energetically preferred crystal planes in the direction of the edge 4 of the semiconductor wafer 1. The distance between the edge 4 of the semiconductor wafer 1 and the region 2 has a required length, such that the defects in the edge 4 that affect the stress field have little effect on the depolarization in the region 2. In addition, the heat treatment is matched to the characteristics of the semiconductor material, such that the slip lines 5 do not extend all the way to the edge 4 and do not leave the region 2. For example, a higher target temperature and / or a longer heat treatment duration might otherwise cause the slip lines to extend all the way to the edge of the semiconductor wafer.

[0039] Figure 2 One of the circular regions 2 for evaluation by BFA analysis and a grid 6 virtually placed thereon are shown. Those cells counted as bad cells are marked by dots.

[0040] Example

[0041] The robustness of semiconductor wafers made of single-crystalline silicon against thermally induced stress is tested on six groups, with each group having five semiconductor wafers in three test runs. All semiconductor wafers have a diameter of 300 mm and are doped with boron.

[0042] The material properties of the semiconductor wafers related to the boron doping level and the interstitial oxygen concentration are given in Table 2. The semiconductor wafers in groups 1 - 3 are substrate wafers with polished sides, while the semiconductor wafers in groups 4 - 6 additionally have a p-doped silicon layer on the epitaxially deposited upper side.

[0043]

[0044] In a vertical furnace from ASM International NV, semiconductor wafers of groups 1 - 4 are subjected to a heat treatment according to program 1, and semiconductor wafers of groups 5 and 6 are subjected to a heat treatment according to program 2, where each semiconductor wafer is placed on three fingers of a long finger boat from the manufacturer FerroTec Materials Technologies.

[0045] Thereafter, a BFA analysis is carried out on a circular area with a radius of 40 mm around the contact sites where contact exists between the semiconductor wafer and the fingers of the boat during the heat treatment, by means of a SIRD system from PVA Metrology & Plasma Solutions GmbH. The shortest distance of the three areas from the semiconductor wafer edge is optimally approximately 10 mm in each case.

[0046] The high - pass filtered depolarization map sent out by the SIRD system is evaluated in the areas, and for this purpose, a depolarization threshold of ±10 DU (depolarization unit) is fixed. The result of the BFA analysis is the number of bad cells in the three areas and the percentage bcf (bad cell fraction) of the number of cells in the three areas.

[0047] Figure 3 This result for the semiconductor wafers of groups 1 - 6 for each test run is shown. As expected, the robustness against thermal stress increases with the increasing concentration of interstitial oxygen, and is more significant in the case of p + doped semiconductor wafers than in the case of p - doped semiconductor wafers. The variation of the measurement results from the test runs is low, and the test method has good reproducibility. The obvious anomaly in the results for the semiconductor wafers from group 6 is explained by the fact that the corresponding semiconductor wafers are from another single crystal pulled in a different way.

Claims

1. A method for testing the robustness of a semiconductor wafer made of single crystal silicon against thermally induced stress, comprising subjecting the semiconductor wafer to a heat treatment in a vertical furnace that matches the properties of the semiconductor material, wherein the semiconductor wafer has a diameter and is resting on contact portions of several fingers of a boat, and the length of the distance of the contact portions from the edge of the semiconductor wafer is not less than 5% of the diameter of the semiconductor wafer and not more than 40% of the diameter of the semiconductor wafer; performing BFA analysis on one or more regions around the contact portions of the semiconductor wafer by means of a SIRD system, wherein the shortest distance of the one or more regions from the edge of the semiconductor wafer is not less than 1 mm and not more than 33% of the diameter of the semiconductor wafer.

2. The method according to claim 1, comprising: selecting the heat treatment according to the concentration of interstitial oxygen and / or according to the resistivity of the semiconductor wafer.

3. The method according to claim 1 or 2, comprising: performing a heat treatment before the heat treatment, wherein the semiconductor wafer is resting on the fingers of the boat at additional contact portions, and the contact portions do not overlap with the additional contact portions.

4. The method according to any one of claims 1 to 3, wherein, The semiconductor wafer has a diameter of 300 mm, and the length of the distance of the contact portions from the edge of the semiconductor wafer is not less than 45 mm.

5. The method according to any one of claims 1 to 4, wherein, The semiconductor wafer has a diameter of 300 mm, and the shortest distance of each region from the edge of the semiconductor wafer is not less than 10 mm.

Images