Three-dimensional memory device having layer contact via structures in memory

Abstract

A three-dimensional memory device includes: an alternating stack of insulating layers and conductive layers; an array extending vertically through the alternately stacked memory openings; a memory-opening-free region in the array of memory openings in a plan view; an array of memory opening filling structures in the array of memory openings; and layer contact elements located within the memory-free opening regions in the plan view. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective memory element at a level of the conductive layers. Each of the layer contact assemblies includes a respective layer contact via structure contacting a respective one of the conductive layers, and a respective insulating spacer laterally surrounding the respective layer contact via structure.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of the entire content of U.S. Non - Provisional Application No. 18 / 233,759, filed on August 14, 2023, entitled "THREE - DIMENSIONAL MEMORY DEVICE WITH LAYER CONTACT VIA STRUCTURES LOCATED IN A MEMORY ARRAY REGION AND METHODS OF FORMING THE SAME", and is hereby incorporated by reference for all purposes, which non - provisional application claims the priority of U.S. Provisional Application No. 63 / 501,182, filed on May 10, 2023. Technical Field

[0003] The present invention generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices including layer contact via structures located in a memory array region and methods of forming the same. Background Art

[0004] A three - dimensional memory device including a three - dimensional vertical NAND string having one bit per cell is disclosed in the article by T. Endoh et al., entitled "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell", published in the Proceedings of the International Electron Devices Meeting (IEDM Proc.) 2001, pages 33 - 36. Summary of the Invention

[0005] According to one aspect of the present disclosure, a three-dimensional memory device includes: an alternating stack of insulating layers and conductive layers; an array of memory openings extending vertically through the alternating stack; a memory-opening-free region in the array of these memory openings in a plan view; an array of memory-opening filling structures in the array of memory openings; and layer contact components in these memory-opening-free regions in the plan view. Each of these memory-opening filling structures includes a corresponding vertical semiconductor channel and a corresponding memory element at levels of these conductive layers. Each of these layer contact components includes a corresponding layer contact via structure contacting a corresponding one of these conductive layers, and a corresponding insulating spacer laterally surrounding the corresponding layer contact via structure.

[0006] According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided. The method includes: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; forming an array of memory openings through the alternating stack, wherein the array of memory openings is arranged to provide a memory-opening-free region therein in a plan view; forming an array of memory-opening filling structures in the array of memory openings, wherein each of these memory-opening filling structures includes a corresponding vertical semiconductor channel and a corresponding memory element at levels of these conductive layers; forming in the region of the memory-opening-free region in the plan view a process via structure including a sacrificial via filling material portion, wherein each of these process via structures vertically extends through a corresponding subset of layers within the alternating stack; replacing the sacrificial material layer with a conductive layer; and replacing these sacrificial via filling material portions with layer contact via structures to form layer contact components, wherein each of these layer contact components includes a corresponding layer contact via structure contacting a corresponding one of these conductive layers, and further includes a corresponding insulating spacer laterally surrounding the corresponding layer contact via structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a vertical cross-sectional view of an exemplary structure after forming an alternating stack of an insulating layer and a sacrificial material layer according to an embodiment of the present disclosure.

[0008] Figure 2A is a vertical cross-sectional view of an exemplary structure after forming memory openings and support openings according to an embodiment of the present disclosure.

[0009] Figure 2B is Figure 2A a top-down view of the exemplary structure of. The vertical plane A-A’ is Figure 2A the vertical cross-section of.

[0010] Figure 3is a vertical cross - sectional view of an exemplary structure after forming a sacrificial memory opening filling structure according to an embodiment of the present disclosure.

[0011] Figure 4 is a vertical cross - sectional view of an exemplary structure after forming a support pillar structure according to an embodiment of the present disclosure.

[0012] Figure 5 is a vertical cross - sectional view of an exemplary structure after removing the sacrificial memory opening filling structure according to an embodiment of the present disclosure.

[0013] Figures 6A to 6H is a vertical cross - sectional view of a memory opening during the formation of a memory opening filling structure.

[0014] Figure 7A is a vertical cross - sectional view of an exemplary structure after forming a memory opening filling structure according to an embodiment of the present disclosure.

[0015] Figure 7B is Figure 7A a top - down view of an exemplary structure. The vertical plane A - A’ is Figure 7A the vertical section.

[0016] Figure 7C is a top - down view of a first alternative configuration of an exemplary structure according to an alternative embodiment of the present disclosure after the processing steps of Figure 7A and Figure 7B

[0017] Figure 7D is a top - down view of a second alternative configuration of an exemplary structure according to another alternative embodiment of the present disclosure after the processing steps of Figure 7A and Figure 7B

[0018] Figure 8A is a vertical cross - sectional view of an exemplary structure after forming a patterned hard mask layer and a contact via cavity according to an embodiment of the present disclosure.

[0019] Figure 8B is Figure 8A a top - down view of an exemplary structure. The vertical plane A - A’ is Figure 8A the plane of the vertical cross - section.

[0020] Figure 8C is a vertical cross - sectional view of an exemplary structure along the vertical plane C - C’ of Figure 8B

[0021] Figure 9Ais a vertical cross - sectional view of an exemplary structure after forming an insulating liner layer, a sacrificial via fill material portion, a sacrificial capping layer, and isolation trenches according to an embodiment of the present disclosure.

[0022] Figure 9B is Figure 9A a top - down view of the exemplary structure. The vertical plane A - A’ is Figure 9A the plane of the vertical cross - sectional view.

[0023] Figure 9C is a vertical cross - sectional view of the exemplary structure along Figure 9B the vertical plane C - C’.

[0024] Figure 10A is a vertical cross - sectional view of an exemplary structure after forming lateral grooves according to an embodiment of the present disclosure.

[0025] Figure 10B is Figure 10A a top - down view of the exemplary structure. The vertical plane A - A’ is Figure 10A the plane of the vertical cross - sectional view.

[0026] Figure 10C is a vertical cross - sectional view of the exemplary structure along Figure 10B the vertical plane C - C’.

[0027] Figure 11A is a vertical cross - sectional view of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0028] Figure 11B is Figure 11A a top - down view of the exemplary structure. The vertical plane A - A’ is Figure 11A the plane of the vertical cross - sectional view.

[0029] Figure 11C is a vertical cross - sectional view of the exemplary structure along Figure 11B the vertical plane C - C’.

[0030] Figure 11D is a vertical cross - sectional view of the region around the memory opening fill structure in an exemplary structure after Figures 11A to 11C the processing step.

[0031] Figure 12A is a vertical cross - sectional view of an exemplary structure after forming an isolation trench fill structure and removing the sacrificial capping layer according to an embodiment of the present disclosure.

[0032] Figure 12B is Figure 12A a top - down view of the exemplary structure. The vertical plane A - A’ is Figure 12AThe plane of the vertical sectional view.

[0033] Figure 12C is along Figure 12B The vertical sectional view of the exemplary structure along the vertical plane C-C’ of

[0034] Figure 13A is the vertical sectional view of the exemplary structure after removing the sacrificial via filling material portion and forming the insulating spacer according to an embodiment of the present disclosure.

[0035] Figure 13B is Figure 13A The top-down view of the exemplary structure of . The vertical plane A-A’ is Figure 13A The plane of the vertical sectional view.

[0036] Figure 14A is the vertical sectional view of the exemplary structure after forming the layer contact via structure and the drain select level dielectric isolation structure according to an embodiment of the present disclosure.

[0037] Figure 14B is Figure 14A The top-down view of the exemplary structure of . The vertical plane A-A’ is Figure 14A The plane of the vertical sectional view.

[0038] Figure 14C is along Figure 14B The vertical sectional view of the exemplary structure along the vertical plane C-C’ of

[0039] Figure 14D is the top-down view of the first alternative configuration of the exemplary structure after the processing step of Figures 14A to 14C according to an alternative embodiment of the present disclosure.

[0040] Figure 14E is the top-down view of the second alternative configuration of the exemplary structure after the processing step of Figures 14A to 14C according to another alternative embodiment of the present disclosure.

[0041] Figure 15A is the vertical sectional view of the exemplary structure after forming the contact level dielectric layer, the drain contact via structure, and the contact level extension via structure according to an embodiment of the present disclosure.

[0042] Figure 15B is Figure 15A The top-down view of the exemplary structure of . The vertical plane A-A’ is Figure 15A The plane of the vertical sectional view.

[0043] Figure 15C is along Figure 15BVertical sectional view of an exemplary structure of the vertical plane C-C'.

[0044] Figure 16A Is a vertical sectional view of an exemplary structure after forming a connection-level dielectric layer, a drain connection via structure, a connection-level extension via structure, a line-level dielectric layer, a bit line, and a layer connection metal line according to an embodiment of the present disclosure.

[0045] Figure 16B Is Figure 16A Top-down view of an exemplary structure. The vertical plane A-A' is Figure 16A The plane of the vertical sectional view.

[0046] Figure 16C Is along Figure 16B Vertical sectional view of an exemplary structure of the vertical plane C-C'.

[0047] Figure 16D Is along Figure 16B Vertical sectional view of an exemplary structure of the vertical plane D-D'.

[0048] Figure 17 Is a vertical sectional view of an exemplary structure after forming an upper dielectric material layer and an upper metal interconnect structure according to an embodiment of the present disclosure.

[0049] Figure 18 Is a vertical sectional view of an exemplary structure after attaching a logic die to a memory die according to an embodiment of the present disclosure.

[0050] Figure 19A Is Figure 18 Magnified vertical sectional view of the region between the bonding interfaces between the logic die and the memory die in an exemplary structure.

[0051] Figure 19B Is along Figure 19A Horizontal sectional view of the horizontal plane B-B'.

[0052] Figure 19C Is along Figure 19A Horizontal sectional view of the horizontal plane C-C'.

[0053] Figure 20A Is an alternative horizontal sectional view of a memory-side bonding pad according to an embodiment of the present disclosure.

[0054] Figure 20B Is an alternative horizontal sectional view of a logic-side bonding pad according to an embodiment of the present disclosure. Detailed Description

[0055] As discussed above, embodiments of the present disclosure relate to three-dimensional memory devices including layer contact via structures located in a memory array region and methods of forming the same, and various aspects of the three-dimensional memory devices are now described in detail.

[0056] The drawings are not drawn to scale. In the case of illustrating a single instance of an element, multiple instances of the element may be replicated unless otherwise explicitly described or clearly indicated that no replication of the element exists. Ordinal numbers such as "first", "second", and "third" are used only to identify similar elements, and different ordinal numbers may be employed across the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0057] Like reference numerals denote like or similar elements. Unless otherwise specified, elements having the same reference numeral are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between the elements providing an edge or surface shared by the elements. If two or more elements do not directly contact each other or one another, the two elements are "separated" from each other or "separated" from one another. As used herein, a first element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, a first element is "directly" located on a second element if there is physical contact between the surface of the first element and the surface of the second element. As used herein, a first element is "electrically connected to" a second element if there is an electrical path composed of at least one conductive material between the first element and the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure in which the shape or composition of at least one component is subsequently modified.

[0058] As used herein, a "layer" refers to a portion of material including a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a range less than the range of the underlying or overlying structure. Further, the layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of a first continuous structure. For example, the layer may be located between the top and bottom surfaces of a first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below it.

[0059] As used herein, if a second surface overlies or underlies a first surface and there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface, the first surface and the second surface are "vertically coincident" with each other. A substantially vertical plane is a plane that linearly extends along a direction that deviates from the vertical direction by an angle less than 5 degrees. The vertical plane or the substantially vertical plane is straight along the vertical direction or the substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0060] As used herein, "memory level" or "memory array level" refers to the level corresponding to the general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) that includes the top surface of an array of memory elements and a second horizontal plane that includes the bottom surface of the array of memory elements. As used herein, a "through-stack" element refers to an element that vertically extends through the memory level.

[0061] As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0x10 -5 S / m to 1.0x10 5 S / m. As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0x10 -5 S / m to 1.0 S / m in the absence of electrical dopants, and is capable of producing a doped material having a conductivity in the range of 1.0 S / m to 1.0x10 7 S / m when appropriately doped with electrical dopants. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to a material having a conductivity greater than 1.0x10 5 S / m. As used herein, "insulating material" or "dielectric material" refers to a material having a conductivity less than 1.0x10 -5 S / m. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with electrical dopants at a high enough atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., to provide a conductivity greater than 1.0x10 5 S / m. A "doped semiconductor material" can be a heavily doped semiconductor material or can include a semiconductor material having a conductivity in the range of 1.0x10 -5 S / m to 1.0x10 7A semiconductor material with an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) at a concentration with a conductivity within the range of S / m. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semi-conductive or conductive and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semi-conductive or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that contains at least one metallic element. All conductivity measurements are performed under standard conditions.

[0062] Generally speaking, a semiconductor package (or "package") refers to a single semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or "chip") or multiple semiconductor chips that are fully bonded, for example, through flip-chip bonding or another chip-to-chip bonding. A package or a chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Generally, a package or a chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operations can be executed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be executed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), and the multiple memory blocks are the smallest units that can be erased in a single erase operation. Each memory block contains multiple pages, and the multiple pages are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0063] Reference Figure 1 , an exemplary structure according to an embodiment of the present disclosure includes a substrate 8. The substrate 8 can be a carrier substrate that is subsequently removed. The substrate 8 can include a semiconductor material (e.g., a silicon wafer), an insulating material, a conductive material, or a combination thereof. The substrate 8 includes a material that provides structural support for the subsequent material portions formed thereon. The substrate 8 includes a substrate material layer 9 at least in its upper portion. In one embodiment, the substrate material layer 9 can be a semiconductor material layer, such as a silicon layer in a silicon wafer or a doped well. In another embodiment, the substrate material layer 9 can be an insulating layer, such as silicon oxide. Optionally, a lower metal interconnect structure 480 can be located below the insulating substrate material layer 9 or can be embedded in the insulating substrate material layer 9. The exemplary structure includes a memory array region 100 where a three-dimensional memory array is subsequently formed.

[0064] An alternating stack of the insulating layer 32 and the sacrificial material layer 42 may be formed over the substrate 8. The alternating stack of the insulating layer 32 and the sacrificial material layer 42 is a vertical alternating sequence of the insulating layer 32 and the sacrificial material layer 42 that alternates along the vertical direction. Each insulating layer 32 may comprise an insulating material, and each sacrificial material layer 42 may comprise a sacrificial material. As used herein, a "sacrificial material" refers to a material that is removed during a subsequent processing step.

[0065] As used herein, an alternating stack of a first element and a second element refers to a structure in which instances of the first element and instances of the second element alternate. Each instance of the first element that is not an end element in the alternating plurality of elements is adjacent to two instances of the second element on both sides, and each instance of the second element that is not an end element in the alternating plurality of elements is adjacent to two instances of the first element at both ends. The first elements may have the same thickness or may have different thicknesses. The second elements may have the same thickness or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, instances of the first element and instances of the second element may form a unit that repeats periodically within the alternating plurality of elements.

[0066] Insulating materials that may be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectrics (e.g., alumina, hafnium oxide, etc.) and their silicates, dielectric metal nitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

[0067] The sacrificial material of the sacrificial material layer 42 includes a material that can be selectively removed relative to the material of the insulating layer 32. As used herein, if a removal process removes a first material at a rate that is at least twice the rate of removal of a second material, then the removal of the first material is "selective" relative to the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0068] The sacrificial material layer 42 may comprise a dielectric material, a semiconductor material, or a conductive material. The material of the sacrificial material layer 42 may subsequently be replaced with conductive electrodes that can be used, for example, as control gate electrodes of a vertical NAND device. In one embodiment, the sacrificial material layer 42 may be a material layer comprising silicon nitride.

[0069] In one embodiment, the insulating layer 32 may comprise silicon oxide, and the sacrificial material layer may comprise a silicon nitride sacrificial material layer. The insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as the precursor material for the CVD process. The second material of the sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0070] The thicknesses of the insulating layer 32 and the sacrificial material layer 42 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be employed for each insulating layer 32 and for each sacrificial material layer 42. The number of repetitions of the insulating layer 32 and sacrificial material layer 42 pairs may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but larger numbers of repetitions may also be employed. In one embodiment, each sacrificial material layer 42 in the vertical alternating sequence (32, 42) may have a uniform thickness that is substantially constant within each respective sacrificial material layer 42. The bottommost layer among the insulating layers 32 is referred to herein as the bottom insulating layer 32B. The topmost layer among the insulating layers 32 is referred to herein as the top insulating layer 32T.

[0071] Reference Figure 2A and Figure 2B , a lithography material stack (not shown), at least including a photoresist layer, may be formed over the top insulating layer 32T and may be patterned lithographically to form an opening therein. As Figure 2BAs shown, the pattern in the lithographic material stack includes a memory - opening - free area (MOFA) without openings therein. The pattern in the lithographic material stack can be transferred through the alternating stack (32, 42) by at least one anisotropic etching using the patterned lithographic material stack as an etch mask. The portions of the underlying patterned lithographic material stack that open to etch the alternating stack (32, 42) are etched to form a memory opening 49 and a support opening 19. As used herein, a "memory opening" refers to a structure in which a memory element such as a memory stack structure is subsequently formed. As used herein, a "support opening" refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. In one embodiment, the diameter of the support opening 19 can be greater than the diameter of the memory opening 49. In one embodiment, the support openings 19 are arranged in a hexagonal close - packed layout in each memory - opening - free area MOFA (e.g., where the peripheral support openings 19 are at the vertices of a hexagon around a middle support opening at the center of a hypothetical hexagon). In other embodiments, the support openings 19 can have different layouts. In one embodiment, each memory - opening - free area MOFA can be laterally surrounded by a group of support openings 19. In one embodiment, there are no memory openings 49 in the memory - opening - free area MOFA and it can be arranged as a two - dimensional array. In one embodiment, the array can include multiple rows of memory - opening - free areas MOFA. In one embodiment, each row of memory - opening - free areas MOFA can include multiple memory - opening - free areas MOFA arranged along a first horizontal direction (e.g., the word - line direction) hd1. However, in other embodiments, the memory - opening - free areas MOFA are not arranged in rows.

[0072] The chemistry of the anisotropic etching process used to etch through the materials of the alternating stack (32, 42) can be alternated to optimize the etching of the first and second materials in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive - ion etchings. The sidewalls of the memory opening 49 and the support opening 19 can be substantially vertical or can be tapered. The patterned lithographic material stack can then be removed, for example, by ashing.

[0073] The memory openings 49 and the support openings 19 may extend from the top surface of the alternating stack (32, 42) to at least a horizontal plane including the topmost surface of the substrate material layer 9. In one embodiment, after the top surface of the substrate material layer 9 is physically exposed at the bottom of each memory opening 49 and each support opening 19, an over-etch into the substrate material layer 9 may optionally be performed. The over-etch may be performed before or after removing the photoresist stack. In other words, the recessed surface of the substrate material layer 9 may be vertically offset from the non-recessed top surface of the substrate material layer 9 by a recess depth. The recess depth may be, for example, in the range of 1 nm to 50 nm, although smaller and larger recess depths may also be employed. The over-etch is optional and may be omitted. If the over-etch is not performed, the bottom surfaces of the memory openings 49 and the support openings 19 may be coplanar with the topmost surface of the substrate material layer 9. Each of the memory openings 49 and the support openings 19 may include one (or more) sidewalls extending substantially perpendicular to the topmost surface of the substrate.

[0074] Reference Figure 3 , in one embodiment, a sacrificial fill material may be deposited in the memory openings 49 and the support openings 19. The sacrificial fill material may be any material that is selectively removable relative to the materials of the insulating layer 32, the sacrificial material layer 42, and the substrate material layer 9. For example, the sacrificial fill material may include a carbon-based material such as amorphous carbon or diamond-like carbon, a semiconductor material such as a silicon-germanium alloy, polysilicon, or amorphous silicon, or a dielectric material such as borosilicate glass or organosilicate glass. Optionally, a thin etch stop liner (not shown) may be employed to facilitate subsequent selective removal of the sacrificial fill material. The excess portion of the sacrificial fill material may be removed from above a horizontal plane including the top surface of the topmost insulating layer 32T. Each remaining portion of the sacrificial fill material filling the memory opening 49 constitutes a sacrificial memory opening fill structure 47. Each remaining portion of the sacrificial fill material filling the support opening 19 constitutes a sacrificial support opening fill structure (not shown).

[0075] A photoresist layer (not shown) may be applied over the exemplary structure and may be patterned lithographically to cover the sacrificial memory opening fill structure 47 and not cover the sacrificial support opening fill structure. The sacrificial support opening fill structure may be removed by removing the sacrificial fill material in the areas not covered by the photoresist layer. The sacrificial fill material may be removed, for example, by ashing or by performing an etching process such as a wet etching process. A cavity is formed in the support opening 19. The photoresist layer may be removed, for example, by ashing.

[0076] Reference Figure 4, A dielectric fill material such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass can be deposited in the support opening 19 using a conformal deposition process such as chemical vapor deposition. Portions of the uppermost insulating layer 32T overlying the dielectric fill material can be removed, for example, by chemical mechanical polishing or by an etchback process such as a wet etch process using dilute hydrofluoric acid. The remaining portions of the dielectric fill material that fill the support opening 19 include support pillar structures 20, which are dielectric pillar structures that provide structural support to the exemplary structure during subsequent processing steps to remove the sacrificial material layer 42. In one embodiment, each memoryless opening region in the memoryless opening region MOFA can be laterally surrounded by a corresponding set of support pillar structures 20.

[0077] Thus, in one embodiment, a cluster of support pillar structures 20 extending vertically through the alternating stack (32, 42) can be formed. Each support pillar structure in the support pillar structures 20 comprises a dielectric fill material such as silicon dioxide, and each cluster of support pillar structures 20 within the cluster of support pillar structures 20 laterally surrounds a corresponding memoryless opening region in the memoryless opening region MOFA. The clusters of support pillar structures 20 can be arranged in a hexagonal close-packed layout or in a different layout in each memoryless opening region in the memoryless opening region MOFA.

[0078] Reference Figure 5 , the sacrificial fill material of the sacrificial memory opening fill structure 47 can be selectively removed relative to the materials of the insulating layer 32, the sacrificial material layer 42, the semiconductor material layer 10, and the support pillar structures 20. The sacrificial memory opening fill structure 47 can be removed by ashing or by performing an etch process such as a wet etch process. A cavity is formed in the volume of the memory opening 49 from which the sacrificial memory opening fill structure 47 is removed.

[0079] Figures 6A to 6H is a vertical cross-section of a memory opening during the formation of the memory opening fill structure 58. The same structural changes occur simultaneously in each of the other memory openings 49. In an alternative embodiment, the steps described above with respect to Figure 3 , Figure 4 and Figure 5 can be omitted. In this alternative embodiment, the memory openings 49 and the support openings 19 are filled with the same set of layers during the same processing step. Thus, the memory opening fill structure 58 is formed in the memory openings 49 while the support structures 20 are formed in the support openings 19. In an alternative embodiment, the memory opening fill structure 58 has the same layers and materials as the support structures 20.

[0080] Reference Figure 6A , illustrates Figure 5Memory opening 49 in the exemplary device structure. The memory opening 49 extends through the alternating stack (32, 42) and optionally into the upper portion of the substrate material layer 9. The recess depth of the bottom surface of each memory opening relative to the top surface of the substrate material layer 9 can range from 0 nm to 30 nm, but larger recess depths can also be employed. Optionally, the sacrificial material layer 42 can be partially laterally recessed, for example, by isotropic etching to form lateral grooves (not shown).

[0081] Reference Figure 6B , an optional base channel portion (e.g., an epitaxial base) 11 can be formed, for example, by selective epitaxy at the bottom portion of each memory opening 49 and each support opening 19. Each base channel portion 11 contains single-crystal semiconductor material (e.g., single-crystalline silicon) that is epitaxially aligned with the single-crystal substrate material layer 9. In one embodiment, the base channel portion 11 can be doped with an electrical dopant of the same conductivity type as the substrate material layer 9. In one embodiment, the top surface of each base channel portion 11 can be formed above the horizontal plane including the top surface of at least one bottommost sacrificial material layer 42. In this case, at least one source select gate electrode can be formed subsequently by replacing each sacrificial material layer 42 located below the horizontal plane including the top surface of the base channel portion 11 with a corresponding conductive material layer. The base channel portion 11 can be the portion of the transistor channel that extends between a source region to be subsequently formed in or above the substrate material layer 9 and a drain region to be subsequently formed in the upper portion of the memory opening 49. A memory cavity 49' exists in the unfilled portion of the memory opening 49 located above the base channel portion 11. In one embodiment, the base channel portion 11 can contain single-crystalline silicon. In one embodiment, the base channel portion 11 can have a doping of a first conductivity type that is the same as the conductivity type of the substrate material layer 9 in contact with the base channel portion.

[0082] Reference Figure 6C , a stack of layers including an optional barrier dielectric layer 52, a memory material layer 54, a dielectric material liner 56, and an optional sacrificial capping material layer 601 can be sequentially deposited in the memory opening 49 by corresponding conformal deposition processes.

[0083] The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. In one embodiment, the blocking dielectric layer 52 comprises alumina. In one embodiment, the blocking dielectric layer 52 may include multiple dielectric metal oxide layers having different material compositions. Alternatively or additionally, the blocking dielectric layer 52 may comprise a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may comprise silicon oxide. The thickness of the blocking dielectric layer 52 may be in the range of 3 nm to 20 nm, although smaller or larger thicknesses may also be employed. Alternatively, the blocking dielectric layer 52 may be omitted, and a backside blocking dielectric layer may be formed after forming a backside recess on the surface of the memory film to be subsequently formed.

[0084] Subsequently, a memory material layer 54 may be formed. Generally speaking, the memory material layer 54 may comprise any memory material capable of storing data bits. The data bits may be stored in the form of trapped charge therein, in the form of the resistance state of the material due to a change in the material phase, resistivity, or ferroelectric properties. In one embodiment, the memory material layer 54 may include a charge storage layer. In one embodiment, the memory material layer 54 may be a continuous layer or a patterned discrete portion of a charge trapping material including a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the memory material layer 54 may include a continuous layer or a patterned discrete portion of a conductive material such as doped polysilicon or a metal material, which is patterned into a plurality of electrically isolated portions (e.g., floating gates) by, for example, forming into the sacrificial material layer 42 within the lateral recess. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically coincident sidewalls, and the memory material layer 54 may be formed as a single continuous layer.

[0085] In another embodiment, the sacrificial material layer 42 may be laterally recessed relative to the sidewalls of the insulating layer 32, and a combination of a deposition process and an anisotropic etching process may be employed to form the memory material layer 54 into a plurality of vertically spaced memory material portions. Although the memory material layer 54 is illustrated as a single continuous layer, embodiments in which the memory material layer 54 is replaced by a plurality of vertically spaced discrete memory material portions (which may be charge trapping material portions or electrically isolated conductive material portions) are expressly contemplated herein. The memory material layer 54 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the memory material layer 54 may be in the range of 2 nm to 20 nm, although smaller and larger thicknesses may also be employed.

[0086] The dielectric material liner 56 comprises a dielectric material. In one embodiment, the dielectric material liner 56 may include a tunneling dielectric layer through which charge tunneling can be performed under suitable electrical bias conditions. Depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed, charge tunneling can be performed by hot carrier injection or by charge transfer induced by Fowler-Nordheim tunneling. The tunneling dielectric layer may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal nitrides, dielectric metal silicates, their alloys and / or their combinations. In one embodiment, the tunneling dielectric layer may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer may include a silicon oxide layer substantially free of carbon or a silicon oxynitride layer substantially free of carbon. The thickness of the tunneling dielectric layer may be in the range of 2 nm to 20 nm, but smaller or larger thicknesses may also be employed. Alternatively, a different type of dielectric material layer may be used as the dielectric material liner 56.

[0087] The optional sacrificial capping material layer 601 comprises a sacrificial material that can subsequently be selectively removed relative to the material of the dielectric material liner 56. In one embodiment, the sacrificial capping material layer 601 may comprise a semiconductor material such as amorphous silicon, or may comprise a carbon-based material such as amorphous carbon or diamond-like carbon (DLC). The sacrificial capping material layer 601 may be formed by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD). The thickness of the sacrificial capping material layer 601 may be in the range of 2 nm to 10 nm, but smaller and larger thicknesses may also be employed. A memory cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 601).

[0088] Reference Figure 6D, at least one anisotropic etching process is employed to anisotropically etch, in sequence, an optional sacrificial capping material layer 601, a dielectric material liner 56, a memory material layer 54, and a barrier dielectric layer 52 that overlie the topmost insulating layer 32T. The portions of the sacrificial capping material layer 601, the dielectric material liner 56, the memory material layer 54, and the barrier dielectric layer 52 that are located above the top surface of the topmost insulating layer 32T can be removed by at least one anisotropic etching process. Additionally, the horizontal portions of the sacrificial capping material layer 601, the dielectric material liner 56, the memory material layer 54, and the barrier dielectric layer 52 at the bottom of each memory cavity 49' can be removed to form an opening in their remaining portions. Each of the sacrificial capping material layer 601, the dielectric material liner 56, the memory material layer 54, and the barrier dielectric layer 52 can be etched by a respective anisotropic etching process employing a respective etching chemical composition, and the respective etching chemistry can be the same or different for the various material layers.

[0089] Each remaining portion of the sacrificial capping material layer 601 can have a tubular configuration. The memory material layer 54 can include a charge trapping material, a floating gate material, a ferroelectric material, a resistive memory material (such as a phase change material) that can provide at least two different levels of resistivity, or any other memory material that can store information by a change of state. In one embodiment, each memory material layer 54 can include a vertical stack of charge storage regions that store charge upon programming. In one embodiment, the memory material layer 54 can be a memory material layer in which each portion adjacent to the sacrificial material layer 42 constitutes a charge storage region.

[0090] The surface of the base channel portion 11 (or the surface of the substrate material layer 9 when the base channel portion 11 is not employed) can be physically exposed under the opening by sacrificing the capping material layer 601, the dielectric material liner 56, the memory material layer 54, and the barrier dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' can be vertically recessed such that the recessed semiconductor surface under the memory cavity 49' is vertically offset from the topmost surface of the base channel portion 11 (or from the substrate material layer 9 when the base channel portion 11 is not employed) by a recess distance. The dielectric material liner 56 is located above the memory material layer 54. A set of the barrier dielectric layer 52, the memory material layer 54, and the dielectric material liner 56 in the memory opening 49 constitutes the memory film 50, which includes a plurality of charge storage regions (including portions of the memory material layer 54) insulated from the surrounding materials by the barrier dielectric layer 52 and the dielectric material liner 56. In one embodiment, the sacrificial capping material layer 601, the dielectric material liner 56, the memory material layer 54, and the barrier dielectric layer 52 can have vertically coincident sidewalls. Optionally, the sacrificial capping material layer 601 can be subsequently removed selectively with respect to the material of the dielectric material liner 56. If the sacrificial capping material layer 601 comprises amorphous silicon, a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) can be performed to remove the sacrificial capping material layer 601.

[0091] Reference Figure 6E , the semiconductor channel layer 60L can be directly deposited on the semiconductor surface of the base channel portion 11, or on the substrate material layer 9 when the base channel portion 11 is omitted, and directly deposited on the dielectric material liner 56 (or on the silicon sacrificial capping material layer 601 if it still exists). The semiconductor channel layer 60L comprises a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0092] In one embodiment, the semiconductor channel layer 60L comprises amorphous silicon or polycrystalline silicon. The semiconductor channel layer 60L can be doped with a first conductivity type that is the same as the conductivity type of the substrate material layer 9 and the base channel portion 11. The semiconductor channel layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer 60L can be in the range of 2 nm to 10 nm, although smaller and larger thicknesses can also be employed. The semiconductor channel layer 60L can partially fill the memory cavity 49' in each memory opening, or can completely fill the cavity in each memory opening.

[0093] Reference Figure 6F, in the case where the memory cavity 49' in each memory opening is not completely filled by the semiconductor channel layer 60L, the dielectric core layer 62L can be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer 62L comprises a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer 62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD) or by a self-planarizing deposition process such as spin coating.

[0094] Reference Figure 6G , for example, the horizontal portion of the dielectric core layer 62L can be removed by a recess etching process such that each remaining portion of the dielectric core layer 62L is located within the corresponding memory opening 49 and has a corresponding top surface below the horizontal plane including the top surface of the topmost insulating layer 32T. Each remaining portion of the dielectric core layer 62L constitutes the dielectric core 62.

[0095] Reference Figure 6H , a doped semiconductor material having a second conductivity type can be deposited within each recessed region above the dielectric core 62. The deposited semiconductor material can be doped with a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in the range of 5.0x10 18 / cm 3 to 2.0x10 21 / cm 3 , but smaller or larger dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

[0096] The excess portion of the deposited semiconductor material doped with the second conductivity type and the horizontal portion of the semiconductor channel layer 60L can be removed from above the horizontal plane including the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP) or a recess etching process. Each remaining portion of the doped semiconductor material having the second conductivity type constitutes the drain region 63. Each remaining portion of the semiconductor channel layer 60L (which has a first conductivity type doping) constitutes the vertical semiconductor channel 60. The vertical semiconductor channel 60 is formed directly on the dielectric material liner 56.

[0097] Each adjacent set of blocking dielectric layer 52, memory material layer 54, and dielectric material liner 56 together constitute a memory film 50, which can store charge or polarization macroscopically for a retention time. As used herein, the macroscopic retention time refers to the retention time suitable for the memory device to operate as a permanent memory device, such as a retention time exceeding 24 hours. In some embodiments, at this step, the blocking dielectric layer 52 may not be present in the memory film 50 and may be formed subsequently as a backside blocking dielectric layer after forming the backside recess.

[0098] Each combination of the memory film 50 within the memory opening 49 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a semiconductor channel, a dielectric material liner, a plurality of memory elements embodied as parts of the memory material layer 54, and optionally a blocking dielectric layer 52. The entire set of material portions filling the memory opening 49 is referred to herein as the memory opening fill structure 58. The entire set of material portions filling the support opening 19 constitutes the support pillar structure.

[0099] Generally speaking, a memory opening fill structure 58 can be formed in each memory opening 49. The memory opening fill structure 58 includes an optional blocking dielectric layer 52, a memory material layer 54, an optional dielectric material liner 56, and a vertical semiconductor channel 60. The dielectric material liner 56 can laterally surround the vertical semiconductor channel 60. The memory material layer 54 can laterally surround the dielectric material liner 56.

[0100] In the case where the blocking dielectric layer 52 is present in each memory opening fill structure 58, the blocking dielectric layer 52 can be formed on the sidewalls of the memory opening 49, and a vertical stack of memory elements (which can include parts of the memory material layer 54) can be formed on the blocking dielectric layer 52. In one embodiment, the vertical stack of memory elements includes parts of a charge storage layer (including the memory material layer 54) at the level of the sacrificial material layer 42.

[0101] Reference Figure 7A and Figure 7B , illustrate exemplary structures after forming the memory opening fill structure 58 and the support pillar structure 20 within the memory opening 49 and the support opening 19, respectively. Examples of the memory opening fill structure 58 can be formed in each memory opening 49 of the Figure 5 structure. Examples of the support pillar structure 20 can be formed in Figure 5within each support opening 19 of the structure. Alternatively, an alternative memory stack structure for the memory film 50 and / or for the vertical semiconductor channels 60 including different layer stacks or structures may be used. In one embodiment, adjacent rows of the memory opening free area MOFA may be laterally spaced along a second horizontal direction (e.g., bit line direction) hd2 by at least one row of the memory opening fill structure 58.

[0102] Reference Figure 7C , illustrates a first alternative configuration of an exemplary structure after the processing steps of Figure 7A and Figure 7B . The first alternative configuration may be derived from the exemplary structure illustrated in Figure 7A and 7B by rearranging the memory opening fill structure 58 and the support pillar structure 20 such that adjacent rows of the memory opening free area MOFA are not laterally spaced by any intervening row of the memory opening fill structure 58 along the second horizontal direction hd2. In this case, clusters of the support pillar structure 20 may be arranged such that each cluster of the support pillar structure 20 laterally surrounds at least one memory opening free area MOFA. The clusters of the support pillar structure 20 extend laterally between columns of the memory opening fill structure 58 along the second horizontal direction hd2.

[0103] Reference Figure 7D , illustrates a second alternative configuration of an exemplary structure after the processing steps of Figure 7A and Figure 7B . The second alternative configuration may be derived from the exemplary structure illustrated in Figure 7A and Figure 7B by rearranging the memory opening fill structure 58 and the support pillar structure 20 such that a cluster of the support pillar structure 20 surrounds a row of the memory opening free area MOFA. The clusters of the support pillar structure 20 extend laterally between rows of the memory opening fill structure 58 along the first horizontal direction hd1.

[0104] Reference Figures 8A to 8C, an insulating capping layer 70 may be formed over the alternating stack (32, 42), the memory opening fill structure 58, and the support pillar structure 20. The insulating capping layer 70 comprises an insulating material, such as silicon oxide, and may have a thickness in the range of 20 nm to 300 nm, although smaller and larger thicknesses may also be employed. Subsequently, contact via cavities 89 having different depths may be formed in the memory opening free area MOFA laterally surrounded by respective clusters of the support pillar structure 20. Each of the contact via cavities 89 vertically extends through a respective subset of the layers within the alternating stack (32, 42) and optionally through at least one of the support pillar structures in the support pillar structure 20. Each of the contact via cavities 89 has a respective bottom surface that includes a section of the respective sacrificial material layer 42. The respective bottom surfaces of at least some of the contact via cavities 89 may also include at least a portion of the top surface of the underlying support pillar structure 20.

[0105] Generally, any suitable method may be used to form the contact via cavities 89. One exemplary method of forming the contact via cavities 89 is described below. In this exemplary method, a patterned hard mask layer 33 may be formed over the alternating stack (32, 42). The patterned hard mask layer 33 may comprise any etch mask material that is resistant to a subsequent ashing process used to remove a patterned photoresist material layer. The patterned hard mask layer 33 may comprise a dielectric metal oxide material, a metal material, or a semiconductor material, such as amorphous silicon. The patterned hard mask layer 33 may be formed by depositing a blanket (unpatterned) hard mask material layer; forming a high-fidelity photoresist material layer, such as a deep ultraviolet (DUV) photoresist material layer, over the blanket hard mask material layer; lithographically patterning the photoresist material layer to form an opening in the area where the contact via cavities 89 are to be subsequently formed; and transferring the pattern in the patterned photoresist layer through the blanket hard mask material layer by performing an anisotropic etching process. An array of openings is formed through the patterned hard mask layer 33. Subsequently, the high-fidelity photoresist material may be removed.

[0106] Subsequently, a series of block-level photoresist layers such as mid-ultraviolet (MUV) photoresist layers in combination with a series of anisotropic etching processes can be employed to sequentially cover corresponding subsets of the openings in the patterned hard mask layer 33 and extend the pattern of the openings in the patterned hard mask layer 33 through a corresponding number of stacks of the insulating layer 32 and the sacrificial material layer 42. For example, approximately half of all the openings through the patterned hard mask layer 33 can be covered by a first block-level photoresist layer, and one insulating layer 32 and one sacrificial material layer 42 can be etched by performing an anisotropic etching process under the openings through the unmasked portion of the sacrificial material layer. Any unmasked portion of the support pillar structure 20 can be co-etched by selecting the etching chemistries of the various etching steps of the anisotropic etching process such that the total etching rate of the material of the support pillar structure 20 matches the total etching rate of the combination of the insulating layer 32 and the sacrificial material layer 42. Subsequently, the first block-level photoresist layer can be removed. Approximately half of all the openings through the patterned hard mask layer 33 can be covered by a second block-level photoresist layer. Approximately half of the unmasked openings are among the openings previously covered by the first block-level photoresist layer, and the remaining unmasked openings are among the openings previously masked by the first block-level photoresist layer. Two pairs of the insulating layer 32 and the sacrificial material layer 42 (i.e., two insulating layers 32 and two sacrificial material layers 42) can be etched by performing an anisotropic etching process under the openings through the unmasked portion of the sacrificial material layer. Any unmasked portion of the support pillar structure 20 can be co-etched by selecting the etching chemistries of the various etching steps of the anisotropic etching process such that the total etching rate of the material of the support pillar structure 20 matches the total etching rate of the combination of the insulating layer 32 and the sacrificial material layer 42. Subsequently, the second block-level photoresist layer can be removed. The above scheme can be repeated until the Nth block-level photoresist layer and the Nth anisotropic etching process etch 2(N - 1) pairs of the insulating layer 32 and the sacrificial material layer 42. A final anisotropic etching process can be performed in the absence of any block-level photoresist layer, for example, to etch through the unmasked portions of a corresponding set of two insulating layers 32 and the sacrificial material layer 42, which sacrificial material layer underlies any opening through the patterned hard mask layer 33.

[0107] Contact via cavities 89 having 2N different depths can be formed in the memory opening-free area MOFA. In an illustrative example, if N is 8, the total number of the sacrificial material layers 42 can be 28, i.e., 256. Subsequently, the patterned hard mask layer 33 can be removed, for example, by performing an etching process that selectively removes the material of the patterned hard mask layer 33 with respect to the materials of the alternating stack (32, 42).

[0108] Reference Figures 9A to 9C, an insulating material such as silicon oxide can be conformally deposited to form an insulating liner layer 81L. The thickness of the insulating liner layer 81L can be in the range of 5 nm to 100 nm, although smaller or larger thicknesses can also be employed.

[0109] A sacrificial fill material can be deposited in the voids within the contact via cavity 89. The sacrificial fill material includes a material that can subsequently be selectively removed relative to the materials of the insulating liner layer 81L and the insulating capping layer 70. For example, the sacrificial fill material can include a carbon-based material such as amorphous carbon or diamond-like carbon, a semiconductor material such as amorphous silicon, polycrystalline silicon, or a silicon-germanium alloy, or a dielectric material such as borosilicate glass or organosilicate glass. An excess portion of the sacrificial fill material can be removed from above a horizontal plane including the top surface of the insulating liner layer 81L. The planarization process can include a recess etching process or a chemical mechanical polishing process. Each remaining portion of the sacrificial fill material constitutes a sacrificial via fill material portion 82.

[0110] Generally, contact via cavities 89 having different depths can be formed in a region of an array of the memoryless opening area MOFA in a plan view, and the insulating liner layer 81L and the sacrificial via fill material can be formed in the via cavities 89. A portion of the sacrificial via fill material can be removed from above a horizontal plane including the topmost surface of the insulating liner layer 81L. The remaining portion of the sacrificial via fill material constitutes the sacrificial via fill material portion 82. An in-process via structure including the sacrificial via fill material portion 82 can be formed in a region of an array of the MOFA memoryless opening area in a plan view. Each in-process via structure includes a corresponding vertically extending cylindrical portion of the insulating liner layer 81L and a corresponding sacrificial via fill material portion 82. Each in-process via structure in the in-process via structures vertically extends through a corresponding subset of the layers within the alternating stack (32, 42).

[0111] A sacrificial capping layer 83 can be deposited over the insulating liner layer 81L and the sacrificial via fill material portion 82. The sacrificial capping layer 83 includes a material that can subsequently be removed. For example, the sacrificial capping layer 83 can include a dielectric material such as silicon oxide or a semiconductor material such as amorphous silicon. The thickness of the sacrificial capping layer 83 can be in the range of 5 nm to 100 nm, although smaller and larger thicknesses can also be employed.

[0112] A photoresist layer (not shown) may be applied over the sacrificial capping layer 83 and patterned lithographically to form elongated openings in the regions between clusters of the memory opening fill structures 58, which may be slit-shaped regions that do not contain any memory opening fill structures 58, any support pillar structures 20, and any sacrificial via fill material portions 82. Anisotropic etching may be employed to transfer the pattern in the photoresist layer through the sacrificial capping layer 83, the insulating liner layer 81L, and the alternating stack (32, 42) to form the lateral isolation trenches 79. The lateral isolation trenches 79 extend vertically from the top surface of the sacrificial capping layer 83 to the top surface of the substrate 8. The lateral isolation trenches 79 extend laterally between adjacent memory blocks of the memory opening fill structures 58 along a first horizontal direction hd1.

[0113] In one embodiment, the lateral isolation trenches 79 may extend laterally along a first horizontal direction (e.g., the word line direction) hd1 and may be laterally spaced from each other along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1, which may be the bit line direction. The memory opening fill structures 58 may be arranged in rows extending along the first horizontal direction hd1. Multiple rows of memory opening fill structures 58 may be located between each adjacent pair of lateral isolation trenches 79 in respective memory blocks. Thus, the lateral isolation trenches 79 separate adjacent memory blocks along the second horizontal direction hd2. Generally speaking, the lateral isolation trenches 79 extending laterally along the first horizontal direction hd1 may be formed through the vertical alternating sequence of the insulating layer 32 and the sacrificial material layer 42. The lateral isolation trenches 79 are laterally spaced along the second horizontal direction hd2.

[0114] For each group of sacrificial via fill material portions 82 arranged along the first horizontal direction hd1, a first lateral isolation trench 79 and a second lateral isolation trench 79 may be formed that extend laterally along the first horizontal direction hd1 and are laterally spaced along the second horizontal direction hd2 through the alternating stack (32, 42), such that the group of sacrificial via fill material portions 82 is located between the first lateral isolation trench 79 and the second lateral isolation trench 79.

[0115] A dopant of a second conductivity type may be implanted into the surface portion of the semiconductor material layer 9 that is physically exposed under the lateral isolation trenches 79. A source region 61 doped with the second conductivity type may be formed under the lateral isolation trenches 79. The photoresist layer may be removed, for example, by ashing.

[0116] Reference Figures 10A to 10C, an etchant that selectively etches the material of the sacrificial material layer 42 with respect to the material of the insulating layer 32, the outermost layer of the storage film 50, and the material of the insulating liner layer 81L can be introduced into the lateral isolation trenches 79, for example, by using an isotropic etching process. For example, the sacrificial material layer 42 may include silicon nitride, and the materials of the insulating layer 32, the insulating liner layer 81L, and the outermost layer of the storage film 50 may include silicon oxide. The backside recesses 43 are formed in the volume from which the sacrificial material layer 42 is removed. For each set of sacrificial via fill material portions 82 located between the first lateral isolation trench 79 and the second lateral isolation trench 79 in the same memory block, the sacrificial material layer 42 between the first lateral isolation trench 79 and the second lateral isolation trench 79 can be removed by providing an isotropic etchant to the first lateral isolation trench 79 and the second lateral isolation trench 79.

[0117] The isotropic etching process can be a wet etching process using a wet etching solution, or can be a vapor phase (dry) etching process in which the etchant is introduced into the lateral isolation trenches 79 in a gaseous phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process in which an exemplary structure is immersed in a wet etching bath containing phosphoric acid, and the wet etching bath selectively etches silicon nitride with respect to silicon oxide, silicon, and various other materials used in the art.

[0118] Each of the backside recesses 43 can be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses 43 can be greater than the height of the corresponding backside recess 43. Each of the backside recesses 43 can extend laterally substantially parallel to the top surface of the substrate 8. The backside recesses 43 can be vertically defined by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each of the backside recesses 43 can always have a uniform height. A plurality of backside recesses 43 are formed at each level of the sacrificial material layer 42. The plurality of backside recesses 43 are laterally spaced apart from each other by the lateral isolation trenches 79.

[0119] Reference Figures 11A to 11D, Optionally, a backside barrier dielectric layer 44 may be optionally deposited in the backside recess 43 and the lateral isolation trenches 79 and over the sacrificial capping layer 83. The backside barrier dielectric layer 44 (if employed) comprises a dielectric metal oxide such as alumina, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one lanthanide element, a combination of aluminum, at least one transition metal element, and / or at least one lanthanide element. Alternatively or additionally, the backside barrier dielectric layer 44 may include a silicon oxide layer. The backside barrier dielectric layer 44 may be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The backside barrier dielectric layer 44 may be formed on the sidewalls of the lateral isolation trenches 79 and the insulating liner layer 81L, the horizontal surfaces and sidewalls of the insulating layer 32, and the portions of the sidewall surfaces of the memory opening fill structure 58 that are physically exposed to the backside recess 43. A backside cavity exists within the portions of each lateral isolation trench 79 that are not filled with the backside barrier dielectric layer 44.

[0120] A metal barrier liner 46A may be deposited in the backside recess 43, in the peripheral portions of the lateral isolation trenches 79, and over the sacrificial capping layer 83. The metal barrier liner 46A comprises a conductive metal material that may be used as a diffusion barrier layer and / or an adhesion promoting layer for subsequent deposition of a metal fill material. The metal barrier liner 46A may comprise a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may comprise a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier liner 46A may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier liner 46A may be in the range of 2 nm to 8 nm, such as 3 nm to 6 nm, although smaller and larger thicknesses may also be employed. In one embodiment, the metal barrier liner 46A may consist essentially of a conductive metal nitride such as TiN.

[0121] A metal fill material is deposited in a plurality of backside recesses 43, on sidewalls of at least one lateral isolation trench 79, and over a top surface of a sacrificial capping layer 83 to form a metal fill material portion 46B. The metal fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material portion 46B can consist essentially of at least one elemental metal. The at least one elemental metal of the metal fill material portion 46B can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material portion 46B can consist essentially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas such as WF6 can be used to deposit the metal fill material portion 46B. In one embodiment, the metal fill material portion 46B can be a tungsten layer containing residual levels of fluorine atoms as impurities. The metal fill material portion 46B is spaced apart from the insulating layer 32 and the memory opening fill structure 58 by a metal barrier liner 46A, which is a metal barrier layer that blocks diffusion of fluorine atoms therethrough.

[0122] Generally, for each set of sacrificial via fill material portions 82 located between a first lateral isolation trench 79 and a second lateral isolation trench 79 in the same memory block, a conductive layer 46 is formed by providing a precursor gas of a conductive material in the conductive layer 46 into the first lateral isolation trench 79 and the second lateral isolation trench 79.

[0123] An etch-back process can be performed to remove portions of the metal fill material portion 46B and the metal barrier liner 46A from inside the lateral isolation trench 79 and from above the sacrificial capping layer 83. The etch-back process can include an isotropic etching process and / or an anisotropic etching process. Each combination of the remaining portions of the metal barrier liner 46A and the remaining portions of the metal fill material portion 46B retained in the respective backside recesses 43 constitutes a conductive layer 46. A backside blocking dielectric layer may or may not be retained in the lateral isolation trench 79.

[0124] Each conductive layer 46 includes a portion of the metal barrier liner 46A and a portion of the metal fill material portion 46B located between a pair of vertically adjacent dielectric material layers such as a pair of insulating layers 32. Each sacrificial material layer 42 can be replaced with a conductive layer 46. Generally, an alternating stack (32, 46) of the insulating layer 32 and the conductive layer 46 can be formed over the substrate 8.

[0125] When forming the conductive layer 46, an alternating stack (32, 46) of the insulating layer 32 and the conductive layer 46 is formed within each memory block located between a pair of adjacent lateral isolation trenches 79. In one embodiment, the lateral extent of each conductive layer 46 may be the same as the lateral spacing between a pair of adjacent lateral isolation trenches 79 that extends throughout each conductive layer in the conductive layer 46.

[0126] Reference Figures 12A to 1 12C, an insulating material layer may be formed in the lateral isolation trenches 79 and over the sacrificial capping layer 83 by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, dielectric metal oxide, organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer may comprise silicon oxide. The insulating material layer may be formed, for example, by low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer may be in the range of 1.5 nm to 60 nm, although smaller or larger thicknesses may also be employed.

[0127] An anisotropic etch is performed to remove the horizontal portions of the insulating material layer from above the sacrificial capping layer 83 and from the bottoms of each of the lateral isolation trenches 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74, which may have a generally tubular configuration. A back cavity exists within the volume surrounded by each insulating spacer 74.

[0128] A back contact via structure 76 may be formed within each back cavity. Each back contact via structure 76 may fill the corresponding cavity. Each contact via structure 76 may be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the back cavity) of the lateral isolation trench 79. For example, the at least one conductive material may include a conductive liner and a conductive fill material portion. The conductive liner may include a conductive metal liner such as TiN, TaN, WN, TiC, TaC, WC, their alloys, or a stack thereof. The thickness of the conductive liner may be in the range of 3 nm to 30 nm, although smaller or larger thicknesses may also be employed. The conductive fill material portion may include a metal or a metal alloy. For example, the conductive fill material portion may include W, Cu, Al, Co, Ru, Ni, their alloys, or a stack thereof.

[0129] An insulating liner layer 81L can be employed as a stop layer to planarize at least one conductive material. If a chemical mechanical planarization (CMP) process is used, the horizontal extension of the insulating liner layer 81L can be used as the CMP stop layer. The horizontal extension of at least one conductive material and the sacrificial capping layer 83 can be removed from above a horizontal plane including the top surface of the horizontal extension of the insulating liner layer 81L. Each remaining continuous portion of at least one conductive material in the lateral isolation trench 79 forms a back contact via structure 76. Each adjacent combination of the insulating spacer 74 and the back contact via structure 76 forms a lateral isolation trench filling structure (74, 76). The top surface of the sacrificial via filling material portion 82 can be physically exposed after the planarization process.

[0130] The alternating stack of the insulating layer 32 and the conductive layer 46 can be contacted by a first lateral isolation trench filling structure (74, 76) and a second lateral isolation trench filling structure (74, 76). The first lateral isolation trench filling structure (74, 76) can have a first dielectric sidewall that laterally extends along a first horizontal direction hd1 and can contact each of the insulating layer 32 and the conductive layer 46 within the alternating stack (32, 46). The second lateral isolation trench filling structure (74, 76) can be laterally spaced from the first lateral isolation trench filling structure (74, 76) along a second horizontal direction hd2, can have a second dielectric sidewall that laterally extends along the first horizontal direction hd1, and can contact each of the insulating layer 32 and the conductive layer 46 within the alternating stack (32, 46).

[0131] Reference Figures 13A to 13B , the sacrificial via filling material portion 82 can be selectively removed relative to the material of the insulating liner layer 81L. For example, a selective etching process or an ashing process (if the sacrificial via filling material portion 82 contains a carbon material) can be used to remove the sacrificial via filling material portion 82. If a selective etching process is used, the selective etching process can include an isotropic etching process or an anisotropic etching process. A via cavity 87 is formed in each volume from which the sacrificial via filling material portion 82 is removed.

[0132] Subsequently, an anisotropic etching process may be performed to remove the overlying insulating cap layer 70 of the insulating liner layer 81L or the horizontal extension portions underlying the corresponding via cavities 87. Each remaining tubular portion of the insulating liner layer 81L constitutes an insulating spacer 81, which is also referred to as a tubular insulating spacer 81 or an insulating via spacer 81. If a backside barrier dielectric layer 44 is employed, the anisotropic etching process may remove the physically exposed portions of the barrier dielectric layer 44 below each via cavity 87, such that the surface of the conductive layer 46 is physically exposed below the via cavity 87. Each via cavity 87 may be laterally surrounded by a corresponding insulating spacer 81. Each conductive layer in the conductive layer 46 may include at least one physically exposed surface segment (e.g., a top surface segment) underlying the corresponding via cavity 87.

[0133] Reference Figures 14A to 14C , at least one conductive material may be deposited in the via cavity 87. The at least one conductive material may include a metal barrier material and a metal fill material. The metal barrier material may include metal nitride materials such as TiN, TaN, and / or WN and / or metal carbide materials such as TiC, TaC, and / or WC. The metal fill material may include W, Ti, Ta, Ru, Co, Mo, Cu, etc. The at least one conductive material may be deposited by chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, or a combination thereof. The excess portion of the at least one conductive material may be removed from above the horizontal plane including the top surface of the insulating cap layer 70 by performing a planarization process that may employ a chemical mechanical polishing (CMP) process or a recess etching process. Each remaining portion of the at least one conductive material filling the corresponding via cavity 87 constitutes a layer contact via structure 84 that contacts the top surface of the corresponding conductive layer 46. Each layer contact via structure 84 may be laterally surrounded by a corresponding insulating spacer 81. Each combination of the layer contact via structure 84 and the corresponding insulating spacer 81 includes a layer contact assembly (81, 84).

[0134] Accordingly, the sacrificial via fill material portion 82 may be replaced with the layer contact via structure 84 to form the layer contact assembly (81, 84). Each layer contact assembly in the layer contact assembly (81, 84) includes a corresponding layer contact via structure 84 that contacts the corresponding conductive layer in the conductive layer 46, and also includes a corresponding insulating spacer 81 that laterally surrounds the corresponding layer contact via structure 84. An array of the layer contact assemblies (81, 84) may be formed in a region of the array of the memoryless opening area MOFA in a plan view. The array of the layer contact assemblies (81, 84) contains an array of the layer contact via structures 84.

[0135] In a device having Figure 14BIn one embodiment of the configuration shown, the array of layer contact via structures 84 includes at least one row of layer contact via structures 84 that are arranged along a first horizontal direction hd1 and are laterally spaced from each other by a sub-array of memory opening fill structures 58. As used herein, a "sub-array" is a part of an array. Thus, each sub-array in the sub-array includes a corresponding subset of the array of memory opening fill structures 58.

[0136] In Figure 14C one embodiment shown, the array of layer contact components (81, 84) includes multiple rows of layer contact components (81, 84). In one embodiment, each row of layer contact components (81, 84) in the multiple rows of layer contact components (81, 84) includes a corresponding plurality of layer contact components (81, 84) that are arranged along a first horizontal direction hd1. The multiple rows of layer contact components (81, 84) are laterally spaced from each other along a second horizontal direction hd2. In one embodiment, the array of memory opening fill structures 58 includes at least one row of memory opening fill structures 58 that extends laterally along the first horizontal direction hd1 and is located between a corresponding pair of adjacent rows of layer contact components (81, 84) within the multiple rows of layer contact components (81, 84).

[0137] In Figure 14E an alternative embodiment of a second alternative configuration of an exemplary structure having a layout of memory opening free areas MOFA based on Figure 7D the array of layer contact components (81, 84) includes a single row of layer contact components (81, 84) per memory block.

[0138] In one embodiment, an alternating stack (32, 46) in each memory block includes a pair of longitudinal sidewalls that extend laterally along the first horizontal direction hd1 between laterally separating trenches 79 and extend vertically from the bottommost layer to the topmost layer of the alternating stack (32, 46). The array of memory opening free areas MOFA is laterally spaced from a longitudinal sidewall of the pair of longitudinal sidewalls by at least one row of memory opening fill structures 58 that is a subset of the array of memory opening fill structures 58 and extends laterally along the first horizontal direction hd1.

[0139] In Figure 14D an alternative embodiment of a first alternative configuration of an exemplary structure having a layout of memory opening free areas MOFA based on Figure 7C the array of layer contact components (81, 84) includes multiple columns of layer contact components (81, 84) arranged along a second horizontal direction hd2 in each memory block.

[0140] A photoresist layer may be applied over the insulating capping layer 70 and may be patterned lithographically to form an elongated opening between a corresponding pair of adjacent memory opening fill structures 58. An anisotropic etching process may be performed to transfer the pattern of the elongated opening in the photoresist layer through portions of the insulating capping layer 70, a subset of the conductive layers 46 (including the topmost conductive layer 46 within each alternating stack (32, 46)), and optionally through a subset of the layer contact via structures 84. Generally, the total number of conductive layers 46 cut beneath the corresponding openings in the photoresist layer may be the same as the total number of drain select levels in which portions of the conductive layers 46 are used as drain select level electrodes. The elongated trenches formed by the anisotropic etching process are referred to herein as drain select level isolation trenches. The photoresist layer may then be subsequently removed, e.g., by ashing.

[0141] A dielectric fill material such as silicon oxide may be deposited in the drain select level isolation trenches. A recess etching process may be performed to remove the horizontal extent of the dielectric fill material above the insulating capping layer 70. Each portion of the dielectric fill material filling a corresponding drain select level isolation trench constitutes a drain select level dielectric isolation structure 72. Generally, the drain select level dielectric isolation structures 72 laterally extend along a first horizontal direction hd1 with a lateral extent greater than the maximum lateral extent of the array of memory opening fill structures 58 along the first horizontal direction hd1. Thus, the lateral extent of the drain select level dielectric isolation structures 72 along the first horizontal direction hd1 may be greater than the maximum lateral extent of the array of layer contact via structures 84 within the alternating stack (32, 46) of the insulating layer 32 and the conductive layer 46. The drain select level dielectric isolation structures 72 vertically extend through at least one conductive layer 46 within the alternating stack (32, 46), including the topmost conductive layer 46 (e.g., through the drain side select gate electrode).

[0142] In one embodiment, the array of layer contact assemblies (81, 84) includes a row of layer contact assemblies (81, 84) arranged along the first horizontal direction hd1; and the row of layer contact assemblies (81, 84) is laterally spaced apart from at least one row of memory opening fill structures 58 within the array of memory opening fill structures 58 by one of the drain select level dielectric isolation structures 72 in the drain select level dielectric isolation structures 72. In one embodiment, the array of layer contact assemblies (81, 84) includes a row of layer contact assemblies (81, 84) arranged along the first horizontal direction hd1; and one of the drain select level dielectric isolation structures 72 in the drain select level dielectric isolation structures 72 extends through an upper portion of each layer contact assembly within the row of layer contact assemblies (81, 84).

[0143] In one embodiment, a cluster of support pillar structures 20 extends vertically through an alternating stack (32, 46). Each support pillar structure in the support pillar structures 20 comprises a dielectric fill material; and each cluster of support pillar structures 20 within the cluster of support pillar structures 20 laterally surrounds a corresponding layer contact component within an array of layer contact components (81, 84) and within a corresponding memoryless opening region within a memoryless opening region MOFA.

[0144] Reference Figure 14D , illustrates a top-down view of a first alternative configuration of an exemplary structure after the processing steps of Figures 14A to 14C . In the first alternative configuration, the array of layer contact via structures 84 comprises at least one column of layer contact via structures 84 that are arranged along a second horizontal direction hd2 and are laterally spaced apart from each other by sub-arrays of memory opening fill structures 58, each of these sub-arrays comprising a corresponding subset of the array of memory opening fill structures 58. The array of layer contact components (81, 84) comprises multiple columns of layer contact components (81, 84). Each row of layer contact components (81, 84) within the multiple rows of layer contact components (81, 84) comprises a corresponding plurality of layer contact components (81, 84) that are arranged along the second horizontal direction hd2. The multiple rows of layer contact components (81, 84) are laterally spaced apart from each other along a first horizontal direction hd1.

[0145] In one embodiment, the alternating stack (32, 46) comprises a pair of longitudinal sidewalls that extend laterally along a first horizontal direction hd1 and extend vertically from the bottommost layer of the alternating stack (32, 46) to the topmost layer of the alternating stack (32, 46). The array of memoryless opening regions MOFA comprises a row of memoryless opening regions MOFA that each extend laterally from one of the pair of longitudinal sidewalls to the other of the pair of longitudinal sidewalls.

[0146] Reference Figure 14E , illustrates a top-down view of a second alternative configuration of an exemplary structure after the processing steps of Figures 14A to 14C . In the second alternative configuration, the alternating stack (32, 46) in each memory block comprises a pair of longitudinal sidewalls that extend laterally along a first horizontal direction hd1 and extend vertically from the bottommost layer of the alternating stack (32, 46) to the topmost layer of the alternating stack (32, 46). The array of memoryless opening regions MOFA is laterally spaced apart from the longitudinal sidewalls of the pair of longitudinal sidewalls by at least one row of memory opening fill structures 58 that is a subset of the array of memory opening fill structures 58 and that extends laterally along the first horizontal direction hd1.

[0147] In one embodiment, an array of layer contact components (81, 84) includes a row of layer contact components (81, 84) arranged along a first horizontal direction hd1. This row of layer contact components (81, 84) is laterally spaced apart from at least one row of memory opening fill structures 58 within the array of memory opening fill structures 58 by one of the drain select level dielectric isolation structures in the drain select level dielectric isolation structure 72.

[0148] In one embodiment, a cluster of support pillar structures 20 extends vertically through the alternating stack (32, 46). Each support pillar structure in the support pillar structures 20 contains a dielectric fill material. Each cluster of support pillar structures 20 within the cluster of support pillar structures 20 laterally surrounds the corresponding layer contact components within the array of layer contact components (81, 84) and within the corresponding memory - free opening regions within the memory - free opening area MOFA.

[0149] Reference Figures 15A to 15C , the contact level dielectric layer 80 can be formed by depositing a dielectric material such as silicon oxide over the insulating cap layer 70, the alternating stack (32, 46), the array of memory opening fill structures 58, and the layer contact via structures 84. The thickness of the contact level dielectric layer 80 can be in the range of 50 nm to 400 nm, although smaller and larger thicknesses can also be employed.

[0150] Contact level via structures (88, 86) can be formed through the contact level dielectric layer 80. The contact level via structures (88, 86) can include drain contact via structures 88 and contact level extension via structures 86. Each drain contact via structure in the drain contact via structures contacts the corresponding memory opening fill structure in the memory opening fill structures 58, and specifically the top surface of the corresponding drain region 63 within the corresponding memory opening fill structure in the memory opening fill structures 58. Each contact level extension via structure in the contact level extension via structures contacts the top surface of the corresponding layer contact via structure in the layer contact via structures 84.

[0151] Reference Figures 16A to 16D , the connection level dielectric layer 90 can be formed over the contact level dielectric layer 80. The connection level dielectric layer 90 contains an inter - level dielectric (ILD) material and can have a thickness in the range of 100 nm to 400 nm, although smaller and larger thicknesses can also be employed. Drain connection via structures 98 and connection level extension via structures 96 can be formed through the connection level dielectric layer 90. Each drain connection via structure in the drain connection via structures 98 contacts the corresponding drain contact via structure in the drain contact via structures 88. Each connection level extension via structure in the connection level extension via structures 96 contacts the corresponding contact level extension via structure in the contact level extension via structures 86.

[0152] The line-level dielectric layer 110 may be formed over the connection-level dielectric layer 90. The line-level dielectric layer 110 includes an interlevel dielectric (ILD) material and may have a thickness in the range of 100 nm to 400 nm, although smaller and larger thicknesses may also be employed. The bit lines 118 and the layer connection metal lines 116 may be formed through the line-level dielectric layer 110. Each bit line 118 extends laterally along a second horizontal direction hd2 and contacts a corresponding subset of the drain connection via structures 98 arranged along the second horizontal direction hd2. Each layer connection metal line 116 extends laterally along the second horizontal direction hd2 and may contact a corresponding connection-level extension via structure 96 in each of the alternating stacks (32, 46). If any memory opening fill structure 58 is located directly below a corresponding layer connection metal line 116, such a memory opening fill structure 58 may include a dummy (i.e., inactive) memory opening fill structure 58 that is not electrically connected to one of the bit lines 118. Such a dummy memory opening fill structure 58 may be located in Figure 14E a second alternative configuration of the exemplary structure. Although three adjacent layer connection metal lines 116 are shown in Figure 16A and Figure 16B there may be two layer connection metal lines 116, more than three layer connection metal lines 116, or no adjacent layer connection metal lines 116 that are not separated by at least one bit line 118 along the first horizontal direction hd1.

[0153] Generally, the bit lines 118 and the layer connection metal lines 116 may be formed at the same level (such as the level of the line-level dielectric layer 110) over the connection-level dielectric layer 90. The bit lines 118 are laterally spaced from each other along a first horizontal direction hd1 and extend laterally along the second horizontal direction hd2. The bit lines 118 contact a corresponding subset of the drain connection via structures 98 and are electrically connected to a corresponding subset of the drain regions 63. The layer connection metal lines 116 are electrically connected to a corresponding subset of the connection-level extension via structures 96, extend laterally along the second horizontal direction hd2, and are staggered with the bit lines 118 along the first horizontal direction hd1. The bit lines 118 and the layer connection metal lines 116 extend laterally over a plurality of alternating stacks (32, 46) along the second horizontal direction hd2. Thus, the lateral extent of the bit lines 118 and the layer connection metal lines 116 along the second horizontal direction hd2 is greater than the maximum lateral extent of any single alternating stack (32, 46) in the corresponding memory block along the second horizontal direction hd2.

[0154] Each layer contact wire in layer contact wires 116 is electrically connected to a corresponding one of the layer contact via structures in layer contact via structures 84, laterally extends along a second horizontal direction hd2, and is staggered with bit lines 118 along a first horizontal direction hd1. The lateral extent of layer contact wires 116 along the second horizontal direction hd2 is greater than the lateral extent of the alternating stack (32, 46) along the second horizontal direction hd2. Accordingly, the lateral extent of layer contact wires 116 along the second horizontal direction hd2 is greater than the width of a memory block having a lateral distance between a first lateral isolation trench 79 and a second lateral isolation trench 79. Each layer contact wire in layer contact wires 116 is electrically connected to a corresponding one of the layer contact via structures in layer contact via structures 84, laterally extends along the second horizontal direction hd2, and is staggered with bit lines 118 along the first horizontal direction hd1.

[0155] Reference Figure 17 , an upper metal interconnect structure 380 and an upper dielectric material layer 360 may be formed above the interlayer dielectric layer 110. The upper metal interconnect structure 380 overlies the alternating stack (32, 46) and is embedded within the upper dielectric material layer 360. The upper metal interconnect structure 380 includes upper metal via structures and upper metal wire structures. In one embodiment, the upper metal via structures may have corresponding lateral extents that increase as a vertical distance from the topmost surface of the alternating stack (32, 46) increases upward. The upper metal interconnect structure 380 may be electrically connected to corresponding nodes of the underlying three-dimensional memory device, such as a set of drain regions 63 or conductive layer 46. A memory side bonding pad 388 may be formed within the upper dielectric material layer 360. The memory side bonding pad 388 may be electrically connected to the upper metal interconnect structure 380. Accordingly, a memory die 900 is provided.

[0156] Reference Figure 18 , a logic die 700 may be provided. The logic die 700 includes a logic side substrate 709 (which may be a semiconductor substrate), logic side semiconductor devices 720 including peripheral circuitry for controlling the operation of the three-dimensional memory device within the memory die 900, a logic side metal interconnect structure 780 embedded within a logic side dielectric material layer 760, and a logic side bonding pad 788 configured to mate with the memory die bonding pad 388. The logic side metal interconnect structure 780 may include logic side metal wires 784 and logic side metal via structures 782. The logic side metal via structures 782 may have corresponding variable lateral extents that increase as a vertical distance from a horizontal plane including an interface between the logic side substrate 709 and the logic side dielectric material layer 760 increases.

[0157] Generally, the logic - side semiconductor device 720 includes a control circuit configured to control the operation of the vertical stacking of memory elements (e.g., memory cells) within each memory opening fill structure 58 in the memory die 900. The logic - side semiconductor device 720 can be electrically connected to the logic - side bonding pad 788 through the logic - side metal interconnect structure 780. Thus, the logic - side bonding pad 788 is electrically connected to the logic - side semiconductor device 720 through the logic - side metal interconnect structure 780.

[0158] The logic die 700 can be attached to the memory die 900, for example, by bonding the memory - side bonding pad 388 to the logic - side bonding pad 788. For example, the memory - side bonding pad 388 can be bonded to the logic - side bonding pad 788 by a metal - to - metal bond such as a copper - to - copper bond. In some embodiments, a hybrid bond can be employed, where the contact surfaces of the upper dielectric material layer 960 and the logic - side dielectric material layer 760 are bonded by a dielectric - to - dielectric bond (such as an oxide - to - oxide bond). The substrate 8 can be omitted or retained in the bonding assembly of the logic die 700 and the memory die 900.

[0159] Generally, various configurations can be employed for the upper metal interconnect structure 380 and the memory - die bonding pad 388 on the side of the memory die 900, and various configurations can be employed for the logic - side metal interconnect structure 780 and the logic - side bonding pad 788 on the side of the logic die 700.

[0160] Reference Figures 19A to 19C , an example of a first exemplary configuration of the upper metal interconnect structure 380, the memory - die bonding pad 388, the logic - side metal interconnect structure 780, and the logic - side bonding pad 788 is illustrated. In Figures 19A to 19C the first exemplary configuration, the upper - level interconnect structure can include memory - side pad - level via structures 386 that provide direct contact between the corresponding layer - connecting metal lines in the layer - connecting metal lines 116 and the corresponding memory - side bonding pads in the memory - side bonding pad 388. In this case, a single metal - wire level can be employed between the three - dimensional memory array and the memory - side bonding pad 388 in the memory die 900.

[0161] In some embodiments, the memory - side bonding pads 388 may be elongated along at least one horizontal direction to bond with a plurality of logic - side bonding pads 788. In some embodiments, a subset of the plurality of logic - side bonding pads 788 may be dummy bonding pads 788D, which are not electrically connected to any devices of the peripheral circuit 720 in the logic die 700, but are used to provide a uniform bond in the bonding structure between the memory - side bonding pads 388 and the active logic - side bonding pads 788A that are electrically connected to the peripheral circuit 720. In this case, at least one of the plurality of bonding pads 788 is an active logic - side bonding pad 788A, which is electrically connected to a corresponding semiconductor device in the logic die 700, for example, through a corresponding logic - side pad - level via structure 786. Alternatively, the plurality of logic - side bonding pads 788 may be elongated and bonded to active and dummy memory - side bonding pads. Thus, the logic - side bonding pads and / or the memory - side bonding pads can be used as lateral interconnections between the corresponding active regions in the logic die 700 and the memory die 900.

[0162] Reference Figures 20A to 20B , illustrates a second exemplary configuration of the upper metal interconnect structure 380, the memory - die bonding pads 388, the logic - side metal interconnect structure 780, and the logic - side bonding pads 788. In Figures 20A to 20B the second exemplary configuration, the memory - side bonding pads 388 and / or the logic - side bonding pads 788 may be formed with pad - level lateral extensions such that the corresponding bonding pads (388, 788) contact the corresponding pad - level via structures (386, 786) at positions laterally offset from the bonding interface between the memory - side bonding pads 388 and the logic - side bonding pads 788.

[0163] Generally, the number of metal interconnect levels in the memory die 900 can be minimized by employing layer - connecting metal wires 116 and by making appropriate modifications to the structure and / or position of the memory - side bonding pads 388 and the logic - side bonding pads 788.

[0164] Collective reference Figures 1 to 20BAnd according to various embodiments of the present disclosure, a three-dimensional memory device includes: an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46; an array of memory openings 49 extending vertically through the alternating stack (32, 46); a memory - opening - free area MOFA in the array of memory openings 49 in a plan view; an array of memory - opening fill structures 58 in the array of memory openings 49, wherein each memory - opening fill structure in the memory - opening fill structures 58 includes a corresponding vertical semiconductor channel 60 and a corresponding memory element (e.g., a portion of a memory film 50 or a floating gate) at a level of the conductive layer 46; and a layer - contact assembly (81, 84) in the memory - opening - free area MOFA in a plan view, wherein each layer - contact assembly in the layer - contact assembly (81, 84) includes a corresponding layer - contact via structure 84 that contacts a corresponding conductive layer in the conductive layer 46, and further includes a corresponding insulating spacer 81 that laterally surrounds the corresponding layer - contact via structure 84.

[0165] In one embodiment, the layer - contact via structure 84 includes at least one row of layer - contact via structures 84 arranged along a first horizontal direction hd1 and laterally spaced apart from each other by a sub - array of memory - opening fill structures 58, and wherein each sub - array in the sub - arrays includes a corresponding subset of the array of memory - opening fill structures 58.

[0166] In one embodiment, each memory - opening fill structure in the memory - opening fill structures 58 further includes a corresponding drain region 63 that contacts the top of the corresponding vertical semiconductor channel 60; and the three - dimensional memory device further includes bit lines 118 that are laterally spaced apart from each other along the first horizontal direction hd1 and laterally extend along a second horizontal direction hd2. Each bit line in the bit lines 118 is electrically connected to a corresponding subset of the drain regions 63. In one embodiment, the three - dimensional memory device further includes layer - connecting metal lines 116 at the same level as the bit lines 118, wherein each layer - connecting metal line in the layer - connecting metal lines 116 is electrically connected to a corresponding layer - contact via structure in the layer - contact via structures 84, laterally extends along the second horizontal direction hd2, and is staggered with the bit lines 118 along the first horizontal direction hd1.

[0167] In one embodiment, a three-dimensional memory device includes: a first lateral isolation trench fill structure (74, 76) having a first dielectric sidewall that extends laterally along a first horizontal direction hd1 and contacts each of an insulating layer 32 and a conductive layer 46 within an alternating stack (32, 46); and a second lateral isolation trench fill structure (74, 76) that is laterally spaced from the first lateral isolation trench fill structure (74, 76) along a second horizontal direction hd2 and has a second dielectric sidewall that extends laterally along the first horizontal direction hd1 and contacts each of the insulating layer 32 and the conductive layer 46 within the alternating stack (32, 46). In one embodiment, a layer connecting metal line 116 has a lateral extent along the second horizontal direction hd2 that is greater than a lateral extent of the alternating stack (32, 46) along the second horizontal direction hd2.

[0168] In Figure 14B In one embodiment as shown, layer contact assemblies (81, 84) include multiple rows of layer contact assemblies (81, 84); each row of layer contact assemblies (81, 84) within the multiple rows of layer contact assemblies (81, 84) includes a corresponding plurality of layer contact assemblies (81, 84) arranged along the first horizontal direction hd1; and the multiple rows of layer contact assemblies (81, 84) are laterally spaced from each other along the second horizontal direction hd2.

[0169] In one embodiment, an array of memory opening fill structures 58 includes at least one row of memory opening fill structures 58 that extends laterally along the first horizontal direction hd1 and is located between a corresponding pair of adjacent rows of layer contact assemblies (81, 84) within the multiple rows of layer contact assemblies (81, 84).

[0170] In Figure 14D In one embodiment as shown, the alternating stack (32, 46) includes a pair of longitudinal sidewalls that extend laterally along the first horizontal direction hd1 and vertically from a lowermost layer to a topmost layer of the alternating stack (32, 46); and a memory opening free area MOFA includes a column of memory opening free areas MOFA each extending laterally from one of the pair of longitudinal sidewalls to the other of the pair of longitudinal sidewalls.

[0171] In one embodiment, the alternating stack (32, 46) includes a pair of longitudinal sidewalls that laterally extend along a first horizontal direction hd1 and vertically extend from the bottommost layer to the topmost layer of the alternating stack (32, 46); and an array of memory opening-free areas MOFA is laterally spaced from a longitudinal sidewall of the pair of longitudinal sidewalls by at least one row of memory opening fill structures 58, the at least one row of memory opening fill structures being a subset of the array of memory opening fill structures 58 and laterally extending along the first horizontal direction hd1.

[0172] In one embodiment, the three-dimensional memory device includes drain select level dielectric isolation structures 72 that laterally extend along a first horizontal direction hd1 and vertically extend through at least one conductive layer 46 including the topmost conductive layer 46 within the alternating stack (32, 46).

[0173] In Figure 14E In the illustrated embodiment, an array of layer contact components (81, 84) includes a row of layer contact components (81, 84) arranged along a first horizontal direction hd1; and the row of layer contact components (81, 84) is laterally spaced from at least one row of memory opening fill structures 58 within the array of memory opening fill structures 58 by one of the drain select level dielectric isolation structures 72.

[0174] In one embodiment, the layer contact components (81, 84) include a row of layer contact components (81, 84) arranged along a first horizontal direction hd1; and one of the drain select level dielectric isolation structures 72 extends through an upper portion of each layer contact component within the row of layer contact components (81, 84).

[0175] In one embodiment, the three-dimensional memory device includes a cluster of support pillar structures 20 that vertically extend through the alternating stack (32, 46), wherein: each support pillar structure within the support pillar structures 20 contains a dielectric fill material; and each cluster of support pillar structures 20 within the cluster of support pillar structures 20 laterally surrounds a corresponding layer contact component within a corresponding memory opening-free area within the layer contact components (81, 84) located within the memory opening-free area MOFA.

[0176] In one embodiment, memory die 900 includes at least one elongated memory-side bonding pad 388. Logic die 700 includes peripheral circuitry 720, at least one active logic-side bonding pad 788A electrically connected to the peripheral circuitry 720 and bonded to the elongated memory-side bonding pad 388, and at least one dummy logic-side bonding pad 788D not electrically connected to the peripheral circuitry 720 and not bonded to the elongated memory-side bonding pad 388.

[0177] Various embodiments of the present disclosure can be used to form the layer contact via structure 84 within the memory array region 100 without forming a staircase region having a stepped surface. Further, by forming the layer contact via structure 84 between the memory opening fill structures 58 in the memory array region 100 rather than in a separate contact region located adjacent to the memory array region 100, the area of the active memory array region 100 is increased while reducing the chip size and the shunt resistance.

[0178] Although the foregoing relates to particularly preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will recognize that various modifications can be made to the disclosed embodiments, and such modifications are intended to be within the scope of the present disclosure. Compatibility is assumed among all embodiments that are not alternatives to each other. The term “comprising” or “including” encompasses all embodiments in which the term “consisting essentially of” or the term “consisting of” replaces the term “comprising” or “including,” unless expressly stated otherwise. Whenever two or more elements are listed as alternatives in the same paragraph or different paragraphs, a Markush group including the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb “able to” is used in the present disclosure to describe the formation of an element or the performance of a processing step, an embodiment in which such element or such processing step is not performed is also clearly contemplated, provided that the resulting apparatus or device is able to provide an equivalent result. Accordingly, whenever the formation of such element or such processing step is omitted and the same result or an equivalent result can be provided, the auxiliary verb “able to” as applied to the formation or performance of the element or the processing step should also be interpreted as “can” or “can, or may not,” and these equivalent results include slightly superior results and slightly inferior results. Where embodiments employing a particular structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise known to be impossible to those of ordinary skill in the art. If publications, patent applications, and / or patents are cited herein, each such document is hereby incorporated by reference in its entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: An alternating stack of insulating layers and conductive layers; An array of memory openings extending vertically through the alternating stack; A memory-opening-free region in the array of memory openings in a plan view; An array of memory-opening filling structures in the array of memory openings, wherein each memory-opening filling structure in the memory-opening filling structures includes a corresponding vertical semiconductor channel and a corresponding memory element at a level of the conductive layer; And A layer contact assembly in the memory-opening-free region in the plan view, wherein each layer contact assembly in the layer contact assemblies includes a corresponding layer contact via structure contacting a corresponding conductive layer in the conductive layers and further includes a corresponding insulating spacer laterally surrounding the corresponding layer contact via structure.

2. The three-dimensional memory device according to claim 1, wherein the layer contact via structure includes at least one row of layer contact via structures arranged along a first horizontal direction and laterally spaced apart from each other by a sub-array of memory-opening filling structures, and wherein each sub-array in the sub-arrays includes a corresponding subset of the array of memory-opening filling structures.

3. The three-dimensional memory device according to claim 1, wherein: Each memory-opening filling structure in the memory-opening filling structures further includes a corresponding drain region contacting a top end of the corresponding vertical semiconductor channel; The three-dimensional memory device further includes bit lines laterally spaced apart from each other along a first horizontal direction and laterally extending along a second horizontal direction; Each bit line in the bit lines is electrically connected to a corresponding subset of the drain regions.

4. The three-dimensional memory device according to claim 3, the three-dimensional memory device further includes layer connection metal lines at a same level as the bit lines, wherein each layer connection metal line in the layer connection metal lines is electrically connected to a corresponding layer contact via structure in the layer contact via structures, laterally extends along the second horizontal direction, and is staggered with the bit lines along the first horizontal direction.

5. The three-dimensional memory device according to claim 4, the three-dimensional memory device further includes: A first lateral isolation trench filling structure having a first dielectric sidewall laterally extending along the first horizontal direction and contacting each of the insulating layer and the conductive layer within the alternating stack; And A second lateral isolation trench filling structure laterally spaced apart from the first lateral isolation trench filling structure along the second horizontal direction and having a second dielectric sidewall laterally extending along the first horizontal direction and contacting each of the insulating layer and the conductive layer within the alternating stack.

6. The three-dimensional memory device according to claim 3, wherein a lateral range of the layer connection metal lines along the second horizontal direction is larger than a lateral range of the alternating stack along the second horizontal direction.

7. The three-dimensional memory device according to claim 1, wherein the three-dimensional memory device further comprises: at least one elongated memory side bonding pad; and a logic die, the logic die comprising: peripheral circuitry; at least one active logic side bonding pad electrically connected to the peripheral circuitry and bonded to the at least one elongated memory side bonding pad; and at least one dummy logic side bonding pad not electrically connected to the peripheral circuitry and not bonded to the at least one elongated memory side bonding pad.

8. The three-dimensional memory device according to claim 1, wherein: the contact assembly includes multiple rows of layer contact assemblies; each row of layer contact assemblies within the multiple rows of layer contact assemblies includes a corresponding plurality of layer contact assemblies arranged along a first horizontal direction; the multiple rows of layer contact assemblies are laterally spaced apart from each other along a second horizontal direction; and the array of memory opening filling structures includes at least one row of memory opening filling structures that laterally extends along the first horizontal direction and is located between a corresponding pair of adjacent rows of layer contact assemblies within the multiple rows of layer contact assemblies.

9. The three-dimensional memory device according to claim 1, wherein: the alternating stack includes a pair of longitudinal sidewalls that laterally extend along a first horizontal direction and vertically extend from the bottommost layer to the topmost layer of the alternating stack; and the memory opening-free region includes a column of memory opening-free regions that laterally extends from one of the pair of longitudinal sidewalls to the other of the pair of longitudinal sidewalls.

10. The three-dimensional memory device according to claim 1, wherein: the alternating stack includes a pair of longitudinal sidewalls that laterally extend along a first horizontal direction and vertically extend from the bottommost layer to the topmost layer of the alternating stack; and the array of memory opening-free regions is laterally spaced apart from the longitudinal sidewalls of the pair of longitudinal sidewalls by at least one row of memory opening filling structures, the at least one row of memory opening filling structures being a subset of the array of memory opening filling structures and laterally extending along the first horizontal direction.

11. The three-dimensional memory device according to claim 1, wherein the three-dimensional memory device further comprises a drain select level dielectric isolation structure that laterally extends along a first horizontal direction and vertically extends through at least one conductive layer including the topmost conductive layer within the alternating stack.

12. The three-dimensional memory device according to claim 11, wherein: the layer contact assembly includes a row of layer contact assemblies arranged along the first horizontal direction; and the row of layer contact assemblies is laterally spaced apart from at least one row of memory opening filling structures within the array of memory opening filling structures by one of the drain select level dielectric isolation structures within the drain select level dielectric isolation structure.

13. The three-dimensional memory device according to claim 11, wherein: The layer contact component includes a row of layer contact components arranged along a first horizontal direction; and one of the drain select level dielectric isolation structures in the drain select level dielectric isolation structure extends through the upper portion of each layer contact component within the row of layer contact components.

14. The three-dimensional memory device according to claim 1, the three-dimensional memory device further comprising a cluster of support pillar structures extending vertically through the alternately stacked support pillar structures, wherein: each support pillar structure in the support pillar structures contains a dielectric filling material; and each cluster of support pillar structures within the cluster of support pillar structures laterally surrounds the corresponding layer contact component within the corresponding memoryless opening region in the memoryless opening region in the layer contact components.

15. A method of forming a three-dimensional memory device, the method comprising: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; forming an array of memory openings through the alternating stack, wherein the array of memory openings is arranged to provide a memoryless opening region therein in a plan view; forming an array of memory opening filling structures in the array of memory openings, wherein each memory opening filling structure in the memory opening filling structures includes a corresponding vertical semiconductor channel and a corresponding memory element at a level of the conductive layer; forming an in-process via structure including a sacrificial via filling material portion in the region of the memoryless opening region in the plan view, wherein each in-process via structure in the in-process via structures extends vertically through a corresponding subset of layers within the alternating stack; replacing the sacrificial material layer with a conductive layer; and replacing the sacrificial via filling material portion with a layer contact via structure to form a layer contact component, wherein each layer contact component in the layer contact components includes a corresponding layer contact via structure contacting a corresponding conductive layer in the conductive layers, and further includes a corresponding insulating spacer laterally surrounding the corresponding layer contact via structure.

16. The method according to claim 15, wherein: each memory opening filling structure in the memory opening filling structures further includes a corresponding drain region contacting the top end of the corresponding vertical semiconductor channel; the method further includes forming a bit line and a layer connection metal line at the same level over the memory opening filling structure and the layer contact component; the bit lines are laterally spaced apart from each other along a first horizontal direction, laterally extend along a second horizontal direction, and are electrically connected to a corresponding subset of the drain regions; and each layer connection metal line in the layer connection metal lines is electrically connected to a corresponding layer contact via structure in the layer contact via structures, laterally extends along the second horizontal direction, and is staggered with the bit lines along the first horizontal direction.

17. The method according to claim 16, the method further comprising forming a first lateral isolation trench and a second lateral isolation trench, the first lateral isolation trench and the second lateral isolation trench laterally extending along a first horizontal direction and laterally spaced apart along a second horizontal direction through the alternating stack, wherein: The sacrificial material layer is removed by providing an etchant to the first lateral isolation trench and the second lateral isolation trench, and the conductive layer is formed by providing a precursor gas of a conductive material for the conductive layer to the first lateral isolation trench and the second lateral isolation trench; and The lateral range of the layer-connecting metal line along the second horizontal direction is larger than the lateral distance between the first lateral isolation trench and the second lateral isolation trench.

18. The method according to claim 15, the method further comprising: Forming via cavities with different depths in the memory-less opening region in the plan view; Depositing an insulating liner layer and a sacrificial via filling material in the via cavities; And Removing a portion of the sacrificial via filling material above a horizontal plane including the top surface of the insulating liner layer, wherein the remaining portion of the sacrificial via filling material includes the sacrificial via filling material portion.

19. The method according to claim 15, the method further comprising: Forming a contact-level dielectric layer over the array of the alternating stack, the memory opening filling structure, and the layer contact via structure; Forming a drain contact via structure and a contact-level extension via structure through the contact-level dielectric layer, wherein each drain contact via structure in the drain contact via structure contacts a corresponding memory opening filling structure in the memory opening filling structure, and each contact-level extension via structure in the contact-level extension via structure contacts a corresponding layer contact via structure in the layer contact via structure; Forming a connection-level dielectric layer over the contact-level dielectric layer; And Forming a drain connection via structure and a connection-level extension via structure through the connection-level dielectric layer, wherein each drain connection via structure in the drain connection via structure contacts a corresponding drain contact via structure in the drain contact via structure, and each connection-level extension via structure in the connection-level extension via structure contacts a corresponding contact-level extension via structure in the contact-level extension via structure.

20. The method according to claim 19, the method further comprising forming a bit line and a layer-connecting metal line at the same level over the connection-level dielectric layer, wherein: The bit line contacts a corresponding subset of the drain connection via structures; and The lateral range of the layer-connecting metal line along the second horizontal direction is larger than the maximum lateral range of the alternating stack along the second horizontal direction.

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