Vertical field effect transistor with self-aligned backside trench epitaxy

Abstract

A semiconductor structure with self-aligned backside trench epitaxy includes a channel fin extending vertically from a bottom source / drain region of a field effect transistor. The bottom source / drain region includes a trench epitaxial layer below the bottommost surface of the channel fin. A high-k metal gate stack is disposed along sidewalls of the channel fin. The high-k metal gate is separated from the bottom source / drain region by a bottom spacer. A top source / drain region is over the topmost surface of the channel fin. The top source / drain region is separated from the high-k metal gate by a top spacer. The semiconductor structure also includes a backside metal contact within the backside interlayer dielectric. The backside metal contact is electrically connected to and vertically aligned with the bottom source / drain region.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention generally relates to the field of semiconductor devices and, more particularly, to vertical field effect transistors (VFETs).

[0002] VFETs have been pursued as potential device options for scaling complementary metal oxide semiconductor (CMOS) to 5 nanometer (nm) nodes and beyond. In contrast to planar CMOS devices, VFETs are vertically oriented, having vertical fins or nanowires extending upward from a substrate. The fins or nanowires form the channel region of the transistor. Source and drain regions are located in electrical contact with the top and bottom ends of the channel region, while a gate is disposed on one or more of the sidewalls of the fin or nanowire. Thus, in a VFET, the direction of current flow between the source and drain regions is perpendicular to the main surface of the substrate. Generally, due to control issues during epitaxial growth, forming bottom source and drain junctions in VFETs can be a challenging task. Therefore, improved techniques for forming bottom source and drain junctions in VFETs would be desirable. SUMMARY OF THE INVENTION

[0003] According to an embodiment of the present disclosure, a semiconductor structure includes a channel fin extending vertically from a bottom source / drain region of a field effect transistor, the bottom source / drain region including a trench epitaxial layer located below the bottommost surface of the channel fin, a high-k metal gate stack disposed along the sidewall of the channel fin, the high-k metal gate being separated from the bottom source / drain region by a bottom spacer, and a top source / drain region located above the topmost surface of the channel fin, the top source / drain region being separated from the high-k metal gate by a top spacer.

[0004] According to another embodiment of the present disclosure, a method of forming a semiconductor structure includes: forming a channel fin extending vertically from a bottom source / drain region of a field effect transistor, the bottom source / drain region including a trench epitaxial layer located below the bottommost surface of the channel fin, forming a high-k metal gate stack disposed along the sidewall of the channel fin, the high-k metal gate being separated from the bottom source / drain region by a bottom spacer, and forming a top source / drain region located above the topmost surface of the channel fin, the top source / drain region being separated from the high-k metal gate by a top spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following detailed description will be best understood in conjunction with the accompanying drawings, which are given by way of example and are not intended to limit the invention solely thereto, where:

[0006] Figure 1 is a top-down view of a semiconductor structure at an intermediate step during a semiconductor manufacturing process, depicting different cross-sectional views for describing embodiments of the present disclosure;

[0007] Figure 2A is a cross-sectional view of a semiconductor structure taken along line X-X as shown, depicting the formation of a first sacrificial layer and a first semiconductor layer; Figure 1

[0008] Figure 2B is a cross-sectional view of a semiconductor structure taken along line Y-Y as shown in accordance with an embodiment of the present disclosure; Figure 1

[0009] Figure 3A is a cross-sectional view of a semiconductor structure taken along line X-X as shown, depicting the patterning of a plurality of channel fin structures; Figure 1

[0010] Figure 3B is a cross-sectional view of a semiconductor structure taken along line Y-Y as shown in accordance with an embodiment of the present disclosure; Figure 1

[0011] Figure 4A is a cross-sectional view of a semiconductor structure taken along line X-X as shown, depicting the completion of front-end process steps, intermediate process contact patterning and metallization, and the formation of back-end process interconnect layers and a carrier wafer; Figure 1

[0012] Figure 4B is a cross-sectional view of a semiconductor structure taken along line Y-Y as shown in accordance with an embodiment of the present disclosure; Figure 1

[0013] Figure 5A is a cross-sectional view of a semiconductor structure taken along line X-X as shown in accordance with an embodiment of the present disclosure, depicting substrate removal; Figure 1

[0014] Figure 5B is a cross-sectional view of a semiconductor structure taken along line Y-Y as shown in accordance with an embodiment of the present disclosure; Figure 1

[0015] Figure 6A is a cross-sectional view of a semiconductor structure taken along line X-X as depicted in, depicting the removal of the first sacrificial layer; Figure 1

[0016] Figure 6B is a cross-sectional view of a semiconductor structure taken along line Y-Y as shown in accordance with an embodiment of the present disclosure; Figure 1

[0017] ​​​​​​​​​​Figure 7A is a cross-sectional view of a semiconductor structure taken along line X-X as shown in Figure 1 which depicts the formation of a first backside interlayer dielectric;

[0018] Figure 7B is a cross-sectional view of a semiconductor structure taken along line Y-Y as shown in Figure 1 accordance with an embodiment of the present disclosure;

[0019] Figure 8A is a cross-sectional view of a semiconductor structure taken along line X-X as shown in Figure 1 which depicts the formation of a plurality of backside contact openings;

[0020] Figure 8B is a cross-sectional view of a semiconductor structure taken along line Y-Y as shown in Figure 1 accordance with an embodiment of the present disclosure;

[0021] Figure 9A is a cross-sectional view of a semiconductor structure taken along line X-X as shown in Figure 1 which depicts the formation of a trench epitaxial layer;

[0022] Figure 9B is a cross-sectional view of a semiconductor structure taken along line Y-Y as shown in Figure 1 accordance with an embodiment of the present disclosure;

[0023] Figure 10A is a cross-sectional view of a semiconductor structure taken along line X-X as shown in Figure 1 which depicts the backside contact metallization;

[0024] Figure 10B is a cross-sectional view of a semiconductor structure taken along line Y-Y as shown in Figure 1 accordance with an embodiment of the present disclosure;

[0025] Figure 11A is a cross-sectional view of a semiconductor structure taken along line X-X as shown in Figure 1 which depicts the formation of a backside interconnect structure; and

[0026] Figure 11B is a cross-sectional view of a semiconductor structure taken along line Y-Y as shown in Figure 1 accordance with an embodiment of the present disclosure.

[0027] The accompanying drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to depict the specific parameters of the present invention. The drawings are intended to depict only typical embodiments of the present invention. In the drawings, like numbers represent like elements. Detailed Description

[0028] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. The present invention, however, may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0029] For purposes of the description hereinafter, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the disclosed structures and methods as oriented in the accompanying drawings. Terms such as "above", "overlying", "on top of", "on the top of", "positioned on" or "positioned on top of" mean that a first element, such as a first structure, is present on a second element, such as a second structure, where intervening elements, such as interface structures, may be present between the first and second elements. The term "in direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are joined without any intervening conductive, insulating, or semiconductor layer at the interface of the two elements.

[0030] To avoid obscuring the presentation of the embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may have been combined together for presentation and illustration purposes and may not have been described in detail in some instances. In other cases, some processing steps or operations known in the art may not have been described at all. It should be understood that the following description is quite focused on the distinguishing features or elements of the various embodiments of the present invention.

[0031] Some non-planar transistor device architectures, such as VFETs, employ semiconductor fins and side gates that can be contacted outside the active region, resulting in increased device density compared to lateral devices. In a VFET, the source-to-drain current flows in a direction perpendicular to the main surface of the substrate. For example, in a known VFET configuration, the main substrate surface is horizontal, and vertical fins extend upward from the substrate surface. The fins form the channel region of the transistor. The source region and the drain region are disposed to make electrical contact with the top and bottom ends of the channel region, while the gate is disposed on one or more fin sidewalls. A bottom junction is formed at the interface between the channel fin and the bottom source / drain (S / D) region, and a top junction is formed at the interface between the channel fin and the top S / D region. As described above, forming the bottom source / drain region in a VFET device can be a challenging task due to control issues during epitaxial growth.

[0032] Accordingly, embodiments of the present invention provide a VFET device and a method of manufacturing the same, in which a bottom source / drain region is formed using a backside interconnect process. Specifically, the proposed VFET structure includes a backside trench epitaxial region formed under each semiconductor channel fin, where a first side of the backside trench epitaxial region is in direct contact with the semiconductor channel fin, and a second side of the backside trench epitaxial region (opposite the first side) is in direct contact with a backside metal contact that is aligned with the backside trench epitaxial region to route the VFET device to a backside interconnect. The backside trench epitaxial region provides the bottom source / drain region for the VFET device. Thus, by using the backside interconnect process, the bottom source / drain contact (CR) of the VFET can be eliminated, which provides significant density and device performance improvements for VFET-based technologies. In addition, by omitting the bottom source / drain module during the front-end process, the manufacturing process is simplified while improving device performance and reliability.

[0033] Embodiments of a VFET device that can be formed with a backside trench epitaxy are described in detail below with reference to Figure 1-11B the accompanying drawings.

[0034] Now referring to Figure 1 , a top-down view of a semiconductor structure 100 at an intermediate step during a semiconductor manufacturing process according to an embodiment of the present disclosure is shown. In particular, Figure 1 different cross-sectional views of the semiconductor structure 100 that will be used to describe the embodiments of the present disclosure are depicted. The cross-sectional views are taken along line X-X and line Y-Y. As shown, line X-X represents a cut line through the nanosheet fin structure 20 of the semiconductor structure 100, and line Y-Y represents a cut line along the nanosheet fin structure 20 in the NFET region 12 and the PFET region 16 of the semiconductor structure 100.

[0035] In this embodiment, the cross-sectional view taken along line Y-Y further includes a view of the NFET region 12 and / or the PFET region 16 and the region (N-P boundary) 14 between the NFET region 12 and the PFET region 16.

[0036] Now refer to Figures 2A to 2B , which shows a cross-sectional view of a semiconductor structure 100 after the formation of a first sacrificial layer 104 and a first semiconductor layer 106 according to an embodiment of the present invention. In this embodiment, Figure 2A is a cross-sectional view of the semiconductor structure 100 taken along line X-X as shown in Figure 1 ; and Figure 2B is a cross-sectional view of the semiconductor structure 100 taken along line Y-Y as shown in Figure 1 .

[0037] In the depicted embodiment, the semiconductor structure 100 includes a substrate 102, a first sacrificial layer 104 located above the substrate 102, and a first semiconductor layer 106 disposed above the first sacrificial layer 104. According to an embodiment, the first sacrificial layer 104 and the first semiconductor layer 106 are vertically stacked on top of each other in a direction perpendicular to the substrate 102, as illustrated in the figure.

[0038] The substrate 102 can be, for example, a bulk substrate, which can be made of any of several known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide or gallium indium phosphide. Generally, the substrate 102 can be approximately but not limited to several hundred micrometers thick. In other embodiments, the substrate 102 can be a layered semiconductor, such as silicon-on-insulator or SiGe-on-insulator, where a buried insulator layer separates the underlying substrate from the top semiconductor layer.

[0039] According to an embodiment, the first sacrificial layer 104 can be formed on the substrate 102 using an epitaxial growth process. For example, the first sacrificial layer 104 can be formed by epitaxially growing a SiGe layer with a germanium concentration varying from about 15 atomic percent to about 35 atomic percent. In some embodiments, the first sacrificial layer 104 can be made of epitaxially grown SiGe with a germanium concentration of about 30 atomic percent. In other embodiments, the first sacrificial layer 104 can be made of silicon dioxide (SiO2). In such embodiments, the combined structure formed by the substrate 102, the first sacrificial layer 104, and the first semiconductor layer 106 is a SOI wafer, where the first sacrificial layer 104 is a buried oxide (BOX) that includes a thickness in the range from about 20 nm to about 100 nm and ranges therebetween. The first sacrificial layer 104 can act as an etch stop layer during subsequent substrate removal.

[0040] The first semiconductor layer 106 can be formed by epitaxially growing a Si layer from the first sacrificial layer 104 to a thickness that varies from about 30 nm to about 250 nm, although other thicknesses are also within the scope of the present invention.

[0041] Generally, the first sacrificial layer 104 and the first semiconductor layer 106 can be formed by epitaxial growth using the substrate 102 as a seed layer. Terms such as "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" refer to the growth of a semiconductor material on the deposition surface of a semiconductor material, where the grown semiconductor material has the same or substantially similar crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gas are controlled and the system parameters are set such that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, the epitaxial semiconductor material has the same or substantially similar crystalline characteristics as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will exhibit a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for forming on a semiconductor surface and does not deposit material on a dielectric surface (such as a silicon dioxide or silicon nitride surface).

[0042] Non-limiting examples of various epitaxial growth processes include rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), metalorganic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), and molecular beam epitaxy (MBE). The temperature of the epitaxial deposition process can be in the range of 500°C to 900°C. Although higher temperatures generally result in faster deposition, faster deposition may lead to crystal defects and film cracking.

[0043] Many different precursors can be used for the epitaxial growth of the first sacrificial layer 104 and the first semiconductor layer 106. In some embodiments, the gas sources for depositing the epitaxial semiconductor material include silicon-containing gas sources, germanium-containing gas sources, or combinations thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source, which includes but is not necessarily limited to silane, disilane, trisilane, tetrasilane, hexachloroethylsilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source, which includes but is not necessarily limited to germane, digermane, halogenated germane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. And an epitaxial silicon-germanium alloy layer can be formed using a combination of these gas sources. Carrier gases such as hydrogen, helium, and argon can be used.

[0044] Now refer to Figures 3A-3B, shows a cross-sectional view of a semiconductor structure 100 after patterning a plurality of channel fin structures 304 (hereinafter referred to as "channel fins") according to an embodiment of the present disclosure. In this embodiment, Figure 3A is a cross-sectional view of the semiconductor structure 100 taken along line X-X as shown in Figure 1 ; Figure 3B is a cross-sectional view of the semiconductor structure 100 taken along line Y-Y as shown in Figure 1 .

[0045] Patterning of the channel fins 304 includes forming a hard mask layer 302 ( Figures 2A-2B ) over the first semiconductor layer 106 by depositing a hard mask material (e.g., silicon nitride) using, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any suitable technique for dielectric deposition. By way of example only, the hard mask layer 302 may be formed to have a thickness varying from about 20 nm to about 200 nm, although thicknesses greater than 200 nm and less than 20 nm may also be used.

[0046] After depositing the hard mask layer 302, photolithographic patterning is then performed on the deposited hard mask layer 302 to form a plurality of individual fin hard masks. According to an exemplary embodiment, reactive ion etching (RIE) may be used to etch through the first semiconductor layer 106 ( Figures 2A-2B ) to form the channel fins 304. The etching process may continue until the top surface of the first sacrificial layer 104 is exposed.

[0047] Now referring to Figures 4A to 4B , shows a cross-sectional view of the semiconductor structure 100 after completion of front-end-of-line (FEOL) processing steps, middle-of-line (MOL) contact patterning and metallization, and formation of back-end-of-line (BEOL) interconnect layers 430 and carrier wafer 440 according to an embodiment of the present disclosure. In this embodiment, Figure 4A is a cross-sectional view of the semiconductor structure 100 taken along line X-X as shown in Figure 1 ; Figure 4B is a cross-sectional view of the semiconductor structure 100 taken along line Y-Y as shown in Figure 1 .

[0048] Known semiconductor manufacturing operations have been used to form as shown in Figures 4A-4BThe semiconductor structure 100 shown. Thus, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Additionally, the various tasks and process steps described herein may be incorporated into a more comprehensive program or process having additional steps or functionality not described in detail herein. In particular, various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and thus, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0049] In the depicted embodiment, the semiconductor structure 100 includes a bottom spacer 402 formed above the first sacrificial layer 104 and adjacent to the bottom portion of the channel fin 304. The bottom spacer 402 may include a dielectric material such as SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, SiOxNy, and combinations thereof. The dielectric material may be a low-k material having a dielectric constant less than about 7, less than about 5, or even less than about 2.5. The bottom spacer 402 may be formed using a combination of known deposition and etching processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical solution deposition, and etching processes including reactive ion etching (RIE), wet etching, or isotropic dry gas etching.

[0050] The semiconductor structure 100 may further include a high-k metal gate stack 406 formed along the sidewalls of each channel fin 304 and in direct contact with the sidewalls of each channel fin 304. For ease of illustration, the high-k metal gate stack 406 is depicted as only one layer. However, as is known to those skilled in the art, the high-k metal gate stack 406 may include a gate dielectric and a gate conductor / metal (e.g., a work function metal (WFM)) deposited over the bottom spacer 402 and adjacent to a portion of the channel fin 304. The high-k metal gate stack 406 may be conformally deposited on the semiconductor structure 100 using, for example, ALD.

[0051] The gate dielectric (not shown) can be formed of one or more gate dielectric films. The gate dielectric film can be a dielectric material having a dielectric constant greater than, for example, 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for high-k dielectric films include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials having a dielectric constant greater than 7.0 include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate dielectric film can also include dopants, such as lanthanum and aluminum. The gate dielectric film can be formed by a suitable deposition process, such as CVD, PECVD, ALD, PVD, chemical solution deposition, or other similar processes. The thickness of the gate dielectric film can vary depending on the deposition process and the composition and amount of the high-k dielectric material used.

[0052] The gate conductor (not shown) of the high-k metal gate stack 406 can include doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metal compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. The conductive material can further include dopants incorporated during or after deposition. In some embodiments, the gate conductor can be a WFM deposited on the gate dielectric film by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, and sputtering. The type of WFM depends on the type of transistor and can vary between n-FET and p-FET devices. P-type WFMs include compositions such as titanium nitride (TiN), ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. N-type WFMs include compositions such as titanium carbide (TiC), titanium aluminum carbide (TiAlC), hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The gate conductor can also include a material of tungsten (W), titanium (Ti), aluminum (Al), cobalt (Co), or nickel (Ni) above the WFM layer of the gate conductor. The gate conductor can be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, and sputtering.

[0053] After forming the high-k metal gate stack 406, a patterning process is performed on the semiconductor structure 100 to remove the excess material.

[0054] In one or more embodiments, a first interlayer dielectric 425 may be formed to fill the voids between the gate structures and other existing devices within the semiconductor structure 100. The interlayer dielectric 425 may be formed by, for example, CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the interlayer dielectric 425 may include silicon oxide, silicon nitride, silicon oxycarbide, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics.

[0055] Typically, after depositing the interlayer dielectric 425, a chemical mechanical polishing (CMP) process is performed on the semiconductor structure 100 to expose the top surface of the channel fins 304.

[0056] Continuing reference Figures 4A-4B , after removing the hard mask layer 402 ( Figures 3A-3B ), the high-k metal gate stack 406 may be recessed below the top surface of the channel fins 304, as shown in the figure. Thereafter, the top spacer 408 may be conformally deposited over the high-k metal gate stack 406 and in direct contact with the high-k metal gate stack 406. In such an embodiment, the top spacer 408 may be deposited using, for example, CVD, PECVD, radio frequency CVD (RFCVD), PVD, ALD, molecular layer deposition (MLD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), sputtering, and / or electroplating. Non-limiting examples of materials for forming the top spacer 408 may include silicon nitride (SiN), silicon boron nitride (SiBN), silicon boron carbon nitride (SiBCN), or silicon oxycarbonitride (SiOCN).

[0057] According to an embodiment, a suitable etching technique (e.g., RIE) may be used to recess the top spacer 408 and expose the top surface of the channel fins 304. Then, a top source / drain region 410 may be formed from the exposed top surface of the channel fins 304 using an epitaxial growth process similar to the epitaxial growth process described above with respect to the first sacrificial layer 104 and the first semiconductor layer 106. As shown, the top spacer 408 may cover the top source / drain regions 410 to electrically isolate each of the top source / drain regions 410 from the high-k metal gate stack 406. As is known to those skilled in the art, the top source / drain regions 410 are formed within the corresponding NFET and PFET regions 12, 16 ( Figure 1 shown) of the semiconductor structure 100. Thus, in an embodiment where the semiconductor structure 100 is a PFET device, the top source / drain region 410 may include, for example, epitaxially grown Si:B. In an embodiment where the semiconductor structure 100 is an NFET device, the top source / drain region 410 may include, for example, epitaxially grown Si:P.

[0058] It should be noted that although the bottom spacer 402 and the top spacer 408 are depicted as being on adjacent opposite sides of the channel fin 304, the bottom spacer 402 and the top spacer 408 surround the entire surface of the channel fin 304. The bottom spacer 402 and the top spacer 408 can determine the position of the p-n junction in the semiconductor structure 100.

[0059] To continue the manufacturing process, a second interlayer dielectric 425 can be formed in the semiconductor structure 100, followed by a planarization process. It should be noted that for ease of illustration, only one layer of the interlayer dielectric 425 is shown in the figures.

[0060] Continuing to refer Figures 4A-4B , subsequently, a plurality of conductive structures including metal contacts 420 can be formed in the semiconductor structure 100 for electrically connecting the FEOL devices to a subsequently formed metal layer. The process of forming the metal contacts 420 is standard and well-known in the art. Typically, the process includes forming trenches (not shown) in the interlayer dielectric 425 and subsequently filling the trenches with a conductive material or a combination of conductive materials to form the metal contacts 420. In one or more embodiments, the conductive material filling the metal contacts 420 can include a silicide liner (e.g., titanium (Ti), nickel (Ni), nickel-platinum (NiPt) alloy, etc.), a metal adhesion liner (e.g., titanium nitride (TiN)), and a conductive metal (e.g., aluminum (Al), tungsten (W), copper (Co), ruthenium (Ru), or any combination thereof).

[0061] The conductive material can be deposited by suitable deposition processes such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, or sputtering. A planarization process (e.g., CMP) is performed to remove any conductive material from the upper surface of the semiconductor structure 100. In the depicted example, the metal contact 420 includes a top source / drain contact extending to the uppermost surface of each of the top source / drain regions 410 and a gate contact to the high-k metal gate stack 406.

[0062] Then, a BEOL interconnect layer 430 can be formed above the FEOL device layer 30. Although not depicted in the figures, the BEOL interconnect layer 430 generally includes contacts, insulating layers (dielectrics), metal layers, and bonding locations for chip-to-package connections, as may be known to those skilled in the art. As described above, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well-known, and thus, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0063] According to an embodiment, after forming the BEOL interconnect layer 430, the semiconductor structure 100 (i.e., semiconductor wafer) is bonded to a carrier wafer (or auxiliary substrate) 440. The carrier wafer 440 can act as a strengthening substrate for providing mechanical strength during the processing (e.g., thinning) of the semiconductor wafer. The process of bonding the semiconductor wafer to the carrier wafer 440 can be achieved by a conventional wafer bonding process, such as dielectric-to-dielectric bonding or Cu-to-Cu bonding.

[0064] Thus, the carrier wafer 440 can include a silicon oxide layer or a SiCN layer, or any other layer suitable for direct bonding techniques applied in existing technology packaging techniques. The bonding of the device wafer to the carrier wafer 440 is performed by such known direct bonding techniques, thereby obtaining Figures 4A to 4B the component shown in

[0065] Now referring to Figures 5A to 5B , a cross-sectional view of the semiconductor structure 100 after substrate removal according to an embodiment of the present disclosure is shown. In this embodiment, Figure 5A is a cross-sectional view of the semiconductor structure 100 taken along line X-X as shown in Figure 1 ; Figure 5B is a cross-sectional view of the semiconductor structure 100 taken along line Y-Y as shown in Figure 1 .

[0066] In the depicted embodiment, after flipping the wafer (not shown), the substrate 102 can be removed using conventional grinding, CMP, and selective etching processes including wet or dry etching techniques. According to an embodiment, the grinding process is performed until the substrate 102 is substantially removed from the semiconductor structure 100 and only a few microns of Si remain. Thereafter, an optional CMP process can be further used to reduce thickness variations, and finally a high-selectivity Si etching process is used to remove the remaining substrate 102 from the semiconductor structure 100. In the depicted embodiment, the first sacrificial layer 104 acts as an etch stop layer during the high-selectivity Si removal process, thereby preventing excessive Si etching that may damage the channel fins 304 and the high-k metal gate stack 406.

[0067] Now referring to Figures 6A to 6B , a cross-sectional view of the semiconductor structure 100 after removing the first sacrificial layer 104 according to an embodiment of the present disclosure is shown. In this embodiment, Figure 6A is a cross-sectional view of the semiconductor structure 100 taken along line X-X as shown in Figure 1 ; Figure 6B is a cross-sectional view of the semiconductor structure 100 taken along line Y-Y as shown in Figure 1 .

[0068] In the depicted embodiment, any suitable etching technique can be used to remove the first sacrificial layer 104 ( Figures 5A to 5B ). In an embodiment where the first sacrificial layer 104 ( Figures 5A-5B ) is made of SiGe, thermal SC1 or dry HCl etching can be used to remove the first sacrificial layer 104. In an embodiment where the first sacrificial layer 104 ( Figures 5A to 5B ) is made of SiO2, DHF wet cleaning can be used to remove the first sacrificial layer 104.

[0069] Now referring to Figures 7A to 7B , a cross-sectional view of a semiconductor structure 100 after forming a first backside interlayer dielectric (BILD) 750 according to an embodiment of the present disclosure is shown. In this embodiment, Figure 7A is a cross-sectional view of the semiconductor structure 100 taken along the line X-X shown in Figure 1 ; and Figure 7B is a cross-sectional view of the semiconductor structure 100 taken along the line Y-Y shown in Figure 1 .

[0070] The first BILD 750 is formed using standard methods and materials, such as those described above with reference to Figures 4A-4B for forming the interlayer dielectric 425. The first BILD 750 is disposed above and in direct contact with the bottommost surface of the channel fin 304 and the bottommost surface of the bottom spacer 402, as shown. In an exemplary embodiment, the thickness of the first BILD 750 can vary between about 40 nm and about 300 nm, and ranges therebetween. In one or more embodiments, a planarization process (e.g., CMP) can be performed on the semiconductor structure 100 after forming the first BILD 750.

[0071] Now referring to Figures 8A to 8B , a cross-sectional view of a semiconductor structure 100 after forming a plurality of backside contact openings 810 (hereinafter referred to as "backside contact openings") according to an embodiment of the present disclosure is shown. In this embodiment, Figure 8A is a cross-sectional view of the semiconductor structure 100 taken along the line X-X shown in Figure 1 ; Figure 8B is a cross-sectional view of the semiconductor structure 100 taken along the line Y-Y shown in Figure 1 .

[0072] As is known to those skilled in the art, patterning the first BILD 750 to form the back contact opening 810 involves exposing the pattern on a photoresist layer (not shown) and transferring the exposed pattern to the first BILD 750. After transferring the pattern and forming the back contact opening 810, any photoresist stripping method known in the art (including, for example, plasma ashing) can be used to remove the photoresist layer. As shown, the back contact opening 810 exposes the bottommost surface of the channel fin 304 and a portion of the bottom spacer 402.

[0073] Now referring to Figures 9A to 9B , a cross-sectional view of the semiconductor structure 100 after forming the trench epitaxial layer 920 on the exposed portion of the channel fin 304 according to an embodiment of the present disclosure is shown. In this embodiment, Figure 9A is a cross-sectional view of the semiconductor structure 100 taken along line X-X as shown in Figure 1 ; Figure 9B is a cross-sectional view of the semiconductor structure 100 taken along line Y-Y as shown in Figure 1 .

[0074] In one or more embodiments, the trench epitaxial layer 920 can be epitaxially grown using, for example, VPE, MBE, or LP. A low-temperature epitaxial process is highly preferred because it causes a large threshold voltage shift in the formed gate at temperatures above about 500°C. In some embodiments, the trench epitaxial layer 920 includes a material similar to the top source / drain region 410 and the same dopant concentration. In other words, the trench epitaxial layer 920 is made compatible with the corresponding top source / drain region 410, i.e., if the top source / drain region 410 is n-type (NFET), then the trench epitaxial layer 920 is also n-type, and if the top source / drain region 410 is p-type (PFET), then the trench epitaxial layer 920 is also p-type act.

[0075] For example, the trench epitaxial layer 920 can be formed to have the crystal structure of the underlying layer. In this case, the trench epitaxial layer 920 can be grown to have the crystal structure of the channel fin 304, and the trench epitaxial layer 920 is the bottom source / drain region of the transistor. In an exemplary embodiment, for an NFET device, the trench epitaxial layer 920 can be formed as silicon doped with phosphorus (Si:P), silicon doped with arsenic (Si:As), etc., and for a PFET device, the trench epitaxial layer 920 can be formed as silicon doped with boron Si:B, germanium doped with boron (Ge:B), silicon germanium doped with boron (SiGe:B), etc.

[0076] Thus, the trench epitaxial layer 920 provides a bottom source / drain region 940 to the semiconductor structure 100. As can be observed in the figure, the (backside) trench epitaxial layer 920 contacts a first (bottom) surface of the channel fin 304, which is opposite to a second (top) surface of the channel fin 304, and the second (top) surface contacts the top source / drain region 410. In an exemplary embodiment, the trench epitaxial layer 920 may be formed to have a thickness varying from about 10 nm to about 50 nm, but other thicknesses are also within the scope contemplated by the present invention. In one or more embodiments, the trench epitaxial layer 920 partially contacts the bottom spacer 402. It should be noted that in some embodiments, according to design requirements, the backside contact opening 810 ( Figures 8A-8B ) may expose regions corresponding to two adjacent channel fins 304, as Figure 8A shown. In this case, after the trench epitaxial layer 920 is formed, a space or gap 960 may be reserved between adjacent channel fins 304, as Figure 9A shown.

[0077] As may be known to those skilled in the art, the diamond / triangular shape observed in the trench epitaxial layer 920 for forming the bottom source / drain region 940 may be a result of different growth rates inherent in each crystal orientation plane of the material forming the trench epitaxial layer 920 during the epitaxial deposition process. The diamond shape provides more surface area for physical contact with the trench epitaxial layer 920. In other embodiments, the trench epitaxial layer 920 may have a shape other than the Figure 9A diamond shape depicted therein.

[0078] Now referring to Figures 10A-10B , a cross-sectional view of the semiconductor structure 100 after backside contact metallization according to an embodiment of the present disclosure is shown. In this embodiment, Figure 10A is a cross-sectional view of the semiconductor structure 100 taken along line X-X as shown in Figure 1 ; and Figure 10B is a cross-sectional view of the semiconductor structure 100 taken along line Y-Y as shown in Figure 1 .

[0079] In this embodiment, the space 960 between the backside contact opening 810 ( Figures 8A-8B ) and the adjacent channel fins 304 can be substantially filled by deposition ( Figure 9AA conductive material is used to form the backside metal contact 1012 in the semiconductor structure 100. Similar conductive materials and similar deposition processes used to form the metal contact 420 can be used to form the backside metal contact 1012. In some embodiments, the backside metal contact 1012 can be formed by depositing layers such as a silicide liner (such as Ti, Ni, NiPt), an adhesion metal liner (such as TiN), and a low-resistance metal (such as Ru, Co, W, or Cu).

[0080] In one or more embodiments, the backside metal contact 1012 can be formed above and in direct contact with adjacent bottom source / drain regions 940 (channel fins 304≥2) within the N2N space of the NFET region 12 (depicted in Figure 1 of the semiconductor structure 100) or within the P2P space of the PFET region 16 (also depicted in Figure 1 ). In such embodiments, the conductive material forming the backside metal contact 1012 is deposited between adjacent bottom source / drain regions 940, substantially filling the space 960 (shown in Figure 9A ) between adjacent channel fins 304. By filling the space 960 ( Figure 9A ) between adjacent channel fins 304, the backside metal contact 1012 can partially wrap a portion of the trench epitaxial layer 920 (i.e., the bottom source / drain region 940) to increase the contact area. Thus, the backside metal contact 1012 at least partially surrounds adjacent bottom source / drain regions 940.

[0081] Now referring to Figures 11A-Figure 11B , a cross-sectional view of the semiconductor structure 100 after forming the backside interconnect structure 1130 according to an embodiment of the present disclosure is shown. In this embodiment, Figure 11A is a cross-sectional view of the semiconductor structure 100 taken along line X-X as shown in Figure 1 ; and Figure 11B is a cross-sectional view of the semiconductor structure 100 taken along line Y-Y as shown in Figure 1 .

[0082] The backside interconnect structure 1130, briefly depicted, can include, for example, Cu-based metal lines and vias made according to known techniques. According to an embodiment, the backside metal contact 1012 can be electrically connected to the backside interconnect structure 1130. Specifically, the backside metal contact 1012 contacts the bottom surface of the backside interconnect structure 1130.

[0083] The resulting semiconductor structure 100 includes a VFET device with self-aligned backside trench epitaxy that provides bottom source / drain regions for the semiconductor structure 100. Embodiments of the present disclosure provide additional options for forming the bottom source / drain regions of the VFET device using a backside interconnect process. In the proposed embodiments, the backside interconnect process may not be limited to power supplies, and they can also be used for signal routing.

[0084] The previously described embodiments provide a semiconductor structure and a method of manufacturing the same, including channel fins extending vertically from bottom source / drain regions of a field-effect transistor, the bottom source / drain regions including a trench epitaxial layer located below the bottommost surface of the channel fins, a high-k metal gate stack disposed along the sidewalls of the channel fins, the high-k metal gate being separated from the bottom source / drain regions by a bottom spacer, and top source / drain regions located above the topmost surface of the channel fins, the top source / drain regions being separated from the high-k metal gate by a top spacer.

[0085] In one or more embodiments, a first side of the trench epitaxial layer is in direct contact with the channel fin, and a second side of the trench epitaxial layer opposite the first side of the trench epitaxial layer is in direct contact with a backside metal contact. In one or more embodiments, the trench epitaxial layer is epitaxially grown using a low-temperature epitaxy process, and the trench epitaxial layer includes a material similar to and having the same dopant concentration as the top source / drain regions.

[0086] Embodiments of the present disclosure also include a front-end-of-line layer including a field-effect transistor, the front-end-of-line layer being electrically connected to a back-end-of-line interconnect layer located on a first side of the front-end-of-line layer, the field-effect transistor including a vertical field-effect transistor, and a backside interlayer dielectric that surrounds the bottom source / drain regions and is located on a second side of the front-end-of-line layer opposite the first side of the front-end-of-line layer.

[0087] Embodiments of the present disclosure also include a metal contact within the interlayer dielectric that is in electrical contact with the uppermost surface of the top source / drain regions, and a backside metal contact within the backside interlayer dielectric that is electrically connected to the bottom source / drain regions and is vertically aligned with the bottom source / drain regions. The backside metal contact is composed of a conductive material including at least one of Ru, Cu, Co, W, and Al.

[0088] In one or more embodiments, the backside metal contact fills a region between two adjacent bottom source / drain regions that partially surrounds a portion of the two adjacent bottom source / drain regions.

[0089] In one or more embodiments, the semiconductor structure further includes a backside interconnect structure electrically connected to the backside metal contact, and a carrier wafer in contact with a surface of the BEOL interconnect layer, the surface being opposite the top source / drain regions and the metal contacts.

[0090] The methods described above are used to fabricate integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in the form of the original wafer (i.e., as a single wafer with multiple unpackaged chips), as die, or in packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with either or both surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices, as part of (a) an intermediate product such as a motherboard or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with a display, keyboard, or other input device and a central processing unit.

[0091] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Optional" or "optionally" means that the subsequent described event or circumstance may or may not occur, and the description includes instances where the event occurs and instances where it does not.

[0092] Spatial relative terms, such as "inner", "outer", "beneath", "below", "lower", "above", "upper", "top", "bottom", etc., may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "beneath" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary term "below" can cover both an above and a below orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein are to be interpreted accordingly.

[0093] As used throughout the specification and claims of this document, approximate language may apply to modify any quantitative representation that can vary permissibly without resulting in a change in the basic function associated therewith. Thus, values modified by one or more terms such as "about", "approximately", and "substantially" are not limited to the specified exact values. In at least some instances, the approximate language may correspond to the precision of the instrument used to measure the value. Herein, as well as throughout the specification and claims, range limitations may be combined and / or interchanged, and these ranges are identified and include all the sub-ranges subsumed therein, unless the context or language indicates otherwise. "About" applied to a particular value of a range applies to both values and may indicate + / - 10% of the value, unless otherwise dependent on the precision of the instrument used to measure the value.

[0094] The description of the various embodiments of the invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: A channel fin extending vertically from a bottom source / drain region of a field effect transistor, the bottom source / drain region including a trench epitaxial layer located below a bottommost surface of the channel fin; A high-k metal gate stack disposed along a sidewall of the channel fin, the high-k metal gate being separated from the bottom source / drain region by a bottom spacer; And A top source / drain region located above a topmost surface of the channel fin, the top source / drain region being separated from the high-k metal gate by a top spacer.

2. The semiconductor structure according to claim 1, further comprising: A front-end-of-line (FEOL) layer including the field effect transistor, the FEOL layer being electrically connected to a back-end-of-line (BEOL) interconnect layer located on a first side of the FEOL layer, wherein the field effect transistor is a vertical field effect transistor; And A backside interlayer dielectric surrounding the bottom source / drain region and located on a second side of the FEOL layer opposite to the first side of the FEOL layer.

3. The semiconductor structure according to claim 2, further comprising: A metal contact within the interlayer dielectric, the metal contact being in electrical contact with a topmost surface of the top source / drain region.

4. The semiconductor structure according to claim 2, further comprising: A backside metal contact within the backside interlayer dielectric, the backside metal contact being electrically connected to the bottom source / drain region and vertically aligned with the bottom source / drain region.

5. The semiconductor structure according to claim 4, wherein the backside metal contact fills a region between two adjacent bottom source / drain regions, the region partially surrounding a portion of the two adjacent bottom source / drain regions.

6. The semiconductor structure according to claim 4, further comprising: A backside interconnect structure electrically connected to the backside metal contact.

7. The semiconductor structure according to claim 3, further comprising: A carrier wafer in contact with a surface of the BEOL interconnect layer opposite to the top source / drain region and the metal contact.

8. The semiconductor structure according to claim 4, wherein, The backside metal contact is composed of a conductive material including at least one of Ru, Cu, Co, W, and Al.

9. The semiconductor structure according to claim 4, wherein a first side of the trench epitaxial layer is in direct contact with the channel fin, and a second side of the trench epitaxial layer opposite to the first side of the trench epitaxial layer is in direct contact with the backside metal contact.

10. The semiconductor structure according to claim 1, wherein the trench epitaxial layer is epitaxially grown using a low-temperature epitaxy process, and wherein the trench epitaxial layer includes a material similar to the top source / drain region and the same dopant concentration.

11. A method of forming a semiconductor structure, comprising: Forming a channel fin extending vertically from a bottom source / drain region of a field effect transistor, the bottom source / drain region including a trench epitaxial layer located below a bottommost surface of the channel fin; Form a high-k metal gate stack disposed along the sidewalls of the channel fin, the high-k metal gate being separated from the bottom source / drain region by a bottom spacer; and Form a top source / drain region located above the topmost surface of the channel fin, the top source / drain region being separated from the high-k metal gate by a top spacer.

12. The method according to claim 11, further comprising: Form a front-end-of-line (FEOL) layer including the field-effect transistor, the FEOL layer being electrically connected to a back-end-of-line (BEOL) interconnect layer located on a first side of the FEOL layer, wherein the field-effect transistor is a vertical field-effect transistor; and Form a backside interlayer dielectric surrounding the bottom source / drain region and located on a second side of the FEOL layer opposite the first side of the FEOL layer.

13. The method according to claim 12, further comprising: Form a metal contact within the interlayer dielectric, the metal contact being in electrical contact with the topmost surface of the top source / drain region.

14. The method according to claim 12, further comprising: Form a backside metal contact within the backside interlayer dielectric, the backside metal contact being electrically connected to the bottom source / drain region and vertically aligned with the bottom source / drain region.

15. The method according to claim 14, wherein the backside metal contact fills a region between two adjacent bottom source / drain regions, the region partially surrounding a portion of the two adjacent bottom source / drain regions.

16. The method according to claim 14, further comprising: Form a backside interconnect structure electrically connected to the backside metal contact.

17. The method according to claim 13, further comprising: Form a carrier wafer in contact with a surface of the BEOL interconnect layer opposite the top source / drain region and the metal contact.

18. The method according to claim 14, wherein, The backside metal contact is composed of a conductive material including at least one of Ru, Cu, Co, W, and Al.

19. The method according to claim 14, wherein a first side of the trench epitaxial layer is in direct contact with the channel fin, and a second side of the trench epitaxial layer opposite the first side of the trench epitaxial layer is in direct contact with the backside metal contact.

20. The method according to claim 11, wherein the trench epitaxial layer is epitaxially grown using a low-temperature epitaxy process, and wherein the trench epitaxial layer includes a material similar to the top source / drain region and the same dopant concentration.

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