Semiconductor structure, semiconductor device and preparation method of semiconductor structure

Abstract

The invention discloses a semiconductor structure, a semiconductor device and a preparation method of a semiconductor, and the semiconductor structure comprises a wafer which is divided into a plurality of semiconductor chip regions and a cutting channel region located between two adjacent semiconductor chips; the closed ring structure is arranged between the chip area and the cutting channel area; the cutting channel region is fully paved with the metal cushion layer, and the metal cushion layer is located on the side, close to the wafer, of the cutting channel region; and the pseudo-closed ring structure fills the cutting channel region and is arranged on the metal cushion layer. The low dielectric material or the silicon oxide material in the cutting channel region is divided into a plurality of small blocks by the metal cushion layer and the pseudo closed ring structure, so that the chip and the closed ring structure can be effectively prevented from being damaged in the wafer cutting process.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure, a semiconductor device, and a method for fabricating the semiconductor structure. Background Technology

[0002] In the semiconductor manufacturing process, multiple chips and dicing lines are formed on a wafer to separate these chips. Cutting is performed along these dicing lines to divide the entire wafer into chips. However, during the cutting process, low-dielectric or oxide materials in the dicing lines are prone to cracking or splitting.

[0003] Therefore, how to prevent cracks or fissures in the material within the dicing channel during wafer dicing remains a pressing issue that needs to be addressed. Summary of the Invention

[0004] Based on this, this application provides a conductor structure, a semiconductor device, and a method for fabricating a semiconductor structure, which can prevent cracks or fissures from forming in the material within the dicing channel during wafer dicing.

[0005] On one hand, according to some embodiments, this application provides a semiconductor structure, characterized in that it includes:

[0006] A wafer, the wafer being divided into multiple chip regions and dicing channels located between two adjacent chip regions;

[0007] A closed-loop structure is disposed between the chip region and the dicing channel region;

[0008] A metal pad, the metal pad covering the dicing area, the metal pad being located on the side of the dicing area closest to the wafer;

[0009] A pseudo-closed ring structure, which fills the cutting channel area, is disposed on the metal pad layer.

[0010] In some embodiments, the cutting channel region includes an enhanced structure region and a linear structure region;

[0011] The enhanced structural region is located close to the closed-loop structure;

[0012] The linear structure region is located on the side of the reinforced structure region away from the closed ring structure.

[0013] In some embodiments, the pseudo-closed loop structure in the enhanced structural region includes contacts and interconnects;

[0014] The metal pad, the contact, and the interconnect are connected sequentially in a direction perpendicular to the wafer;

[0015] The interconnects of two adjacent pseudo-closed ring structures are partially connected.

[0016] In some embodiments, the interconnection portions of the two adjacent pseudo-closed loop structures are connected in an alternating manner.

[0017] In some embodiments, the pseudo-closed loop structure of the linear structure region includes a first linear pseudo-closed loop structure and a second linear pseudo-closed loop structure;

[0018] The first linear pseudo-closed ring structure includes a third contact and a third interconnect, the metal pad, the third contact and the third interconnect are connected sequentially in a direction perpendicular to the wafer;

[0019] The second linear pseudo-closed loop structure includes a fourth interconnect line, which is disposed above the metal pad layer;

[0020] The first linear pseudo-closed ring structure and the second linear pseudo-closed ring structure are not arranged continuously.

[0021] In some embodiments, the first linear pseudo-closed ring structure and the second linear pseudo-closed ring structure are not arranged continuously.

[0022] In some embodiments, the projection pattern of the contact within the cutting channel area is a closed ring;

[0023] The projection pattern of the interconnect line within the cutting channel area is a closed ring.

[0024] On the other hand, according to some embodiments, this application also provides a semiconductor device, including:

[0025] chip;

[0026] A dicing channel that surrounds the chip;

[0027] A closed-loop structure is disposed between the chip and the dicing channel;

[0028] A metal padding layer that covers the cutting groove;

[0029] A pseudo-closed ring structure is provided, which fills the cutting channel and is located on the metal pad layer.

[0030] In some embodiments, the cutting channel includes a reinforced structural region disposed near the closed loop structure;

[0031] The pseudo-closed loop structure in the enhanced structural region includes contacts and interconnects;

[0032] The metal pad, the contact, and the interconnect are connected sequentially in a direction perpendicular to the wafer;

[0033] The interconnecting lines of two adjacent pseudo-closed ring structures are partially connected;

[0034] The interconnecting positions of the two adjacent pseudo-closed ring structures are staggered.

[0035] In some embodiments, the cutting channel further includes a linear structure region disposed on the side of the reinforced structure region away from the closed ring structure;

[0036] The pseudo-closed ring structure of the linear structure region includes a first linear pseudo-closed ring structure, which includes a third contact and a third interconnect, the metal pad, and the third contact and the third interconnect are connected sequentially in a direction perpendicular to the wafer.

[0037] The pseudo-closed ring structure of the linear structure region includes a second linear pseudo-closed ring structure;

[0038] The second linear pseudo-closed loop structure includes a fourth interconnect line, which is disposed above the metal pad layer.

[0039] On the other hand, according to some embodiments, this application also provides a method for fabricating a semiconductor structure, including:

[0040] A wafer is provided, the wafer including a plurality of chip regions and a dicing channel region between two adjacent chip regions, the dicing channel region including an enhancement structure region and a linear structure region, the enhancement structure region being disposed close to a closed ring structure, and the linear structure region being disposed on the side of the enhancement structure region away from the closed ring structure;

[0041] A closed-loop structure is formed, wherein the closed-loop structure is disposed between the chip region and the dicing channel region;

[0042] A metal pad is formed within the cutting groove area and covers the entire cutting groove area;

[0043] A pseudo-closed ring structure is formed, which fills the cutting channel area and is formed on the metal pad layer.

[0044] In some embodiments, contacts are formed on the metal pad, the contacts being discrete from each other, and the projected pattern within the cutting channel area is a closed ring.

[0045] Interconnecting lines are formed, and the projection pattern of the interconnecting lines within the cutting channel area is a closed ring.

[0046] Two adjacent interconnects formed in the enhanced structure region are partially connected, and the locations of the partial connections are staggered.

[0047] The interconnects formed in the linear structure region include fourth interconnects that are connected to a contact and fourth interconnects that are not connected to a contact.

[0048] The third interconnect line that is connected to the contact and the fourth interconnect line that is not connected to the contact are not arranged discontinuously.

[0049] The semiconductor structure and its fabrication method provided in this application have at least the following beneficial effects:

[0050] The semiconductor structure, semiconductor device, and semiconductor structure fabrication method provided in this application form a metal pad layer in the dicing channel and cover the entire dicing channel. A pseudo-closed ring structure is then filled in the dicing channel. The pseudo-closed ring structure is formed on the metal pad layer. Together with the metal pad layer, the pseudo-closed ring structure divides the low-dielectric material or oxide material in the dicing channel into many small pieces. This effectively prevents the low-dielectric material or oxide material in the dicing channel from cracking or generating gaps during the wafer dicing process. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A schematic plan view of a semiconductor structure provided for some embodiments of this application;

[0053] Figure 2 Some embodiments of this application Figure 1 A partial plan view of region A of the provided semiconductor structure;

[0054] Figure 3 Some embodiments of this application Figure 1 A partially magnified planar view of region A of the provided semiconductor structure;

[0055] Figure 4 This is a schematic diagram of the cross-sectional structure of a semiconductor structure provided in some embodiments of this application;

[0056] Figure 5 Some embodiments of this application Figure 3 A schematic diagram of the cross-sectional structure of the provided semiconductor structure along the tangent line AA;

[0057] Figure 6 Some embodiments of this application Figure 3 A schematic diagram of the cross-sectional structure of the provided semiconductor structure along the BB tangent;

[0058] Figure 7 Some embodiments of this application Figure 3 A schematic diagram of the cross-sectional structure of the provided semiconductor structure along the CC tangent;

[0059] Figure 8a , Figure 8b and Figure 8c Some embodiments of this application Figure 3 A partially enlarged planar view of region 402 of the provided semiconductor structure;

[0060] Figure 9 Some embodiments of this application Figure 1 A partial plan view of region B of the provided semiconductor structure;

[0061] Figure 10 Some embodiments of this application Figure 1 A partial plan view of region C of the provided semiconductor structure;

[0062] Figure 11 For other embodiments of this application Figure 1 A partial plan view of region C of the provided semiconductor structure;

[0063] Explanation of reference numerals in the attached figures:

[0064] 1. Chip area; 101. Chip; 2. Closed-loop structure; 3. Cut-out area; 4. Pseudo-closed-loop structure; 401. Enhanced pseudo-closed-loop structure; 402. Linear pseudo-closed-loop structure; 6. First linear pseudo-closed-loop structure; 7. Second linear pseudo-closed-loop structure; 8. Metal pad; 9. Contact; 901. First contact; 902. Second contact; 903. Third contact; 10. Interconnect; 1001. First interconnect; 1002. Second interconnect; 1003. Third interconnect; 1004. Fourth interconnect. Detailed Implementation

[0065] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0067] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to," it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first doped region may be referred to as a second doped region, and similarly, a second doped region may be referred to as a first doped region; the first doped region and the second doped region are different doped regions.

[0068] Spatial relation terms such as “on top of” can be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, the element or feature described as “on top of” will be oriented “below” other elements or features. Therefore, the exemplary term “on top of” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0069] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0070] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0071] Figure 1A schematic plan view of the semiconductor structure provided for some embodiments of this application. Please refer to... Figure 1 The wafer includes multiple chip regions 1 and dicing channels 3 between adjacent chip regions. In this embodiment, the multiple chip regions 1 can be formed on the wafer in an array. The wafer can be a silicon wafer, silicon-germanium wafer, silicon carbide wafer, silicon-on-insulator (SOI) wafer, germanium-on-insulator (GOI) wafer, glass wafer, III-V compound wafer (e.g., silicon nitride or gallium arsenide), oxide semiconductor wafer, or other dicable wafers. The size of the wafer can be 6 inches, 8 inches, or 12 inches and is not limited. The chip regions 1 can form computing chips, memory chips, image chips, and other chips fabricated on the wafer, including multiple devices (not shown). The chip regions 1 can be arranged in an array of rectangles or squares on the wafer according to design requirements, and the size and formation of the chip regions 1 are not specifically limited. Dice channels 3 are provided between adjacent chip regions 1, and the dicing channels 3 are arranged in a grid pattern, dividing the wafer into multiple individual chip regions 1. In some disclosed embodiments, the dicing area is filled with a low-dielectric material or some silicon oxide material (not shown). During the wafer dicing process, the low-dielectric material or silicon oxide material is subjected to high temperature and stress, which may cause it to crack, thereby affecting the dicing quality and even damaging the devices in the chip.

[0072] Figure 2 Some embodiments of this application Figure 1 A partial plan view of region A of the provided semiconductor structure. (Reference) Figure 2 The wafer also includes a closed-loop structure 2, which surrounds each chip 101 and is located between the chip 101 and the dicing area 3. In this embodiment, the closed-loop structure can be a single ring, two rings, or multiple rings. During the wafer dicing process, the closed-loop structure can protect the devices in the chip from damage.

[0073] Continue to refer to Figure 2 A pseudo-closed ring structure 4 is provided in the cutting channel area 3. The pseudo-closed ring structure 4 is arranged side by side with the closed ring structure 2. The distance between adjacent pseudo-closed ring structures 4 can be greater than the distance between adjacent closed rings 2. The shape of the pseudo-closed ring structure 4 can be the same as the shape of the closed ring structure 2, or partially the same, partially different, or completely different from the shape of the closed ring structure 2. The pseudo-closed ring structure 4 divides the cutting channel area 3 into blocks of different sizes. In this way, the stress on the low dielectric material or silicon oxide material in the cutting channel 3 during the cutting process will also be decomposed, and the cracks or fissures will be correspondingly interrupted, which can more easily protect the devices in the chip area 1 from damage.

[0074] Figure 3 Some embodiments of this application Figure 1A partially enlarged planar view of region A of the provided semiconductor structure. Specifically, in some embodiments of this application, the dicing region 3 may include an enhancement structure region and a linear structure region. The enhancement structure region is closer to the closed ring 2, and the linear structure region is located on the side of the enhancement structure region away from the closed ring 2. This can be understood as the tangent line from one chip 101 to an adjacent chip 110 including chip 101 - closed ring structure 2 - enhancement structure region - linear structure region - enhancement structure region - closed ring structure 2 - chip 101. The sizes of the enhancement structure region and the linear structure region can be set according to the size of the dicing channel. For example, when the size of the dicing region 3 is 30μm, 40μm, 50μm, or 60μm, the enhancement structure region can be smaller than the linear structure region. The size of the enhancement structure region can be large, for example, 5μm, 8μm, 10μm or 12μm. When the size of the dicing region 3 is 65μm, 75μm, 85μm or 100μm, the size of the enhancement structure region can be 15μm, 18μm, 21μm or 25μm. The size of the dicing region 3, as well as the size and ratio of the enhancement structure region and the linear structure region, are not limited and can be adjusted according to design requirements. Although the pseudo-closed ring structure 4 of the enhancement structure region and the linear structure region have different shapes, they both divide the low dielectric material or silicon oxide material in the dicing region into many small pieces, which can effectively prevent the chip 101 and the closed ring 2 from being damaged during the wafer dicing process.

[0075] Continue to refer to Figure 3 An enhanced structure region and a linear structure region are simultaneously set in the dicing zone 3. The enhanced structure region is closer to the chip region 1 and the closed ring structure. Since the linear structure region is easier to cut, it can prevent the cutter or laser from shifting towards the chip 101 or the closed ring structure 2 during wafer dicing.

[0076] Figure 4 Some embodiments of this application Figure 3 A schematic cross-sectional view of the provided semiconductor structure is shown. The dicing zone 3 includes a metal pad 8, contacts 9, and interconnects 10, which are stacked and connected in a direction perpendicular to the wafer surface to form a single unit. In some embodiments, the projection shape of the contacts 9 and interconnects 10 in the dicing zone is a closed ring, which can serve as a closed ring structure during wafer dicing, effectively preventing damage to the chip 1 and the closed ring 2.

[0077] Figure 5 , Figure 6 and Figure 7 These are some embodiments of this application. Figure 3The provided semiconductor structure is shown in the cross-sectional diagram along the tangents AA, BB, and CC. Specifically, in some embodiments, a metal pad 8 is provided in the dicing region 3. The metal pad 8 is located on the side of the dicing region 3 closest to the wafer, i.e., at the bottom of the dicing region 3. The material of the metal pad 8 can be copper, tungsten, aluminum, cobalt, nickel, or a compound of two or more of the above metals. In addition, the metal pad 8 can also be multilayered, with one or more barrier material layers (not shown) formed around the metal pad 8 to prevent the metal material of the metal pad 8 from diffusing into the dielectric layer in the dicing region. At the same time, it can also improve the adhesion between the metal pad 8 and the dielectric material in the dicing region 3, preventing cracks from appearing between the metal pad 8 and the dielectric material. The material of the barrier layer can be one or more of titanium, titanium nitride, tantalum, and tantalum nitride. The metal pad 8 is a whole in the dicing region, covering the entire dicing region 3. This makes the pseudo-closed ring structure 4 in the dicing region 3 a whole, strengthening the pseudo-closed ring junction structure 4 in the dicing region 3. During the dicing process, it can better prevent the breakage of low dielectric materials or silicon oxide materials.

[0078] Continue to refer to Figure 4 , Figure 5 and Figure 6 In some embodiments, the pseudo-closed ring structure 4 formed in the enhanced structure region can be an enhanced pseudo-closed ring structure 401. The enhanced pseudo-closed ring structure 401 includes two parts: a contact 9 and an interconnect 10. The contact 9 is connected to the metal pad layer 8, and the interconnect 10 is located above the contact 9 and connected to the contact 9. In the direction perpendicular to the wafer, the metal pad layer 8, the contact 9, and the interconnect 10 are stacked sequentially to form a whole. The material of the contact 9 can be copper, tungsten, aluminum, cobalt, nickel, or a compound of two or more of the above metals. In addition, a barrier material layer (not shown) can be placed around the contact 9 to prevent the metal material of the contact 9 from diffusing into the dielectric layer in the dicing channel. At the same time, it can also improve the adhesion between the contact 9 and the dielectric material in the dicing channel region 3 and prevent cracks from appearing between the contact 9 and the dielectric material. The material of the barrier layer can be one or more of titanium, titanium nitride, tantalum, and tantalum nitride. Interconnect 10 may include multiple layers of metal interconnects and metal plug structures between the metal interconnects. In some embodiments, it may include a 3-layer metal interconnect and 2-layer plug structure, a 4-layer metal interconnect and 3-layer plug structure, a 5-layer metal interconnect and 4-layer plug structure, or other multi-layer metal interconnect and plug structures. The material of interconnect 10 may be copper, tungsten, aluminum, cobalt, nickel, or compounds of two or more of the above metals. Alternatively, one layer of the interconnect may be copper, and another layer may be tungsten or aluminum, or the metal materials between different layers may be different. The plug materials between the metal layers may also be different. (Reference) Figure 5In some embodiments, the enhanced pseudo-closed-loop structure 401 includes a first interconnect 1001 connecting adjacent interconnects together, and a first contact 901 connected to the first interconnect 1001, the first contact 901 being connected to the metal pad 8. Similarly, refer to... Figure 6 The second contact 902 and the second interconnect 1002 of the enhanced pseudo-closed-loop structure 401 are independent of each other, and adjacent enhanced pseudo-closed-loop structures 401 are arranged side by side. (Reference) Figure 3 In some embodiments, the positions of the first interconnect 1001 are staggered, that is, the enhanced pseudo-closed ring structure 401 has a wall-like structure. In this way, the adjacent pseudo-closed ring structures are independent of each other and support each other to enhance strength, dividing the low dielectric material or silicon oxide material in the dicing area 3 into smaller blocks. When the wafer is diced, the damage to the devices in the chip 101 can be better reduced.

[0079] refer to Figure 3 and Figure 7 The pseudo-closed-loop structures in the linear structure region are arranged in rows outside the reinforced structure region. These pseudo-closed-loop structures in the linear structure region are linear pseudo-closed-loop structures 402, and the spacing between the linear pseudo-closed-loop structures 402 is greater than or equal to the spacing between the reinforced pseudo-closed-loop structures 401. The linear pseudo-closed-loop structures 402 may include a first linear pseudo-closed-loop structure 6 that has contact with and is connected to the metal pad 8, and a second linear pseudo-closed-loop structure 7 that does not have contact and is not connected to the metal pad 5. (Reference) Figure 7 The first linear pseudo-closed ring structure 6 includes a third contact 903 and a third interconnect 1003. The metal pad 8, the third contact 903, and the third interconnect 1003 are stacked sequentially in a direction perpendicular to the wafer to form a closed ring structure. The material of the third contact 903 can be copper, tungsten, aluminum, cobalt, nickel, or a compound of two or more of these metals. Furthermore, a barrier material layer (not shown) can be present around the third contact 903 to prevent the metal material from diffusing into the dielectric layer in the dicing area. This barrier layer also improves the adhesion between the third contact 903 and the dielectric material in the dicing area, preventing cracks from forming between the third contact 903 and the dielectric material. The barrier layer can be one or more of titanium, titanium nitride, tantalum, and tantalum nitride. The third interconnect 1003 can include multiple layers of metal interconnects and metal plug structures between the metal interconnects. In some embodiments, it can include a 3-layer metal interconnect and a 2-layer plug structure, a 4-layer metal interconnect and a 3-layer plug structure, a 5-layer metal interconnect and a 4-layer plug structure, or other multi-layer metal interconnect and plug structures. The material of interconnect 1003 can be copper, tungsten, aluminum, cobalt, nickel, or a compound of two or more of the above metals. Alternatively, one layer of the third interconnect 1003 can be copper, and the other layer can be tungsten or aluminum. Or, the metal materials of different layers can be different, and the plug materials between the metal layers can also be different.

[0080] Continue to refer to Figure 7 The linear pseudo-closed ring structure 402 also includes a second linear pseudo-closed ring structure 7 that does not have contact and is not connected to the metal pad layer 8. The second linear pseudo-closed ring structure 7 only has a fourth interconnect structure 1004, has no contact, is not connected to the metal pad layer 8, and is located in the low-dielectric material or silicon oxide material in the dicing area, and is on the same plane as the third interconnect 1003 in the first linear pseudo-closed ring structure 6. The second linear pseudo-closed ring structure 7 does not have contact, which can reduce the process burden of etching contact holes during contact layer preparation, saving material and time costs. At the same time, the stress of the dicing area can be adjusted by adjusting the number of contacts.

[0081] Figure 8a , Figure 8b and Figure 8c Some embodiments of this application Figure 3 The provided magnified plan view of region 402 of the semiconductor structure is for reference. Figure 7 The first linear pseudo-closed loop structure 6 and the second linear pseudo-closed loop structure 7 are not arranged continuously. The number of consecutive arrangements of the first linear pseudo-closed loop structure 6 does not exceed 5, and the number of consecutive arrangements of the second linear pseudo-closed loop structure 7 does not exceed 5. In some embodiments, the first linear pseudo-closed loop structure 6 and the second linear pseudo-closed loop structure 7 are arranged alternately, that is, one first linear pseudo-closed loop structure 6 and one second linear pseudo-closed loop structure 7 constitute a unit, and are repeatedly arranged, for example... Figure 8b As shown; in some embodiments, two first linear pseudo-closed loop structures 6 and two second linear pseudo-closed loop structures 7 are arranged alternately, that is, two first linear pseudo-closed loop structures 6 and two second linear pseudo-closed loop structures 7 form a unit and are repeatedly arranged, for example... Figure 6 As shown; similarly, two first linear pseudo-closed loop structures 6 and three pseudo-closed loop structures 7 are arranged alternately, that is, two first linear pseudo-closed loop structures 6 and three second linear pseudo-closed loop structures 7 form a unit, and are repeatedly arranged, for example. Figure 8a As shown; a first linear pseudo-closed loop structure 6 and three second linear pseudo-closed loop structures 7 are arranged alternately, that is, one first linear pseudo-closed loop structure 6 and three second linear pseudo-closed loop structures 7 form a unit, which are repeated. For example... Figure 8c As shown.

[0082] refer to Figure 2 and Figure 9 , Figure 9 These are some embodiments of this application. Figure 1A partial plan view of region B of the provided semiconductor structure. The pseudo-closed ring structure 4 projects onto the dicing area 3 in a closed ring shape. The pseudo-closed ring structure 4 extends from the four corners of chip 101 along its four sides, with the corner shapes identical to those in region A. Contact 9 connects to the metal pad 8, and its projection onto the dicing area 3 is also a closed ring. Interconnect line 10 connects to contact 9, and its projection onto the dicing area 3 is also a closed ring. The pseudo-closed ring structure 4 is a closed ring structure, which can better prevent damage to devices within the chip during wafer dicing.

[0083] refer to Figure 1 and Figure 10 The dicing regions 3 are arranged in a grid pattern on the wafer, extending along a first direction and a second direction. The width of the dicing region extending along the first direction is X, and the width of the dicing region extending along the second direction is Y. When X equals Y, that is, when the widths of the dicing regions 3 extending along the first direction and the second direction are equal, since the pseudo-closed ring structure 4 has the same shape and size at the four corners and around the perimeter of the chip 101, refer to... Figure 10 The pseudo-closed ring structure 4 has the same shape and size in both the cutting channel region 3 extending along the first direction and the cutting channel region 3 extending along the second direction, allowing for neat arrangement. When X is not equal to Y, that is, when the width of the cutting channel region 3 extending along the first direction and the width of the cutting channel region 3 extending along the second direction are not equal (e.g., X is less than Y), meaning the width of the cutting channel region 3 extending along the first direction is less than the width of the cutting channel region 3 extending along the second direction, refer to... Figure 11 Linear pseudo-closed ring structures 4 are filled in the portion of the dicing area 3 extending along the second direction that is wider than the dicing area 3 extending along the first direction. The number of pseudo-linear closed ring structures 4, as well as the number of first linear pseudo-closed rings 6 and second linear pseudo-closed ring structures 7, are determined based on the difference between Y and X. The arrangement of the first linear pseudo-closed ring structures 6 and second linear pseudo-closed ring structures 7 can be the same as or different from the arrangement of the first linear pseudo-closed ring structures 6 and second linear pseudo-closed ring structures 7 around the chip. The pseudo-closed ring structures 4 are uniformly filled in the dicing area, which can adjust the stress of the wafer and divide the low-dielectric material or silicon oxide material in the wafer into small pieces. During wafer dicing, this can prevent cracking in the dicing area and reduce damage to the chip.

[0084] In another aspect, some embodiments of this application also disclose a semiconductor device, including: a chip 101, which is prepared by dicing along a dicing region 3 of a wafer; a dicing track surrounding the chip, and a closed ring structure 2 disposed between the dicing track and the chip 101; a metal pad 8 located on the side of the dicing track near the wafer, the metal pad 8 covering the bottom of the dicing track; and a pseudo-closed ring structure 4 filling the dicing track and located above the metal pad 8.

[0085] Specifically, in some embodiments, chip 101 may include computing chips, storage chips, image chips, and other chips fabricated on the wafer; the closed-loop structure 2 may be a single-ring, double-ring, or multi-ring structure. During wafer dicing, the closed-loop structure 2 can protect the devices in the chip from damage; the dicing track is arranged around the chip, located outside the closed-loop structure 2, and has a sufficiently large width to prevent damage to the devices in chip 101 during wafer dicing; the metal pad layer 8 disposed in the dicing track covers the bottom of the dicing track and is exposed to the cut surface of the dicing track, which can improve the stress on the wafer and enhance the strength of the pseudo-closed-loop structure 4 in the dicing track, thus preventing damage to the devices in the chip during wafer dicing.

[0086] refer to Figure 3 , Figure 4 , Figure 5 and Figure 6In some embodiments, the dicing channel may include an enhanced structure region disposed near the closed ring 2 and surrounding the closed ring structure. The pseudo-closed ring structure located in the enhanced structure region is an enhanced pseudo-closed ring structure 401, which includes a contact 9 and an interconnect 10. The contact 9 is connected to a metal pad 10, and the interconnect 10 is located above and connected to the contact 9. The metal pad 8, contact 9, and interconnect 10 are stacked and connected sequentially in a direction perpendicular to the wafer. The interconnect portions of adjacent pseudo-closed ring structures are connected, and the locations of these connections are staggered. Specifically, in some embodiments, the material of the contact 8 may be copper, tungsten, aluminum, cobalt, nickel, or a compound of two or more of these metals. Furthermore, a barrier material layer (not shown) may be present around the contact to prevent the metal material of the contact 9 from diffusing into the dielectric layer in the dicing channel. This also improves the adhesion between the contact 9 and the dielectric material in the dicing channel, preventing cracks from forming between the contact 9 and the dielectric material. The barrier layer may be one or more of titanium, titanium nitride, tantalum, and tantalum nitride. Interconnect 10 may include multiple layers of metal interconnects and metal plug structures between the metal interconnects. In some embodiments, it may include a 3-layer metal interconnect and a 2-layer plug structure, a 4-layer metal interconnect and a 3-layer plug structure, a 5-layer metal interconnect and a 4-layer plug structure, or other multi-layer metal interconnect and plug structures. The material of interconnect 10 may be copper, tungsten, aluminum, cobalt, nickel, or a compound of two or more of the above metals. Alternatively, one layer of the interconnect may be copper, and another layer may be tungsten or aluminum, or the metal materials between different layers may be different, and the plug materials between the metal layers may also be different. In some embodiments, the adjacent pseudo-closed ring structures are interleaved, that is, the enhanced pseudo-closed ring structure 401 has a wall-like structure. In this way, the adjacent pseudo-closed rings are independent of each other but support each other, which can enhance the strength and divide the low-dielectric material or silicon oxide material in the dicing channel into smaller blocks. During wafer dicing, damage to the devices inside the chip can be better reduced.

[0087] refer to Figure 3 , Figure 4 and Figure 7 In some embodiments, the cutting path further includes a linear structure region surrounding the reinforcing structure region. The pseudo-closed-loop structure of the linear structure region is a linear pseudo-closed-loop structure 402, which includes a first linear pseudo-closed-loop structure 6 having contact with and connection to the metal pad layer. (Reference) Figure 7The first linear pseudo-closed ring structure 6 includes a third contact 903 and a third interconnect 1003. The metal pad 8, the third contact 903, and the interconnect 1003 are stacked sequentially in a direction perpendicular to the wafer to form the first linear pseudo-closed ring structure 6. The material of the third contact 903 can be copper, tungsten, aluminum, cobalt, nickel, or a compound of two or more of these metals. Furthermore, a barrier material layer (not shown) can be present around the third contact 903 to prevent the metal material of the contact from diffusing into the dielectric layer in the dicing channel. This also improves the adhesion between the third contact 903 and the dielectric material in the dicing channel, preventing cracks from forming between the third contact 903 and the dielectric material. The barrier layer can be one or more of titanium, titanium nitride, tantalum, and tantalum nitride. The third interconnect 1003 can include multiple layers of metal interconnects and metal plug structures between the metal interconnects. In some embodiments, it can include a 3-layer metal interconnect and a 2-layer plug structure, a 4-layer metal interconnect and a 3-layer plug structure, a 5-layer metal interconnect and a 4-layer plug structure, or other multi-layer metal interconnect and plug structures. The material of the third interconnect 1003 can be copper, tungsten, aluminum, cobalt, nickel, or a compound of two or more of the above metals. Alternatively, one layer of the third interconnect 1003 can be copper, and the other layer can be tungsten or aluminum. Or, the metal materials of different layers can be different, and the plug materials between the metal layers can also be different.

[0088] In some embodiments, the linear pseudo-closed ring structure 402 further includes a second linear pseudo-closed ring structure 7 that has no contact and is not connected to the metal pad layer. The second linear pseudo-closed ring structure 7 only has a fourth interconnect structure 1004, has no contact, is not connected to the metal pad layer 8, and is located in the low-dielectric material or silicon oxide material in the dicing channel, and is on the same plane as the third interconnect in the first linear pseudo-closed ring structure 6. The second linear pseudo-closed ring structure 7 has no contact, which can reduce the process burden of etching contact holes during contact layer preparation, saving material and time costs. At the same time, the stress of the dicing channel can be adjusted by adjusting the number of contacts.

[0089] Furthermore, some embodiments of this application also disclose a method for fabricating a semiconductor structure, including: providing a wafer, the wafer including multiple chip regions and dicing channels between two adjacent chip regions; forming a closed-loop structure located between the chip regions and the dicing channels; forming a metal pad layer in the dicing channels, the metal pad layer covering the bottom of the dicing pad layer; and forming a pseudo-closed-loop structure formed on the metal pad layer and filling the dicing channels. Specifically, in some embodiments, the multiple chip regions may be formed on the wafer in an array, and the wafer may be a silicon wafer, a silicon-germanium wafer, a silicon carbide wafer, a silicon-on-insulator (SOI) wafer, a germanium-on-insulator (GOI) wafer, a glass wafer, a III-V compound wafer (e.g., silicon nitride or gallium arsenide), an oxide semiconductor wafer, or other dicable wafers. The size of the wafer may be 6 inches, 8 inches, or 12 inches and is not limited thereto. The chip regions may form computing chips, storage chips, image chips, and other chips fabricated on the wafer, including but not limited to multiple devices (not shown). Chip regions can be arranged in an array of rectangles or squares on the wafer according to design requirements, and there are no specific limitations on the size and formation of the chip regions. A dicing channel is provided between two adjacent chip regions, and the dicing channels are arranged in a grid pattern to divide the wafer into multiple individual chip regions. In addition, in some embodiments, the dicing channel may include an enhancement structure region and a linear structure region. The enhancement structure region is closer to the closing ring, and the linear structure region is located on the side of the enhancement structure region away from the closing ring.

[0090] In some embodiments, a metal pad is provided in the dicing area, located on the side of the dicing area closest to the wafer, i.e., at the bottom of the dicing area. The metal pad can be made of copper, tungsten, aluminum, cobalt, nickel, or a compound of two or more of these metals. Furthermore, the metal pad can be multilayered, with one or more barrier material layers (not shown) formed around the metal pad to prevent the metal material of the metal pad from diffusing into the dielectric layer in the dicing area. This also improves the adhesion between the metal pad and the dielectric material in the dicing area, preventing cracks from forming between them. The barrier layer can be made of one or more of titanium, titanium nitride, tantalum, and tantalum nitride. The metal pad is integral within the dicing area, covering the entire dicing region. This integrates the pseudo-closed ring structure within the dicing area, strengthening the pseudo-closed ring junction and further preventing the breakage of low-dielectric materials or silicon oxide materials during the dicing process.

[0091] In some embodiments, a closed-loop structure surrounds the chip area. The closed-loop structure can be a single-ring, double-ring, or multi-ring structure. During wafer dicing, the closed-loop structure protects the devices in the chip from damage. A pseudo-closed-loop structure is arranged side-by-side with the closed-loop structure. The distance between adjacent pseudo-closed-loop structures can be greater than the distance between adjacent closed-loop structures. The shape of the pseudo-closed-loop can be the same as, partially the same as, partially different from, or completely different from the closed-loop. The pseudo-closed-loop structure divides the dicing area into blocks of varying sizes. This causes the stress on the low-dielectric material or silicon oxide material in the dicing area to decompose, crack, or break accordingly, thus relatively easily protecting the devices in chip 1 from damage.

[0092] In some embodiments, contacts are formed on a metal pad, and these contacts are independent of each other. The projected pattern on the dicing area is a closed ring. Specifically, the contacts are arranged around the closed ring structure and are formed synchronously with the closed ring structure. The material of the contacts can be copper, tungsten, aluminum, cobalt, nickel, or a compound of two or more of the above metals. In addition, a barrier material layer (not shown) can be placed around the contacts to prevent the metal material of the contacts from diffusing into the dielectric layer in the dicing area. This also improves the adhesion between the contacts and the dielectric material in the dicing area and prevents cracks from forming between the contacts and the dielectric material. The material of the barrier layer can be one or more of titanium, titanium nitride, tantalum, and tantalum nitride.

[0093] In some embodiments, interconnects are formed at the contacts, and the interconnects are discrete from each other. The projected pattern on the cut channel area is a closed ring. Specifically, the interconnects may include multiple layers of metal interconnects and metal plug structures between the metal interconnects. In some embodiments, it may include a 3-layer metal interconnect and a 2-layer plug structure, a 4-layer metal interconnect and a 3-layer plug structure, a 5-layer metal interconnect and a 4-layer plug structure, or other multi-layer metal interconnects and plug structures. The material of the interconnects may be copper, tungsten, aluminum, cobalt, nickel, or compounds of two or more of the above metals. Alternatively, one layer of the interconnect may be copper, and another layer may be tungsten or aluminum, or the metal materials between different layers may be different. The plug materials between the metal layers may also be different.

[0094] In some embodiments, two adjacent interconnects formed in the enhanced structure region are partially connected, and the connection positions are staggered, that is, the interconnects in the enhanced structure region have a wall-like structure. In this way, the adjacent interconnects are independent of each other and support each other, which can enhance strength and divide the low dielectric material or silicon oxide material in the dicing channel into smaller blocks. When the wafer is diced, damage to the devices inside the chip can be better reduced.

[0095] In some embodiments, the interconnects forming the linear structure region include interconnects connected to contacts and interconnects not connected to contacts, and the interconnects connected to contacts and interconnects not connected to contacts are not arranged discontinuously. Specifically, the metal pad, the contact, and the interconnects connected to the contact form a first linear pseudo-closed-loop structure, and the metal pad and the interconnects not connected to the contact form a second linear pseudo-closed-loop structure. Specifically, in some embodiments, the first linear pseudo-closed-loop structure includes contacts and interconnects, and the metal pad, the contact, and the interconnects are stacked sequentially in a direction perpendicular to the wafer to form a closed-loop structure. The material of the contact can be copper, tungsten, aluminum, cobalt, nickel, or a compound of two or more of the above metals. In addition, a barrier material layer (not shown) can be placed around the contact to prevent the metal material of the contact from diffusing into the dielectric layer in the dicing channel, and at the same time, it can improve the adhesion between the contact and the dielectric material in the dicing channel and prevent cracks from appearing between the contact and the dielectric material. The material of the barrier layer can be one or more of titanium, titanium nitride, tantalum, and tantalum nitride. Interconnects can include multilayer metal interconnects and metal plug structures between the metal interconnects. In some embodiments, they can include 3 layers of metal interconnects and 2 layers of plug structures, 4 layers of metal interconnects and 3 layers of plug structures, 5 layers of metal interconnects and 4 layers of plug structures, or other multilayer metal interconnect and plug structures. The interconnect material can be copper, tungsten, aluminum, cobalt, nickel, or compounds of two or more of the above metals. Alternatively, one layer of the interconnect can be copper, and another layer can be tungsten or aluminum, or the metal materials between different layers can be different. The plug materials between the metal layers can also be different. The second linear pseudo-closed-loop structure only has interconnect structures, no contacts, and is not connected to the metal pad layer. It is located in the low-dielectric material or silicon oxide material in the dicing channel and is on the same plane as the interconnects in the first linear pseudo-closed-loop structure. The second linear pseudo-closed-loop structure does not have contacts, which reduces the process burden of etching contact holes during contact layer preparation, saving material and time costs. Simultaneously, the stress in the dicing channel region can be adjusted by regulating the number of contacts.

[0096] It should be noted that the methods for preparing the semiconductor structures in the embodiments of this application can all be used to prepare the corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structure embodiments can be substituted and supplemented for each other without conflict, so that those skilled in the art can understand the technical content of this application.

[0097] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0098] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A wafer, the wafer being divided into multiple chip regions and dicing channels located between two adjacent chip regions; A closed-loop structure is disposed between the chip region and the dicing channel region; A metal pad, the metal pad covering the dicing area, the metal pad being located on the side of the dicing area closest to the wafer; A pseudo-closed ring structure, which fills the cutting channel area, is disposed on the metal pad layer.

2. The semiconductor structure according to claim 1, characterized in that, The cutting channel area includes an enhanced structural area and a linear structural area; The enhanced structural region is located close to the closed-loop structure; The linear structure region is located on the side of the reinforced structure region away from the closed ring structure.

3. The semiconductor structure according to claim 2, characterized in that, The pseudo-closed loop structure located in the enhanced structural region includes contacts and interconnects; The metal pad, the contact, and the interconnect are connected sequentially in a direction perpendicular to the wafer; The interconnecting lines of two adjacent pseudo-closed ring structures are partially connected; The interconnecting positions of the two adjacent pseudo-closed ring structures are staggered.

4. The semiconductor structure according to claim 2, characterized in that, The pseudo-closed ring structure of the linear structure region includes a first linear pseudo-closed ring structure and a second linear pseudo-closed ring structure. The first linear pseudo-closed ring structure includes a third contact and a third interconnect, the metal pad, the third contact and the third interconnect are connected sequentially in a direction perpendicular to the wafer; The second linear pseudo-closed loop structure includes a fourth interconnect line, which is disposed above the metal pad layer; The first linear pseudo-closed ring structure and the second linear pseudo-closed ring structure are not arranged continuously.

5. The semiconductor structure according to claim 3 or 4, characterized in that, The projection pattern of the contact within the cutting channel area is a closed ring; The projection pattern of the interconnect line within the cutting channel area is a closed ring.

6. A semiconductor device, characterized in that, include: chip; A dicing channel that surrounds the chip; A closed-loop structure is disposed between the chip and the dicing channel; A metal padding layer that covers the cutting groove; A pseudo-closed ring structure is provided, which fills the cutting channel and is located on the metal pad layer.

7. The semiconductor device according to claim 6, characterized in that, The cutting channel includes an enhanced structural region, which is located close to the closed ring structure; The pseudo-closed loop structure in the enhanced structural region includes contacts and interconnects; The metal pad, the contact, and the interconnect are connected sequentially in a direction perpendicular to the wafer; The interconnecting lines of two adjacent pseudo-closed ring structures are partially connected; The interconnecting positions of the two adjacent pseudo-closed ring structures are staggered.

8. The semiconductor device according to claim 7, characterized in that, The cutting channel also includes a linear structure region, which is located on the side of the reinforced structure region away from the closed ring structure; The pseudo-closed ring structure of the linear structure region includes a first linear pseudo-closed ring structure, which includes a third contact and a third interconnect, the metal pad, and the third contact and the third interconnect are connected sequentially in a direction perpendicular to the wafer. The pseudo-closed ring structure of the linear structure region includes a second linear pseudo-closed ring structure; The second linear pseudo-closed loop structure includes a fourth interconnect line, which is disposed above the metal pad layer.

9. A method for fabricating a semiconductor structure, characterized in that, include: A wafer is provided, the wafer including a plurality of chip regions and a dicing channel region between two adjacent chip regions, the dicing channel region including an enhancement structure region and a linear structure region, the enhancement structure region being disposed close to a closed ring structure, and the linear structure region being disposed on the side of the enhancement structure region away from the closed ring structure; A closed-loop structure is formed, wherein the closed-loop structure is disposed between the chip region and the dicing channel region; A metal pad is formed within the cutting groove area and covers the entire cutting groove area; A pseudo-closed ring structure is formed, which fills the cutting channel area and is formed on the metal pad layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, Contacts are formed on the metal pad, and the contacts are independent of each other. The projected pattern in the cutting area is a closed ring. Interconnecting lines are formed, and the projection pattern of the interconnecting lines within the cutting channel area is a closed ring. Two adjacent interconnects formed in the enhanced structure region are partially connected, and the locations of the partial connections are staggered. The interconnects formed in the linear structure region include a fourth interconnect connected to a contact and a fourth interconnect not connected to a contact, wherein the third interconnect connected to a contact and the fourth interconnect not connected to a contact are not arranged discontinuously.

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