Driving and control integrated control system and FPGA current loop configuration method

Abstract

The invention provides a driving integrated control system which can be realized through a single chip SOC. The single chip SOC is provided with a first processor, a second processor and an FPGA unit, and the first processor, the second processor and the FPGA unit are accessed through an AXI bus. The control system comprises a plurality of position sensors, a plurality of speed sensors and a plurality of current collectors. And the plurality of position sensors can respectively collect position information of rotors connected with the plurality of driving shafts. The multiple speed sensors can collect speed information of the rotors connected with the multiple driving shafts respectively. And the plurality of current collectors can respectively collect output current for driving the plurality of driving shafts to rotate. The invention further provides an FPGA current loop configuration method. According to the method, the multi-axis current loop is conveniently realized, the convenience of software development is realized, the real-time high efficiency and reconfigurability of FPGA operation are ensured, and the multi-axis collaboration is easily realized.

Description

Technical Field

[0001] The present invention relates to the field of advanced manufacturing of integrated drive and control and numerically controlled special equipment. Specifically, the present invention relates to an integrated drive control system and an FPGA current loop configuration method. Background Art

[0002] Existing servo drivers are generally single-axis or dual-axis servo drivers. Since a single MCU or DSP cannot directly control servo motors with more than two axes, especially the current loop, when a multi-axis servo driver is required, multiple single-axis drivers need to be spliced together. In traditional servo motor control technologies, there is an architecture of MCU plus FPGA. FPGA implements a relatively simple current loop. Because it is very difficult and complex to implement complex algorithms and add or change algorithms in FPGA logic, it is not easy to implement and requires continuous optimization and adjustment. Summary of the Invention

[0003] The object of the present invention is to provide an integrated drive and control system.

[0004] Another object of the present invention is to provide an FPGA current loop configuration method.

[0005] The present invention provides an integrated drive and control system, which can be implemented by a single chip SOC; the single chip SOC has a first processor, a second processor and an FPGA unit: the first processor and the second processor access the FPGA unit through the AXI bus, and data is transmitted between the first processor and the second processor through the API interface;

[0006] The control system includes:

[0007] Multiple position sensors, which can respectively collect the rotor position information connected to the multiple drive shafts;

[0008] Multiple speed sensors, which can respectively collect the rotor speed information connected to the multiple drive shafts;

[0009] Multiple current collectors, which can respectively collect the output current driving the multiple drive shafts to rotate;

[0010] Wherein, the first processor is configured to receive or store the numerical control drive program; the first processor is configured to obtain the drive information corresponding to the multiple drive shafts according to the instruction lines of the multiple drive shafts in the numerical control drive program;

[0011] The second processor can share data with the first processor; the second processor is configured with speed loop control units and position loop control units respectively corresponding to multiple drive shafts; the speed loop control unit can receive the rotor speed information of the speed sensor; the speed loop control unit can compare the set speed information according to the rotor speed information and output the speed feedback information of multiple drive shafts;

[0012] The position loop control unit can receive the rotor position information of the position sensor; the position loop control unit can compare the set rotation position information according to the rotor position information and output the position feedback information of multiple drive shafts;

[0013] Obtain the multi-axis current loop algorithm code and the multi-axis host communication interface code according to the set multi-axis current loop program; the multi-axis current loop program includes the address information or identification information of the first processor and the second processor;

[0014] Generate a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code; generate a multi-axis current loop communication IP core according to the multi-axis host communication interface code; the multi-axis current loop communication IP core includes the address information or identification information of the first processor and the second processor;

[0015] The FPGA unit configures the multi-axis current loop algorithm IP core and the multi-axis current loop communication IP core;

[0016] The second processor accesses the multi-axis current loop algorithm IP core through the multi-axis current loop communication IP core; the multi-axis current loop communication IP core obtains the set output shaft rotation drive information; the FPGA unit is configured to obtain the set output current through the multi-axis current loop algorithm IP core according to the set output shaft rotation drive information; the FPGA unit is configured to be able to receive the output current of the rotation of the multiple drive shafts; the FPGA unit can obtain and output the current feedback information of the multiple drive shafts through the multi-axis current loop algorithm IP core according to the output current of the rotation of the multiple drive shafts and the set output current;

[0017] When the multi-axis current loop algorithm code is C language code, the steps of generating a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code include:

[0018] According to the multi-axis current loop algorithm C language code, generate a multi-axis current loop algorithm in HDL language through HLS software;

[0019] Generate a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm in HDL language;

[0020] When the multi-axis host communication interface code is C language code, the steps of generating a multi-axis current loop algorithm IP core according to the multi-axis host communication interface code include:

[0021] According to the multi-axis host communication C language code, generate the multi-axis host communication interface code in HDL language through HLS software;

[0022] Generate a multi-axis current loop algorithm IP core according to the multi-axis host communication interface code in HDL language;

[0023] The FPGA unit is configured with a PWM control module; the PWM control module drives the plurality of drive shafts to rotate according to the output current for driving the plurality of drive shafts to rotate.

[0024] Preferably, the first processor is further configured to drive the second processor to run after the first processor acquires the drive information.

[0025] Preferably, the drive information includes identification information of a plurality of drive shafts, set rotation position information, set output shaft rotation drive information, and set speed information.

[0026] Preferably, the first processor is further configured to obtain drive information corresponding to the plurality of drive shafts through trajectory analysis according to the command lines of the plurality of drive shafts in the numerical control drive program.

[0027] The present invention also provides an FPGA current loop configuration method. The control system has a plurality of drive shafts and can drive the drive shafts through a numerical control drive program; the numerical control drive program has command lines capable of driving the plurality of drive shafts; the drive integrated control system is implemented by a single chip SOC; the single chip SOC has a first processor, a second processor, and an FPGA unit: the first processor and the second processor access the FPGA unit through the AXI bus, and data is transmitted between the first processor and the second processor through the API interface;

[0028] The control system includes:

[0029] A plurality of position sensors capable of respectively collecting rotor position information connected to the plurality of drive shafts;

[0030] A plurality of speed sensors capable of respectively collecting rotor speed information connected to the plurality of drive shafts;

[0031] A plurality of current collectors capable of respectively collecting output current for driving the plurality of drive shafts to rotate;

[0032] Among them, the first processor is configured to receive or store the numerical control driver program; the first processor is configured to obtain drive information corresponding to multiple drive axes according to the instruction lines of multiple drive axes in the numerical control driver program;

[0033] The second processor can share data with the first processor; the second processor is configured with a speed loop control unit and a position loop control unit respectively corresponding to multiple drive axes; the speed loop control unit can receive the rotor speed information of the speed sensor; the speed loop control unit can compare the set speed information according to the rotor speed information and output the speed feedback information of multiple drive axes;

[0034] The position loop control unit can receive the rotor position information of the position sensor; the position loop control unit can compare the set rotation position information according to the rotor position information and output the position feedback information of multiple drive axes;

[0035] Obtain the multi-axis current loop algorithm code and the multi-axis host communication interface code according to the set multi-axis current loop program; the multi-axis current loop program includes the address information or identification information of the first processor and the second processor;

[0036] Generate a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code; generate a multi-axis current loop communication IP core according to the multi-axis host communication interface code; the multi-axis current loop communication IP core includes the address information or identification information of the first processor and the second processor;

[0037] The FPGA unit configures the multi-axis current loop algorithm IP core and the multi-axis current loop communication IP core;

[0038] The second processor accesses the multi-axis current loop algorithm IP core through the multi-axis current loop communication IP core; the multi-axis current loop communication IP core obtains the set output axis rotation drive information; the FPGA unit is configured to obtain the set output current through the multi-axis current loop algorithm IP core according to the set output axis rotation drive information; the FPGA unit is configured to be able to receive the output currents of the rotations of multiple drive axes; the FPGA unit can obtain and output the current feedback information of multiple drive axes through the multi-axis current loop algorithm IP core according to the output currents of the rotations of multiple drive axes and the set output current;

[0039] When the multi-axis current loop algorithm code is C language code, the steps of generating a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code include:

[0040] Generate a multi-axis current loop algorithm in HDL language through HLS software according to the multi-axis current loop algorithm C language code;

[0041] Generate a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm of the HDL language;

[0042] When the multi-axis host communication interface code is C language code, the steps of generating a multi-axis current loop algorithm IP core according to the multi-axis host communication interface code include:

[0043] According to the multi-axis host communication interface C language code, generate the multi-axis host communication interface code of the HDL language through HLS software;

[0044] Generate a multi-axis current loop algorithm IP core according to the multi-axis host communication interface code of the HDL language;

[0045] The FPGA unit is configured with a PWM control module; the PWM control module drives the plurality of drive shafts to rotate according to the output current for rotating the plurality of drive shafts.

[0046] Preferably, the first processor is further configured to drive the second processor to run when the first processor obtains the drive information.

[0047] Preferably, the drive information includes identification information of a plurality of drive shafts, set rotation position information, set output shaft rotation drive information, and set speed information.

[0048] Preferably, the first processor is further configured to obtain drive information corresponding to a plurality of drive shafts through trajectory analysis according to the instruction lines of the plurality of drive shafts in the numerical control drive program.

[0049] The present invention has achieved the following beneficial technical effects compared with the prior art:

[0050] The present invention is converted into an IP form of FPGA through HLS and implemented by FPGA logic. By modifying the C language, the algorithm of the current loop can be reconstructed, and the C language can relatively simply implement complex and high-performance algorithms. This method is convenient for implementing a multi-axis current loop, has the convenience of software development, ensures the real-time efficiency and reconfigurability of FPGA operation, and is easy to achieve multi-axis coordination. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0052] Figure 1 It is a schematic structural diagram for illustrating the integration of driving and control.

[0053] Figure 2 It is a framework schematic diagram for illustrating the configuration process.

[0054] Figure 3 It is a schematic diagram for illustrating the process of generating the current loop IP.

[0055] Label description

[0056] 101 First processor

[0057] 102 Second processor

[0058] 103 FPGA unit

[0059] 200 Multi-axis current loop communication IP core

[0060] 301 Current collector

[0061] 302 Position sensor

[0062] 303 Speed sensor

[0063] 304 PWM control module Detailed implementation manners

[0064] For a clearer understanding of the technical features, objectives, and effects of the invention, the specific implementation manners of the invention will now be described with reference to the accompanying drawings. In the figures, the same reference numerals denote components having the same or similar structures but the same functions.

[0065] In this document, "schematic" means "serving as an example, instance, or illustration", and any illustration or implementation manner described as "schematic" in this document should not be construed as a more preferred or advantageous technical solution. To make the drawings concise, only the parts related to this exemplary embodiment are schematically shown in each figure, and they do not represent the actual structure and true proportion of the product.

[0066] The present invention provides a drive-integrated control system, which can be implemented by a single-chip SOC. Figure 1 It is a schematic diagram for illustrating the structure of the drive-control integration. Refer to Figure 1 , the single-chip SOC has a first processor 101, a second processor 102, and an FPGA unit 103. The first processor 101 and the second processor 102 access the FPGA unit 103 through the AXI bus, and data is transmitted between the first processor 101 and the second processor 102 through the API interface.

[0067] The control system includes multiple position sensors 302, multiple speed sensors 303, and multiple current collectors 301. The multiple position sensors 302 can respectively collect the rotor position information of the multiple drive shafts. The multiple speed sensors 303 can respectively collect the rotor speed information of the multiple drive shafts. The multiple current collectors 301 can respectively collect the output current that drives the rotation of the multiple drive shafts.

[0068] Figure 2 is a framework schematic diagram for illustrating the configuration process. Refer to Figure 2 , the first processor 101 is configured to receive or store the numerical control driver program. The first processor 101 is configured to obtain the drive information corresponding to the multiple drive shafts according to the instruction lines of the multiple drive shafts in the numerical control driver program. The second processor 102 and the first processor 101 can share data. The second processor 102 is configured with speed loop control units and position loop control units respectively corresponding to the multiple drive shafts. The speed loop control unit can receive the rotor speed information of the speed sensor 303. The speed loop control unit can compare the set speed information according to the rotor speed information and output the speed feedback information of the multiple drive shafts.

[0069] The position loop control unit can receive the rotor position information of the position sensor 302. The position loop control unit can compare the set rotation position information according to the rotor position information and output the position feedback information of the multiple drive shafts.

[0070] Obtain the multi-axis current loop algorithm code and the multi-axis host communication interface code according to the set multi-axis current loop program. The multi-axis current loop program includes the address information or identification information of the first processor 101 and the second processor 102.

[0071] Generate a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code. Generate a multi-axis current loop communication IP core 200 according to the multi-axis host communication interface code. The multi-axis current loop communication IP core 200 includes the address information or identification information of the first processor 101 and the second processor 102.

[0072] The FPGA unit 103 configures the multi-axis current loop algorithm IP core and the multi-axis current loop communication IP core 200.

[0073] The second processor accesses the multi-axis current loop algorithm IP core through the multi-axis current loop communication IP core. The multi-axis current loop communication IP core obtains the set output shaft rotation drive information. The FPGA unit 103 is configured to obtain the set output current through the multi-axis current loop algorithm IP core according to the set output shaft rotation drive information. The FPGA unit 103 is configured to be able to receive the output current of the rotation of the multiple drive shafts. The FPGA unit 103 can obtain and output the current feedback information of the multiple drive shafts through the multi-axis current loop algorithm IP core according to the output current of the rotation of the multiple drive shafts and the set output current.

[0074] Figure 3 is a schematic diagram for explaining the generation process of the current loop IP. Refer to Figure 3 , when the multi-axis current loop algorithm code is C language code, the steps for generating the multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code include:

[0075] Generate the multi-axis current loop algorithm in HDL language through the HLS software according to the multi-axis current loop algorithm C language code;

[0076] Generate the multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm in HDL language.

[0077] When the multi-axis host communication interface code is C language code, the steps for generating the multi-axis current loop algorithm IP core according to the multi-axis host communication interface code include:

[0078] Generate the multi-axis host communication interface code in HDL language through the HLS software according to the multi-axis host communication interface C language code;

[0079] Generate the multi-axis current loop algorithm IP core according to the multi-axis host communication interface code in HDL language.

[0080] The FPGA unit configures a PWM control module 304. The PWM control module 304 drives multiple drive shafts to rotate according to the output current for driving the multiple drive shafts to rotate, where PWM means pulse width modulation.

[0081] The present invention is converted into the IP form of the FPGA through HLS, implemented by the FPGA logic, and the algorithm of the current loop can be reconstructed by modifying the C language. The C language can relatively simply implement complex and high-performance algorithms. This method is convenient for implementing the multi-axis current loop, has the convenience of software development, ensures the real-time efficiency and reconfigurability of the FPGA operation, and is easy to achieve multi-axis coordination.

[0082] In the illustrative embodiment, the first processor 101 is further configured to drive the second processor 102 to run when the first processor 101 obtains the drive information.

[0083] In the illustrative embodiment, the drive information includes identification information of multiple drive shafts, set rotation position information, set output shaft rotation drive information, and set speed information.

[0084] In the illustrative embodiment, the first processor 101 is further configured to obtain the drive information corresponding to the multiple drive shafts through trajectory analysis according to the instruction lines of the multiple drive shafts in the numerical control drive program.

[0085] The present invention also provides an FPGA current loop configuration method, as Figure 1As shown, the control system has multiple drive shafts and can drive the drive shafts through a numerical control drive program. The numerical control drive program has instruction lines capable of driving multiple drive shafts. The drive integrated control system is implemented by a single-chip SOC. The single-chip SOC has a first processor 101, a second processor 102, and an FPGA unit 103. The first processor 101 and the second processor 102 access the FPGA unit 103 through the AXI bus, and data is transmitted between the first processor 101 and the second processor 102 through the API interface.

[0086] The control system includes multiple position sensors 302, multiple speed sensors 303, and multiple current collectors 301. The multiple position sensors 302 can respectively collect the rotor position information connected to the multiple drive shafts. The multiple speed sensors 303 can respectively collect the rotor speed information connected to the multiple drive shafts. The multiple current collectors 301 can respectively collect the output current that drives the multiple drive shafts to rotate.

[0087] As Figure 2 shown, the first processor 101 is configured to receive or store the numerical control drive program. The first processor 101 is configured to obtain the drive information corresponding to the multiple drive shafts according to the instruction lines of the multiple drive shafts in the numerical control drive program.

[0088] The second processor 102 and the first processor 101 can share data. The second processor 102 is configured with speed loop control units and position loop control units respectively corresponding to the multiple drive shafts. The speed loop control unit can receive the rotor speed information of the speed sensor 303. The speed loop control unit can compare the set speed information according to the rotor speed information and output the speed feedback information of the multiple drive shafts.

[0089] The position loop control unit can receive the rotor position information of the position sensor 302. The position loop control unit can compare the set rotation position information according to the rotor position information and output the position feedback information of the multiple drive shafts.

[0090] Obtain the multi-axis current loop algorithm code and the multi-axis host communication interface code according to the set multi-axis current loop program. The multi-axis current loop program includes the address information or identification information of the first processor 101 and the second processor 102.

[0091] Generate a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code. Generate a multi-axis current loop communication IP core 200 according to the multi-axis host communication interface code. The multi-axis current loop communication IP core 200 includes the address information or identification information of the first processor 101 and the second processor 102.

[0092] The FPGA unit 103 configures the multi-axis current loop algorithm IP core and the multi-axis current loop communication IP core 200.

[0093] The second processor accesses the multi-axis current loop algorithm IP core through the multi-axis current loop communication IP core. The multi-axis current loop communication IP core obtains the set rotation drive information of the output axis. The FPGA unit 103 is configured to obtain the set output current through the multi-axis current loop algorithm IP core according to the set rotation drive information of the output axis. The FPGA unit 103 is configured to be able to receive the output currents for rotating multiple drive axes. The FPGA unit 103 can obtain and output the current feedback information of multiple drive axes through the multi-axis current loop algorithm IP core based on the output currents for rotating multiple drive axes and the set output current.

[0094] As Figure 3 shown, when the multi-axis current loop algorithm code is C language code, the steps of generating the multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code include:

[0095] Generating the multi-axis current loop algorithm in HDL language through the HLS software according to the multi-axis current loop algorithm C language code;

[0096] Generating the multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm in HDL language.

[0097] When the multi-axis host communication interface code is C language code, the steps of generating the multi-axis current loop algorithm IP core according to the multi-axis host communication interface code include:

[0098] Generating the multi-axis host communication interface code in HDL language through the HLS software according to the multi-axis host communication interface C language code;

[0099] Generating the multi-axis current loop algorithm IP core according to the multi-axis host communication interface code in HDL language.

[0100] The FPGA unit configures a PWM control module 304. The PWM control module 304 drives multiple drive axes to rotate according to the output currents for rotating multiple drive axes, where PWM means Pulse Width Modulation.

[0101] In the illustrative embodiment, the first processor 101 is further configured to drive the second processor 102 to run when the first processor 101 obtains the drive information.

[0102] In the illustrative embodiment, the drive information includes the identification information of multiple drive axes, the set rotation position information, the set rotation drive information of the output axis, and the set speed information.

[0103] In the illustrative embodiment, the first processor 101 is further configured to obtain the drive information corresponding to multiple drive axes through trajectory analysis according to the instruction lines of multiple drive axes in the numerical control drive program.

[0104] It should be understood that although this specification is described in accordance with various embodiments, not every embodiment contains only one independent technical solution. This narrative style of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0105] The series of detailed descriptions listed above are only specific descriptions of the feasible embodiments of the present invention, and they are not intended to limit the protection scope of the present invention. Any equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. Integrated drive and control system, characterized in that, It can be implemented by a single-chip SOC; the single-chip SOC has a first processor, a second processor, and an FPGA unit: the first processor and the second processor access the FPGA unit through the AXI bus, and data is transmitted between the first processor and the second processor through the API interface; The control system includes: Multiple position sensors, which can respectively collect the rotor position information connected to the multiple drive shafts; Multiple speed sensors, which can respectively collect the rotor speed information connected to the multiple drive shafts; Multiple current collectors, which can respectively collect the output current driving the multiple drive shafts to rotate; Wherein, the first processor is configured to receive or store the numerical control drive program; the first processor is configured to obtain the drive information corresponding to the multiple drive shafts according to the instruction lines of the multiple drive shafts in the numerical control drive program; The second processor and the first processor can share data; the second processor is configured with a speed loop control unit and a position loop control unit respectively corresponding to the multiple drive shafts; the speed loop control unit can receive the rotor speed information of the speed sensor; the speed loop control unit can compare the set speed information according to the rotor speed information and output the speed feedback information of the multiple drive shafts; The position loop control unit can receive the rotor position information of the position sensor; the position loop control unit can compare the set rotation position information according to the rotor position information and output the position feedback information of the multiple drive shafts; Obtain the multi-axis current loop algorithm code and the multi-axis host communication interface code according to the set multi-axis current loop program; the multi-axis current loop program includes the address information or identification information of the first processor and the second processor; Generate a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code; generate a multi-axis current loop communication IP core according to the multi-axis host communication interface code; the multi-axis current loop communication IP core includes the address information or identification information of the first processor and the second processor; The FPGA unit configures the multi-axis current loop algorithm IP core and the multi-axis current loop communication IP core; The second processor accesses the multi-axis current loop algorithm IP core through the multi-axis current loop communication IP core; the multi-axis current loop communication IP core obtains the set output shaft rotation drive information; the FPGA unit is configured to obtain the set output current through the multi-axis current loop algorithm IP core according to the set output shaft rotation drive information; the FPGA unit is configured to be able to receive the output current of the multiple drive shafts rotating; the FPGA unit can obtain and output the current feedback information of the multiple drive shafts through the multi-axis current loop algorithm IP core according to the output current of the multiple drive shafts rotating and the set output current; When the multi-axis current loop algorithm code is C language code, the steps of generating a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code include: According to the multi-axis current loop algorithm C language code, generate the multi-axis current loop algorithm in HDL language through HLS software; Generate the multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm in HDL language; When the multi-axis host communication interface code is C language code, the steps of generating the multi-axis current loop algorithm IP core according to the multi-axis host communication interface code include: According to the multi-axis host communication interface C language code, generate the multi-axis host communication interface code in HDL language through HLS software; Generate the multi-axis current loop algorithm IP core according to the multi-axis host communication interface code in HDL language; The FPGA unit is configured with a PWM control module; the PWM control module drives the plurality of drive shafts to rotate according to the output current for driving the plurality of drive shafts to rotate.

2. The integrated driving and control system according to claim 1, characterized in that, The first processor is further configured to drive the second processor to run when the first processor obtains the drive information.

3. The integrated driving and control system according to claim 1, characterized in that, The drive information includes identification information of a plurality of drive shafts, set rotation position information, set output shaft rotation drive information, and set speed information.

4. The integrated driving and control system according to claim 1, wherein, The first processor is further configured to obtain drive information corresponding to the plurality of drive shafts through trajectory analysis according to the instruction lines of the plurality of drive shafts in the numerical control drive program.

5. FPGA current loop configuration method, the control system has multiple drive shafts and can drive the drive shafts through a numerical control driver program; the numerical control driver program has instruction lines capable of driving the multiple drive shafts; characterized in that, The drive integrated control system is implemented by a single-chip SOC; the single-chip SOC has a first processor, a second processor, and an FPGA unit: the first processor and the second processor access the FPGA unit through the AXI bus, and data is transmitted between the first processor and the second processor through the API interface; The control system includes: A plurality of position sensors capable of respectively collecting the rotor position information connected to the plurality of drive shafts; A plurality of speed sensors capable of respectively collecting the rotor speed information connected to the plurality of drive shafts; A plurality of current collectors capable of respectively collecting the output current for driving the plurality of drive shafts to rotate; Wherein, the first processor is configured to receive or store the numerical control drive program; the first processor is configured to obtain drive information corresponding to the plurality of drive shafts according to the instruction lines of the plurality of drive shafts in the numerical control drive program; The second processor and the first processor can share data; the second processor is configured with a speed loop control unit and a position loop control unit respectively corresponding to the plurality of drive shafts; the speed loop control unit can receive the rotor speed information of the speed sensor; the speed loop control unit can output speed feedback information of the plurality of drive shafts according to the comparison between the rotor speed information and the set speed information; The position loop control unit can receive the rotor position information of the position sensor; the position loop control unit can output position feedback information of the plurality of drive shafts according to the comparison between the rotor position information and the set rotation position information; Obtain the multi-axis current loop algorithm code and the multi-axis host communication interface code according to the set multi-axis current loop program; the multi-axis current loop program includes the address information or identification information of the first processor and the second processor; Generate a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code; generate a multi-axis current loop communication IP core according to the multi-axis host communication interface code; the multi-axis current loop communication IP core includes the address information or identification information of the first processor and the second processor; The FPGA unit configures the multi-axis current loop algorithm IP core and the multi-axis current loop communication IP core; The second processor accesses the multi-axis current loop algorithm IP core through the multi-axis current loop communication IP core; the multi-axis current loop communication IP core obtains the set output axis rotation drive information; the FPGA unit is configured to obtain a set output current through the multi-axis current loop algorithm IP core according to the set output axis rotation drive information; the FPGA unit is configured to receive the output currents of the rotations of the multiple drive axes; the FPGA unit can obtain and output the current feedback information of the multiple drive axes through the multi-axis current loop algorithm IP core according to the output currents of the rotations of the multiple drive axes and the set output current; When the multi-axis current loop algorithm code is C language code, the steps of generating a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm code include: Generate a multi-axis current loop algorithm in HDL language through HLS software according to the multi-axis current loop algorithm C language code; Generate a multi-axis current loop algorithm IP core according to the multi-axis current loop algorithm in HDL language; When the multi-axis host communication interface code is C language code, the steps of generating a multi-axis current loop algorithm IP core according to the multi-axis host communication interface code include: Generate a multi-axis host communication interface code in HDL language through HLS software according to the multi-axis host communication interface C language code; Generate a multi-axis current loop algorithm IP core according to the multi-axis host communication interface code in HDL language; The FPGA unit configures a PWM control module; the PWM control module drives the rotations of the multiple drive axes according to the output currents of the rotations of the multiple drive axes.

6. The FPGA current loop configuration method according to claim 5, wherein, The first processor is further configured to drive the second processor to run when the first processor obtains the drive information.

7. The FPGA current loop configuration method according to claim 5, characterized in that, The drive information includes the identification information of multiple drive axes, set rotation position information, set output axis rotation drive information, and set speed information.

8. The FPGA current loop configuration method according to claim 5, wherein, The first processor is further configured to obtain drive information corresponding to the multiple drive axes through trajectory analysis according to the instruction lines of the multiple drive axes in the numerical control drive program.

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