Code generation method, device, electronic device and storage medium

Abstract

The present disclosure provides a code generation method, device, electronic device and storage medium, which relate to the field of computer technology. The method includes: obtaining a logical directed graph; converting the logical directed graph into a tree structure; converting the tree structure into a recursive structure; the recursive structure includes a branch microstructure and a linear microstructure; converting the branch microstructure and the linear microstructure into a program language structure; extracting a variable relationship directed graph corresponding to the logical directed graph; the variable relationship directed graph includes variables with determined variable types; performing variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph; based on scope identification rules, identifying the scope of the variables corresponding to the branch microstructure and the linear microstructure; generating a code file corresponding to the logical directed graph based on the program language structure, the logical flow directed graph, the variable type and the scope of the variable. The present disclosure can improve the efficiency and accuracy of converting the logical directed graph into a code file.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a code generation method, device, electronic device, and storage medium. Background Art

[0002] A program flow chart graphically represents the flow and logical relationships of a program, organizing the code logic in the form of nodes and lines. There are various forms of program flow charts, such as program design flow charts, algorithm flow charts, and visual logic flow codes. Program flow charts have certain advantages in terms of overall visualization, but are difficult to fully reflect logical details. For example, they lack complex programming language features such as variable types and data structure definitions, and do not have the executable nature of the program. Therefore, it is often necessary to convert program flow charts into executable program codes. In the prior art, program flow charts are usually converted into program codes manually, or automatically converted into executable program codes with low readability. When the flow chart is relatively complex, the former requires higher labor costs, while the latter often produces codes with extremely poor readability and extremely low reusability. Therefore, there is an urgent need for a method that can automatically convert program flow charts into executable program codes with high accuracy, high reusability, and good readability. Summary of the Invention

[0003] The present disclosure provides a code generation method, device, electronic device, and storage medium to at least solve the above technical problems existing in the prior art.

[0004] According to a first aspect of the present disclosure, a code generation method is provided, the method comprising: obtaining a logical directed graph; converting the logical directed graph into a tree structure; converting the tree structure into a recursive structure; the recursive structure including a branch microstructure and a linear microstructure; converting the branch microstructure and the linear microstructure into a programming language structure; extracting a variable relationship directed graph corresponding to the logical directed graph; the variable relationship directed graph including variables of determined variable types; performing variable type reasoning based on the variable relationship directed graph to obtain all variable types in the logical directed graph; identifying the scope of the variables corresponding to the branch microstructure and the linear microstructure based on a scope identification rule; and generating a code file corresponding to the logical directed graph based on the programming language structure, the logical directed graph, the variable types, and the scope of the variables.

[0005] In one possible implementation, converting the logical directed graph into a tree structure includes: merging all non-branched paths in the logical directed graph into a single node to obtain a first directed graph; traversing each edge in the first directed graph, and in response to the level span of the current edge being greater than 1, adding empty nodes to the current edge so that the level span of each edge is 1 to obtain a second directed graph; the level span is the maximum value of the difference between the number of levels of the starting node and the end node of the current edge; performing a breadth-first traversal on the second directed graph to determine the target node in the second directed graph; the target node is the first node in the second directed graph that has multiple parent nodes; based on the target node, performing a topology structure adjustment operation on the second directed graph to obtain the tree structure.

[0006] In one possible implementation, the topology adjustment operation is performed on the second directed graph based on the target node to obtain the tree structure, including: in response to the existence of a sibling node of the target node, a split operation is performed on the target node, and the target node in the second directed graph after the split operation is determined, until the split operation is performed on all target nodes with sibling nodes in the second directed graph to obtain a third directed graph; in response to the existence of the same type of parent node for the target nodes in the third directed graph, the same type of parent nodes are merged; the parent node of the same type of parent node is the same node; in response to the fact that the target node in the third directed graph does not have the same type of parent node, a split operation is performed on the target node in the third directed graph; and the target node in the third directed graph is re-determined until the target node does not exist in the third directed graph to obtain the tree structure.

[0007] In one embodiment, converting the tree structure into a recursive structure includes: traversing the tree structure to determine the number of child nodes of each node in the tree structure; in response to the presence of multiple child nodes of the node, determining the microstructure of the node and all of its child nodes as a branch microstructure; in response to the absence of multiple child nodes of the node, determining the microstructure of the node and its child nodes as a linear microstructure; and combining all of the branch microstructures and linear microstructures to obtain the recursive structure.

[0008] In one possible implementation, the variable type reasoning is performed based on the variable relationship directed graph to obtain all variable types in the logical directed graph, including: traversing the variable relationship directed graph from the parent node to the child node, and determining the variable type of the child node of the first node based on the first node whose variable type has been determined; traversing the variable relationship directed graph from the child node to the parent node, and determining the variable type of the parent node of the second node based on the second node whose variable type has been determined.

[0009] In one possible implementation, the scope of the variables corresponding to the branch microstructure and the linear microstructure is identified based on the scope identification rule, including: constructing declared variables and self-declared variables for each node; the declared variables are variables that have been declared before the node, and the self-declared variables are variables that need to be declared in the node; based on the first scope identification rule corresponding to the branch microstructure, determining the self-declared variables corresponding to the branch microstructure node and the declared variables of the subgraph leaf nodes in the branch microstructure; based on the second scope identification rule corresponding to the linear microstructure, determining the self-declared variables corresponding to the linear microstructure node and the declared variables of the subgraph leaf nodes in the linear microstructure; based on the declared variables and self-declared variables of each node, determining the scope of all variables.

[0010] In one possible implementation, the determining of the self-declared variables corresponding to the branch microstructure node and the declared variables of the subgraph leaf nodes in the branch microstructure based on the first scope identification rule corresponding to the branch microstructure includes: determining the self-declared variables of the subgraph root node corresponding to the branch microstructure node as the self-declared variables corresponding to the branch microstructure node; determining the sum of the declared variables and the self-declared variables of the subgraph root node corresponding to the branch microstructure node as the declared variables of the subgraph leaf nodes in the branch microstructure; determining the self-declared variables corresponding to the linear microstructure node and the declared variables of the subgraph leaf nodes in the linear microstructure based on the second scope identification rule corresponding to the linear microstructure includes: determining the sum of the self-declared variables of all nodes in the subgraph corresponding to the linear microstructure node as the self-declared variables corresponding to the linear microstructure node; and determining the sum of the declared variables and the self-declared variables of the parent node of the leaf node in the subgraph corresponding to the linear microstructure node as the declared variables of the subgraph leaf nodes in the linear microstructure.

[0011] According to a second aspect of the present disclosure, a code generation device is provided, which includes: an extraction module for obtaining a logical directed graph; a conversion module for converting the logical directed graph into a tree structure; the conversion module is also used to convert the tree structure into a recursive structure; the recursive structure includes a branch microstructure and a linear microstructure; the conversion module is also used to convert the branch microstructure and the linear microstructure into a program language structure; the extraction module is also used to extract a variable relationship directed graph corresponding to the logical directed graph; the variable relationship directed graph includes variables with determined variable types; an inference module is used to perform variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph; an identification module is used to identify the scope of the variables corresponding to the branch microstructure and the linear microstructure based on a scope identification rule; and a generation module is used to generate a code file corresponding to the logical directed graph based on the program language structure, the logical directed graph, the variable type and the scope of the variable.

[0012] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0013] at least one processor; and

[0014] a memory communicatively connected to the at least one processor; wherein,

[0015] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0016] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0017] The present invention discloses a code generation method, device, electronic device, and storage medium, which converts a logical directed graph into a tree structure, converts the tree structure into a recursive structure including a branch microstructure and a linear microstructure, and converts the branch microstructure and the linear microstructure into a programming language structure. The method then performs variable type inference based on a variable relationship directed graph corresponding to the logical directed graph to obtain all variable types in the logical directed graph, and identifies the scopes of the variables corresponding to the branch microstructure and the linear microstructure based on scope identification rules. Finally, the method generates a code file corresponding to the logical directed graph based on the programming language structure, variable type, and variable scope. Thus, the logical directed graph can be automatically converted into a code file, improving conversion efficiency. Furthermore, based on the customized method for converting the logical directed graph into a tree structure, the method for performing variable type inference, and the method for identifying variable scope, the accuracy of converting the logical directed graph into a code file can be improved.

[0018] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0020] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0021] Figure 1 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 1 ;

[0022] Figure 2 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 2 ;

[0023] Figure 3 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 3 ;

[0024] Figure 4 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 4 ;

[0025] Figure 5 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 5 ;

[0026] Figure 6 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 1 ;

[0027] Figure 7 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 2 ;

[0028] Figure 8 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 3 ;

[0029] Figure 9 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 4 ;

[0030] Figure 10 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 5 ;

[0031] Figure 11 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 6 ;

[0032] Figure 12 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 7 ;

[0033] Figure 13 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 8 ;

[0034] Figure 14 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 9 ;

[0035] Figure 15 A schematic structural diagram of a code generation device according to an embodiment of the present disclosure is shown;

[0036] Figure 16 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0037] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.

[0038] Figure 1 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 1 ,like Figure 1 As shown, a code generation method includes:

[0039] Step S101: Obtain a logical directed graph.

[0040] In this example, we first need to obtain a logical directed graph. This graph contains node and line information. Nodes represent specific business logic, and edges between nodes can have conditions, such as if / else statements, or they can be conditional. This directed graph can be extracted from logic flow files, natural language descriptions, or designed independently.

[0041] Step S102: convert the logical directed graph into a tree structure.

[0042] In this embodiment, the logical directed graph needs to be converted into a tree structure. The logical directed graph is a complex graph structure that may have complex relationships such as multiple branches and loops. In order to simplify the subsequent processing process, it needs to be converted into a tree structure. The tree structure is a hierarchical structure, and each node has at most one parent node, which makes the subsequent code generation process simpler and more efficient. The core of the conversion process is to process the multi-branch nodes in the graph (that is, nodes with multiple parent nodes) to ensure that the converted tree structure can accurately reflect the logical relationship of the original logic flow. For example, for a node with multiple parent nodes, it is necessary to split or merge it to eliminate the multi-branch situation and ultimately obtain a loop-free tree structure.

[0043] Step S103: convert the tree structure into a recursive structure.

[0044] In this embodiment, after completing the conversion from the logical directed graph to a tree structure, the tree structure needs to be converted into a recursive structure. A recursive structure is a structure recursively composed of a branching microstructure and a linear microstructure, which can better adapt to the structural characteristics of the programming language. Specifically, each node and its child nodes in the tree structure can be regarded as a microstructure, which can be divided into a branching microstructure or a linear microstructure based on the number of child nodes and the logical relationship between the nodes. The branching microstructure usually corresponds to the conditional branch structure (such as if / else) in the programming language, while the linear microstructure corresponds to the code block executed sequentially.

[0045] Step S104: convert the branch microstructure and the linear microstructure into a programming language structure.

[0046] In this embodiment, within a recursive structure, the branching microstructure and the linear microstructure correspond to different structures in a programming language. The branching microstructure can be converted into conditional branch statements (such as if / else), while the linear microstructure can be converted into code blocks that execute sequentially. For example, if a branching microstructure contains a parent node and multiple child nodes, it can be converted into an if / else statement, with the parent node's logical condition serving as the condition of the if statement and the child node's logic serving as the code blocks in the if and else branches, respectively. The linear microstructure is converted into code blocks that execute sequentially according to the logical order.

[0047] Step S105: extracting the variable relationship directed graph corresponding to the logical directed graph.

[0048] In this embodiment, the variable relationship directed graph corresponding to the logical directed graph also needs to be extracted. This can be done by scanning all variables in the file corresponding to the logical directed graph, along with their assignment relationships, function call relationships, and so on, to construct a directed graph in which nodes represent variables and edges represent relationships between them. For example, if variable "x" is assigned the value of variable "y," then an edge pointing from variable "y" to variable "x" is added to the variable relationship directed graph.

[0049] In one possible implementation method, the variable relationship directed graph corresponding to the logical directed graph can be extracted based on the following method: scan the file corresponding to the logical directed graph and the Java file of its implementation class, and obtain the attribute variable types of all entities based on format parsing and string regular matching; extract all variables appearing in the logical flow; assign types to variables or parameters that have been strictly declared in the file corresponding to the logical directed graph; construct a variable relationship directed graph based on the assignment relationship formed by the input parameters of the calling function and the output parameters of the calling function, the attribute relationship of multi-level variables, the sequence or element relationship of array variables, etc., for variable type reasoning.

[0050] Step S106: Perform variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph.

[0051] In this embodiment, the process of variable type inference based on the variable relationship directed graph is to infer the type of each variable by analyzing the relationships between variables. Specifically, starting from a variable of known type, the types of other variables are gradually inferred based on the assignment relationships and function call relationships in the variable relationship directed graph. For example, if variable "x" is assigned the value of variable "y", and the type of "y" is known to be an integer, then it can be inferred that the type of "x" is also an integer.

[0052] Step S107 : identifying the scopes of the variables corresponding to the branch microstructure and the linear microstructure based on the scope identification rule.

[0053] In this embodiment, in a programming language, the scope of a variable refers to the effective range of the variable. Based on scope identification rules, the scope of variables in branch microstructures and linear microstructures can be identified. Specifically, for each microstructure, the scope of the variable is determined based on its structural characteristics and the location of the variable declaration. For example, in a branch microstructure, the scope of a variable in a branch condition may be limited to the conditional statement, while the scope of a variable within the branch may extend to the entire branch code block.

[0054] Step S108 : generating a code file corresponding to the logical directed graph based on the program language structure, the logical directed graph, the variable type, and the variable scope.

[0055] In this embodiment, after completing all the above steps, a final code file can be generated based on the programming language structure, variable types, and variable scopes. The specific process involves combining the code blocks in the programming language structure in a logical order, inserting variable declaration statements at appropriate locations, and organizing the code blocks based on variable scopes. In one example, the generated code file is a complete Java code file that accurately implements the logical functions of the logical directed graph while maintaining good readability and maintainability.

[0056] In the present disclosure, a logical directed graph is converted into a tree structure, which is then converted into a recursive structure containing branch microstructures and linear microstructures. The branch microstructures and linear microstructures are then converted into programming language structures. Then, variable type inference is performed based on the variable relationship directed graph corresponding to the logical flow file to obtain all variable types in the logical directed graph. Based on scope identification rules, the scopes of the variables corresponding to the branch microstructures and linear microstructures are identified. Finally, based on the programming language structure, variable types, and variable scopes, a code file corresponding to the logical directed graph is generated. Thus, the logical directed graph can be automatically converted into a code file, improving conversion efficiency.

[0057] Figure 2 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 2 ,like Figure 2 As shown, step S102 "converting the logical directed graph into a tree structure" includes:

[0058] Step S201: merge all non-branched paths in the logical directed graph into a single node to obtain a first directed graph.

[0059] In this embodiment, in the process of converting the logical directed graph into a tree structure, it is first necessary to remove the empty nodes from the logical directed graph. Figure 6 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 1 ,like Figure 6 As shown, Figure 6 The logical directed graph on the left includes nodes A, B, C, D, E, and F. If node F is an empty node, then node F needs to be removed to obtain Figure 6 The logical directed graph on the right. The logical directed graph then needs to be simplified, meaning all forkless paths in the logical directed graph are merged into a single node. A forkless path is one that starts from one node and follows a unique path to another node without any branches in between. Figure 7 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 2 ,like Figure 7 As shown, Figure 7The logical directed graph on the left has removed the empty nodes, including nodes A, B, C, D, E, and F. Node C to node E and node D to node F are non-branching paths, so nodes C to node E can be merged into node C1, and nodes D to node F can be merged into node D1, resulting in Figure 7 The first directed graph on the right.

[0060] Step S202 traverses each edge in the first directed graph, and in response to the level span of the current edge being greater than 1, adds an empty node to the current edge so that the level span of each edge is 1, thereby obtaining a second directed graph.

[0061] In this embodiment, after obtaining the first directed graph, in order to further regularize the graph structure, each edge in the first directed graph needs to be processed. Specifically, each edge in the first directed graph is traversed to check whether the level span of the current edge is greater than 1. The level span is the maximum difference between the number of levels of the starting node and the end node of the current edge. If the level span is greater than 1, it means that this edge spans multiple levels, and it is necessary to add empty nodes to the edge to make the level span of each edge 1.

[0062] Figure 8 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 3 ,like Figure 8 As shown, Figure 8 The first directed graph on the left includes nodes A, B, and D. The level of node A is 1, the level of node B is 2, and the level of node D is 3. Obviously, the level span of the edge from node A to node D is 2. Therefore, it is necessary to add an empty node in the edge from node A to node D, and get Figure 8 In the second directed graph on the right, the level span of each edge in the second directed graph is 1.

[0063] Step S203: Perform breadth-first traversal on the second directed graph to determine a target node in the second directed graph.

[0064] In this embodiment, after obtaining the second directed graph, it is necessary to determine the target node therein. The target node is the first node in the second directed graph that has multiple parent nodes. To find the target node, a breadth-first traversal is performed on the second directed graph. Breadth-first traversal is an algorithm that traverses a graph layer by layer, starting from the root node and checking the number of parent nodes for each node layer by layer.

[0065] Figure 9 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 4 ,like Figure 9 As shown, Figure 9The logical directed graph on the left includes nodes A, B, C, D, E, X, and Y. After the operations of steps S201 to S202, we get Figure 9 The second directed graph on the right, node G is Figure 9 The first node in the second directed graph on the right has multiple parent nodes, so node G is the target node.

[0066] Step S204: Based on the target node, perform a topology adjustment operation on the second directed graph to obtain a tree structure.

[0067] In this embodiment, after determining the target node, a topology adjustment operation is performed on the second directed graph based on the target node to convert it into a tree structure. Specific operations include splitting or merging operations based on the target node to eliminate multiple branches, ultimately converting the second directed graph into a tree structure.

[0068] In the present disclosure, a method for converting a logical directed graph into a tree structure based on a customized method can improve the accuracy of converting the logical directed graph into a tree structure.

[0069] Figure 3 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 3 ,like Figure 3 As shown, step S204 "based on the target node, performing a topology adjustment operation on the second directed graph to obtain a tree structure" includes:

[0070] Step S301: In response to the target node having a sibling node, a split operation is performed on the target node, and the target node in the second directed graph after the split operation is determined, until the split operation is performed on all target nodes with sibling nodes in the second directed graph to obtain a third directed graph.

[0071] In this embodiment, during the topology adjustment of the second directed graph, if the target node has sibling nodes, indicating that its parent node has multiple branches, the target node needs to be split. Specifically, the target node's logic is split into multiple independent parts, each corresponding to a parent node. In other words, the target node can be copied, and the target node's parent node is pointed to the copied new target node. Figure 10 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 5 ,like Figure 10 As shown, Figure 10 In the second directed graph on the left, the target node is node G. Node G has a sibling node E, so node G needs to be split to obtain nodes G1 and G2, thus obtaining Figure 10 The third directed graph in the middle.

[0072] Step S302: In response to the target nodes in the third directed graph having parent nodes of the same type, the parent nodes of the same type are merged.

[0073] In this embodiment, after obtaining the third directed graph, if the parent nodes of the target node belong to the same class, that is, the parent nodes of these parent nodes are the same node, then these parent nodes can be merged. Specifically, if the sum of the branch conditions of the parent nodes in the same class constitutes a complete event (i.e., includes all nodes under the grandparent node of that class), then all parent nodes in the same class are formed into a tree node, with an empty node as the root node and all parent nodes in the same class as the child nodes of the root node, thereby forming a branching microstructure. If this does not constitute a complete event (i.e., the parent node of the target node is a child node of the grandparent node), then these conditions are aggregated and the parent nodes in the class are merged to form a tree node.

[0074] like Figure 10 As shown, Figure 10 The target node in the third directed graph is node G2. The two parent nodes of node G1 are node C and node D. The parent nodes of node C and node D are both node A. Therefore, node G2 has the same parent node. Therefore, node C and node D can be merged to obtain node P. Node P is the tree node, thus obtaining Figure 10 The tree structure on the right.

[0075] Step S303: In response to the target node in the third directed graph not having a parent node of the same type, a split operation is performed on the target node in the third directed graph.

[0076] Step S304: re-determine the target node in the third directed graph until there is no target node in the third directed graph, thereby obtaining a tree structure.

[0077] In this embodiment, if the parent nodes of the target node do not belong to the same class, that is, their parent nodes are different, then the target node is continuously split. Through repeated splitting and merging operations, the third directed graph is eventually converted into a tree structure.

[0078] Figure 4 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 4 ,like Figure 4 As shown, step S103 "converting the tree structure into a recursive structure" includes:

[0079] Step S401: traverse the tree structure to determine the number of child nodes of each node in the tree structure.

[0080] In this embodiment, in the process of converting the tree structure into a recursive structure, the tree structure needs to be traversed first to determine the number of child nodes of each node. Specifically, starting from the root node, the tree structure is traversed layer by layer to count the number of child nodes of each node.

[0081] Step S402 : In response to the node having multiple child nodes, the microstructure of the node and all the child nodes of the node is determined as a branch microstructure.

[0082] In this embodiment, after determining the number of child nodes of each node, if a node has multiple child nodes, the structure formed by this node and its child nodes can be regarded as a branch microstructure. The branch microstructure usually corresponds to a conditional branch structure (such as if / else) in a programming language. Figure 11 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 6 ,like Figure 11 As shown, Figure 11 Node B in the tree structure on the left has two child nodes. Then we can take node B and its child nodes E and G1 as a branch microstructure, and get Figure 11 The middle node in the tree structure is B1.

[0083] Step S403 : In response to the node not having multiple child nodes, determining the microstructure of the node and its child nodes as a linear microstructure.

[0084] In this embodiment, if a node has only one child node, then the structure formed by this node and its child nodes can be regarded as a linear microstructure. In programming languages, linear microstructures usually correspond to code blocks that are executed sequentially. Figure 11 As shown, Figure 11 If the node P in the tree structure on the left has a child node, then the node P and its child node G2 are determined as a linear microstructure, and we get Figure 11 The middle node in the tree structure is P1.

[0085] Step S404: All branch microstructures and linear microstructures are combined to obtain a recursive structure.

[0086] In this embodiment, after determining the branch microstructure and the linear microstructure, these microstructures are combined according to the structural relationship of the tree to form a recursive structure. The recursive structure is composed of branch microstructures and linear microstructures recursively, which can well represent the logical structure of the program. For example, a tree structure may contain multiple branch microstructures and linear microstructures. Through recursive combination, a complete recursive structure can be obtained. The generation of the recursive structure is based on the hierarchical relationship of the tree structure and the logical relationship of the microstructure, providing a structural form closer to the target language for subsequent code generation. Figure 11 As shown, Figure 11 The tree structure on the left is transformed into Figure 11 The intermediate tree structure is finally converted to Figure 11 The recursive structure on the right.

[0087] Figure 12 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 7 ,like Figure 12 As shown, for the recursive structure Figure 12 The branch microstructure on the left, which includes node A, node B and node C, can be converted into Figure 12 The programming language structure on the right. Figure 13 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 8 ,like Figure 13 As shown, for the recursive structure Figure 13 The linear microstructure on the left, which includes nodes D, E, and F, can be transformed into Figure 13 The programming language structure on the right.

[0088] In another embodiment, step S106 of “performing variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph” includes:

[0089] Traversing the variable relationship directed graph from the parent node to the child node, and determining the variable type of the child node of the first node according to the first node whose variable type has been determined;

[0090] The variable relationship directed graph is traversed from the child node to the parent node, and the variable type of the parent node of the second node is determined according to the second node of which the variable type has been determined.

[0091] In this embodiment, in the process of variable type inference, it is first necessary to traverse the variable relationship directed graph from the parent node to the child node. Specifically, starting from a variable node of a known type, the variable type of its child node is inferred based on the assignment relationship or function call relationship. For example, if the variable "x" is assigned the value of the variable "y", and it is known that the type of "y" is an integer, then it can be inferred that the type of "x" is also an integer. This traversal method from the parent node to the child node is based on the assignment relationship and logical dependency between variables, and can effectively infer the variable type of the child node.

[0092] In this embodiment, in the process of variable type reasoning, in addition to traversing from parent nodes to child nodes, it is also necessary to traverse the variable relationship directed graph from child nodes to parent nodes. Specifically, starting from a variable node of known type, the variable type of its parent node is inferred based on the assignment relationship or function call relationship. For example, if the variable "z" is assigned from the variable "w", and it is known that the type of "z" is a string, then it can be inferred that the type of "w" is also a string. This traversal method from child nodes to parent nodes is based on the reverse assignment relationship and logical dependency between variables, and can effectively supplement and verify the inference results of variable types.

[0093] Figure 5 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 5 ,like Figure 5 As shown, step S107 "identifying the scopes of variables corresponding to the branch microstructure and the linear microstructure based on the scope identification rule" includes:

[0094] Step S501: Construct declared variables and self-declared variables for each node.

[0095] In this embodiment, when identifying variable scope, it is first necessary to construct declared variables and self-declared variables for each node. Declared variables are variables that have been declared before the node, while self-declared variables are variables that need to be declared in the node. For example, in a node, if variable "a" has been declared in the previous node, it is a declared variable; if variable "b" needs to be declared in the current node, it is a self-declared variable. By distinguishing between declared and self-declared variables, the scope of the variable can be determined more accurately.

[0096] Step S502 : Based on the first scope identification rule corresponding to the branch microstructure, determine the self-declared variables corresponding to the branch microstructure node and the declared variables of the subgraph leaf nodes in the branch microstructure.

[0097] In this embodiment, when identifying the scope of variables in a branch microstructure, it is necessary to identify it based on the first scope identification rule. Specifically, for each node in the branch microstructure, its corresponding self-declared variables and declared variables are determined based on its position and logical relationship in the branch microstructure. For example, in a branch microstructure, the scope of the variable in the branch condition may be limited to the conditional statement, while the scope of the variable inside the branch may extend to the entire branch code block. Through this scope identification rule based on the characteristics of the branch microstructure, the scope of each variable can be accurately determined.

[0098] Step S503 : Based on the second scope identification rule corresponding to the linear microstructure, determine the self-declared variables corresponding to the linear microstructure nodes and the declared variables of the subgraph leaf nodes in the linear microstructure.

[0099] In this embodiment, the scope of variables in a linear microstructure is identified based on the second scope identification rule. Specifically, for each node in the linear microstructure, its corresponding self-declared variables and declared variables are determined based on its position and logical relationship within the linear microstructure. For example, in a linear microstructure, the scope of a variable may extend from its declaration location to the end of the entire linear microstructure.

[0100] Step S504: Determine the scope of all variables based on the declared variables and self-declared variables of each node.

[0101] In the present disclosure, based on the method of customizing the variable scope identification, the accuracy of variable scope identification can be improved.

[0102] In one embodiment, step S502 of “determining, based on the first scope identification rule corresponding to the branch microstructure, the self-declared variables corresponding to the branch microstructure node and the declared variables of the subgraph leaf nodes in the branch microstructure” includes:

[0103] Determine the self-declared variable of the subgraph root node corresponding to the branch microstructure node as the self-declared variable corresponding to the branch microstructure node;

[0104] The sum of the declared variables and self-declared variables of the subgraph root node corresponding to the branch microstructure node is determined as the declared variables of the subgraph leaf node in the branch microstructure.

[0105] In this embodiment, when identifying the scope of variables in a branch microstructure, the self-declared variables of the subgraph root node corresponding to the branch microstructure node are directly determined as the self-declared variables of the branch microstructure node. In other words, the self-declared variables of the branch microstructure node equal the self-declared variables of the subgraph root node.

[0106] In this embodiment, when identifying the scope of variables in a branching microstructure, the declared variables of a subgraph leaf node in the branching microstructure are determined as the sum of the declared variables of the subgraph root node and the self-declared variables. In other words, the declared variables of a subgraph leaf node = the declared variables of the root node + the self-declared variables of the root node.

[0107] In one embodiment, step S503 of “determining, based on the second scope identification rule corresponding to the linear microstructure, the self-declared variables corresponding to the linear microstructure nodes and the declared variables of the subgraph leaf nodes in the linear microstructure” includes:

[0108] The sum of the self-declared variables of all nodes in the subgraph corresponding to the linear microstructure node is determined as the self-declared variable corresponding to the linear microstructure node;

[0109] The sum of the declared variables and self-declared variables of the parent node of the leaf node in the subgraph corresponding to the linear microstructure node is determined as the declared variables of the leaf node in the subgraph in the linear microstructure.

[0110] In this embodiment, in a linear microstructure, the self-declared variables of a node are the sum of the self-declared variables of all nodes in its subgraph. In other words, the self-declared variables of a simple path structure node are equal to the sum of the self-declared variables of all nodes in its subgraph.

[0111] In this embodiment, in a linear microstructure, the declared variables of a leaf node in a subgraph are the sum of its parent node's declared variables and its self-declared variables. That is, the declared variables of a child node in a subgraph = the declared variables of its parent node + the self-declared variables of its parent node.

[0112] Figure 14 A schematic diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 9 ,like Figure 14 As shown, for the branch microstructure G2, its subgraph is a structure composed of nodes C, G1 and D, and X represents the self-declared variable and Y represents the declared variable. Then the calculation formula of the self-declared variable of the branch microstructure G2 is ,in, is the self-declared variable of the branch microstructure G2, is the self-declared variable of the subgraph root node C; the calculation formula of the declared variable of the subgraph leaf node D is ,in, is the declared variable of the subgraph leaf node D, is the self-declared variable of the subgraph root node C, It is a declared variable of the subgraph root node C.

[0113] For the linear microstructure G1, its subgraph is a structure composed of nodes A and B, and X represents the self-declared variable and Y represents the declared variable. Then the calculation formula of the self-declared variable of the linear microstructure G1 is ,in, is the self-declared variable of the linear microstructure G1, is the self-declared variable of subgraph node A, is the self-declared variable of subgraph node B; the calculation formula of the declared variable of subgraph node B is ,in, is the declared variable of child node B in the subgraph, It is the self-declared variable of the parent node of child node B. A declared variable of the parent node of child node B.

[0114] Figure 15 A schematic diagram of the structure of a code generating device according to an embodiment of the present disclosure is shown. Figure 15 As shown, a code generating device includes:

[0115] The extraction module 10 is used to obtain a logical directed graph; the conversion module 11 is used to convert the logical directed graph into a tree structure; the conversion module 11 is also used to convert the tree structure into a recursive structure; the recursive structure includes a branch microstructure and a linear microstructure; the conversion module 11 is also used to convert the branch microstructure and the linear microstructure into a programming language structure; the extraction module 10 is also used to extract a variable relationship directed graph corresponding to the logical directed graph; the variable relationship directed graph includes variables with determined variable types; the reasoning module 12 is used to perform variable type reasoning based on the variable relationship directed graph to obtain all variable types in the logical directed graph; the identification module 13 is used to identify the scope of variables corresponding to the branch microstructure and the linear microstructure based on the scope identification rule; the generation module 14 is used to generate a code file corresponding to the logical directed graph based on the programming language structure, the logical directed graph, the variable type and the scope of the variable.

[0116] In one embodiment, the conversion module 11 is also used to: merge all non-branched paths in the logical directed graph into a single node to obtain a first directed graph; traverse each edge in the first directed graph, and in response to the level span of the current edge being greater than 1, add empty nodes to the current edge so that the level span of each edge is 1 to obtain a second directed graph; the level span is the maximum value of the difference between the number of levels of the starting node and the end node of the current edge; perform a breadth-first traversal on the second directed graph to determine the target node in the second directed graph; the target node is the first node in the second directed graph that has multiple parent nodes; based on the target node, perform a topology structure adjustment operation on the second directed graph to obtain a tree structure.

[0117] In one embodiment, the conversion module 11 is also used to: in response to the existence of a sibling node of the target node, perform a split operation on the target node, and determine the target node in the second directed graph after the split operation, until the split operation is performed on all target nodes with sibling nodes in the second directed graph to obtain a third directed graph; in response to the existence of the same type of parent node for the target nodes in the third directed graph, merge the same type of parent nodes; the parent node of the same type of parent node is the same node; in response to the fact that the target node in the third directed graph does not have the same type of parent node, perform a split operation on the target node in the third directed graph; re-determine the target node in the third directed graph until the target node does not exist in the third directed graph to obtain a tree structure.

[0118] In one embodiment, the conversion module 11 is further used to: traverse the tree structure to determine the number of child nodes of each node in the tree structure; in response to the presence of multiple child nodes of a node, determine the microstructure of the node and all of its child nodes as a branch microstructure; in response to the absence of multiple child nodes of a node, determine the microstructure of the node and its child nodes as a linear microstructure; and combine all branch microstructures and linear microstructures to obtain a recursive structure.

[0119] In one embodiment, the reasoning module 12 is further used to: traverse the variable relationship directed graph from the parent node to the child node, and determine the variable type of the child node of the first node based on the first node whose variable type has been determined; traverse the variable relationship directed graph from the child node to the parent node, and determine the variable type of the parent node of the second node based on the second node whose variable type has been determined.

[0120] In one embodiment, the identification module 13 is further used to: construct declared variables and self-declared variables for each node; declared variables are variables that have been declared before the node, and self-declared variables are variables that need to be declared in the node; based on the first scope identification rule corresponding to the branch microstructure, determine the self-declared variables corresponding to the branch microstructure node and the declared variables of the subgraph leaf nodes in the branch microstructure; based on the second scope identification rule corresponding to the linear microstructure, determine the self-declared variables corresponding to the linear microstructure node and the declared variables of the subgraph leaf nodes in the linear microstructure; based on the declared variables and self-declared variables of each node, determine the scope of all variables.

[0121] In one embodiment, the identification module 13 is further used to: determine the self-declared variables of the subgraph root node corresponding to the branch microstructure node as the self-declared variables corresponding to the branch microstructure node; and determine the sum of the declared variables and the self-declared variables of the subgraph root node corresponding to the branch microstructure node as the declared variables of the subgraph leaf node in the branch microstructure.

[0122] In one embodiment, the identification module 13 is further used to: determine the sum of the self-declared variables of all nodes in the subgraph corresponding to the linear microstructure node as the self-declared variable corresponding to the linear microstructure node; and determine the sum of the declared variables and self-declared variables of the parent node of the leaf node in the subgraph corresponding to the linear microstructure node as the declared variable of the leaf node of the subgraph in the linear microstructure.

[0123] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0124] Figure 16A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0125] like Figure 16 As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. Computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to bus 804.

[0126] Various components in device 800 are connected to I / O interface 805, including an input unit 806, such as a keyboard, mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0127] The computing unit 801 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as a code generation method. For example, in some embodiments, a code generation method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the code generation method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform a code generation method by any other suitable means (e.g., via firmware).

[0128] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0129] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0130] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0131] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0132] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0133] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0134] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions of this disclosure can be achieved, and this document is not limited here.

[0135] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0136] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A code generation method, characterized in that: The method comprises: Get the logical directed graph; Converting the logical directed graph into a tree structure; Converting the tree structure into a recursive structure; the recursive structure includes a branch microstructure and a linear microstructure; Converting the branch microstructure and the linear microstructure into a programming language structure; Extracting a variable relationship directed graph corresponding to the logical directed graph; wherein the variable relationship directed graph includes variables of determined variable types; Performing variable type reasoning based on the variable relationship directed graph to obtain all variable types in the logical directed graph; Based on a scope identification rule, identifying the scopes of the variables corresponding to the branch microstructure and the linear microstructure; Generate a code file corresponding to the logical directed graph based on the program language structure, the logical directed graph, the variable type, and the scope of the variable; The converting of the logical directed graph into a tree structure comprises: Merging all non-bifurcated paths in the logical directed graph into a single node to obtain a first directed graph; Traversing each edge in the first directed graph, and in response to a level span of a current edge being greater than 1, adding an empty node to the current edge so that the level span of each edge is 1, thereby obtaining a second directed graph; the level span being the maximum value of the difference between the number of levels of the starting node and the ending node of the current edge; Performing a breadth-first traversal on the second directed graph to determine a target node in the second directed graph; the target node is the first node in the second directed graph that has multiple parent nodes; Based on the target node, performing a topology adjustment operation on the second directed graph to obtain the tree structure; The step of performing a topology adjustment operation on the second directed graph based on the target node to obtain the tree structure includes: In response to the target node having a sibling node, performing a split operation on the target node, and determining a target node in the second directed graph after the split operation, until the split operation is performed on all target nodes in the second directed graph that have sibling nodes, to obtain a third directed graph; In response to the target nodes in the third directed graph having parent nodes of the same type, merging the parent nodes of the same type; the parent nodes of the parent nodes of the same type are the same node; In response to the target node in the third directed graph not having a parent node of the same type, performing a split operation on the target node in the third directed graph; The target node in the third directed graph is re-determined until no target node exists in the third directed graph, thereby obtaining the tree structure.

2. The method according to claim 1, characterized in that The converting the tree structure into a recursive structure comprises: Traversing the tree structure to determine the number of child nodes of each node in the tree structure; In response to the node having multiple child nodes, determining the microstructure of the node and all the child nodes of the node as a branch microstructure; In response to the node not having multiple child nodes, determining the microstructure of the node and the child nodes of the node as a linear microstructure; The recursive structure is obtained by combining all the branch microstructures and linear microstructures.

3. The method according to claim 1, characterized in that The variable type reasoning based on the variable relationship directed graph to obtain all variable types in the logical directed graph includes: Traversing the variable relationship directed graph from the parent node to the child node, and determining the variable type of the child node of the first node according to the first node whose variable type has been determined; The variable relationship directed graph is traversed from the child node to the parent node, and the variable type of the parent node of the second node is determined according to the second node of which the variable type has been determined.

4. The method according to claim 1, wherein The identifying the scopes of the variables corresponding to the branch microstructure and the linear microstructure based on the scope identification rule includes: Construct declared variables and self-declared variables for each node; the declared variables are variables that have been declared before the node, and the self-declared variables are variables that need to be declared in the node; Determining, based on a first scope identification rule corresponding to the branch microstructure, self-declared variables corresponding to the branch microstructure node and declared variables of the subgraph leaf nodes in the branch microstructure; Determining, based on a second scope identification rule corresponding to the linear microstructure, self-declared variables corresponding to the linear microstructure nodes and declared variables of the subgraph leaf nodes in the linear microstructure; Determines the scope of all variables based on each node's declared and self-declared variables.

5. The method according to claim 4, characterized in that The determining, based on the first scope identification rule corresponding to the branch microstructure, the self-declared variables corresponding to the branch microstructure node and the declared variables of the subgraph leaf nodes in the branch microstructure includes: Determining the self-declared variable of the subgraph root node corresponding to the branch microstructure node as the self-declared variable corresponding to the branch microstructure node; Determine the sum of the declared variables and the self-declared variables of the subgraph root node corresponding to the branch microstructure node as the declared variables of the subgraph leaf node in the branch microstructure; The determining, based on the second scope identification rule corresponding to the linear microstructure, the self-declared variables corresponding to the linear microstructure nodes and the declared variables of the subgraph leaf nodes in the linear microstructure includes: Determine the sum of the self-declared variables of all nodes in the subgraph corresponding to the linear microstructure node as the self-declared variable corresponding to the linear microstructure node; The sum of the declared variables and self-declared variables of the parent node of the leaf node in the subgraph corresponding to the linear microstructure node is determined as the declared variables of the leaf node in the subgraph in the linear microstructure.

6. A code generating device, characterized in that: The device comprises: Extraction module, used to obtain the logical directed graph; A conversion module, configured to convert the logical directed graph into a tree structure; The conversion module is further configured to convert the tree structure into a recursive structure; the recursive structure includes a branch microstructure and a linear microstructure; The conversion module is further used to convert the branch microstructure and the linear microstructure into a programming language structure; The extraction module is further configured to extract a variable relationship directed graph corresponding to the logical directed graph; the variable relationship directed graph includes variables of determined variable types; An inference module, configured to perform variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph; an identification module, configured to identify scopes of variables corresponding to the branch microstructure and the linear microstructure based on a scope identification rule; A generation module, configured to generate a code file corresponding to the logical directed graph based on the program language structure, the logical directed graph, the variable types, and the scopes of the variables; The converting of the logical directed graph into a tree structure comprises: Merging all non-bifurcated paths in the logical directed graph into a single node to obtain a first directed graph; Traversing each edge in the first directed graph, and in response to a level span of a current edge being greater than 1, adding an empty node to the current edge so that the level span of each edge is 1, thereby obtaining a second directed graph; the level span being the maximum value of the difference between the number of levels of the starting node and the ending node of the current edge; Performing a breadth-first traversal on the second directed graph to determine a target node in the second directed graph; the target node is the first node in the second directed graph that has multiple parent nodes; Based on the target node, performing a topology adjustment operation on the second directed graph to obtain the tree structure; The step of performing a topology adjustment operation on the second directed graph based on the target node to obtain the tree structure includes: In response to the target node having a sibling node, performing a split operation on the target node, and determining a target node in the second directed graph after the split operation, until the split operation is performed on all target nodes in the second directed graph that have sibling nodes, to obtain a third directed graph; In response to the target nodes in the third directed graph having parent nodes of the same type, merging the parent nodes of the same type; the parent nodes of the parent nodes of the same type are the same node; In response to the target node in the third directed graph not having a parent node of the same type, performing a split operation on the target node in the third directed graph; The target node in the third directed graph is re-determined until no target node exists in the third directed graph, thereby obtaining the tree structure.

7. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 5.

8. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 5.

Images