Branch prediction method, cyclic stack structure and related equipment

Abstract

The invention provides a branch prediction method, a loop stack structure and related equipment, and the method comprises the steps: obtaining a branch instruction, determining whether the branch instruction belongs to a target instruction or not, and enabling the target instruction to be a backward jump condition branch instruction; if the branch instruction belongs to the target instruction, executing a first updating operation for a loop stack according to the branch instruction; if the branch instruction does not belong to the target instruction, the type of the branch instruction is determined, a second updating operation is executed on the loop stack according to the type of the branch instruction, and the type of the branch instruction comprises a calling function type, a loop jumping-out type and a returning type.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a branch prediction method, a loop stack structure, and related devices. Background Art

[0002] Branch instructions control the execution of the program flow during the execution of a program. A branch prediction mechanism can eliminate the latency of branch instructions, reduce pipeline bubbles, and increase instruction parallelism. The accuracy of a branch prediction algorithm has a very important impact on the performance of a processor. A wrong branch prediction will cause the pipeline to flush, greatly damaging the performance and energy efficiency ratio of the processor; while an accurate branch prediction can effectively reduce the penalty caused by wrong prediction, improve the performance of the processor, and reduce the execution on the wrong path to improve the power consumption performance.

[0003] In related technologies, a branch prediction method with multi-dimensional correlation is proposed, which is mainly implemented based on an Inner Most Loop Iteration (IMLI) counter. However, the innermost loop is a "relative" concept, while the traditional IMLI counter adopts a relatively simple maintenance method and looks for an "absolute" innermost loop. The IMLI counter does not fully explore the possible correlations in all innermost loops, and there is a possibility of wrong prediction. Moreover, the existing method cannot handle loop structures with special exits. Summary of the Invention

[0004] The present disclosure provides a branch prediction method, a loop stack structure, and related devices to at least solve the above technical problems existing in the prior art.

[0005] In a first aspect, an embodiment of the present disclosure provides a branch prediction method, where the method includes:

[0006] Obtain a branch instruction, and determine whether the branch instruction belongs to a target instruction, where the target instruction is a conditional branch instruction that jumps backward;

[0007] If the branch instruction belongs to the target instruction, perform a first update operation on the loop stack according to the branch instruction;

[0008] If the branch instruction does not belong to the target instruction, determine the type of the branch instruction, and perform a second update operation on the loop stack according to the type of the branch instruction, where the type of the branch instruction includes: function call type, loop exit type, return type.

[0009] In a second aspect, an embodiment of the present disclosure provides a loop stack structure, where the structure includes: a first flag bit, a loop iteration counter, a function call counter, and a second flag bit; where

[0010] The first identification bit is used to indicate a loop label for recording a branch instruction, and the loop label is calculated according to the count value of the program counter;

[0011] The loop iteration counter is used to record the loop iteration count value of the branch instruction;

[0012] The function call counter is used to record the number of times of loop calling sub-functions of the branch instruction;

[0013] The second identification bit is used to record whether the entry corresponding to the branch instruction is valid.

[0014] In a third aspect, an embodiment of the present disclosure provides a processor core, and the processor core includes:

[0015] An obtaining unit is used to obtain a branch instruction;

[0016] A processing unit is used to determine whether the branch instruction belongs to a target instruction, and the target instruction is a conditional branch instruction that jumps backward; if the branch instruction belongs to the target instruction, a first update operation is performed on the loop stack according to the branch instruction; if the branch instruction does not belong to the target instruction, the branch instruction type is determined, and a second update operation is performed on the loop stack according to the branch instruction type, and the branch instruction type includes: function call type, loop exit type, return type.

[0017] In a fourth aspect, an embodiment of the present disclosure provides a processor, and the processor includes at least one processor core, and each processor core is configured to execute the branch prediction method.

[0018] In a fifth aspect, an embodiment of the present disclosure provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. The processor includes at least one processor core, and when the processor core executes the program, the steps of the branch prediction method are implemented.

[0019] A branch prediction method, a loop stack structure, and related devices provided by an embodiment of the present disclosure, the method includes: obtaining a branch instruction, determining whether the branch instruction belongs to a target instruction, where the target instruction is a conditional branch instruction that jumps backward; if the branch instruction belongs to the target instruction, performing a first update operation on the loop stack according to the branch instruction; if the branch instruction does not belong to the target instruction, determining the branch instruction type, and performing a second update operation on the loop stack according to the branch instruction type, where the branch instruction type includes: function call type, loop exit type, return type. In this way, by identifying the conditional branch instruction that jumps backward as the target instruction, the loop situation can be optimized, thereby reducing mispredictions; by classifying different types of branch instructions, the accuracy and efficiency of branch prediction are optimized.

[0020] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a flowchart of a branch prediction method provided by an embodiment of the present disclosure;

[0022] Figure 2 is a schematic diagram of branch prediction of a predictor provided by an application embodiment of the present disclosure;

[0023] Figure 3 is another schematic diagram of branch prediction of a predictor provided by an application embodiment of the present disclosure;

[0024] Figure 4 is a schematic diagram of a loop stack structure provided by an embodiment of the present disclosure;

[0025] Figure 5 is a flowchart of a branch prediction method provided by an application embodiment of the present disclosure;

[0026] Figure 6 is a schematic diagram of the structure of a processor core provided by an embodiment of the present disclosure;

[0027] Figure 7 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] To make the objectives, features, and advantages of the present disclosure more apparent and understandable, the following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0029] Figure 1 A flowchart of a branch prediction method provided for an embodiment of the present disclosure; as Figure 1 shown, the method includes:

[0030] Step 101: Obtain a branch instruction, and determine whether the branch instruction belongs to a target instruction, where the target instruction is a conditional branch instruction that jumps backward;

[0031] Step 102: If the branch instruction belongs to the target instruction, perform a first update operation on the loop stack according to the branch instruction;

[0032] Step 103: If the branch instruction does not belong to the target instruction, determine the branch instruction type, and perform a second update operation on the loop stack according to the branch instruction type, where the branch instruction type includes: function call type, loop exit type, return type.

[0033] In some embodiments, branch prediction is a technique in computer architecture used to improve the execution efficiency of programs, especially in the presence of conditional jumps (such as if statements, loops, etc.). Processors typically use pipelining techniques to increase the speed of instruction execution. Pipelining decomposes the instruction execution process into multiple stages (such as instruction fetching, decoding, execution, etc.) and allows different instructions to be processed in parallel at different stages.

[0034] Branch instructions are instructions that disrupt the pipeline. For example, if, for, while, switch, etc. When the processor encounters a conditional jump instruction, it needs to first determine whether the condition is true or false before it can decide which instruction to jump to. If the processor waits until the condition judgment result to fetch the next instruction, this will cause the pipeline to stall and waste precious processing time. To reduce pipeline stalls, the processor uses branch prediction techniques to try to predict the jump direction in advance, thereby loading instructions in advance. When the prediction is correct, the processor can continue the execution of the pipeline; when the prediction is incorrect, the incorrect instructions need to be cleared and the correct instructions need to be reloaded. Although there is some cost, overall, the performance is improved.

[0035] By the method provided in the embodiments of the present disclosure, identifying a conditional branch instruction that jumps backward as the target instruction can optimize for loop situations, thereby reducing mispredictions. Especially in loop scenarios, the behavior of branch instructions is relatively regular, and the prediction accuracy is improved. Classify different types of branch instructions to optimize the accuracy and efficiency of branch prediction.

[0036] When the branch instruction belongs to the target instruction, perform a first update operation; when it does not belong to the target instruction, for different types of branch instructions (such as function calls, breaking out of a loop, or returning, etc.), adopt different update operations, so as to better adapt to different instruction types, avoid excessive prediction operations on instructions of non-loop structures, reduce the computational overhead, and improve the overall system performance.

[0037] By updating the loop stack, the storage of historical information for branch prediction is optimized, enabling the branch predictor to better utilize historical information, reducing repeated calculations, and increasing the prediction hit rate.

[0038] In some embodiments, the performing the first update operation on the loop stack according to the branch instruction includes:

[0039] Determine the loop label of the branch instruction, and match the loop label with the first identification bit at the top of the loop stack;

[0040] If the loop label matches the first identification bit, increment the loop iteration counter of the first identification bit by 1 according to the jump direction of the branch instruction or update the second identification bit at the top of the loop stack;

[0041] If the loop label does not match the first identification bit, add a new entry to the loop stack according to the loop label.

[0042] Here, the loop stack is a storage structure that can be used to save loop-related information; during the loop process, the loop stack can track loop iterations in program execution to help predict future branch behaviors.

[0043] The loop label of the branch instruction can also be called a tag bit (Tag), which is obtained by hashing calculation of the PC (Program Counter). Among them, in branch prediction, the PC is also called the instruction pointer, or the instruction address register, or just a part of the instruction timing (in some computers), which is used to indicate the address of the branch instruction, or to identify a certain branch instruction. The Tag can be used as an index to look up entries in the loop stack to determine whether the currently executed instruction belongs to a known loop.

[0044] Here, a loop label, i.e., Tag, is regarded as a marker for a loop and is used to determine whether a branch instruction and the instruction at the top of the loop stack belong to the same loop.

[0045] Specifically, if the loop label matches the first flag bit, it is considered to belong to the same loop (i.e., the same branch), and the loop iteration counter of the first flag bit is incremented by 1 according to the jump direction of the branch instruction or the second flag bit at the top of the loop stack is updated; if the loop label does not match the first flag bit, it is considered not to belong to the same loop (i.e., not the same branch), and a new entry is added to the loop stack according to the loop label.

[0046] Specifically, if the branch instruction and the instruction at the top of the current loop stack do not belong to the same loop and the branch direction of the branch instruction has jumped (i.e., the branch instruction is a conditional branch instruction that jumps backward and the branch direction has jumped), then a new top of the stack is allocated according to the loop label.

[0047] If the branch instruction and the instruction at the top of the current loop stack belong to the same loop, then an update is required according to the jump of the branch direction, including:

[0048] If the branch direction of the branch instruction has jumped (i.e., the branch instruction is a conditional branch instruction that jumps backward and the branch direction has jumped), then the loop iteration counter (denoted as IMLIcount) of the first flag bit is incremented by 1;

[0049] If the branch direction is non-jumping, it is regarded as the end of the loop, the second flag bit (denoted as Enable) at the top of the loop stack is updated, the second flag bit (Enable) is set low (e.g., from 1 to 0 to turn off the loop function), and the pointer is moved downward.

[0050] In this way, by matching the loop label with the flag bit at the top of the stack, accurate tracking of different iterations of the same loop is ensured, and the prediction accuracy of branch instructions within the loop is improved, especially when there are multiple conditional branches inside the loop.

[0051] Perform corresponding processing according to the matching result. For example, update the counter in the loop stack according to the jump direction of the branch instruction, which can accurately track the progress of each loop iteration, avoid repeated prediction or misprediction of the loop count. If the loop label does not match the identification bit at the top of the stack, add a new entry to ensure that the stack will not overflow or overwrite existing information due to mismatched loop structures, and ensure that the status of each different loop can be correctly stored and updated. When the loop label matches the identification bit at the top of the stack, only update the counter or the identification bit, without performing a complete stack operation, reducing resource consumption and improving the overall system execution efficiency. This method utilizes the dynamic management of loop labels and loop stacks, can adapt to different types of loop structures, whether it is a single loop or a multi-layer nested loop, improving the flexibility and accuracy of subsequent branch prediction. And there is no need to frequently clear and reset the stack status, reducing the overhead during execution, especially when dealing with nested or complex loops.

[0052] In some embodiments, perform a second update operation on the loop stack according to the type of the branch instruction, including:

[0053] If the type of the branch instruction is a function call type, increment the function call counter at the top of the loop stack by 1.

[0054] Here, the function call type may be a Call instruction. If the branch instruction is a Call instruction, increment the function call counter (denoted as Call_cnt) at the top of the loop stack by 1.

[0055] In order to accurately track the number of function calls and ensure that the hierarchical structure of function calls can be correctly managed when processing branch instructions in a loop, by saving a function call counter at the top of the stack, when a function is called, this function call counter is incremented by 1 to effectively record the depth of the current function call. In this way, accurately tracking the hierarchical relationship of function calls helps to accurately return to the upper-level call when needed.

[0056] In some embodiments, perform a second update operation on the loop stack according to the type of the branch instruction, including:

[0057] If the type of the branch instruction is a loop exit type, delete the entry at the top of the loop stack and point the pointer of the loop stack to the next lower-level loop.

[0058] Here, the instruction of the loop exit type may be a Break instruction.

[0059] In a program with nested loops, each level of loop may have different control flows. When executing an instruction to break out of the current loop, the program needs to ensure that it exits from the correct level. By deleting the top entry of the stack and pointing the stack pointer to the next level of loop, it can be ensured that the break operation exits from the current loop level rather than from the wrong loop level. In this way, it can correctly resume to the outer loop and continue to execute the logic of the outer loop.

[0060] In some embodiments, the determining the type of branch instruction includes:

[0061] If the branch instruction is a downward jump instruction and the target address of the jump is the address corresponding to the top of the loop stack minus the target value, determine that the branch instruction is of the type of breaking out of the loop.

[0062] Here, a method for determining whether a branch instruction is an instruction of the type of breaking out of the loop is provided. If the branch instruction is a downward jump instruction and the target address is exactly the address corresponding to the top of the stack minus 4 (i.e., the target value is 4), it is considered to be a Break statement instruction.

[0063] Here, if the branch instruction is a downward jump instruction, it means that the control flow of the program will jump to a position smaller than the current address, usually outside the current loop or structural block. Such jumps are often used to break out of loops, end a code block, or skip certain execution paths. Downward jump instructions are usually used in conjunction with conditional statements such as break or continue to control or break out of loops.

[0064] By determining whether the target address of the jump is exactly the address corresponding to the top of the stack minus 4, the relationship between the jump target address and the top address of the loop stack is compared to determine whether it is an operation of breaking out of the loop. This method, by comparing the difference between the target address and the top address, determines whether the jump occurs outside the loop, so as to effectively identify whether it is a break instruction or other instructions for breaking out of the loop.

[0065] In this way, the instructions for breaking out of the loop are correctly identified to manage the control flow more efficiently and accurately, especially in complex loop and branch structures.

[0066] In some embodiments, performing a second update operation on the loop stack according to the type of branch instruction includes:

[0067] If the type of branch instruction is the return type, traverse the function call counters of the valid entries in the loop stack. If the function call counter is 0, delete the corresponding entry until the first entry with a non-zero function call counter is determined, and subtract 1 from the function call counter of the entry; if there is no entry with a non-zero function call counter, delete all entries.

[0068] Here, the instruction of the return type can be the Return instruction.

[0069] A processing method for an instruction of the return type, such as the Return instruction, is proposed. That is, starting from the position pointed to by the current loop stack pointer, traverse and detect the function call counters of all valid entries. If the function call counter is equal to 0, directly delete the entry until the first entry with a non-zero function call counter is encountered, and at the same time decrement its function call counter by 1 or traverse all valid entries.

[0070] Specifically, when the Return instruction is encountered, traversing the function call counters in the stack can ensure that only valid and incompletely ended function call information remains in the stack, avoiding unnecessary data residues.

[0071] By checking and reducing the function call counter (i.e., tracking the number of calls of the current function), the stack entries that are no longer needed are effectively released, avoiding wasting memory resources. If there are no incompletely ended function calls in the stack (i.e., the function call counter is 0), all entries are deleted. If there are still incompletely finished function calls, the corresponding counter is decremented by 1 to ensure that the stack structure is always correct.

[0072] In this way, by reducing the number of invalid entries, unnecessary stack traversals and storage are reduced, improving the program running efficiency.

[0073] In some embodiments, the method further includes:

[0074] Using the first predictor and / or the second predictor to perform branch prediction according to the updated loop stack to obtain a prediction result.

[0075] Here, through the cooperation of the first predictor and / or the second predictor, combined with the updated loop stack, the behavior of the conditional branch can be predicted. The prediction result may include: whether the branch instruction will jump or continue to execute.

[0076] In this way, by knowing the program execution path in advance through branch prediction, the instruction pipeline stall or flush phenomenon caused by branch jumps can be reduced (for example, reloading data during wrong prediction).

[0077] In some embodiments, the using the first predictor and / or the second predictor to perform branch prediction according to the updated loop stack includes at least one of the following:

[0078] The first predictor obtains the loop iteration count value of the branch instruction from the updated loop stack and performs branch prediction according to the loop label and the loop iteration count value of the branch instruction;

[0079] The second predictor obtains the loop iteration count value of the branch instruction from the updated loop stack, determines the historical information corresponding to the branch instruction according to the loop label and loop iteration count value of the branch instruction, and performs branch prediction according to the historical information.

[0080] Here, the first predictor is a predictor based on IMLI-SIC (IMLI Single Indirect Cache, Indirect Memory Level Indexing-Single Indirect Cache), and the second predictor is a predictor based on IMLI-OH (IMLI-One-Hot Encoding, Indirect Memory Level Indexing-One-Hot Encoding).

[0081] Combined Figure 2 Speaking of which, PC represents the program counter, which stores the address of the currently executed instruction;

[0082] The IMLI counter monitors the iteration index of the innermost loop in the program when fetching instructions and records the loop iteration count value.

[0083] The saturation counter is used to monitor the execution times, jump times, etc. of instructions.

[0084] IMLI-SIC represents a branch prediction method that uses a single indirect cache (SIC) to store branch history information and is indexed through the memory access pattern.

[0085] The first predictor can obtain the loop iteration count value related to the current branch instruction (such as Figure 4 IMLIcount in) from the updated loop stack. According to the loop label (Tag) and loop iteration count value of the branch instruction, the first predictor can predict whether a branch occurs. For example, if a certain loop has been executed multiple times, the first predictor can speculate whether to continue or jump out of the current loop.

[0086] Combined Figure 3 Speaking of which, IMLI historical information represents the historical records related to IMLI, such as the previous branch execution situation;

[0087] PIPE represents the pipeline (Pipeline);

[0088] IMLI-OH is another prediction method, which means using one-hot encoding to represent the historical behavior of branches and predicting it.

[0089] The second predictor can also obtain the loop iteration count value from the updated loop stack. Based on the loop tag of the branch instruction and the loop iteration count value, the second predictor can make a prediction by combining the historical information of the branch instruction to determine whether to continue or break out of the current loop. Here, the historical information generally refers to the data related to the previous execution of the branch instruction (for example, the records of previous jumps or non-jumps).

[0090] Here, the two prediction tables of IMLI-OH and IMLI-SIC can read the loop iteration counter value in the table entry pointed to by the current pointer from IMLI-STACK for training and prediction of the branch predictor table. That is, IMLI-STACK provides the loop iteration count value for the two prediction tables of IMLI-OH and IMLI-SIC.

[0091] Combined with the loop iteration count value, the first predictor and the second predictor cooperate to make predictions, which can more accurately predict branch instructions when executing a loop, thereby improving the execution efficiency of the program and reducing latency. Specifically, considering that the traditional IMLI counter does not fully exploit all possible correlations in the innermost loop, the innermost loop is a "relative" concept, while the traditional IMLI counter adopts a relatively simple maintenance method to find an "absolute" innermost loop; moreover, the traditional method cannot handle loop structures with special exits. The embodiments of the present disclosure take into account the structural complexity of the loop at the same time. The exit of the loop not only means that the loop condition is not satisfied, but also includes cases such as Break and Return. By using the loop stack structure to solve the defects of the traditional IMLI counter (that is, simply counting IMLI_count (incrementing for backward jumps and clearing to 0 for non-jumps)), the relationship of the loop nesting structure is constructed through the loop stack of the embodiments of the present disclosure, and the detection of loop exits such as Break or Return instructions is realized, and the loop iteration count is more accurately counted, thereby further improving the branch prediction performance.

[0092] Figure 4 This is a schematic diagram of a loop stack structure provided by an embodiment of the present disclosure; as Figure 4 shown, the loop stack structure includes: a first identification bit, a loop iteration counter, a function call counter, and a second identification bit; wherein,

[0093] The first identification bit is used to indicate and record the loop tag of the branch instruction, and the loop tag is calculated according to the count value of the program counter;

[0094] The loop iteration counter is used to record the loop iteration count value of the branch instruction;

[0095] The function call counter is used to record the number of times the loop calls a sub-function of the branch instruction;

[0096] The second identification bit is used to record whether the entry corresponding to the branch instruction is valid.

[0097] Figure 4 In it, Tag represents the first identification bit, that is, a marker used to identify the branch prediction information of a specific loop or branch instruction, which is used to assist the predictor in distinguishing different loops or branch instructions. In the loop stack, Tag is a unique identifier used to represent the identity of the current loop or branch instruction. For example, during the push operation of a loop, a specific tag (Tag) may be assigned each time entering the loop to help distinguish different loop execution paths.

[0098] IMLI count represents the loop iteration counter; among them, IMLI (Inner Most Loop Iteration, the innermost loop iteration) refers to loop iteration information, which is usually related to the number of loop iterations and the current iteration number. In the loop stack, IMLI count is used to record the iteration number of the current loop, such as for recording the number of executed loop iterations, and whether the condition is met to jump out of the loop or continue execution.

[0099] Call_cnt represents the function call counter, which is used for the call counting of functions or subroutines. For a recursively or repeatedly called function, Call_cnt can record the number of times the function is called. This value in the loop stack can also be used to analyze the nesting of loops or the depth of function calls, thereby assisting branch prediction.

[0100] Enable represents the second identification bit; in the loop stack, Enable can be used to indicate whether to enable the current branch prediction, loop prediction, or a specific prediction mode. If Enable is 1, it means that the current loop prediction and branch prediction are valid and prediction operations can be performed; if it is 0, it means that the prediction function is disabled, and the processor may choose not to perform prediction or use other methods for processing.

[0101] The above branch prediction method is implemented by using the loop stack structure, and by classifying and processing different types of branch instructions, the accuracy and efficiency of branch prediction are optimized.

[0102] Figure 5 It is a schematic flowchart of a branch prediction method provided by an application embodiment of the present disclosure; as Figure 5 shown, the branch prediction method adopts a loop stack as shown in Figure 4 shown, where Tag is obtained by PC hashing and is used to compare whether it is the same branch instruction, IMLI count is used to count the number of loop iterations, Call_cnt is used to record how many times the loop calls a subfunction, and Enable indicates whether the entry is valid.

[0103] The branch prediction method includes:

[0104] Step 501: Determine whether the branch instruction is a conditional instruction for backward jump; if it is a conditional instruction for backward jump, go to Step 502; if it is not a conditional instruction for backward jump, go to Step 503;

[0105] Here, the conditional branch for backward jump is used as the judgment condition for the loop. If it is a conditional instruction for backward jump, it is considered to enter the loop. If it is not a conditional instruction for backward jump, it is considered not to enter the loop, and the instruction type needs to be further judged.

[0106] Step 502: Label matching; if the label matches, go to Step 5021 to update the loop iteration counter; if the label does not match, go to Step 5022 to allocate a new table entry;

[0107] Here, it is judged whether it is the same branch by whether the Tag of the branch instruction matches the first identification bit at the current stack top;

[0108] If the Tag of the branch instruction is different from the first identification bit at the current stack top, that is, the label does not match and it is not the same branch, and a jump occurs, then a new stack top is allocated;

[0109] If the Tag of the branch instruction is the same as the first identification bit at the current stack top, that is, the label matches and it is the same branch, then the loop iteration counter (IMLIcount) is updated according to the branch jump direction; specifically, if it is the same branch and the branch direction is jump, then IMLIcount is incremented by 1; if the direction is not jump, it is considered that the loop ends, the Enable of this table entry is set low, and the pointer is moved down, and a new table entry is allocated at the stack top.

[0110] Step 503: Determine whether it is a Call instruction, a Break instruction or a Return instruction; if it is a Call instruction, go to Step 5031 to update the function call counter; if it is a Break instruction, go to Step 5032 to clear the table entry; if it is a Return instruction, go to Step 5033 to traverse the stack and clear the table entries until a table entry with a non-zero function call counter is encountered;

[0111] Here, it is considered that if the jump is downward and the target address is exactly 4 less than the address corresponding to the stack top, it is considered a Break instruction, then the stack top needs to be deleted, and at the same time, the loop stack pointer points to the next layer of the loop.

[0112] If a Call instruction is encountered, the function call counter at the stack top is incremented by 1;

[0113] If a Return instruction is encountered, start traversing and detecting the function call counters of all valid table entries from the position pointed to by the current loop stack pointer. If the function call counter is equal to 0, directly delete the table entry until the first table entry with a non-zero function call counter is encountered and its function call counter is decremented by 1, or all valid table entries have been traversed.

[0114] Embodiments of the present disclosure provide a processor, which includes at least one processor core, and each processor core is configured to execute the branch prediction method.

[0115] Embodiments of the present disclosure provide a processor core, which is configured to execute the branch prediction method.

[0116] As Figure 6 shown, Figure 6 is a schematic structural diagram of a processor core provided by an embodiment of the present disclosure; the processor core includes:

[0117] An acquisition unit, configured to acquire a branch instruction;

[0118] A processing unit, configured to determine whether the branch instruction belongs to a target instruction, where the target instruction is a conditional branch instruction that jumps backward; if the branch instruction belongs to the target instruction, perform a first update operation on the loop stack according to the branch instruction; if the branch instruction does not belong to the target instruction, determine the branch instruction type, and perform a second update operation on the loop stack according to the branch instruction type, where the branch instruction type includes: function call type, loop exit type, return type.

[0119] In some embodiments, the processing unit is configured to determine the loop label of the branch instruction, and match the loop label with the first identification bit at the top of the loop stack;

[0120] If the loop label matches the first identification bit, increment the loop iteration counter of the first identification bit or update the second identification bit at the top of the loop stack according to the jump direction of the branch instruction;

[0121] If the loop label does not match the first identification bit, add a new table entry to the loop stack according to the loop label.

[0122] In some embodiments, the processing unit is configured to, if the branch instruction type is a function call type, increment the function call counter at the top of the loop stack by 1.

[0123] In some embodiments, the processing unit is configured to, if the branch instruction type is a loop exit type, delete the table entry at the top of the loop stack and point the pointer of the loop stack to the next lower-level loop.

[0124] In some embodiments, the processing unit is configured to determine that the branch instruction is of the loop-exiting type if the branch instruction is a downward jump instruction and the target address of the jump is the address corresponding to the top of the loop stack minus the target value.

[0125] In some embodiments, the processing unit is configured to, if the branch instruction type is the return type, traverse the function call counters of the valid entries in the loop stack. If the function call counter is 0, delete the corresponding entry until the first entry with a non-zero function call counter is determined, and subtract 1 from the function call counter of the entry; if there is no entry with a non-zero function call counter, delete all entries.

[0126] In some embodiments, the processing unit is further configured to perform branch prediction using the first predictor and / or the second predictor based on the updated loop stack to obtain a prediction result.

[0127] In some embodiments, the performing branch prediction using the first predictor and / or the second predictor based on the updated loop stack includes at least one of the following:

[0128] The first predictor obtains the loop iteration count value of the branch instruction from the updated loop stack and performs branch prediction based on the loop label and the loop iteration count value of the branch instruction;

[0129] The second predictor obtains the loop iteration count value of the branch instruction from the updated loop stack, determines the historical information corresponding to the branch instruction based on the loop label and the loop iteration count value of the branch instruction, and performs branch prediction based on the historical information.

[0130] It should be noted that: when the above-mentioned processor core implements the corresponding branch prediction method, only the above-mentioned division of each program unit is used for illustration. In actual applications, the above-mentioned processing can be allocated to different program units according to needs, that is, the internal structure of the processor core is divided into different program units to complete all or part of the above-mentioned processing. In addition, the above-mentioned processor core and the corresponding method embodiment belong to the same concept, and the specific implementation process can be seen in the method embodiment, which will not be repeated here.

[0131] Figure 7 The following is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure, as Figure 7 shown, the electronic device 70 includes: a processor 701 and a memory 702 for storing a computer program that can run on the processor;

[0132] The processor 701 includes at least one processor core, and when the processor core is used to run the computer program, it executes the branch prediction method.

[0133] In practical applications, the electronic device 70 may further include: at least one network interface 703. Each component in the electronic device 70 is coupled together through a bus system 704. It can be understood that the bus system 704 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 704 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, in Figure 6 all kinds of buses are labeled as the bus system 704. Among them, the number of the processors 701 can be at least one. The network interface 703 is used for the wired or wireless communication between the electronic device 70 and other devices.

[0134] The memory 702 in the embodiments of the present disclosure is used to store various types of data to support the operation of the electronic device 70.

[0135] The method disclosed in the above embodiments of the present disclosure can be applied to the processor 701 or implemented by the processor 701. The processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of the processor 701 or the instructions in software form. The above-mentioned processor 701 may be a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 701 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present disclosure. The general-purpose processor may be a microprocessor or any conventional processor, etc. Combining the steps of the method disclosed in the embodiments of the present disclosure, it can be directly embodied as being executed and completed by the hardware decoding processor, or executed and completed by the combination of the hardware and software modules in the decoding processor. The software module may be located in the storage medium, and this storage medium is located in the memory 702. The processor 701 reads the information in the memory 702 and combines its hardware to complete the steps of the foregoing method.

[0136] In an exemplary embodiment, the electronic device 70 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontroller units (MCUs), microprocessors, or other electronic components for performing the foregoing method.

[0137] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined, or may be integrated into another system, or some features may be ignored or not executed. In addition, the couplings, direct couplings, or communication connections between the various components shown or discussed may be through some interfaces. The indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0138] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0139] In addition, in each embodiment of the present disclosure, the functional units may all be integrated in one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated in one unit; the above integrated units may be implemented in the form of hardware, or in the form of hardware plus software functional units.

[0140] Those of ordinary skill in the art will understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps including those of the above method embodiments. The foregoing storage medium includes various media that can store program codes, such as removable storage devices, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0141] Alternatively, if the above integrated units are implemented in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present disclosure, in essence or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the various embodiments of the present disclosure. The foregoing storage medium includes various media that can store program codes, such as removable storage devices, ROM, RAM, magnetic disks, or optical discs.

[0142] It should be understood that various forms of the processes shown above can be used, reordering, adding, or deleting steps. For example, the steps recited in the present disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved. There is no limitation herein.

[0143] In the above description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0144] Unless otherwise defined, all technical and scientific terms used in the present disclosure have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the present disclosure are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0145] It should be understood that in the various embodiments of the present disclosure, the magnitude of the serial numbers of the respective implementation processes does not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation processes of the embodiments of the present disclosure.

[0146] In the above description, the terms "first" and "second" are only used to distinguish similar objects and do not represent a specific order for the objects. The terms "first" and "second" are only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. It can be understood that, where permitted, "first" and "second" may be interchanged in a specific order or sequence so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein. In the description of the present disclosure, "a plurality of" means two or more unless otherwise specifically defined.

[0147] As described above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A branch prediction method, characterized in that, The method includes: Obtain a branch instruction and determine whether the branch instruction belongs to a target instruction, where the target instruction is a conditional branch instruction that jumps backward; If the branch instruction belongs to the target instruction, perform a first update operation on the loop stack according to the branch instruction; If the branch instruction does not belong to the target instruction, determine the branch instruction type and perform a second update operation on the loop stack according to the branch instruction type, where the branch instruction type includes: function call type, loop exit type, return type.

2. The method according to claim 1, wherein The performing a first update operation on the loop stack according to the branch instruction includes: Determine the loop label of the branch instruction and match the loop label with the first identification bit at the top of the loop stack; If the loop label matches the first identification bit, increment the loop iteration counter of the first identification bit by 1 according to the jump direction of the branch instruction or update the second identification bit at the top of the loop stack; If the loop label does not match the first identification bit, add a new entry to the loop stack according to the loop label.

3. The method according to claim 1, wherein The performing a second update operation on the loop stack according to the branch instruction type includes: If the branch instruction type is function call type, increment the function call counter at the top of the loop stack by 1.

4. The method according to claim 1, characterized in that The performing a second update operation on the loop stack according to the branch instruction type includes: If the branch instruction type is loop exit type, delete the entry at the top of the loop stack and point the pointer of the loop stack to the next lower-level loop.

5. The method according to claim 4, wherein The determining the branch instruction type includes: If the branch instruction is a downward jump instruction and the target address of the jump is the address corresponding to the top of the loop stack minus the target value, determine that the branch instruction is of the loop exit type.

6. The method according to claim 1, wherein The performing a second update operation on the loop stack according to the branch instruction type includes: If the branch instruction type is return type, traverse the function call counters of the valid entries in the loop stack. If the function call counter is 0, delete the corresponding entry until the first entry with a non-zero function call counter is determined, and decrement the function call counter of the entry by 1; if there is no entry with a non-zero function call counter, delete all entries.

7. The method according to claim 1, characterized in that, The method further includes: Using a first predictor and / or a second predictor, perform branch prediction according to the updated loop stack to obtain a prediction result.

8. The method according to claim 7, characterized in that The using a first predictor and / or a second predictor to perform branch prediction according to the updated loop stack includes at least one of the following: The first predictor obtains the loop iteration count value of the branch instruction from the updated loop stack and performs branch prediction according to the loop label and the loop iteration count value of the branch instruction; The second predictor obtains the loop iteration count value of the branch instruction from the updated loop stack, determines the historical information corresponding to the branch instruction according to the loop label and the loop iteration count value of the branch instruction, and performs branch prediction according to the historical information.

9. A circular stack structure, characterized in that, The structure includes: a first identification bit, a loop iteration counter, a function call counter, and a second identification bit; wherein, The first identification bit is used to indicate a loop label for recording a branch instruction, and the loop label is calculated based on the count value of the program counter; The loop iteration counter is used to record the loop iteration count value of the branch instruction; The function call counter is used to record the number of times of loop calling a sub-function of the branch instruction; The second identification bit is used to record whether the table entry corresponding to the branch instruction is valid.

10. A processor core, characterized in that, The processor core includes: An acquisition unit for acquiring a branch instruction; A processing unit for determining whether the branch instruction belongs to a target instruction, where the target instruction is a conditional branch instruction that jumps backward; if the branch instruction belongs to the target instruction, perform a first update operation on the loop stack according to the branch instruction; if the branch instruction does not belong to the target instruction, determine the branch instruction type, and perform a second update operation on the loop stack according to the branch instruction type, where the branch instruction type includes: function call type, loop exit type, return type.

11. A processor, characterized in that, The processor includes at least one processor core, and each processor core is configured to execute the branch prediction method according to any one of claims 1 to 8.

12. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor includes at least one processor core, and when the processor core executes the program, the steps of the method according to any one of claims 1 to 8 are implemented.

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