A multi-functional improved branch recording buffer system

Abstract

The application provides a multi-functional improved branch record buffer system, belonging to the technical field of CPU buffer, and comprising a BRB hardware structure and a working process of the BRB hardware; the BRB hardware comprises a record branch key information link and a multi-pointer cooperative management link; the working process of the BRB hardware comprises the following steps: S1, an allocation stage step, S2, an analysis stage step, S3, a submission and release step, and S4, an error processing step, which comprises a prediction error triggering link and a pipeline rollback link; in view of the problems of rollback and error positioning difficulty in the branch prediction management system in the traditional CPU out-of-order execution, the application sends the correct updated data to the BPU through the BRB, and can accurately rollback and clear the younger branch entries when encountering an error branch.

Description

Technical Field

[0001] This invention relates to the field of CPU buffer technology, and more specifically to a multifunctional improved branch record buffer system. Background Technology

[0002] As CPU performance demands continue to increase, higher requirements are being placed on branch prediction performance. Many high-end CPUs currently use out-of-order branch instruction parsing to maximize performance, which leads to the following problems:

[0003] Uncertainty in updating branch prediction unit components: Traditional branch prediction structures assume that branches are parsed sequentially and the results are written back to the branch prediction unit (BPU). However, when out-of-order parsing occurs, younger but incorrect branches may update the BPU first, wasting prediction resources and potentially reducing prediction accuracy.

[0004] Branch information is scattered and management is complex: A branch instruction will access and update multiple prediction-related components (such as the Global History Register GHR, BTB, return address stack RAS, etc.) during the process from instruction fetch to final commit. Without unified management, it is easy for update and rollback chaos to occur in out-of-order branches.

[0005] Rapid rollback and error localization are required: When a branch prediction error occurs, the pipeline needs to be refreshed and rolled back to the correct branch. Without a unified record of all branch information and the ability to quickly locate the erroneous branch, a significant number of clock cycles are wasted, reducing processor throughput efficiency.

[0006] Traditional CPU out-of-order execution branch prediction management systems have the following problems:

[0007] 1. Incorrect prediction update: When younger branches complete first, the branch prediction unit (BPU) may be incorrectly updated, reducing prediction accuracy;

[0008] 2. Dispersed branch information: Branch-related data (such as target address, historical records, etc.) are scattered across multiple components (BTB, RAS, GHR, etc.), making management complex;

[0009] 3. Low rollback efficiency: When a prediction error occurs, multiple cycles are required to locate the erroneous branch, which slows down the pipeline efficiency.

[0010] 4. Inability to balance out-of-order parsing and branch prediction updates: When the younger branch completes first, it often needs to wait for the results of the older branch, or it may cause incorrect updates to be written to the BPU first.

[0011] 5. Difficult rollback and error localization: If a branch prediction error occurs, a large number of searches or interactions of multiple pipeline signals are required to find the initial erroneous branch.

[0012] 6. Lack of centralized management: Branch prediction information (branch type, target PC, direction information, historical information, whether it is an error path, etc.) is often scattered in different components, which is not conducive to rapid scheduling and resource reuse.

[0013] Modern CPUs increasingly employ 4-issue, 6-issue, or even higher issue widths, meaning multiple instructions, including multiple branches, may be issued per cycle. The execution unit may parse branch instructions in the order of their actual completion time, rather than necessarily in program order. This poses a challenge to the branch predictor component, which requires serial updates. A typical BPU contains various components such as the BTB, branch predictor, return address stack (RAS), and global history register (GHR). Once a branch is parsed, these resources need to be updated. Without unified management, erroneous writes, duplicate updates, or wasted resources can easily occur.

[0014] This invention proposes a multifunctional improved branch record buffer system to solve problems such as lack of unified management, easy occurrence of erroneous writes, duplicate updates, or waste of resources. Summary of the Invention

[0015] This invention can centrally manage the branch information of all branches in transit between the CPU front-end fetch unit and the execution unit, arbitrate the branch parsing order, update the BPU components, and accurately perform rollback processing when needed, thereby effectively improving the accuracy of branch prediction and pipeline efficiency, and overcoming the problems in the background art mentioned above.

[0016] Based on the above technical concept, the technical solution adopted by this invention is as follows:

[0017] A multi-functional improved branch record buffer system, including BRB hardware architecture and BRB hardware workflow;

[0018] BRB hardware includes a process for recording key branch information and a process for managing multiple pointers collaboratively.

[0019] The workflow of BRB hardware includes the following steps:

[0020] S1, the allocation phase step, which includes the instruction fetching unit branch detection step and the unidentified branch processing step;

[0021] S2, the parsing phase steps, which include the execution unit feedback loop and the sequence guarantee loop;

[0022] S3, the commit and release steps, which include the ROB commit branch command step and the resource release step;

[0023] S4, Error Handling Steps, which include error prediction and pipeline rollback.

[0024] Further defining the above technical solution, the step of recording key branch information includes defining entry fields, which include the following fields:

[0025] Branch PC: The address of the branch instruction, used to match the branch resolution result returned by the execution unit;

[0026] BrType: Branch type;

[0027] Predicted Target: The predicted target address;

[0028] Actual Target: The actual target address after the execution unit resolves the branch;

[0029] Direction: The actual jump direction;

[0030] BP Info: Additional information about the predictor's dependencies;

[0031] Resolve Status: Marks the status of the entry;

[0032] Checkpoint: Saves the critical state of the BPU before branch resolution.

[0033] Further defining the above technical solution, the multi-pointer collaborative management step includes:

[0034] Branch Pointer: Points to the oldest branch entry that needs to be updated. Update condition: The execution unit sends a branch resolution valid signal and the branch is the entry pointed to by the pointer.

[0035] Deallocation Pointer: Points to the oldest releasable entry. Advancement condition: The branch has been committed and the BPU update is complete.

[0036] Early Flush Pointer: Dynamically points to the earliest potentially faulty branch, clearing all entries after this pointer;

[0037] Commit Pointer: Points to the branch commands that have been committed sequentially; Advancement condition: The branch is committed through the reorder buffer and there are no exceptions.

[0038] Further defining the above technical solution, in step S1, the allocation stage includes the branch detection step of the instruction fetching unit, which includes pre-decoding and identifying branch instructions, allocating idle BRB entries, and writing prediction information provided by Branch PC, BrType, and BPU. The unidentified branch processing step includes allocating BRB entries, marking the prediction information as invalid, and waiting for the execution unit to supplement if the branch prediction unit does not predict the branch.

[0039] Further defining the above technical solution, in step S2, the parsing phase, the execution unit feedback loop includes sending resolve_pc, actual_target, and direction signals. BRB matches entries through Branch PC and updates the Actual Target and Direction fields.

[0040] Further defining the above technical solution, the sequential guarantee step includes updating the entry content only if the parsed branch is not the entry currently pointed to by the BranchPointer, without triggering a BPU update; and triggering a BPU update arbitration when the BranchPointer moves to that entry.

[0041] Further defining the above technical solution, in step S3, the commit and release step, the ROB commit branch instruction includes sending a commit_pc signal, the BRB marks the corresponding entry as "committed", and advances the Commit Pointer to the next parsed but not committed entry; the resource release step includes releasing the entry to the release queue when the entry pointed to by the Deallocation Pointer has been committed and the BPU update is completed.

[0042] Further defining the above technical solution, in step S4, the error handling step, the error prediction triggering stage includes the BPU or execution unit sending an error prediction branch instruction pc signal, and the BRB locating the erroneous branch entry through binary search or hardware acceleration matching; the pipeline rollback stage includes activating the Early Flush Pointer, clearing all subsequent entries, and if the Checkpoint is saved, restoring the branch prediction unit to the state before the erroneous branch.

[0043] Further limitations on the above technical solution include a key circuit structure, which includes parallel matching logic and a performance optimization structure. The parallel matching logic includes a PC matcher and a priority encoder. The PC matcher includes a comparator for comparing BRB entries, a parallel matching branch parsing pc or an error prediction pc, and a priority encoder that converts multiple matching results into an index of the highest priority entries.

[0044] Further defining the above technical solution, the performance optimization structure is configured to pre-release some entries when the difference between DeallocationPointer and Branch Pointer exceeds a threshold, supporting priority allocation.

[0045] Compared with the prior art, the beneficial effects of the present invention are:

[0046] 1. By setting up a unified branch record buffer (BRB) in the CPU front-end / middle stage, all branch instruction information in the pipeline is centrally recorded and managed.

[0047] 2. Enable the BRB to have several pointers to track the branch parsing order, reclaimable entries, and the scope of cleanup when an early flush occurs during pre-decoding.

[0048] 3. When a branch is parsed or committed, BRB will send the correct update data to BPU and can accurately roll back and clear younger branch entries when encountering an incorrect branch. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of an improved BRB structure in a multifunctional improved branch record buffer system of the present invention;

[0051] Figure 2 This is a flowchart illustrating the multi-pointer management mechanism in a multifunctional improved branch record buffer system according to the present invention. Detailed Implementation

[0052] The following is in conjunction with the appendix Figures 1-2 The present invention will be described in further detail below.

[0053] Example 1: This example provides a multifunctional improved branch record buffer system, such as... Figures 1-2 As shown, this includes the BRB hardware structure and the BRB hardware workflow.

[0054] BRB hardware includes a process for recording key branch information and a process for managing multiple pointers collaboratively.

[0055] The workflow of BRB hardware includes the following steps:

[0056] S1, the allocation phase step, which includes the instruction fetching unit branch detection step and the unidentified branch processing step;

[0057] S2, the parsing phase steps, which include the execution unit feedback loop and the sequence guarantee loop;

[0058] S3, the commit and release steps, which include the ROB commit branch command step and the resource release step;

[0059] S4, Error Handling Steps, which include error prediction and pipeline rollback.

[0060] The process of recording key branch information includes defining entry fields, which include the following fields:

[0061] Branch PC: The address of the branch instruction, used to match the parsed result returned by the execution unit;

[0062] BrType: Branch type;

[0063] Predicted Target: The predicted target address;

[0064] Actual Target: The actual target address after the execution unit resolves the branch;

[0065] Direction: The actual jump direction;

[0066] BP Info: Additional information about the predictor's dependencies;

[0067] Resolve Status: Marks the status of the entry;

[0068] Checkpoint: Saves the critical state of the branch prediction unit before branch resolution.

[0069] The multi-pointer collaborative management process includes:

[0070] Branch Pointer: Points to the oldest branch entry that needs to be updated. Update condition: The execution unit sends a branch resolution valid signal and the branch is the entry pointed to by the pointer.

[0071] Deallocation Pointer: Points to the oldest releasable entry. Advancement condition: The branch has been committed and the BPU update is complete.

[0072] Early Flush Pointer: Dynamically points to the earliest potentially faulty branch, clearing all entries after this pointer;

[0073] Commit Pointer: Points to the branch commands that have been committed sequentially; Advancement condition: The branch is committed through the reorder buffer and there are no exceptions.

[0074] The S1 allocation stage step includes the branch detection step of the instruction fetching unit, which includes pre-decoding and identifying branch instructions, allocating idle BRB entries, and writing prediction information provided by Branch PC, BrType, and BPU. The unidentified branch processing step includes allocating BRB entries, marking the prediction information as invalid, and waiting for the execution unit to supplement if the branch prediction unit does not predict the branch.

[0075] S2, the parsing phase step, includes the execution unit feedback loop sending resolve_pc, actual_target, and direction signals. BRB matches entries through Branch PC and updates the Actual Target and Direction fields.

[0076] The sequential guarantee mechanism includes updating the content of the resolved branch if it is not the current entry pointed to by the Branch Pointer, without triggering the branch prediction unit to update. When the Branch Pointer moves to the entry, the branch prediction unit is triggered to update the arbitration.

[0077] The S3 step, the commit and release step, includes the ROB commit branch instruction step, which includes sending the commit_pc signal, the BRB marking the corresponding entry as "committed", and advancing the Commit Pointer to the next parsed but uncommitted entry; the resource release step includes releasing the entry to the release queue when the entry pointed to by the Deallocation Pointer has been committed and the branch prediction unit has been updated.

[0078] S4, the error handling step, includes the error prediction triggering step, which involves the branch prediction unit or execution unit sending a branch pc signal predicting the error, and the BRB locating the erroneous branch entry through binary search or hardware acceleration matching; the pipeline rollback step includes activating the Early Flush Pointer, clearing all subsequent entries, and if the Checkpoint is saved, restoring the BPU to the state before the erroneous branch.

[0079] It also includes a key circuit structure, which includes parallel matching logic and a performance optimization structure. The parallel matching logic includes a PC matcher and a priority encoder. The PC matcher includes a comparator for comparing BRB entries, a PC for parallel matching branch parsing, or a PC for error prediction branches. The priority encoder includes converting multiple matching results into an index of the highest priority entries.

[0080] The performance optimization structure is configured to pre-release some entries when the difference between the Deallocation Pointer and the Branch Pointer exceeds a threshold, supporting priority allocation.

[0081] Example 2: This example provides a multifunctional improved branch record buffer system, such as... Figures 1-2 As shown, the hardware structure of BRB is also included:

[0082] BRB Entry: Each entry records the PC, branch type (Br Type), target PC, branch direction (taken / not-taken), and additional information required by the prediction unit (BP Info) for this branch. Branch instructions from the instructions provided during the fetch stage are pre-decoded and written to the BRB to ensure that even if the branch instruction is not recognized as a branch instruction in the branch prediction unit, it can still occupy the BRB entry.

[0083] BRB Pointers:

[0084] 1. Branch Pointer: Points to the branch entry that is currently being parsed or will be parsed next. After the execution unit issues a branch parsing signal, this pointer moves to the corresponding entry.

[0085] 2. Deallocation Pointer: Points to deallocate BRB entries, usually one item behind BranchPointer, used to update multiple branches and release resources simultaneously when certain conditions are met;

[0086] 3. Early Flush Pointer: Points to the branch position that can be refreshed early. If some pipelines fail prematurely, the entries after this pointer will be cleared.

[0087] Commit Pointer: Points to the branch commands that have been committed sequentially. This pointer indicates that the current branch command has been successfully committed and will not appear on an incorrect path and be flushed.

[0088] Workflow:

[0089] Branch Allocation: When the IFU recognizes a branch instruction, it writes the branch information into an empty entry in the BRB. If the branch is not recognized by the BPU and there is no prediction result, it can be registered in the BRB as a placeholder, and the complete information can be added later during parsing.

[0090] Branch Update (Resolve & Retire): After the execution unit finishes executing the branch instruction, it sends a branch resolution signal to the BRB, along with the actual jump result of the current branch, and compares it with the previous prediction. If an older branch has not yet been updated, it needs to wait for the older branch to be updated first. When it is the turn of this branch, it uses the branch result recorded in the BRB to determine which components in the branch prediction unit need to be updated, and completes the update process according to the arbitration of the read / write port.

[0091] Flush: If a branch is determined to be a misprediction, BRB quickly locates the entry using the EarlyFlush Pointer or Retire Pointer. All younger branches following the entry are then cleared to prevent updates to mispredicted paths.

[0092] Deallocation: Once a branch has been committed and all components in the branch prediction unit have been updated, there is no longer a need to occupy an entry in the BRB. The BRB releases the entry based on the Deallocation Pointer to allow new branch instructions to be allocated to this area.

[0093] Core functions and effects:

[0094] Maintain the order of branch parsing: Even if a younger branch parses first, the BRB can still arbitrate and schedule the update order of the BPU to avoid writing in the wrong order.

[0095] Centralized branch management: All information regarding branch type, target, prediction information, and resolution status is uniformly recorded in the BRB.

[0096] Quick rollback and relocation: If an error branch occurs, the pipeline can be cleaned up and rolled back immediately.

[0097] Improve prediction accuracy and resource utilization: Avoid wasting BPU resources on young, flawed branches.

[0098] Improved BRB structure: Allows branch instructions to be written to the corresponding entries in any out-of-order order, and retains all branch information until the instruction is committed.

[0099] Multi-pointer management mechanism: Branch resolution and rollback are maintained collaboratively through Branch Pointer, Deallocation Pointer and Early FlushPointer.

[0100] Centralized BPU Update: During branch parsing, the BRB determines how and when to update or roll back components such as the BTB, Return Address Stack (RAS), and Global History register.

[0101] Flush rollback: BRB can quickly locate the correct path and clear younger entries based on different pointers after an error branch is discovered, thus improving error handling efficiency.

[0102] Effectively supports out-of-order parsing: There is no need to force branches to parse in age order, thereby improving the parallelism of execution units.

[0103] Accurate and fast branch rollback: BRB pointer-based management can find erroneous branches and remove erroneous paths in the shortest possible time.

[0104] Prediction accuracy is more guaranteed: No more further mispredictions will be caused by incorrect updates to BPU components due to young, faulty branches.

[0105] Unified centralized management: All branch information is aggregated within the BRB, avoiding the difficulty of coordinating multiple scattered structures.

[0106] Storage content: Different prediction information can be stored according to different branch predictors.

[0107] Pointer quantity and logical variations: Different types of flushes can be distinguished by adding or removing pointers or adding other pointers, depending on the processor pipeline depth or the maximum concurrency of branch instructions.

[0108] Branch merging: If you want to compress two branch records into a single entry under certain circumstances, you can also fine-tune the BRB structure. However, you must ensure that the update and rollback logic are consistent.

[0109] More flexible allocation strategies: For example, in high-pressure scenarios, BRBs can use circular buffers or be allocated by priority to reduce allocation contention.

[0110] Compatible with other prediction components: This invention can be used with various branch prediction algorithms such as TAGE and GShare. It only requires reporting the corresponding information during branch parsing.

[0111] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention, enabling those skilled in the art to understand and apply the invention. However, it should not be construed that the specific implementation of the present invention is limited to these descriptions.

Claims

1. A multi-functional improved branch recording buffer system, characterized by, The BRB hardware structure and the working process of the BRB hardware, wherein: The BRB hardware structure comprises a record branch key information link and a multi-pointer cooperative management link; The record branch key information link comprises entry field definition, and the field definition comprises the following fields: Branch PC: branch instruction address, used for matching the branch resolution result returned by an execution unit; BrType: branch type; Predicted Target: predicted target address; Actual Target: actual target address after the execution unit resolves the branch; Direction: actual jump direction; BP Info: additional information relied on by a predictor; Resolve Status: entry state marker; Checkpoint: save the BPU key state before branch resolution; The multi-pointer cooperative management link comprises: Branch Pointer: points to the oldest branch entry that needs to be updated, and the update condition is that the execution unit sends a branch resolution effective signal and the branch is the entry pointed to by the pointer; Deallocation Pointer: points to the oldest entry that can be released, and the promotion condition is that the branch has been committed and the BPU update is completed; Early Flush Pointer: dynamically points to the earliest possible incorrect branch, and the clearing range is all entries after the pointer; Commit Pointer: the promotion condition is that the branch is committed through the reordering buffer, and there is no exception; The working process of the BRB hardware comprises the following steps: S1, an allocation stage step, which comprises a branch detection unit of the instruction unit and an unidentified branch processing link; the branch detection unit of the instruction unit comprises pre-decoding identification of a branch instruction, allocation of a free BRB entry, writing of Branch PC, BrType and predicted information provided by the BPU, and the unidentified branch processing link comprises, if the branch prediction unit does not predict the branch, still allocating the BRB entry, marking the predicted information as invalid, and waiting for the execution unit to supplement; S2, a resolution stage step, which comprises an execution unit feedback link and a sequential guarantee link; the execution unit feedback link comprises sending of resolve_pc, actual_target and direction signals, and the BRB matches the entry through Branch PC, and updates Actual Target and Direction fields; the sequential guarantee link comprises, if the resolved branch is not the entry currently pointed to by the Branch Pointer, only updating the entry content, not triggering the BPU update, and when the Branch Pointer moves to the entry, triggering the BPU update arbitration; S3, a commit and release step, including a ROB commit branch instruction link and a resource release link; the ROB commit branch instruction link includes sending a commit_pc signal, the BRB marking the corresponding entry as "committed", and advancing the Commit Pointer to the next parsed but uncommitted entry; the resource release link includes releasing the entry to the releasable queue when the entry pointed to by the Deallocation Pointer is committed and the BPU update is completed; S4, an error handling step, including a prediction error triggering link and a pipeline rollback link; the prediction error triggering link includes the BPU or the execution unit sending a prediction error pc signal, and the BRB locating the error branch entry by binary search or hardware acceleration matching; the pipeline rollback link includes activating the Early Flush Pointer, clearing all entries after the pointer, and if the Checkpoint is saved, restoring the branch prediction unit to the state before the error branch.

2. The multi-functional improved branch recording buffer system according to claim 1, wherein, Further including a key circuit structure, the key circuit structure including parallel matching logic and performance optimization structure, the parallel matching logic including a PC matcher and a priority encoder, the PC matcher including a comparator for comparing BRB entries, and the priority encoder including converting multiple matching results into the highest priority entry index.

3. The multi-functional improved branch recording buffer system according to claim 2, wherein, The performance optimization structure is configured to pre-release part of the entries when the difference between the Deallocation Pointer and the Branch Pointer exceeds a threshold, and supports priority allocation.

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