Cache storage system and using method, device, equipment and medium thereof

Abstract

The invention provides a cache storage using method and device, equipment and a medium, which are used for solving the technical problems of large bumping probability and serious performance reduction caused by large width of a cache storage area when the cache storage is used in the related technology. The method comprises the following steps: transversely dividing a cache storage area into a plurality of cache lines; and longitudinally dividing each cache line into a plurality of cache blocks with the same number, wherein the source graph and the cache storage graph are used for placing data by establishing a mapping relationship.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular, to a method, device, equipment and medium for using a cache memory. Background Art

[0002] In the related art, when using a cache memory, the cache memory Cache is usually arranged in three ways: fully associative, direct mapped, and set associative. However, a cache line corresponds to multiple disk address sets, and thus, when executing a read data strategy, the problem of cache thrashing frequently occurs, resulting in a small support angle and a large cache thrashing probability. Therefore, there is an urgent need for a method to reduce the occurrence frequency of cache thrashing without significantly increasing the hardware cost. Summary of the Invention

[0003] The present invention provides a method, device, equipment and medium for using a cache memory, so as to solve the technical problem in the related art that when using a cache memory, the width of the cache storage area is large, resulting in a large thrashing probability and serious performance degradation.

[0004] In a first aspect, an embodiment of the present invention provides a method for using a cache memory, the method including:

[0005] Horizontally dividing a cache storage area into a plurality of cache lines;

[0006] Vertically dividing each cache line into a plurality of cache blocks with the same number, wherein data is placed by establishing a mapping relationship between a source graph and a cache storage graph.

[0007] In a possible implementation manner, in the method provided by the embodiment of the present invention, each cache line has the same height and each cache line has the same width.

[0008] In a possible implementation manner, in the method provided by the embodiment of the present invention, the method further includes:

[0009] When reading data in the cache storage area, determining two target cache lines according to the coordinates of a source graph;

[0010] Determining a reading coordinate based on the two target cache lines;

[0011] Determining a reading area corresponding to the source graph in the cache storage area by using the reading coordinate.

[0012] In a possible implementation manner, in the method provided by the embodiment of the present invention, the method further includes:

[0013] When replacing the data in the cache storage area, determine the instructions for the first cache line to be replaced, the second cache line to be replaced, and the replacement data based on the replacement coordinates of the replacement area;

[0014] Replace the data of the first cache line to be replaced and the second cache line to be replaced through the instructions.

[0015] In a possible implementation manner, in the method provided by the embodiment of the present invention, the replacement coordinates include a first horizontal coordinate, a second horizontal coordinate, a first vertical coordinate, and a second vertical coordinate; then the instructions for determining the first cache line to be replaced, the second cache line to be replaced, and the replacement data based on the replacement coordinates of the replacement area include:

[0016] Obtain the replacement identifier of the area to be replaced;

[0017] Determine the first cache line to be replaced and the second cache line to be replaced in sequence according to the first horizontal coordinate, the first vertical coordinate, the second horizontal coordinate, and the second vertical coordinate, and determine whether the replacement identifier is hit;

[0018] Determine the instructions according to the hit result.

[0019] In a possible implementation manner, in the method provided by the embodiment of the present invention, if the first horizontal coordinate hits the replacement identifier, perform the first instruction on the first cache line to be replaced; if the second horizontal coordinate hits the replacement identifier, perform the first instruction on the first cache line to be replaced.

[0020] In a possible implementation manner, in the method provided by the embodiment of the present invention, each cache line is provided with a first pointer and a second pointer, and the pointer state of each cache line is determined by the first pointer and the second pointer. If the first vertical coordinate hits the replacement identifier, determine the corresponding instruction according to the pointer state of the first cache line to be replaced;

[0021] If the second vertical coordinate hits the replacement identifier, determine the corresponding instruction according to the pointer state of the second cache line to be replaced.

[0022] In a second aspect, an embodiment of the present invention provides a device for using a cache storage, including:

[0023] A first processing unit for horizontally dividing the cache storage area into multiple cache lines;

[0024] A second processing unit for vertically dividing each cache line into multiple cache blocks with the same quantity, where the source graph and the cache storage graph place data by establishing a mapping relationship.

[0025] In a possible implementation manner, in the device provided by the embodiment of the present invention, the height of each cache line is the same, and the width of each cache line is the same.

[0026] In a possible implementation manner, in the device provided by the embodiment of the present invention, a reading unit is further included, and the reading unit is configured to:

[0027] When reading data in the cache storage area, determine two target cache lines according to the coordinates of the source map;

[0028] Determine the reading coordinates based on the two target cache lines;

[0029] Use the reading coordinates to determine the reading area corresponding to the source map in the cache storage area.

[0030] In a possible implementation manner, in the device provided by the embodiment of the present invention, a replacement unit is further included, and the replacement unit is configured to:

[0031] When replacing data in the cache storage area, determine the first cache line to be replaced, the second cache line to be replaced, and the instruction for the replacement data based on the replacement coordinates of the replacement area;

[0032] Replace the data of the first cache line to be replaced and the second cache line to be replaced through the instruction.

[0033] In a possible implementation manner, in the device provided by the embodiment of the present invention, the replacement coordinates include a first horizontal coordinate, a second horizontal coordinate, a first vertical coordinate, and a second vertical coordinate; then the replacement unit is specifically configured to:

[0034] Obtain the replacement identifier of the area to be replaced;

[0035] Determine the first cache line to be replaced and the second cache line to be replaced in sequence according to the first horizontal coordinate, the first vertical coordinate, the second horizontal coordinate, and the second vertical coordinate, and determine whether the replacement identifier is hit;

[0036] Determine the instruction according to the hit result.

[0037] In a possible implementation manner, in the device provided by the embodiment of the present invention, if the first horizontal coordinate hits the replacement identifier, the replacement unit is specifically configured to perform a first instruction on the first cache line to be replaced; if the second horizontal coordinate hits the replacement identifier, the replacement unit is specifically configured to perform a first instruction on the first cache line to be replaced.

[0038] In a possible implementation manner, in the device provided by the embodiment of the present invention, each cache line is provided with a first pointer and a second pointer, and the pointer state of each cache line is determined by the first pointer and the second pointer. If the first vertical coordinate hits the replacement identifier, the replacement unit is specifically configured to determine the corresponding instruction according to the pointer state of the first cache line to be replaced;

[0039] If the second vertical coordinate hits the replacement identifier, the replacement unit is specifically configured to determine the corresponding instruction according to the pointer state of the second cache line to be replaced.

[0040] In a third aspect, an embodiment of the present invention provides an electronic device, including: at least one processor, at least one memory, and computer program instructions stored in the memory. When the computer program instructions are executed by the processor, the method provided in the first aspect of the embodiment of the present invention is implemented.

[0041] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by the processor, the method provided in the first aspect of the embodiment of the present invention is implemented.

[0042] In the embodiment of the present invention, first, the cache storage area is horizontally divided into multiple cache lines; then each cache line is vertically divided into multiple cache blocks with the same number. Compared with the related art, by horizontally and vertically setting the cache storage area, the width of the cache line is lower under the same storage space, supporting large-angle rotation, and significantly reducing the thrashing probability. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a mapping schematic diagram of a cache storage area provided in the background art of the present invention;

[0044] Figure 2 It is a flowchart schematic diagram of a method for using cache storage provided in an embodiment of the present invention;

[0045] Figure 3 It is a schematic diagram of the principle of Warp transformation provided in an embodiment of the present invention;

[0046] Figure 4 It is a schematic diagram of the structure of a cache storage area provided in an embodiment of the present invention;

[0047] Figure 5 It is a schematic diagram of the cache line division of a cache storage area provided in an embodiment of the present invention;

[0048] Figure 6 It is a flowchart schematic diagram of a method for using cache storage in reading provided in an embodiment of the present invention;

[0049] Figure 7 It is a flowchart schematic diagram of a method for using cache storage in replacement provided in an embodiment of the present invention;

[0050] Figure 8 It is a schematic diagram of the specific state of a cache line in a cache storage area provided in an embodiment of the present invention;

[0051] Figure 9 It is a schematic diagram of the first six state jumps provided in an embodiment of the present invention;

[0052] Figure 10 Schematic diagrams of the last six state jumps provided by the embodiments of the present invention;

[0053] Figure 11 Schematic diagrams of six pointer relationships of cache lines in a cache memory area provided by the embodiments of the present invention;

[0054] Figure 12 Schematic diagram of the structure of a cache storage usage device provided by the embodiments of the present invention;

[0055] Figure 13 Schematic diagram of the structure of an electronic device provided by the embodiments of the present invention. Detailed implementation manners

[0056] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Apparently, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0057] The following explains some terms appearing in the text:

[0058] 1. In the embodiments of the present invention, the term "and / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0059] 2. In the embodiments of the present invention, the term "cache" refers to a cache memory, a special memory subsystem in which frequently used data is replicated for fast access.

[0060] 3. In the embodiments of the present invention, the term "line" refers to a cache line, which is a cache unit containing multiple words, usually containing 32 bytes or 64 bytes.

[0061] 4. In the embodiments of the present invention, the term "clear" refers to an instruction to clear the cache at the current position.

[0062] 5. In the embodiments of the present invention, the term "skip" refers to an instruction to skip the cache at the current position.

[0063] 6. In the embodiments of the present invention, the term "decr" refers to an instruction to decrement the numerical value cached at the current position by one.

[0064] 7. In the embodiments of the present invention, the term "incr" is an instruction to increment the numerical value cached at the current position by one.

[0065] 8. In the embodiments of the present invention, the term "warp transformation" is an image processing technique used to distort or transform an image or a part thereof to present a new shape.

[0066] In the related art, when using cache memory, three methods, namely fully associative, direct mapped, and set associative, are usually used to arrange the cache memory Cache. However, as Figure 1 can be seen, the cache lines mapped by addresses 0x00, 0x40, and 0x80 are the same. Therefore, if the data currently stored in this cache line is 0x40, but the data is read in the order of 0x00, 0x40, 0x80, when accessing the address 0x00, the data is not in the cache, resulting in a cache miss. Although the data will be loaded from the cache memory to the cache line in the 0th row of the cache later, when continuing to access the address 0x40, it still indexes to the cache line in the 0th row of the cache. Since the data stored in the cache line at this time is the data corresponding to the address 0x00, a cache miss will still occur at this time, and then the data at the address 0x40 will be loaded from the main memory into the first cache line. Similarly, when continuing to access the address 0x80, a cache miss will still occur. Thus, it is equivalent to reading data from the cache memory every time, so the existence of the cache does not improve the performance. When accessing the next address, the data cached at the previous address will be replaced. This phenomenon is called cache thrashing. This phenomenon not only reduces the cache performance of the cache memory but also causes the online expansion and online contraction processes of the cache memory to slow down, affecting the user's business and resulting in a decline in the user experience. Therefore, there is an urgent need for a method to reduce the occurrence frequency of cache thrashing without significantly increasing the hardware cost.

[0067] The following describes in more detail the method, device, equipment, and medium for using cache memory provided by the present invention with reference to the accompanying drawings and embodiments.

[0068] The embodiments of the present invention provide a method for using cache memory, as Figure 2 shown, including:

[0069] Step S201: Horizontally divide the cache memory area into multiple cache lines.

[0070] In an example of the present disclosure, the cache area is horizontally divided into a plurality of cache lines, that is, the cache area Cache is first divided into a plurality of cache lines line.

[0071] Step S202: Vertically divide each cache line into a plurality of cache blocks with the same quantity.

[0072] In an example of the present disclosure, the multiple lines are further vertically divided into a plurality of cache blocks block. In this embodiment, the data stored in the Cache area can be one-dimensional data or two-dimensional images, and the embodiments of the present disclosure do not limit this. Preferably, better usage effects can be obtained when storing two-dimensional graphics data. When storing two-dimensional graphic data, a warp transformation is required, such as Figure 2 As shown, the source image is stored in the main memory and is stored in the cache by establishing the relationship between the block image and the block address. The relationships between various images in the warp transformation are as Figure 4 As shown, sw is the width of the source picture, referring to the width of the source image; sh is the height of the source picture, referring to the height of the source image; sx is the x location of the source picture, referring to the abscissa of the source image; sy is the y localtion of the source picture, referring to the ordinate of the source image; cw is the width of the cache picture, referring to the width of the cache image; ch is the height of the cache picture, referring to the height of the cache image; cx is the x location of the cache picture, referring to the abscissa of the cache image;

[0073] "cy" refers to the y - coordinate of the cache picture; "bw" refers to the width of the block picture; "bh" refers to the height of the block picture; "bx" refers to the x - coordinate of the block picture; "by" refers to the y - coordinate of the block picture; "sx0" refers to the left - hand coordinate of the window; "sx1" refers to the right - hand coordinate of the window; "sy0" refers to the upper - hand coordinate of the window; "sy1" refers to the lower - hand coordinate of the window. Among them, bx = sx % bw = cx % bw; by = sy % bh = cy % bh; the source picture and the cache picture adopt direct mapping, cx = sx % cw; cy = sy % ch. Therefore, the Cache is divided into cw / bw lines in the horizontal direction, and each line has ch / bh blocks in the vertical direction. The division of lines is as shown in Figure 5 As shown. In this way, because the cache is sliced into lines in the horizontal direction, only when the rotation angle is greater than ctan(ch / bw) will cache thrashing occur, significantly reducing the probability of thrashing.

[0074] As Figure 6 As shown, the specific process of using the cache storage provided by the embodiment of the present invention during reading may include the following steps:

[0075] Step S601, determine two target cache lines according to the coordinates of the source picture.

[0076] In an example of the present disclosure, first, determine the coordinates of the window picture according to the source picture, and then select two target cache lines to be read according to the coordinates of the window picture.

[0077] Step S602, determine the reading coordinates based on the two target cache lines.

[0078] In an example of the present disclosure, for the two target cache lines determined in step S601, make comparisons horizontally and vertically to obtain the left - hand horizontal hit flag (xhit0), the left - hand vertical hit flag (yhit0), the right - hand horizontal hit flag (xhit1), and the right - hand vertical hit flag (yhit1). Finally, hit = xhit0 & yhit0 & xhit1 & yhit1.

[0079] Step S603, use the reading coordinates to determine the reading area corresponding to the source picture in the cache storage area.

[0080] In an example of the present disclosure, using the read coordinates determined in the above steps, the read area corresponding to the source image in the cache storage area is read. By using the method of the embodiments of the present disclosure, only 10 comparators are used, and it does not change with the number of lines. Compared with the fully connected structure, the timing is faster, the access area is more accurate. At the same time, due to the adoption of the bidirectional FIFO mechanism longitudinally, the hardware resources and the bh are decoupled. The height of the block can be smaller, reducing the granularity of the main memory access longitudinally, thereby reducing the probability of cross-page and reducing performance waste.

[0081] The following will Figure 7 describe in detail the replacement process of the method for using the cache storage in the embodiments of the present disclosure.

[0082] Step S701: Determine the first cache line to be replaced, the second cache line to be replaced, and the instruction for the replacement data based on the replacement coordinates of the replacement area.

[0083] In an example of the present disclosure, the replacement coordinates include a first horizontal coordinate, a second horizontal coordinate, a first vertical coordinate, and a second vertical coordinate. Then, in this step, specifically, the replacement identifier of the area to be replaced needs to be obtained first, and then the first cache line to be replaced and the second cache line to be replaced are determined in sequence according to the first horizontal coordinate, the first vertical coordinate, the second horizontal coordinate, and the second vertical coordinate, and it is judged whether the replacement identifier is hit. Finally, the instruction is determined according to the hit result. Each cache line is provided with a first pointer and a second pointer, and the pointer state of each cache line is determined by the first pointer and the second pointer. Then, the judgment process is as follows: judge in sequence: if the first horizontal coordinate hits the replacement identifier, perform the first instruction on the first cache line to be replaced; if the first vertical coordinate hits the replacement identifier, determine the corresponding instruction according to the pointer state of the first cache line to be replaced; if the second horizontal coordinate hits the replacement identifier, perform the first instruction on the first cache line to be replaced; if the second vertical coordinate hits the replacement identifier, determine the corresponding instruction according to the pointer state of the second cache line to be replaced.

[0084] Generally, there are two write data strategies:

[0085] 1. The strategy for writing I / O data is the WB strategy (Write Back). The write I / O data requested by the host will be temporarily stored in the cache of the cache storage. After the I / O data is written into the cache of the cache storage, a data write completion signal is immediately sent to the host (that is, the host is immediately responded to), which can greatly reduce the response delay of the host.

[0086] 2. The strategy for writing I / O data is the WT strategy (Write Through). For write events, the data written to the cache is not responded immediately. After the write I / O data is written to the storage medium of the cache, the host is then responded to. For read events, after the data is read from the storage medium of the cache, the host is responded to, thus improving the reliability of reading and writing.

[0087] In one example, according to the relationship between the window coordinates and the line, four hit flags can be obtained: the left horizontal, the left vertical, the right horizontal, and the right vertical, which are respectively judged corresponding to the first horizontal coordinate, the first vertical coordinate, the second horizontal coordinate, and the second vertical coordinate. Four data replacement operations are defined: the clear operation, the skip operation, the decr operation, and the incr operation. In this embodiment, if the coordinate is not hit, it is considered a hit. If the first horizontal coordinate hits the replacement flag, a clear operation is performed on the first cache line to be replaced; if the first vertical coordinate hits the replacement flag, the skip operation / decr operation / incr operation is determined according to the pointer state of the first cache line to be replaced; if the second horizontal coordinate hits the replacement flag, a clear operation is performed on the first cache line to be replaced; if the second vertical coordinate hits the replacement flag, the skip operation / decr operation / incr operation is determined according to the pointer state of the second cache line to be replaced.

[0088] For each line, there are two pointers, the first pointer ylp and the second pointer yhp in the vertical direction. Through these two pointers, three states can be combined: the empty state, the half state, and the full state. The specific states are corresponding as Figure 8 shown. For each line, according to the three states and the four replacement operations, 12 state transition situations can be combined. The state transition is schematically shown as Figure 9 and Figure 10 shown. According to the upper and lower edges of the window and the upper and lower pointers of the line, 7 relationships can be arranged and combined, such as Figure 11 shown.

[0089] Step S702, replace the data of the first cache line to be replaced and the second cache line to be replaced through an instruction.

[0090] When running the method disclosed in this disclosure, since a two-way fifo mechanism is adopted for the line in the vertical direction, the granularity of accessing the main memory in the vertical direction is small, the probability of crossing pages is small, and the performance consumption is reduced. And since the number of comparators is small and fixed, it does not change with the number of lines. The requirements for the timing and area of the hardware are relatively low. At the same time, since the cache is sliced in the horizontal direction for the line, the support angle is larger and the cache thrashing probability is smaller, thus improving the overall performance.

[0091] Such as Figure 12As shown, based on the same inventive concept of the method for using a cache, the present invention further provides an apparatus for using a cache, including:

[0092] A first processing unit 1201, configured to horizontally divide a cache storage area into multiple cache lines;

[0093] A second processing unit 1202, configured to vertically divide each cache line into multiple cache blocks with the same number, wherein data is placed in the source graph and the cache storage graph by establishing a mapping relationship.

[0094] In a possible implementation manner, in the apparatus provided by the embodiment of the present invention, the height of each cache line is the same, and the width of each cache line is the same.

[0095] In a possible implementation manner, in the apparatus provided by the embodiment of the present invention, a reading unit 1203 is further included, and the reading unit 1203 is configured to:

[0096] When reading data in the cache storage area, determine two target cache lines according to the coordinates of the source graph;

[0097] Determine the reading coordinates based on the two target cache lines;

[0098] Use the reading coordinates to determine the reading area corresponding to the source graph in the cache storage area.

[0099] In a possible implementation manner, in the apparatus provided by the embodiment of the present invention, a replacement unit 1204 is further included, and the replacement unit 1204 is configured to:

[0100] When replacing data in the cache storage area, determine a first cache line to be replaced, a second cache line to be replaced, and an instruction for the replacement data based on the replacement coordinates of the replacement area;

[0101] Replace the data of the first cache line to be replaced and the second cache line to be replaced through the instruction.

[0102] In a possible implementation manner, in the apparatus provided by the embodiment of the present invention, the replacement coordinates include a first horizontal coordinate, a second horizontal coordinate, a first vertical coordinate, and a second vertical coordinate; then the replacement unit 1204 is specifically configured to:

[0103] Obtain the replacement identifier of the area to be replaced;

[0104] Determine the first cache line to be replaced and the second cache line to be replaced in sequence according to the first horizontal coordinate, the first vertical coordinate, the second horizontal coordinate, and the second vertical coordinate, and determine whether the replacement identifier is hit;

[0105] Determine the instruction according to the hit result.

[0106] In a possible implementation manner, in the device provided by the embodiment of the present invention, if the horizontal first coordinate hits the replacement identifier, the replacement unit 1204 is specifically configured to perform a first instruction on the first cache line to be replaced; if the horizontal second coordinate hits the replacement identifier, the replacement unit 1204 is specifically configured to perform a first instruction on the first cache line to be replaced.

[0107] In a possible implementation manner, in the device provided by the embodiment of the present invention, each cache line is provided with a first pointer and a second pointer, and the pointer state of each cache line is determined by the first pointer and the second pointer. Then, if the vertical first coordinate hits the replacement identifier, the replacement unit 1204 is specifically configured to determine the corresponding instruction according to the pointer state of the first cache line to be replaced;

[0108] If the vertical second coordinate hits the replacement identifier, the replacement unit 1204 is specifically configured to determine the corresponding instruction according to the pointer state of the second cache line to be replaced.

[0109] In addition, the method and device for using the cache memory in the embodiment of the present invention described in combination with Figures 1-12 can be implemented by an electronic device. Figure 13 The schematic diagram of the hardware structure of the electronic device provided by the embodiment of the present invention is shown.

[0110] Specifically, refer to Figure 13 below, which shows the schematic diagram of the structure suitable for implementing the electronic device 1300 in the embodiments of the present disclosure. Figure 13 The electronic device shown is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present disclosure.

[0111] As Figure 13 shown, the electronic device 1300 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 1301, which may execute various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1302 or the program loaded from the storage device 1308 into the random access memory (RAM) 1303 to implement the voice control method of the embodiments as described in the present disclosure. In the RAM 1303, various programs and data required for the operation of the electronic device 1300 are also stored. The processing device 1301, the ROM 1302, and the RAM 1303 are connected to each other through a bus 1304. The input / output (I / O) interface 1305 is also connected to the bus 1304.

[0112] Typically, the following devices can be connected to the I / O interface 1305: an input device 1306 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1308 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1309. The communication device 1309 can allow the electronic device 1300 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 13 the electronic device 1300 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. More or fewer devices can be alternatively implemented or had.

[0113] Specifically, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program contains program codes for executing the method shown in the flowchart, so as to implement the voice control method as described above. In such an embodiment, the computer program can be downloaded and installed from a network through the communication device 1309, or installed from the storage device 1308, or installed from the ROM 1302. When the computer program is executed by the processing device 1301, the above functions defined in the method of the embodiment of the present disclosure are executed.

[0114] It should be noted that the computer-readable medium described above can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device. In the present disclosure, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, and this computer-readable signal medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0115] In some embodiments, the client and the server can communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include local area networks ("LAN"), wide area networks ("WAN"), the Internet (e.g., the Internet), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.

[0116] The above computer-readable medium can be included in the above electronic device; or it can exist separately and not be assembled into the electronic device.

[0117] The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by the electronic device, the electronic device is caused to:

[0118] Horizontally divide the cache area into multiple cache lines;

[0119] Each cache line is longitudinally divided into a plurality of cache blocks with the same quantity, wherein the source graph and the cache graph place data by establishing a mapping relationship.

[0120] Optionally, when one or more of the above programs are executed by the electronic device, the electronic device may further execute the other steps described in the foregoing embodiments.

[0121] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages or combinations thereof. The foregoing programming languages include, but are not limited to, object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may execute entirely on the user's computer, partially on the user's computer, execute as a stand-alone software package, execute partially on the user's computer and partially on a remote computer, or execute entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (for example, by connecting through the Internet service provider via the Internet).

[0122] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0123] The units described in the embodiments of the present disclosure may be implemented in software or in hardware. In some cases, the name of the unit does not constitute a limitation on the unit itself.

[0124] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), Systems on a Chip (SOCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0125] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM or Flash Memory), an optical fiber, a portable Compact Disc Read Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0126] In an embodiment of the present invention, first, the cache storage area is horizontally divided into a plurality of cache lines; then each cache line is vertically divided into a plurality of cache blocks with the same quantity. Compared with the related art, by horizontally and vertically arranging the cache storage area, the width of the cache line is lower under the same storage space, supporting large-angle rotation and significantly reducing the thrashing probability.

[0127] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0128] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and combinations of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable data processing devices to produce a machine, such that the instructions executed by the processors of the computer or other programmable data processing devices produce means for implementing the functions specified in the flowchart Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0129] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufacture including instruction means that implement the functions specified in the flowchart Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0130] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in the flowchart Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0131] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0132] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A method for using a cache, characterized in that, including: horizontally dividing a cache storage area into a plurality of cache lines; vertically dividing each of the cache lines into a plurality of cache blocks with the same quantity, wherein data of a source graph and a cache storage graph are placed through establishing a mapping relationship.

2. The method for using a cache according to claim 1, wherein Each of the cache lines has the same height, and each of the cache lines has the same width.

3. The method for using a cache according to claim 2, wherein The method further includes: when reading data of the cache storage area, determining two target cache lines according to coordinates of the source graph; determining a reading coordinate based on the two target cache lines; determining a reading area corresponding to the source graph in the cache storage area by using the reading coordinate.

4. The method for using a cache according to claim 2, wherein The method further includes: when replacing data of the cache storage area, determining a first cache line to be replaced, a second cache line to be replaced and an instruction for replacing data based on replacement coordinates of a replacement area; replacing data of the first cache line to be replaced and the second cache line to be replaced through the instruction.

5. The method for using a cache according to claim 4, wherein The replacement coordinates include a first horizontal coordinate, a second horizontal coordinate, a first vertical coordinate and a second vertical coordinate; then the determining the first cache line to be replaced, the second cache line to be replaced and the instruction for replacing data based on the replacement coordinates of the replacement area includes: obtaining a replacement identifier of the area to be replaced; successively determining the first cache line to be replaced and the second cache line to be replaced according to the first horizontal coordinate, the first vertical coordinate, the second horizontal coordinate and the second vertical coordinate, and determining whether the replacement identifier is hit; determining the instruction according to a hit result.

6. The method for using a cache according to claim 5, characterized in that, If the first horizontal coordinate hits the replacement identifier, performing a first instruction on the first cache line to be replaced; if the second horizontal coordinate hits the replacement identifier, performing the first instruction on the first cache line to be replaced.

7. The method for using a cache according to claim 5, characterized in that, Each of the cache lines is provided with a first pointer and a second pointer, and a pointer state of each of the cache lines is determined by the first pointer and the second pointer; then if the first vertical coordinate hits the replacement identifier, determining a corresponding instruction according to the pointer state of the first cache line to be replaced; if the second vertical coordinate hits the replacement identifier, determining a corresponding instruction according to the pointer state of the second cache line to be replaced.

8. An apparatus for using a cache, characterized in that, including: a first processing unit, configured to horizontally divide a cache storage area into a plurality of cache lines; a second processing unit, configured to vertically divide each of the cache lines into a plurality of cache blocks with the same quantity, wherein data of a source graph and a cache storage graph are placed through establishing a mapping relationship.

9. An electronic device, characterized in that, including: at least one processor, at least one memory, and computer program instructions stored in the memory, where when the computer program instructions are executed by the processor, the method according to any one of claims 1-7 is implemented.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, when the computer program instructions are executed by the processor, the method according to any one of claims 1-7 is implemented.

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