Signal transmission method

Abstract

A signal transmission method is suitable for a first connector which is arranged on a backboard and supports modular extensible input and output specifications and a second connector of a hard disk array interface card, and comprises the following steps: providing a first logic value to an A8th pin and an A26th pin of the second connector through the first connector, the controller can know that the control signal of the light emitting diode of the hard disk is transmitted through the two-wire interface; providing a clock pulse signal to the hard disk through the controller via the A11th pin and the A12th pin of the second connector and the first connector; and a plurality of elastic pins of the first connector, a connecting wire as a jumper wire and the second connector are electrically connected to form two groups of two-wire interfaces, and a hard disk reset signal and a hard disk setting signal of the second hard disk are provided.

Description

Technical Field

[0001] The present invention relates to a signal transmission method, and in particular to a signal transmission method for a hard disk array and an interface card. Background Art

[0002] The Modular Extensible I / O (M-XIO) specification is developed by a working group of the Data Center-Modular Hardware System (DC-MHS) sub-project of the Open Computing Project (OCP). When applied to a computer system, a first hard disk and a second hard disk provided on a backplane are to be electrically connected to a controller of a hard disk array interface card through a first connector provided on the backplane, a connection line, and a second connector provided on a hard disk array (RAID) interface card to transmit various signals.

[0003] More specifically, the first connector supports the Modular Extensible I / O specification and includes a first connector having a pin A1 to a pin A37 and a pin B1 to a pin B37. That is to say, the pin A1 to the pin A37 and the pin B1 to the pin B37 must conform to the content defined by the M-XIO specification. The hard disk array interface card is removably provided on a motherboard, and the second connector also includes a pin A1 to a pin A37 and a pin B1 to a pin B37.

[0004] However, the pin A1 to the pin A37 and the pin B1 to the pin B37 of the existing second connector are not completely the same or compatible with the pins defined by the first connector. As shown in the following table, there are 12 pins with different or incompatible definitions. Therefore, when the connection line makes electrical connections to the first connector and the second connector, the signals of these 12 pins cannot be correctly transmitted, and thus the existing hard disk array interface cards on the market cannot transmit signals through connectors that conform to the M-XIO specification, which becomes a problem to be solved.

[0005]

[0006] Summary of the Invention

[0007] The purpose of the present invention is to provide a signal transmission method for a hard disk array and an interface card.

[0008] Accordingly, the present invention provides a signal transmission method, which is applicable to a first connector disposed on a backplane and supporting a modular scalable input / output specification, and a second connector of a hard disk array interface card. A first hard disk and a second hard disk disposed on the backplane are electrically connected to a controller of the hard disk array interface card via the first connector, a connection line, and the second connector. Both the first connector and the second connector include pin A1 to pin A37 and pin B1 to pin B37. The signal transmission method includes steps (A) to (C).

[0009] In step (A), a first logic value is provided at pin A8 and pin A26 of the second connector through the first connector, so that the controller knows that the control signals of the light-emitting diodes of the first hard disk and the second hard disk are transmitted through a two-wire interface.

[0010] In step (B), a clock signal is provided to the first hard disk and the second hard disk through the controller via pin A11 and pin A12 of the second connector, and pin A11 and pin A12 of the first connector.

[0011] In step (C), a plurality of flexible pins of the first connector defined in the modular scalable input / output specification, the connection line is used as a jumper, and the second connector are electrically connected to form two sets of two-wire interfaces, and a hard disk reset signal and a hard disk setting signal of the second hard disk are provided. The hard disk setting signal is used to indicate whether the second hard disk is installed.

[0012] In some embodiments, in step (C), the flexible pins of the first connector include pin A9, pin A26, pin A27, pin B26, pin B27, pin B29, and pin B30.

[0013] In some embodiments, in step (C), jumper wires are made via the connection wires through the A26 pin and the A27 pin of the first connector to electrically connect to the B8 pin and the B9 pin of the second connector respectively, thereby forming the two-wire interface. Jumper wires are made via the connection wires through the B26 pin and the B27 pin of the first connector to electrically connect to the B26 pin and the B27 pin of the second connector respectively, thereby forming the two-wire interface. Jumper wires are made via the connection wires through the B29 pin and the B30 pin of the first connector to electrically connect to the B29 pin and the B30 pin of the second connector respectively, thereby providing the hard disk reset signal and the hard disk setting signal of the second hard disk.

[0014] In other embodiments, in step (B), through the firmware setting of the controller, the controller outputs the clock signal to the A11 pin and the A12 pin of the second connector, and transmits it via the connection wires to the A11 pin and the A12 pin of the first connector, and then inputs it to a clock buffer, and outputs two groups of the clock signals to the first hard disk and the second hard disk respectively, and the clock buffer is arranged on the backplane.

[0015] In other embodiments, in step (A), one end of a resistor arranged on the backplane is electrically connected to the power supply voltage, and the other end of the resistor is electrically connected to the A8 pin of the first connector, so as to provide the first logic value via the connection wires and the A8 pin of the second connector. The A8 pin of the first connector also makes a jumper wire via the connection wires to electrically connect to the A26 pin of the second connector.

[0016] In some embodiments, in step (A), a diode is arranged between the resistor and the A8 pin of the first connector, and the anode end of the diode is electrically connected to the other end of the resistor, and the cathode end of the diode is electrically connected to the A8 pin of the first connector.

[0017] In other embodiments, in step (A), an electrical connection is formed by using one of the elastic pins of the first connector that does not overlap with the one selected in step (C), the connection wires to make a jumper wire, and the A8 pin and the A26 pin of the second connector, so as to provide the first logic value.

[0018] The beneficial effects of the present invention are as follows: The first logical value is provided through the first connector to conform to the signals required by the controller via the A8 pin and the A26 pin, and two clock signals required by the first hard disk and the second hard disk are provided through the A11 pin and the A12 pin. Moreover, the elastic pins and the connection line are used for jumpers to provide the two two-wire interfaces, as well as the hard disk reset signal and the hard disk setting signal of the second hard disk. Therefore, a signal transmission method that conforms to the existing hard disk array interface card and the connector of the M-XIO specification can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a block diagram showing the components between a main board and a backplane to which the signal transmission method of the present invention is applicable; and

[0020] Figure 2 is a flowchart showing an embodiment of the signal transmission method of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0022] Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

[0023] Refer to Figure 1 and Figure 2 The signal transmission method of the present invention is applicable to a first connector 11, a first hard disk 12, a second hard disk 13, a connection line, and a second connector 21 and a controller 22 of a hard disk array (RAID) interface card 2 provided on a main board 3, which are provided on a backplane 1.

[0024] The first connector 11 supports the Modular eXtensible Input / Output (M-XIO) specification and includes pins A1 to A37 and pins B1 to B37 defined by the M-XIO specification. Among them, pin A8 (3p3AUX_MGMT) is used to transmit an optional power, that is, it can be selected to transmit a power voltage or not. Pins A9, A26, A27, B26, B27, pin 29, and pin B30 are flexible pins defined by the M-XIO specification. Pins A29 and A30 are data signals of the Universal Serial Bus (USB). Pins B8 (SMSCL_A) and B9 (SMSDA_A) are used for a two-wire interface. In the definition of the M-XIO specification, the master of the two-wire interface must be a Baseboard Management Controller (BMC).

[0025] The second connector 21 includes two connectors of model SFF-8654, and respectively includes pins A1 to A37 and pins B1 to B37. In this embodiment, the control signals of the light-emitting diodes of the first hard disk 12 and the second hard disk 13 are transmitted through a two-wire interface. And the design of the backplane 1 does not support the Universal Backplane Management (UBM) protocol. Therefore, the controller 22 does not need to receive the originally defined signals via pin A9 (2W_RESETA, SDataOut) and pin A27 (2W_RESETB, SDataOut) of the second connector 21.

[0026] The signal transmission method includes steps S1 to S3.

[0027] In step S1, a first logical value (such as logic 1) is provided through the first connector 11 at pins A8 and A26 of the second connector 21. The definitions of pins A8 and A26 are BP_TYPE, which is used to indicate that when the controller 22 receives the first logical value via pins A8 and A26 respectively, the controller 22 controls the control signals of the light-emitting diodes of the first hard disk 12 and the second hard disk 13 to be transmitted through a two-wire interface.

[0028] In this embodiment, a power supply voltage (such as 3.3 volts) is electrically connected to a first end of a resistor provided on the backplane 1, a second end of the resistor is electrically connected to an anodic end of a diode, and a cathodic end of the diode is electrically connected to the A8 pin of the first connector 11 to provide the first logic value via the connection line and the A8 pin of the second connector 21. The A8 pin of the first connector 11 is also jumpered via the connection line to electrically connect to the A26 pin of the second connector 21 to provide the first logic value, so that the controller 22 knows that the control signals of the light-emitting diodes of the first hard disk 12 and the second hard disk 13 are transmitted through a two-wire interface. Thus, when the backplane 1 is not used for the main board 3 and the hard disk array interface card 2 of this case, and the A8 pin of the first connector 11 is used to transmit an alternative power supply, for example, when the backplane 1 is used for another main board, the setting of the diode can prevent the power supply voltage (such as 3.3 volts) of the other main board from flowing back to the power supply voltage (such as 3.1 volts) of the backplane 1.

[0029] In other embodiments, the diode for preventing voltage backflow can also be omitted. Or, in other embodiments, both the resistor and the diode are omitted, and instead, an electrical connection is formed through one of the elastic pins of the first connector 11, the connection line for jumpering, and the A8 pin and the A26 pin of the second connector 21 to provide the first logic value.

[0030] In step S2, the A11 pin and the A12 pin defined by the first connector 11, and the A11 pin and the A12 pin defined by the second connector 21 are the same. Therefore, the controller 22 provides a clock signal to the first hard disk 12 and the second hard disk 13 via the A11 pin and the A12 pin of the second connector 21, and the A11 pin and the A12 pin of the first connector 11. More specifically, through the firmware setting of the controller 22, the controller 22 outputs the clock signal to the A11 pin and the A12 pin of the second connector 21 to be transmitted to the A11 pin and the A12 pin of the first connector 11 via the connection line, and the clock signal is received by a one-to-two (i.e., one input end and two output ends) clock buffer provided on the backplane 1 to output two sets of the clock signal to the first hard disk 12 and the second hard disk 13 respectively.

[0031] In step S3, electrical connections are formed among the elastic pins of the first connector 11, the jumper wire of the connection line, and the second connector 21 to form two sets of two-wire interfaces (2W-CLKA, SClockA and 2W-DATAA, SLoadA are one set, and 2W-CLKB, SClockB and 2W-DATAB, SLoadB are the other set), and a hard disk reset signal (PERSTB#, SDataInB) and a hard disk setting signal (CPRSNTB#, CNTRLR_TYPEB) of the second hard disk 13 are provided. The hard disk setting signal is used to indicate the installed state of the second hard disk 13.

[0032] For example, in this embodiment, through the A26 pin and the A27 pin of the first connector 11, a jumper is made via the connection line to electrically connect to the B8 pin and the B9 pin of the second connector 21 respectively, thereby forming one of the two-wire interfaces (2W-CLKA, SClockA and 2W-DATAA). Through the B26 pin and the B27 pin of the first connector 11, via the connection line, they are electrically connected to the B26 pin and the B27 pin of the second connector 21 respectively, thereby forming another of the two-wire interfaces (2W-CLKB, SClockB and 2W-DATAB, SLoadB). Through the B29 pin and the B30 pin of the first connector 11, via the connection line, they are electrically connected to the B29 pin and the B30 pin of the second connector 21 respectively, thereby providing the hard disk reset signal and the hard disk setting signal of the second hard disk 13 respectively.

[0033] It should be further noted that: among the first connector 11 and the second connector 21, the remaining pins not mentioned in steps S1 to S3 on how to connect all adopt a one-to-one connection method, that is, for example, the A1 pin to the A7 pin of the first connector 11 are electrically connected to the A1 pin to the A7 pin of the second connector 21 respectively via the connection line.

[0034] Furthermore, since the master of the two-wire interface formed by the B8 pin (2W-CLKA, SClockA) and the B9 pin (2W-DATAA, SLoadA) of the second connector 21 must be the controller 22. And the master of the two-wire interface formed by the B8 pin (SMSCL_A) and the B9 pin (SMSDA_A) of the first connector 11 must be the baseboard management controller. Therefore, although both are two-wire interfaces, due to different requirements for the master, the B8 pin (2W-CLKA, SClockA) and the B9 pin (2W-DATAA, SLoadA) need to be provided through other flexible pins and cannot be provided through the B8 pin (SMSCL_A) and the B9 pin (SMSDA_A).

[0035] In addition, in other embodiments, when step S1 provides the first logical value through one of the flexible pins of the first connector 11, the flexible pin (such as the A9 pin) selected in step S1 does not overlap with the flexible pins (such as the A26 pin, the A27 pin, the B26 pin, the B27 pin, the B29 pin, and the B30 pin) of the first connector 11 selected in step S3.

[0036] In summary, by providing the first logical value through the first connector 11 to meet the signals required by the controller 22 via the A8 pin and the A26 pin, and providing two groups of clock signals required by the first hard disk 12 and the second hard disk 13 through the A11 pin and the A12 pin, and making jumpers with the connecting wires through the flexible pins to provide the two groups of two-wire interfaces, and the hard disk reset signal and the hard disk setting signal of the second hard disk 13, a signal transmission method that conforms to the existing hard disk array interface card 2 and the connector of the M-XIO specification can be realized, so the object of the present invention can be truly achieved.

[0037] However, the above are only embodiments of the present invention, and the scope of implementation of the present invention cannot be limited thereby. All simple equivalent changes and modifications made according to the content of the claims and the patent specification of the present invention still fall within the scope covered by the present invention patent.

Claims

1. A signal transmission method, applicable to a first connector disposed on a backplane and supporting a modular scalable input / output specification, and a second connector of a hard disk array interface card. A first hard disk and a second hard disk disposed on the backplane are electrically connected to a controller of the hard disk array interface card via the first connector, a connection line, and the second connector. The first connector and the second connector both include pin A1 to pin A37 and pin B1 to pin B37, and are characterized in that: The method for transmitting the signals includes the following steps: (A) Provide a first logic value at the A8 pin and the A26 pin of the second connector through the first connector, so that the controller knows that the control signals of the light-emitting diodes of the first hard disk and the second hard disk are transmitted through a two-wire interface; (B) Provide a clock signal to the first hard disk and the second hard disk through the A11 pin and the A12 pin of the second connector and the A11 pin and the A12 pin of the first connector via the controller; And (C) Form two sets of two-wire interfaces by making electrical connections through a plurality of flexible pins of the first connector defined in the modular scalable input / output specification, making jumpers with the connection wires, and the second connector, and provide the hard disk reset signal and the hard disk setting signal of the second hard disk, and the hard disk setting signal is used to indicate whether the second hard disk is installed; 2. The signal transmission method according to claim 1, wherein: In step (C), the flexible pins of the first connector include the A9 pin, the A26 pin, the A27 pin, the B26 pin, the B27 pin, the B29 pin, and the B30 pin; 3. The signal transmission method according to claim 2, characterized in that: In step (C), through the A26 pin and the A27 pin of the first connector, make jumpers with the connection wires to electrically connect to the B8 pin and the B9 pin of the second connector respectively, so as to form the two-wire interface, through the B26 pin and the B27 pin of the first connector, via the connection wires, to electrically connect to the B26 pin and the B27 pin of the second connector respectively, so as to form the two-wire interface, through the B29 pin and the B30 pin of the first connector, via the connection wires, to electrically connect to the B29 pin and the B30 pin of the second connector respectively, and provide the hard disk reset signal and the hard disk setting signal of the second hard disk respectively; 4. The signal transmission method according to claim 1, wherein: In step (B), through the firmware setting of the controller, the controller outputs the clock signal to the A11 pin and the A12 pin of the second connector, so as to be transmitted to the A11 pin and the A12 pin of the first connector via the connection wires, and then input to a clock buffer, and output two sets of the clock signals to the first hard disk and the second hard disk respectively, and the clock buffer is arranged on the backplane; 5. The signal transmission method according to claim 1, wherein: In step (A), the first end of a resistor arranged on the backplane is electrically connected to the power supply voltage, and the second end of the resistor is electrically connected to the A8 pin of the first connector, so as to provide the first logic value via the connection wires and the A8 pin of the second connector, and the A8 pin of the first connector also makes a jumper with the connection wires to electrically connect to the A26 pin of the second connector.

6. The signal transmission method according to claim 5, wherein: In step (A), a diode is disposed between the resistor and the A8 pin of the first connector, and the anode terminal of the diode is electrically connected to the second end of the resistor, and the cathode terminal of the diode is electrically connected to the A8 pin of the first connector.

7. The signal transmission method according to claim 1, wherein: In step (A), an electrical connection is formed through one of the elastic pins of the first connector that does not overlap with those selected in step (C), a jumper is made with the connection line, and the A8 pin and the A26 pin of the second connector to provide the first logic value.

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