Sparse matrix-vector multiplication implementation method and system for Sunway processors

Abstract

The present application relates to the field of computer technology, and in particular to a sparse matrix-vector multiplication implementation method and system for the Sunway processor. The implementation method includes: a task division step, obtaining an input sparse matrix, grouping the matrix elements, and allocating them to the slave cores of the Sunway processor; a memory allocation step, obtaining a coefficient vector, and configuring the storage space for storing the sparse matrix and the coefficient vector in the slave core memory based on the number of data transmissions in the sparse matrix and the coefficient vector; a vector multiplication implementation step, allocating data based on the configured storage space, and performing vector multiplication operations. This application is used to minimize the waiting time caused by data loading during vector multiplication.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method and system for implementing sparse matrix-vector multiplication for a Sunway processor. Background Art

[0002] Sparse Matrix-Vector Multiplication (SpMV) is considered one of the most important scientific and engineering computational methods of the past decade. Numerical simulations in many applications, such as fluid dynamics simulation software (Openfoam) and medical imaging, often involve solving large-scale sparse matrix linear equations. The performance of SpMV operations has a decisive impact on the entire linear equation solution process, and thus directly affects the computational efficiency and performance of the entire application system. Consequently, the implementation and optimization of SpMV on various high-performance architectures, such as multi-core CPUs and GPUs, has become a hot topic of research.

[0003] The CSR format (Compressed Sparse Row, CSR) is the most popular sparse matrix storage method, with the advantages of high storage efficiency, high efficiency of sparse matrix arithmetic operations, efficient row slicing, and fast matrix-vector product operations. The CSR storage format uses three arrays value 、 row_ptr 、 col_ind To represent the value, column number, and row offset respectively, Value All non-zero elements are stored. row_ind Records the row label corresponding to each non-zero element, col_ind The column indices of the non-zero elements are stored in .

[0004] Because the number of non-zero elements in sparse matrices is very small and their distribution is often highly irregular and random, this data characteristic directly leads to irregular memory access, limiting the hardware's vectorization capabilities. Furthermore, irregular access patterns significantly reduce cache hit rates, severely limiting overall floating-point performance. Summary of the Invention

[0005] The embodiments of the present application provide a sparse matrix-vector multiplication implementation method and system for the Sunway processor, so as to at least solve the problems of irregularity in the memory access process or low cache hit rate in the related art.

[0006] In a first aspect, an embodiment of the present application provides a method for implementing sparse matrix-vector multiplication for a Sunway processor, including:

[0007] In the task division step, the input sparse matrix A is obtained, the matrix elements are grouped, and then distributed to the slave cores of the Sunway processor;

[0008] A memory allocation step of obtaining a coefficient vector and configuring a storage space for storing the sparse matrix A and the coefficient vector X in a slave core memory based on the number of data transmissions in the sparse matrix A and the coefficient vector X;

[0009] The vector multiplication implementation steps allocate data based on the configured storage space and perform vector multiplication operations.

[0010] In some embodiments, the memory allocation step further comprises:

[0011] Perform vector multiplication on the first memory of the sparse matrix stored in the kernel local memory LDM, the second memory storing the coefficient vector, and a remaining memory, access the dynamic data of the coefficient vector via RMA, and access the static data of the sparse matrix and the coefficient vector via DMA, and count the number of DMA accesses, the number of RMA accesses, and the corresponding single access time during the operation;

[0012] The total running time is calculated based on the number of DMA accesses, RMA accesses and the corresponding single access time during the operation, so as to configure the first memory, the second memory and the remaining memory to minimize the total running time. The remaining memory is used to store code and other variables. The sparse matrix includes non-zero element values. , column indices of non-zero elements and the number of non-zero elements at the beginning of the current row , the coefficient vector includes static data and dynamic data .

[0013] Based on the above algorithm, the coefficient vector corresponding to the non-zero elements is loaded through RMA access or DMA access to perform sparse matrix-vector multiplication, generate a result vector, use an RMA counter to increment and count the number of RMA accesses, and use a DMA counter to increment and count the number of DMA accesses to calculate the total runtime. The embodiment of the present application optimizes the configuration ratio of the first memory, the second memory, and the remaining memory with the goal of minimizing the total runtime, so as to minimize the waiting time caused by data loading during the vector multiplication process.

[0014] In some embodiments, the memory allocation step further comprises a coefficient vector allocation step:

[0015] Configuring the second memory space to include a static cache area and a dynamic cache area;

[0016] After the static data is divided equally according to the number of slave cores used, it is stored in the static cache in the order of the slave cores;

[0017] The dynamic cache area is configured to include 8 data blocks, each of which stores 128 dynamic data.

[0018] In some embodiments, the vector multiplication implementing step further comprises:

[0019] Configure the temporary cache area T1 and the protection cache area T2 in the slave core local memory LDM.

[0020] Temporary cache T1 is used to store data blocks with a single access count and their indexes. When a data block in temporary cache T1 is accessed more than once, it is considered to be a frequently accessed data block. The data block's index and access count are stored in a temporary linked list B1. The index of the data block with the largest access count in temporary linked list B1 is also recorded, thereby saving metadata information eliminated from temporary cache T1 to temporary linked list B1.

[0021] The protection cache area T2 is used to store data blocks that are accessed at least twice. The sizes of the temporary cache area and the protection cache area are dynamically adjusted according to load performance to adapt to the cache pressure in different computing stages.

[0022] In some embodiments, when the protection buffer T2 is not full, the data block with the maximum number of accesses in the temporary linked list B1 is stored in the protection buffer T2.

[0023] In some embodiments, when the protection cache T2 is full, the maximum access count B1_max of the data block in the temporary linked list B1 and the minimum access count T2_min of the data block in the protection cache T2 are determined, and the data block index with a larger access count is stored in the protection cache T2, and the data block index with a smaller access count is stored in a protection linked list B2, that is, the metadata information eliminated from the protection cache T2 is saved in the protection linked list B2.

[0024] In some embodiments, if the maximum number of accesses B2_max in the protection linked list B2 is greater than the minimum number of accesses T2_min in the protection cache area T2, the data block indices corresponding to the two are swapped, that is, the data block indices with a larger number of accesses are stored in the protection cache area T2, and the data block indices with a smaller number of accesses are eliminated from the protection linked list B2. The cache distribution is corrected through the swap operation to ensure that the data blocks with a larger number of accesses are returned to the protection cache area T2, prevent long-term low-frequency data blocks from occupying the cache space, avoid repeated loading of data from the remote core group, and enable the cache to dynamically adapt to the changing trend of hot data and improve the hit rate.

[0025] In some embodiments, the matrix elements are grouped based on the first constraint, and the m is the total number of matrix elements, is the number of matrix rows, is the number of matrix columns, For the The number of elements in the row, The first processor of Sunway The first constraint is configured as follows:

[0026] when When for .

[0027] Based on this, after allocation, the number of matrix rows executed by each slave core is basically the same. After completing the element allocation of the first 63 slave cores, all the remaining elements are handed over to the last slave core for calculation and processing. This can effectively avoid the problem of load imbalance caused by large differences in row elements in equal row allocation.

[0028] In a second aspect, an embodiment of the present application provides a sparse matrix-vector multiplication implementation system for a Sunway processor, which is used to implement the sparse matrix-vector multiplication implementation method described in the first aspect above, including:

[0029] The task division unit obtains the input sparse matrix A, groups the matrix elements, and distributes them to the slave cores of the Sunway processor;

[0030] a memory allocation unit, which obtains a coefficient vector and configures a storage space for storing the sparse matrix A and the coefficient vector from a core memory based on the number of data transmissions in the sparse matrix A and the coefficient vector X;

[0031] The vector multiplication implementation unit allocates data based on the configured storage space and performs vector multiplication operations.

[0032] In some embodiments, the memory allocation unit further includes a coefficient vector allocation unit.

[0033] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0035] Figure 1 is a flowchart of a method for implementing sparse matrix-vector multiplication according to an embodiment of the present application;

[0036] Figure 2 is a step-by-step flow chart of a method for implementing sparse matrix-vector multiplication according to an embodiment of the present application;

[0037] Figure 3 Schematic diagram of the memory allocation process according to an embodiment of the present application;

[0038] Figure 4 2 is a schematic diagram of the principle of the coefficient vector allocation step according to an embodiment of the present application;

[0039] Figure 5 1 is a schematic diagram of a configuration of a temporary buffer area T1 and a protection buffer area T2 according to an embodiment of the present application;

[0040] Figure 6 This is a structural block diagram of a sparse matrix-vector multiplication implementation system for the Sunway processor according to an embodiment of the present application.

[0041] In the figure: 1. Task division unit; 2. Memory allocation unit; 201. Coefficient vector allocation unit;

[0042] 3. Vector multiplication implementation unit. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is described and illustrated below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely used to explain this application and are not intended to limit this application. Based on the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art without making any creative efforts are within the scope of protection of this application.

[0044] Obviously, the drawings described below are merely examples or embodiments of the present application. Those skilled in the art can, without inventive effort, apply the present application to other similar scenarios based on these drawings. Furthermore, it is also understood that, although the effort involved in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, changes in design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as an insufficiency of the content disclosed in this application.

[0045] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this application may be combined with other embodiments unless there is a conflict.

[0046] Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by persons of ordinary skill in the art to which this application belongs. The terms "a," "an," "an," "the," and similar expressions used herein do not denote quantitative limitations and may refer to either the singular or the plural. The terms "comprise," "include," "have," and any variations thereof, used herein, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or modules (units) is not limited to the listed steps or units but may also include steps or units not listed, or may include other steps or units inherent to the process, method, product, or apparatus. The terms "connected," "connected," "coupled," and similar expressions used herein are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. As used herein, "plurality" means two or more. "And / or" describes an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" may mean: A exists alone; A and B exist simultaneously; or B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0047] The Sunway multi-core processor is composed of a general-purpose computing master core and streamlined computing slave cores, with high fixed-point and floating-point peak performance and high practical application performance. The Sunway multi-core processor integrates 6 core groups, each core group includes 1 master core and a slave core array, and 1 slave core array contains 64 slave cores; two system interfaces are integrated on the chip, and the above main components are connected through a ring network.

[0048] When a program is running, the main process runs on the MPE, which is essentially a general-purpose processor in which complex computational tasks can be assigned to CPEs. Each CPE is a lightweight core that executes a single thread. The slave cores of the Sunway multi-core chip are managed as a basic unit, arranged in an 8x8 array. Interactions between and outside the slave cores are interconnected via an intra-array network. A fast scratchpad memory called the LDM (Local Data Memory) is embedded in each CPE core, providing users with explicit control over data locality. The 64 CPE cores are arranged in an 8x8 grid and connected via row / column and signal / data buses. The MPE shares main memory with all CPEs in a CG, but when loading and storing contiguous data blocks via DMA (Direct Memory Access), the entire CPE set can maintain a much higher aggregate bandwidth than the MPE.

[0049] The Shenwei processor's slave core LDM memory access speed is very fast, equivalent to a high-speed cache, and can be completed in a few beats, while a slave core accessing the master core requires more than 200 beats. To enable communication within the core group, the Shenwei processor has designed two interfaces: DMA (Direct Memory Access) and RMA (Random Access Memory). Communication between slave cores and the master core uses DMA, and communication between slave cores uses RMA.

[0050] In sparse matrix-vector multiplication (SpMV), the number of non-zero elements in a sparse matrix is ​​very small. To effectively save storage space and reduce computation time, sparse matrices are typically stored in a compressed format. In short, only non-zero elements are stored. The sparse matrix in this application is stored in CSR format.

[0051] This embodiment provides a sparse matrix-vector multiplication implementation method for the Sunway processor. Figure 1-Figure 2 Flowchart of the sparse matrix-vector multiplication implementation method for the Sunway processor according to an embodiment of the present application. Figures 1 to 2 As shown, the process includes the following steps:

[0052] Task division step S1: obtain the input sparse matrix A, group the matrix elements, and distribute them to the slave cores of the Sunway processor;

[0053] Memory allocation step S2, obtaining a coefficient vector, and configuring storage space for storing the sparse matrix A and the coefficient vector X in a slave core memory based on the number of data transmissions in the sparse matrix A and the coefficient vector X;

[0054] The vector multiplication is implemented in step S3, where data is allocated based on the configured storage space and a vector multiplication operation is performed.

[0055] Based on the above steps, the embodiment of the present application balances the slave core load by reasonably dividing the tasks and distributing them to the slave cores, optimizes the memory structure, and configures the local memory space in the slave cores to minimize data reading across slave cores or within slave cores, thereby reducing data transmission bottlenecks.

[0056] In some embodiments, the memory allocation step S2 further includes:

[0057] Perform vector multiplication on the first memory of the sparse matrix stored in the kernel local memory LDM, the second memory storing the coefficient vector, and a remaining memory, access the dynamic data of the coefficient vector via RMA, and access the static data of the sparse matrix and the coefficient vector via DMA, and count the number of DMA accesses, the number of RMA accesses, and the corresponding single access time during the operation;

[0058] The total running time is calculated based on the number of DMA accesses, RMA accesses and the corresponding single access time during the operation, so as to configure the first memory, the second memory and the remaining memory to minimize the total running time. The remaining memory is used to store code and other variables. The sparse matrix includes non-zero element values. , column indices of non-zero elements and the number of non-zero elements at the beginning of the current row , the coefficient vector includes static data and dynamic data ;

[0059] Specifically, the vector multiplication process refers to the following pseudo code example:

[0060]

[0061] Based on the above algorithm, the coefficient vector corresponding to the non-zero elements is loaded through RMA access or DMA access to perform sparse matrix-vector multiplication, generate a result vector, use an RMA counter to count the number of RMA accesses, and use a DMA counter to count the number of DMA accesses to calculate the total running time. T time The embodiment of the present application optimizes the configuration ratio of the first memory, the second memory, and the remaining memory with the minimum total running time as the goal, so as to minimize the waiting time caused by data loading during the vector multiplication process.

[0062] In one embodiment, after testing, the first memory is configured as 56.25% of the space of the slave core local memory LDM to store the data of the sparse matrix, the second memory is configured as 28.125% of the storage space of the slave core local memory LDM to store the coefficient vector, and the remaining memory is configured as 15.625% of the space of the slave core local memory to store the code and other variables. The total running time is the shortest and the effect is the best.

[0063] When the scale of the sparse matrix is ​​large, considering that the scale of the coefficient vector generally requires a large storage space, and the local memory of the slave core is limited, there is a situation where the current coefficient vector cannot be stored. Therefore, the embodiment of the present application allocates the coefficient vector according to the number of slave cores used. Specifically:

[0064] In some embodiments, the memory allocation step S2 further includes a coefficient vector allocation step S201:

[0065] Configuring the second memory space to include a static cache area and a dynamic cache area;

[0066] like Figure 4 As shown, the static data is divided equally according to the number of slave cores used, such as C0 to C63, and stored in the static cache in sequence according to the slave core order, starting from the LDM of slave core C0. After the storage is completed, if there is remaining space in the static cache, the subsequent vector data will continue to be stored;

[0067] The dynamic cache area is configured to include 8 data blocks, each of which stores 128 dynamic data. The dynamic cache area is divided into a private segment private, a continuous shared segment share, and a cache.

[0068] Based on the above coefficient vector allocation step S201, each slave core adopts a double-buffer mode to store coefficient vectors, that is, it is divided into static data and dynamic data. Based on this, when performing vector multiplication, if the coefficient vector required by the current slave core is stored in the current slave core, it can be directly loaded. If it is in other slave cores, the matrix subscript of the current non-zero element is used to determine the slave core to which the required coefficient belongs, and the corresponding slave core is loaded through RMA access, such as Figure 4 As shown, the double-cache strategy improves the hit rate of x and reduces time complexity. It combines static allocation with dynamic access, effectively improving the hit rate and timeliness of vector access. Compared with traditional centralized vector storage and unified scheduling mechanisms, this method is more adaptable to computing scenarios with uneven distribution of sparse matrix elements and frequent changes in coefficient vector hot spots, thereby reducing overall computational latency and communication load, and improving the overall throughput performance of vector multiplication operations.

[0069] In other possible implementations, the number of data blocks and the capacity of a single block in the dynamic cache area can be dynamically adjusted according to the application scenario, for example, the number of blocks can be adjusted from 8 to 16 or 32, or the number of dynamic data stored in each block can be set to 64, 256, and other variants to adapt to different data access modes.

[0070] Furthermore, when the data to be accessed is not in the current slave core during data access during the calculation process, that is, a miss, it is necessary to access other slave cores to obtain data. Therefore, the number of communication accesses will increase and the computing performance will be reduced. Therefore, it is necessary to further increase the hit rate and reduce communication with other slave cores.

[0071] In some embodiments, the vector multiplication step S3 further includes:

[0072] The temporary cache area T1 and the protection cache area T2 are configured in the slave core local memory LDM. The principle is as follows: Figure 5 As shown,

[0073] Temporary cache T1 is used to store data blocks with a single access count and their indexes. When a data block in temporary cache T1 is accessed more than once, it is considered to be a frequently accessed data block. The data block's index and access count are stored in a temporary linked list B1. The index of the data block with the largest access count in temporary linked list B1 is also recorded, thereby saving metadata information eliminated from temporary cache T1 to temporary linked list B1.

[0074] The protection cache area T2 is used to store data blocks that are accessed at least twice. The sizes of the temporary cache area and the protection cache area are dynamically adjusted according to load performance to adapt to the cache pressure in different computing stages.

[0075] In some embodiments, when the protection buffer T2 is not full, the data block with the maximum number of accesses in the temporary linked list B1 is stored in the protection buffer T2.

[0076] In some embodiments, when the protection cache T2 is full, the maximum access count B1_max of the data block in the temporary linked list B1 and the minimum access count T2_min of the data block in the protection cache T2 are determined, and the data block index with a larger access count is stored in the protection cache T2, and the data block index with a smaller access count is stored in a protection linked list B2, that is, the metadata information eliminated from the protection cache T2 is saved in the protection linked list B2.

[0077] In some embodiments, if the maximum number of accesses B2_max in the protection linked list B2 is greater than the minimum number of accesses T2_min in the protection cache area T2, the data block indices corresponding to the two are swapped, that is, the data block indices with a larger number of accesses are stored in the protection cache area T2, and the data block indices with a smaller number of accesses are eliminated from the protection linked list B2. The cache distribution is corrected through the swap operation to ensure that the data blocks with a larger number of accesses are returned to the protection cache area T2, prevent long-term low-frequency data blocks from occupying the cache space, avoid repeated loading of data from the remote core group, and enable the cache to dynamically adapt to the changing trend of hot data and improve the hit rate.

[0078] Specifically, the adjustment process of the temporary buffer area T1 and the protection buffer area T2 is shown in the following pseudo code example:

[0079]

[0080] Based on the above steps, the present application implements dynamic management of the data block distribution of the slave core local memory LDM, optimizes the cache hit rate, and reduces the latency of remote memory access between core groups. In sparse computing, data blocks that are frequently accessed can reside for a long time. Data blocks that have not been recorded by any cache partition are added to the end of the temporary cache area T1 as new access blocks. The history of eliminated data blocks is tracked through the temporary linked list B1 and the protection linked list B2, and new frequently accessed data blocks or long-term low-frequency data blocks are eliminated. The size of the temporary cache area T1 and the protection cache area T2 are adaptively adjusted. During the calculation process, frequently accessed vector element blocks (such as those near the diagonal) will enter the protection cache area T2, and sparse area blocks will be eliminated to the temporary linked list B1 and the protection linked list B2. A multi-level cache management strategy driven by access heat is constructed, which effectively avoids the elimination of frequently used data blocks, and is used to optimize the efficiency of coefficient vector access in vector multiplication operations of the slave core, thereby reducing the number of RMA accesses between core groups and reducing the total running time.

[0081] In some embodiments, considering that each computing core group of the Sunway processor includes 1 master core and 64 slave cores, in order to make the number of elements calculated by each slave core uniform and to achieve load balancing for sparse matrices with irregular structures, the matrix elements are grouped based on the first constraint condition, and the number of elements is recorded as follows: m is the total number of matrix elements, is the number of matrix rows, is the number of matrix columns, For the The number of elements in the row, For the The number of elements in the row, The first processor of Sunway The first constraint is configured as follows:

[0082] when When for .

[0083] Based on this, after allocation, the number of matrix rows executed by each slave core is basically the same. After completing the element allocation of the first 63 slave cores, all the remaining elements are handed over to the last slave core for calculation and processing. This can effectively avoid the problem of load imbalance caused by large differences in row elements in equal row allocation.

[0084] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0085] The present embodiment also provides a sparse matrix-vector multiplication implementation system for the Shenwei processor, which is used to implement the above-mentioned embodiments and preferred implementation modes, and those that have been described will not be repeated here. As used below, the terms "module", "unit", "sub-unit", etc. can implement a combination of software and / or hardware for a predetermined function. Although the systems described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceived.

[0086] Figure 6 : is a structural block diagram of a sparse matrix-vector multiplication implementation system for a Sunway processor according to an embodiment of the present application. Figure 6 As shown, the system includes:

[0087] The task division unit obtains the input sparse matrix A, groups the matrix elements, and distributes them to the slave cores of the Sunway processor;

[0088] a memory allocation unit, which obtains a coefficient vector and configures a storage space for storing the sparse matrix A and the coefficient vector from a core memory based on the number of data transmissions in the sparse matrix A and the coefficient vector X;

[0089] The vector multiplication implementation unit allocates data based on the configured storage space and performs vector multiplication operations.

[0090] In some embodiments, the memory allocation unit further includes a coefficient vector allocation unit.

[0091] It should be noted that the above modules can be functional modules or program modules, and can be implemented through software or hardware. For modules implemented through hardware, the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0092] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A sparse matrix-vector multiplication implementation method for Sunway processors, characterized in that: include: The task division step obtains the input sparse matrix, groups the matrix elements, and distributes them to the slave cores of the Sunway processor; A memory allocation step of obtaining a coefficient vector and configuring a storage space for storing the sparse matrix and the coefficient vector in a slave core memory based on the number of data transmissions in the sparse matrix and the coefficient vector; The vector multiplication implementation step allocates data based on the configured storage space and performs a vector multiplication operation, and the vector multiplication implementation step further includes: Configure the temporary cache and protection cache in the slave core local memory LDM. The sizes of the temporary cache and protection cache are dynamically adjusted according to the load performance. The temporary buffer is used to store data blocks and their subscripts that have been accessed once. When the number of accesses to a data block in the temporary buffer is greater than one, the subscript and access count of the data block are stored in a temporary linked list, thereby saving the metadata information eliminated from the temporary buffer in the temporary linked list. The protection buffer is used to store data blocks that are accessed at least twice. When the protection buffer is not full, the data block with the largest number of accesses in the temporary linked list is stored in the protection buffer. When the protection cache is full, determine the maximum number of accesses to the data block in the temporary linked list and the minimum number of accesses to the data block in the protection cache, store the data block index with a larger number of accesses in the protection cache, and store the data block index with a smaller number of accesses in a protection linked list. If the maximum number of accesses in the protection linked list is greater than the minimum number of accesses in the protection cache, swap the corresponding data block indexes, that is, store the data block index with a larger number of accesses in the protection cache, and eliminate the data block index with a smaller number of accesses. Correct the cache distribution in the protection linked list through the swap operation to ensure that the data block with a larger number of accesses returns to the protection cache.

2. The sparse matrix-vector multiplication implementation method for the Sunway processor according to claim 1, characterized in that: The memory allocation step further comprises: Perform vector multiplication on the first memory of the sparse matrix stored in the kernel local memory LDM, the second memory storing the coefficient vector, and a remaining memory, access the dynamic data of the coefficient vector via RMA, and access the static data of the sparse matrix and the coefficient vector via DMA, and count the number of DMA accesses, the number of RMA accesses, and the corresponding single access time during the operation; The total running time is calculated based on the number of DMA accesses, the number of RMA accesses and the corresponding single access time during the operation process, and the first memory, the second memory and the remaining memory are configured with the goal of minimizing the total running time.

3. The method for implementing sparse matrix-vector multiplication for a Shenwei processor according to claim 2, wherein: The memory allocation step further includes a coefficient vector allocation step: Configuring the second memory space to include a static cache area and a dynamic cache area; After the static data is divided equally according to the number of slave cores used, it is stored in the static cache in the order of the slave cores; The dynamic cache area is configured to include 8 data blocks, each of which stores 128 dynamic data.

4. The method for implementing sparse matrix-vector multiplication for a Sunway processor according to claim 1, wherein: The matrix elements are grouped based on the first constraint, m is the total number of matrix elements, is the number of matrix rows, is the number of matrix columns, For the The number of elements in the row, The first processor of Sunway The first constraint is configured as follows: when When for .

5. A sparse matrix-vector multiplication implementation system for Sunway processors, characterized in that: A method for implementing a sparse matrix-vector multiplication according to any one of claims 1 to 4, comprising: The task division unit obtains the input sparse matrix, groups the matrix elements, and distributes them to the slave cores of the Sunway processor; a memory allocation unit, which obtains a coefficient vector and configures a storage space for storing the sparse matrix and the coefficient vector from a core memory based on a number of data transmissions in the sparse matrix and the coefficient vector; The vector multiplication implementation unit allocates data based on the configured storage space and performs vector multiplication operations.

6. The sparse matrix-vector multiplication implementation system for the Sunway processor according to claim 5, characterized in that: The memory allocation unit further includes a coefficient vector allocation unit.

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