Automatic verification method and device for PARA analysis, electronic equipment and storage medium
By parsing the register configuration form and automatically generating verification code, the problem of inefficient register verification is solved, the full process automation and efficient register verification are realized, and maintenance costs are reduced.
Patent Information
- Application Number
- CN202510459795.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-14
- Publication Date
- 2025-07-25
AI Technical Summary
In the prior art, the register configuration form parsing and verification process is inefficient, prone to errors, difficult to achieve batch processing and undifferentiated coverage, and high maintenance costs.
By entering and parsing the register configuration form, extracting register information, matching the verification method template according to the register type, automatically generate verification code, and integrating it into the verification framework to perform automated verification. Use Python scripts and Pandas library to process the register configuration form, detect conflicts and generate error reports.
It realizes full-process automation of register verification, improves efficiency, reduces manual coding errors, adapts to changes without refactoring, and reduces maintenance costs.
Smart Images
Figure CN120373221A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic technologies, and in particular, to an automated verification method, apparatus, electronic device, and storage medium for PARA parsing. Background Art
[0002] The background art of register PARA (register configuration form) parsing stems from the automated requirements for register configuration management in hardware design and development and chip verification. With the increasing complexity of chips (such as an SoC integrating tens of thousands of registers), the traditional method of manually writing register driver code and verification logic is inefficient and error-prone. Therefore, automated parsing and verification technologies have emerged.
[0003] For thousands of registers to generate corresponding verification codes, registers have various types, and different types of registers require different verification methods. Moreover, some registers have unused bit positions (invalid bit positions) at the beginning of the design. Manual coding is inefficient, and manually writing code is prone to introducing errors, resulting in the desynchronization between the design document and the actual code, leading to verification failures. The data and parameters in the register configuration form are complex and diverse, and the rules are dynamic. There may be address overlaps, bit width overflows, and combination conflicts in a large-scale register set. Conditional dependencies between fields (such as when the A field of the address is set to 1, the B field must be 0) require the construction of complex verification schemes. In order to parse out the required text, and then generate respective corresponding test cases according to the register types, such as RW registers, RO registers, RWTS registers, SC registers, and RONI registers, etc., to achieve the technology from PARA parsing to automated verification. Summary of the Invention
[0004] In view of this, the purpose of the present invention is to provide an automated verification method, apparatus, electronic device, and storage medium for PARA parsing.
[0005] In a first aspect, an embodiment of the present invention provides an automated verification method for PARA parsing, the method comprising:
[0006] Input and parse a register configuration form to extract register information; wherein, the register information at least includes the register type;
[0007] Match a corresponding verification method template according to the register type;
[0008] Automatically generate verification code for the register type based on the register information and the matched verification method template;
[0009] Integrate the verification code into a verification framework to perform automated verification and obtain the verification result of the register.
[0010] In combination with the first aspect, the register type is RW type or RWTS type; the register information further includes the register address, valid bit mask, and initial value;
[0011] The steps for automatically generating verification code for the register type based on the register information and the matching verification method template include:
[0012] Obtain the verification steps in the verification method template, and the verification steps include: reading the initial value and comparing it with the form configuration, writing all 1s and checking the valid bits, writing 0xaa and checking, writing 0x55 and checking, writing a random value and checking;
[0013] Fill in the verification method template according to the register address, valid bit mask, and initial value to generate executable verification code.
[0014] In combination with the first aspect, the register type is RO type; the register information further includes the signal name;
[0015] The steps for automatically generating verification code for the register type based on the register information and the matching verification method template include:
[0016] Add a signal path field to the register configuration form and specify the RTL signal hierarchical path corresponding to the register;
[0017] Extract the RTL signal hierarchical path when parsing the signal path field and generate the HDL path information required for backdoor access;
[0018] Obtain the verification steps in the verification method template that matches the register, and the verification steps include: backdoor writing all 1s and checking, backdoor writing all 0s and checking, backdoor writing 0xaa and checking, backdoor writing 0x55 and checking, backdoor writing a random value and checking:
[0019] Modify the RTL signal value definition general backdoor operation function through the HDL path information;
[0020] Fill in the verification method template according to the signal name to generate executable verification code.
[0021] In combination with the first aspect, the register type is SC type; the register information further includes the signal mapping;
[0022] The steps for automatically generating verification code for the register type based on the register information and the matching verification method template include:
[0023] Obtain the verification steps in the verification method template that matches the register, and the verification steps include: initialization check, trigger test;
[0024] Fill in the verification method template according to the signal mapping to generate executable verification code.
[0025] In combination with the first aspect, the register type is the RONI type; the register information further includes an initial value;
[0026] The steps of automatically generating verification code for the register type based on the register information and the matched verification method template include:
[0027] Generating SV code based on a specified script in combination with the verification method template;
[0028] Filling the verification method template according to the initial value to generate executable verification code.
[0029] In combination with the first aspect, the steps of inputting and parsing a register configuration form to extract register information include:
[0030] Parsing the register configuration form through a Python script in combination with the Pandas library to generate a structured data file including register address, register type, valid bits, initial value, bit width, and signal name; wherein, the register configuration form is in CSV or Excel format.
[0031] In combination with the first aspect, it further includes a rule verification engine for detecting conflicts in the register configuration form, including address overlap, bit width out-of-bounds, and conditional dependency errors between fields, and generating an error report during the parsing stage.
[0032] In the second aspect, an embodiment of the present application further provides an automated verification device for PARA parsing, and the device includes:
[0033] An information extraction module for inputting and parsing a register configuration form to extract register information; wherein, the register information at least includes a register type;
[0034] A matching module for matching a corresponding verification method template according to the register type;
[0035] A generation module for automatically generating verification code for the register type based on the register information and the matched verification method template;
[0036] A verification module for integrating the verification code into a verification framework to perform automated verification and obtaining a verification result of the register.
[0037] In the third aspect, the present application provides an electronic device, the electronic device includes a memory and a processor, the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to execute the above method.
[0038] Fourthly, the present application provides a readable storage medium, in which computer program instructions are stored. When the computer program instructions are read and run by a processor, the above-mentioned method is executed.
[0039] The embodiments of the present invention bring the following beneficial effects: The automated verification method, device, electronic device, and storage medium for PARA parsing provided by the present application. The method includes: inputting and parsing a register configuration form to extract register information; wherein the register information at least includes the register type; matching a corresponding verification method template according to the register type; automatically generating verification code for the register type based on the register information and the matched verification method template; integrating the verification code into a verification framework to perform automated verification to obtain the verification result of the register.
[0040] In the present invention, a corresponding verification method template is matched based on the register type, and then verification code corresponding to the register type is automatically generated based on the verification method template and the register information for adaptive verification. Compared with the prior art method of manually writing and analyzing the configuration form item by item, the verification code is automatically generated based on the register type through a predefined verification template, which can be processed in batches and is not prone to errors. The whole process is automated and all registers are covered without difference, and it can adapt to changes without reconstruction, which can effectively improve the verification efficiency and reduce the maintenance cost.
[0041] Other features and advantages of the present invention will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention are achieved and obtained by the structures specifically pointed out in the specification, claims, and drawings.
[0042] To make the above-mentioned objectives, features, and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given, and in conjunction with the accompanying drawings, the detailed description is as follows. Description of the Drawings
[0043] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required to be used in the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0044] Figure 1 It is a flowchart of the automated verification method for PARA parsing provided by the embodiments of the present invention;
[0045] Figure 2 It is a schematic structural diagram of the automated verification device for PARA parsing provided by the embodiments of the present invention;
[0046] Figure 3 Schematic diagram of the electronic device provided by the embodiment of the present invention.
[0047] Reference numerals:
[0048] 10 - Information extraction module, 20 - Matching module, 30 - Generation module, 40 - Verification module;
[0049] 130 - Processor, 131 - Memory, 132 - Bus, 133 - Communication interface. Detailed implementation manners
[0050] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0051] To facilitate the understanding of this embodiment, the technical terms designed in this application will be briefly introduced below.
[0052] PARA parsing generally refers to the process of analyzing and extracting information from specific structured data (such as XML, JSON, etc.). The core lies in decomposing complex data into operable units. This method is widely used in data processing, web crawlers, and information management systems.
[0053] After introducing the technical terms involved in this application, next, the application scenarios and design concepts of the embodiments of this application will be briefly introduced.
[0054] In the existing register verification process, it is necessary to manually write code, which is cumbersome, has a large workload and is error-prone, and it is difficult to achieve batch register verification.
[0055] Based on this, the embodiments of this application provide an automated verification method, device, electronic device, and storage medium for PARA parsing.
[0056] Embodiment 1
[0057] This application provides an automated verification method for PARA parsing. As shown in Figure 1 The method includes:
[0058] S110, input and parse the register configuration form to extract register information; wherein, the register information includes at least the register type.
[0059] S120, match the corresponding verification method template according to the register type.
[0060] S130. Automatically generate verification code for the register type based on the register information and the matching verification method template.
[0061] S140. Integrate the verification code into the verification framework to perform automated verification and obtain the verification result of the register.
[0062] In the present invention, a verification method template corresponding to the register type is matched, and then verification code corresponding to the register type is automatically generated based on the verification method template and the register information for adaptive verification. Compared with the existing method of manually writing and analyzing the configuration form item by item, the verification code is automatically generated based on the register type through a predefined verification template, which can be processed in batches and is not prone to errors. The whole process is automated and all registers are covered without discrimination, and it can adapt to changes without reconstruction, which can effectively improve the verification efficiency and reduce the maintenance cost.
[0063] Combined with the first aspect, the register type is RW type or RWTS type; the register information further includes the register address, the valid bit mask, and the initial value. Step S130 includes:
[0064] S131. Obtain the verification steps in the verification method template, and the verification steps include: reading the initial value and comparing it with the form configuration, writing all 1s and checking the valid bits, writing 0xaa and checking, writing 0x55 and checking, writing a random value and checking;
[0065] S132. Fill the verification method template according to the register address, the valid bit mask, and the initial value to generate executable verification code.
[0066] In this embodiment, a verification method template is predefined according to the register type (RW or RWTS) to clarify the test logic different from that of other types of registers. The verification steps include: reading the initial value and comparing it with the configuration, writing all 1s to check the valid bits, writing 0xAA to check, writing 0x55 to check, writing a random value to check. After performing the automated verification in step S140, a verification result will be obtained for each verification step, and the combined verification results of all steps can be used to obtain the verification result of the register. Through the above steps, the full automation of generating verification code from register configuration is realized, covering the RW / RWTS register type, ensuring the double improvement of verification efficiency and quality.
[0067] Combined with the first aspect, the register type is RO type; the register information further includes the signal name. Step S130 includes:
[0068] S133. Add a signal path field to the register configuration form and specify the RTL signal hierarchical path corresponding to the register.
[0069] An example of the register configuration form (PARA) is as follows:
[0070]
[0071] Among them, SignalPath: the RTL signal path corresponding to the register (such as top.dut.status_reg), which is used for backdoor writing.
[0072] ValidBits: the valid bit mask to ensure that only the allowed bits are modified (for example, only some bits of an RO register may be readable).
[0073] S134 extracts the RTL signal hierarchical path when parsing the signal path field and generates the HDL path information required for backdoor access.
[0074] S135 obtains the verification steps in the verification method template that matches the register. The verification steps include: backdoor writing all 1s and checking, backdoor writing all 0s and checking, backdoor writing 0xaa and checking, backdoor writing 0x55 and checking, backdoor writing a random value and checking.
[0075] S136 modifies the RTL signal value through the HDL path information to define a general backdoor operation function.
[0076] uvm_hdl_force is the backdoor operation function; define a function named RO_REG_TEST_SPI. The first parameter is the HDL path information, the second parameter is the register address, the third parameter is the valid bit mask, and the fourth parameter is the initial value. Here, taking the backdoor operation function to write the value 'hff and reading the value from the front door as an example, print check OK if the information comparison is successful; print check ERROR if the information comparison fails.
[0077] An example of the implementation code is as follows:
[0078] task RO_REG_TEST_SPI(string name, logic[7:0]mask, logic[7:0]inival);
[0079] logic[7:0]rdata;
[0080] uvm_hdl_force(name, ('hff));
[0081] spi_single_wrie4_read(addr, rdata);
[0082] if((mask&('hff))!= rdata)begin
[0083] `uvm_error("BACK_DOOR CHECK", $sformatf("addr[0x%0h], reg[%s]: back_door force FF check ERROR!!! exp: %0h, actual: %0h", addr, name, (mask & ('hff)), rdata))
[0084] end
[0085] else begin
[0086] `uvm_error("BACK_DOOR CHECK", $sformatf("addr[0x%0h], reg[%s]: back_door force FF check OK!!!! addr, name, UVM_LOW).
[0087] The RO_REG_TEST_SPI function is called as follows:
[0088] RO_REG_TEST_SPI("harness.U_DIG_SDS.U_DIG_TOP.U_SPI_TOP, sync_rpt", 24, 8'b000100000, 0).
[0089] S137. Fill in the verification method template according to the signal name to generate executable verification code.
[0090] For RO registers, since they cannot be written through the front door (bus interface), their underlying signal values need to be directly modified through backdoor access (BackdoorAccess), and then read through the front door to verify the function. In this embodiment, according to the register type (RO, i.e., read-only memory), a verification method template is predefined to clarify the test logic different from other types of registers. The verification steps include: backdoor write all 1s and check, backdoor write all 0s and check, backdoor write 0xaa and check, backdoor write 0x55 and check, backdoor write random values and check. After performing the automated verification in step S140, a verification result will be obtained for each verification step. Combining all the verification results can obtain the verification result of this register. Through the above steps, the full automation generation from register configuration to verification code is realized, covering the RO register type, ensuring the double improvement of verification efficiency and quality.
[0091] Combined with the first aspect, the register type is the SC type; the register information further includes signal mapping. Step S130 includes:
[0092] S138. Obtain the verification steps in the verification method template that match the register. The verification steps include: initialization check, trigger test:
[0093] S139. Fill the verification method template according to the signal mapping to generate executable verification code.
[0094] An example of the register configuration form is as follows:
[0095]
[0096] For SC (Self-Clearing) type registers, SC (Self-Clearing) type registers usually have the following characteristics: automatically clear to zero after writing 1 to trigger the function; each control bit corresponds to an independent hardware signal; it is necessary to verify the pulse behavior (0→1→0) of the trigger signal.
[0097] The verification steps include: initialization check, trigger test. After performing the automated verification in step S140, assert whether a_trig, b_trig, and c_trig have jumped from 0 to 1 and then back to 0 respectively. Thus, a verification result will be obtained for each verification step, and combining all the verification results can obtain the verification result of the register. Through the above steps, the fully automated generation from register configuration to verification code is realized, covering the SC register type, ensuring the double improvement of verification efficiency and quality.
[0098] Combined with the first aspect, the register type is RONI type; the register information also includes the initial value.
[0099] Step S130 includes:
[0100] S130a. Generate SV code based on the specified script and the verification method template.
[0101] S130b. Fill the verification method template according to the initial value to generate executable verification code.
[0102] For RONI (Read-Only Non-Interruptible) type registers, RONI type registers usually have the following characteristics: read-only attribute, cannot be written through the bus; non-interruptible characteristic (NI), that is, value changes do not trigger interrupts; static initial value, that is, the value is fixed after reset, usually reflecting hardware configuration or version information; signal direct connection: the value is directly driven by hardware logic. In this application, by adding register information to the matching verification method template and then performing verification, the process of automatically generating RONI verification written in SV language is realized, and the register value is read and compared with the initial value in the form to check whether it is correct. Specifically, the register value can be read from the front door, the initial value comparison and signal consistency check can be performed, and the backdoor signal value comparison can also be performed.
[0103] Combined with the first aspect, step S110 includes:
[0104] Parse the register configuration form through a Python script combined with the Pandas library to generate a structured data file including register address, register type, valid bits, initial value, bit width, and signal name; among them, the register configuration form is in CSV or Excel format.
[0105] In this embodiment, the text format used is CSV type, the script uses Python, and the register configuration form is parsed through a Python script combined with the Pandas library. The verification code is written in SystemVerilog language, and the generated code includes register address mapping, read / write operation sequences, and assertion logic, and is integrated into the UVM verification framework.
[0106] Among them, the verification framework checks the register reset value through uvm_reg_hw_reset_seq, checks the read / write consistency through uvm_reg_access_seq, and checks the correctness of the register HDL path through uvm_reg_mem_hdl_paths_seq.
[0107] Combined with the first aspect, it further includes a rule verification engine for detecting conflicts in the register configuration form, including address overlap, bit width out-of-bounds, and field-level conditional dependency errors, and generating an error report during the parsing stage.
[0108] In this application, a three-layer automated verification architecture is constructed: specifically, an input layer, a parsing engine layer, and a verification execution layer; in the input layer, a standardized CSV form is used as the input, which contains the parsed register information (such as register address, type, valid bits, signal mapping, initial value, etc.); in the parsing engine layer, a structured data file (.dat) is generated through parsing based on Python scripts to characterize the register attributes, and then in the verification execution layer, the verification steps in the verification method template are executed to obtain the verification result. The verification process has a high degree of automation, reducing the labor intensity of manual coding required for each verification and also reducing the error rate.
[0109] Combined with the first aspect, the above method also supports generating register parsing code and verification logic through an AI model. The AI model automatically generates matching Python scripts and SystemVerilog code based on the input register type and verification requirements.
[0110] Specifically, the user provides a natural language description, for example: "It is required to verify the RW register at address 0x1000, with a width of 32 bits, a reset value of 0x0, a valid bit mask of 0xFFFF, and a signal name of data_out[31:0]".
[0111] Subsequently, the AI model extracts the register information, then the AI generates a UVM register model, and then automatically binds and verifies the register verification method.
[0112] In the second aspect, an embodiment of the present application provides an automated verification device for PARA parsing. Combined with Figure 2 As shown, the device includes: an information extraction module 10, a matching module 20, a generation module 30, and a verification module 40.
[0113] The information extraction module 10 is used to input and parse the register configuration form to extract register information; among them, the register information includes at least the register type.
[0114] The matching module 20 is used to match the corresponding verification method template according to the register type.
[0115] The generation module 30 is used to automatically generate verification code for the register type based on the register information and the matched verification method template.
[0116] The verification module 40 is used to integrate the verification code into the verification framework to perform automated verification and obtain the verification result of the register.
[0117] In the third aspect, an embodiment of the present application provides an electronic device. Combined with Figure 3As shown, the electronic device includes a memory 131 and a processor 130. The memory 131 is used to store computer programs, and the processor 130 runs the computer programs to enable the electronic device to execute the above-mentioned method.
[0118] Furthermore, in combination with Figure 3 the electronic device shown also includes a bus 132 and a communication interface 133. The processor 130, the communication interface 133, and the memory 131 are connected through the bus 132.
[0119] Among them, the memory 131 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory. Through at least one communication interface 133 (which can be wired or wireless), a communication connection is established between this system network element and at least one other network element, and the Internet, wide area network, local area network, metropolitan area network, etc. can be used. The bus 132 can be an ISA bus, a PCI bus, an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity of representation, Figure 3 only a bidirectional arrow is used in [the figure] to represent it, but it does not mean that there is only one bus or one type of bus.
[0120] The processor 130 may be an integrated circuit chip with the ability to process signals. In the implementation process, the steps of the above method can be completed by the integrated logic circuit of the hardware in the processor 130 or the instructions in the form of software. The above-mentioned processor 130 may be a general-purpose processor, including a central processing unit (CPU for short), a network processor (NP for short), etc.; it may also be a digital signal processor (DSP for short), an application specific integrated circuit (ASIC for short), a field-programmable gate array (FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present invention can be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of the hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory 131, and the processor 130 reads the information in the memory 131 and combines its hardware to complete the steps of the method in the foregoing embodiments.
[0121] Fourthly, an embodiment of the present application provides a readable storage medium. When computer program instructions stored in the readable storage medium are read and run by a processor, the above-mentioned method is executed.
[0122] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems and devices described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated here.
[0123] In addition, in the description of the embodiments of the present invention, unless otherwise clearly defined and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may be the communication inside two elements. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.
[0124] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.
[0125] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.
[0126] Finally, it should be noted that the above embodiments are only specific embodiments of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting them. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art within the technical scope disclosed by the present invention can still modify the technical solutions described in the foregoing embodiments, or can easily think of changes, or make equivalent replacements for some of the technical features; and these modifications, changes, or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims
1. An automated verification method for PARA parsing, characterized in that, The method includes: Input and parse a register configuration form to extract register information; wherein, the register information at least includes the register type; Match the corresponding verification method template according to the register type; Automatically generate verification code for the register type based on the register information and the matched verification method template; Integrate the verification code into a verification framework to perform automated verification to obtain the verification result of the register.
2. The method according to claim 1, wherein The register type is RW type or RWTS type; the register information further includes the register address, valid bit mask, and initial value; The step of automatically generating verification code for the register type based on the register information and the matched verification method template includes: Obtain the verification steps in the verification method template, and the verification steps include: reading the initial value and comparing it with the form configuration, writing all 1s and checking the valid bits, writing 0xaa and checking, writing 0x55 and checking, writing a random value and checking; Fill the verification method template according to the register address, the valid bit mask, and the initial value to generate executable verification code.
3. The method according to claim 1, wherein The register type is RO type; the register information further includes the signal name; The step of automatically generating verification code for the register type based on the register information and the matched verification method template includes: Add a signal path field to the register configuration form and specify the RTL signal hierarchical path corresponding to the register; Extract the RTL signal hierarchical path when parsing the signal path field and generate the HDL path information required for backdoor access; Obtain the verification steps in the verification method template that matches the register, and the verification steps include: backdoor writing all 1s and checking, backdoor writing all 0s and checking, backdoor writing 0xaa and checking, backdoor writing 0x55 and checking, backdoor writing a random value and checking: Modify the RTL signal value definition to a general backdoor operation function through the HDL path information; Fill the verification method template according to the signal name to generate executable verification code.
4. The method according to claim 1, wherein The register type is SC type; the register information further includes the signal mapping; The step of automatically generating verification code for the register type based on the register information and the matched verification method template includes: Obtain the verification steps in the verification method template that matches the register, and the verification steps include: initialization check, trigger test; Fill the verification method template according to the signal mapping to generate executable verification code.
5. The method according to claim 1, characterized in that, The register type is RONI type; the register information further includes the initial value; The step of automatically generating verification code for the register type based on the register information and the matched verification method template includes: Generate SV code based on a specified script in combination with the verification method template; Fill the verification method template according to the initial value to generate executable verification code.
6. The method according to any one of claims 1-5, characterized in that The step of inputting and parsing a register configuration form to extract register information includes: Parse the register configuration form through a Python script combined with the Pandas library to generate a structured data file including register address, register type, valid bits, initial value, bit width, and signal name; wherein, the register configuration form is in CSV or Excel format.
7. The method for PARA parsing according to claim 1, characterized in that, It further includes a rule verification engine for detecting conflicts in the register configuration form, including address overlap, bit width out-of-bounds, and inter-field conditional dependency errors, and generating an error report during the parsing stage.
8. An automated verification device for PARA parsing, characterized in that The device includes: An information extraction module for inputting and parsing the register configuration form to extract register information; wherein, the register information includes at least the register type. A matching module for matching the corresponding verification method template according to the register type. A generation module for automatically generating verification code for the register type based on the register information and the matched verification method template. A verification module for integrating the verification code into a verification framework to perform automated verification and obtain the verification result of the register.
9. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to execute the method according to any one of claims 1 to 7.
10. A storage medium, characterized in that, Computer program instructions are stored in the storage medium, and when the computer program instructions are read and run by a processor, the method according to any one of claims 1 to 7 is executed.